1/*
2 * Copyright 2021 The Chromium OS Authors
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/g0/stm32g081Xb.dtsi>
9#include <st/g0/stm32g081rbtx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/input/input-event-codes.h>
11
12/ {
13	model = "STM32G081B EVAL board";
14	compatible = "st,stm32g081-eval";
15
16	chosen {
17		zephyr,console = &usart3;
18		zephyr,shell-uart = &usart3;
19		zephyr,sram = &sram0;
20		zephyr,flash = &flash0;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		led_1: led1 {
26			gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
27			label = "LED1";
28		};
29		led_2: led2 {
30			gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>;
31			label = "LED2";
32		};
33		led_3: led3 {
34			gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
35			label = "LED3";
36		};
37		led_4: led4 {
38			gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
39			label = "LED4";
40		};
41	};
42
43	gpio_keys {
44		compatible = "gpio-keys";
45		joy_sel: button0 {
46			label = "JOY_SEL";
47			gpios = <&gpioa 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
48			zephyr,code = <INPUT_KEY_ENTER>;
49		};
50		joy_left: button1 {
51			label = "JOY_LEFT";
52			gpios = <&gpioc 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
53			zephyr,code = <INPUT_KEY_LEFT>;
54		};
55		joy_down: button2 {
56			label = "JOY_DOWN";
57			gpios = <&gpioc 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
58			zephyr,code = <INPUT_KEY_DOWN>;
59		};
60		joy_right: button3 {
61			label = "JOY_RIGHT";
62			gpios = <&gpioc 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
63			zephyr,code = <INPUT_KEY_RIGHT>;
64		};
65		joy_up: button4 {
66			label = "JOY_UP";
67			gpios = <&gpioc 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
68			zephyr,code = <INPUT_KEY_UP>;
69		};
70	};
71
72	aliases {
73		led0 = &led_1;
74		led1 = &led_2;
75		led2 = &led_3;
76		led3 = &led_4;
77		sw0 = &joy_sel;
78		sw1 = &joy_left;
79		sw2 = &joy_down;
80		sw3 = &joy_right;
81		sw4 = &joy_up;
82		watchdog0 = &iwdg;
83		volt-sensor0 = &vref;
84		volt-sensor1 = &vbat;
85	};
86};
87
88&clk_hsi {
89	status = "okay";
90};
91
92&pll {
93	div-m = <1>;
94	mul-n = <8>;
95	div-p = <2>;
96	div-q = <2>;
97	div-r = <2>;
98	clocks = <&clk_hsi>;
99	status = "okay";
100};
101
102&rcc {
103	clocks = <&pll>;
104	clock-frequency = <DT_FREQ_M(64)>;
105	ahb-prescaler = <1>;
106	apb1-prescaler = <1>;
107};
108
109&usart3 {
110	pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
111	pinctrl-names = "default";
112	current-speed = <115200>;
113	status = "okay";
114};
115
116&tim15_ch1_pc1 {
117	slew-rate = "very-high-speed";
118	bias-pull-up;
119	drive-open-drain;
120};
121
122&timers15 {
123	status = "okay";
124	pwm15: pwm {
125		status = "okay";
126		pinctrl-0 = <&tim15_ch1_pc1>;
127		pinctrl-names = "default";
128	};
129};
130
131&adc1 {
132	pinctrl-0 = <&adc1_in3_pa3 &adc1_in9_pb1>;
133	pinctrl-names = "default";
134	st,adc-clock-source = "SYNC";
135	st,adc-prescaler = <4>;
136	status = "okay";
137
138	#address-cells = <1>;
139	#size-cells = <0>;
140
141	channel@3 {
142		reg = <3>;
143		zephyr,gain = "ADC_GAIN_1";
144		zephyr,reference = "ADC_REF_INTERNAL";
145		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
146		zephyr,resolution = <12>;
147		zephyr,vref-mv = <3300>;
148	};
149
150	channel@9 {
151		reg = <9>;
152		zephyr,gain = "ADC_GAIN_1";
153		zephyr,reference = "ADC_REF_INTERNAL";
154		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
155		zephyr,resolution = <12>;
156		zephyr,vref-mv = <3300>;
157	};
158};
159
160&ucpd1 {
161	status = "okay";
162
163	/*
164	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
165	 * a prescaler who's output feeds the 'half-bit' divider which is used
166	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
167	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168	 * range is 9 <--> 18 MHz.
169	 *
170	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
171	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
172	 *          +-------+          +-------+   |            +-----------+
173	 *                                         |            +-----------+
174	 *                                         +----------->| ifrgap_cnt|
175	 *                                                      +-----------+
176	 * Requirements:
177	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
178	 *   2. tTransitionWindow - 12 to 20 uSec
179	 *   3. tInterframGap - uSec
180	 *
181	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
182	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
183	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
184	 */
185	psc-ucpdclk = <1>;
186	hbitclkdiv = <27>;
187	pinctrl-0 = <&ucpd1_cc1_pa8 &ucpd1_cc2_pb15>;
188	pinctrl-names = "default";
189};
190
191&ucpd2 {
192	status = "okay";
193
194	/*
195	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
196	 * a prescaler who's output feeds the 'half-bit' divider which is used
197	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
198	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
199	 * range is 9 <--> 18 MHz.
200	 *
201	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
202	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
203	 *          +-------+          +-------+   |            +-----------+
204	 *                                         |            +-----------+
205	 *                                         +----------->| ifrgap_cnt|
206	 *                                                      +-----------+
207	 * Requirements:
208	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
209	 *   2. tTransitionWindow - 12 to 20 uSec
210	 *   3. tInterframGap - uSec
211	 *
212	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
213	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
214	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
215	 */
216	psc-ucpdclk = <1>;
217	hbitclkdiv = <27>;
218	pinctrl-0 = <&ucpd2_cc1_pd0 &ucpd2_cc2_pd2>;
219	pinctrl-names = "default";
220};
221
222&iwdg {
223	status = "okay";
224};
225
226&vref {
227	status = "okay";
228};
229
230&vbat {
231	status = "okay";
232};
233