| /Zephyr-latest/soc/arm/beetle/ |
| D | soc_registers.h | 33 /* Offset: 0x030 (r/w)APB peripheral access control set */
35 /* Offset: 0x034 (r/w)APB peripheral access control clear */
64 /* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
66 /* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
68 /* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
70 /* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
72 /* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
74 /* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
81 /* Offset: 0x0c8 (r/w) APB peripheral reset select set */
83 /* Offset: 0x0cc (r/w) APB peripheral reset select clear */
[all …]
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| D | power.c | 68 /* Enable AHB and APB clocks */ in clock_active_init()
72 /* Configure APB Peripheral Clock in active state */ in clock_active_init()
83 /* Configure APB Peripheral Clock in sleep state */ in clock_sleep_init()
94 /* Configure APB Peripheral Clock in deep sleep state */ in clock_deepsleep_init()
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| D | soc_pins.h | 28 /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
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| D | soc.h | 38 /* Beetle SoC APB Devices */
71 /* Beetle SoC APB peripherals */
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.cmsdk_apb | 1 # ARM CMSDK APB SoC UART configuration options
7 bool "ARM CMSDK APB UART driver"
13 This option enables the UART driver for ARM CMSDK APB UART.
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| /Zephyr-latest/dts/bindings/clock/ |
| D | silabs,si32-apb.yaml | 5 description: Silabs Si32 APB clock controller node
7 compatible: "silabs,si32-apb"
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| D | nuvoton,numaker-scc.yaml | 44 Configure APB Clock Divider register
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| D | st,stm32wb0-rcc.yaml | 49 The CLK_SYS is used to clock the CPU, AHB, APB, memories and PKA.
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| /Zephyr-latest/soc/ene/kb1200/ |
| D | soc.c | 31 /* AHB/APB clock select 96MHz/48MHz */ in clock_init()
34 /* AHB/APB clock select 48MHz/24MHz */ in clock_init()
37 /* AHB/APB clock select 24MHz/12MHz */ in clock_init()
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| /Zephyr-latest/drivers/watchdog/ |
| D | Kconfig.cmsdk_apb | 7 bool "CMSDK APB Watchdog Driver for ARM family of MCUs"
12 Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM
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| D | wdt_dw.h | 17 * The DW_apb_wdt is an APB slave peripheral that can be used to prevent system lockup that may be
214 * Width of the APB Data Bus to which this component is attached.
219 * APB data width is 8 bits
224 * APB data width is 16 bits
229 * APB data width is 32 bits
544 * @brief Width of the APB Data Bus to which this component is attached.
547 * @return APB data width
548 * 0x0 (APB_8BITS): APB data width is 8 bits
549 * 0x1 (APB_16BITS): APB data width is 16 bits
550 * 0x2 (APB_32BITS): APB data width is 32 bits
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| /Zephyr-latest/boards/nordic/nrf54l15dk/support/ |
| D | nrf54l_05_10_15_cpuflpr.JLinkScript | 2 // Base address where DMI registers can be found in the APB address space
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_gd32.c | 147 * Up to a certain threshold value of APB{1,2} prescaler, timer in clock_control_gd32_get_rate()
150 * threshold, timer clock is set to a multiple of the APB in clock_control_gd32_get_rate()
171 * If the APB prescaler equals 1, the timer clock frequencies in clock_control_gd32_get_rate()
172 * are set to the same frequency as that of the APB domain. in clock_control_gd32_get_rate()
173 * Otherwise, they are set to twice the frequency of the APB in clock_control_gd32_get_rate()
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| D | Kconfig.si32 | 16 bool "SI32 APB clock control"
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| /Zephyr-latest/boards/nordic/nrf54h20dk/support/ |
| D | nrf54h20_cpuflpr.JLinkScript | 2 // Base address where DMI registers can be found in the APB address space
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| D | nrf54h20_cpuppr.JLinkScript | 2 // Base address where DMI registers can be found in the APB address space
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| /Zephyr-latest/boards/gaisler/gr716a_mini/doc/ |
| D | index.rst | 87 AHB/APB Bridge Cobham Gaisler
88 AHB/APB Bridge Cobham Gaisler
89 AHB/APB Bridge Cobham Gaisler
90 AHB/APB Bridge Cobham Gaisler
93 AHB/APB Bridge Cobham Gaisler
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_esp32.c | 26 * of extra entropy from a hardware randomness source every APB clock cycle in entropy_esp32_get_u32()
28 * faster than it is added, this function needs to wait for at least 16 APB in entropy_esp32_get_u32()
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| /Zephyr-latest/dts/riscv/starfive/ |
| D | starfive_jh7100_beagle_v.dtsi | 137 compatible = "ns16550", "snps,dw-apb-uart";
150 compatible = "ns16550", "snps,dw-apb-uart";
163 compatible = "ns16550", "snps,dw-apb-uart";
176 compatible = "ns16550", "snps,dw-apb-uart";
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | gmac_fixup_samd5x.h | 9 * APB-specific symbols, in order to accommodate different SoC series with the
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| /Zephyr-latest/samples/drivers/counter/maxim_ds3231/src/ |
| D | main.c | 85 void timespec_add(struct timespec *apb, in timespec_add() argument
89 apb->tv_nsec = a->tv_nsec + b->tv_nsec; in timespec_add()
90 apb->tv_sec = a->tv_sec + b->tv_sec; in timespec_add()
91 if (apb->tv_nsec >= NSEC_PER_SEC) { in timespec_add()
92 apb->tv_sec += 1; in timespec_add()
93 apb->tv_nsec -= NSEC_PER_SEC; in timespec_add()
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| /Zephyr-latest/dts/bindings/reset/ |
| D | st,stm32-rcc-rctl.yaml | 7 and APB (Advanced Peripheral) bus domains.
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| /Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/ |
| D | esp32s2-xtensa-intmux.h | 90 #define PMS_DMA_APB_I_ILG_INTR_SOURCE 80 /* illegal APB access, level */
101 #define APB_ADC_INTR_SOURCE 89 /* APB ADC, level */
104 #define APB_PERI_ERROR_INTR_SOURCE 92 /* APB peripherals error, level */
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| /Zephyr-latest/dts/arm/silabs/ |
| D | sim3u.dtsi | 54 clk_apb: clk-apb {
55 compatible = "silabs,si32-apb";
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| /Zephyr-latest/boards/snps/nsim/arc_v/ |
| D | rmx1xx.dtsi | 41 compatible = "ns16550", "snps,dw-apb-uart";
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