| /Zephyr-latest/dts/bindings/gpio/ |
| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
26 10 I2C SDA 30 31 GPIO 11 GPIO
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
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| D | atmel-xplained-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
32 This binding provides a nexus mapping for 10 pins where pins are disposed
36 Bind Pin Name Pin Pin Pin Name Bind
41 GND 9 10 VDD(+3.3V)
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
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| D | sparkfun,micromod-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
[all …]
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| D | seeed-xiao-header.yaml | 4 # SPDX-License-Identifier: Apache-2.0
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
16 has three power pins, followed by four inputs labeled 10 at the
19 This binding provides a nexus mapping for 10 pins where parent pins 0
20 through 10 correspond to D0 through D10, as depicted below:
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
[all …]
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| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
[all …]
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| D | nxp,lcd-8080.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,lcd-8080"
8 GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel).
9 These pins are exposed on a 32 pin connector. The pins have the
12 Pin Number Usage
22 10 GPIO to control LCD backlight
24 12 LCD 8080 interface D/C pin
25 13 LCD 8080 interface CS pin
26 14 LCD 8080 interface WR pin
27 15 LCD 8080 interface RD pin
[all …]
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| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
40 6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
42 10 UART(RX) 13 14 UART(TX) 11
[all …]
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| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
[all …]
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| /Zephyr-latest/samples/drivers/i2c/rtio_loopback/boards/ |
| D | b_u585i_iot02a.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
7 * i2c1 PB9 CN3:10 PB8 CN3:7
8 * i2c2 PH5 CN2:10 PH4 CN2:7
10 * Short Pin PB9 to PH5, and PB8 to PH4, for the test to pass.
15 i2c-controller = &i2c1;
16 i2c-controller-target = &i2c2;
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| /Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/ |
| D | b_u585i_iot02a.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
7 * i2c1 PB9 CN3:10 PB8 CN3:7
8 * i2c2 PH5 CN2:10 PH4 CN2:7
10 * Short Pin PB9 to PH5, and PB8 to PH4, for the test to pass.
13 /delete-node/ &eeprom0;
17 compatible = "zephyr,i2c-target-eeprom";
25 compatible = "zephyr,i2c-target-eeprom";
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| /Zephyr-latest/boards/shields/x_nucleo_eeprma2/ |
| D | x_nucleo_eeprma2.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
40 address-width = <16>;
[all …]
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| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.spiram | 2 # SPDX-License-Identifier: Apache-2.0
7 bool "Support for external, SPI-connected RAM"
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
66 bool "ESP-PSRAM64, LY68L6400 or APS6408"
134 bool "Move Read-Only Data in Flash to PSRAM"
148 Enable MSPI Error-Correcting Code function when accessing SPIRAM.
149 If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
153 menu "PSRAM clock and cs IO for ESP32-DOWD"
161 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
[all …]
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | wiznet,w5500.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: W5500 standalone 10/100BASE-T Ethernet controller with SPI interface
8 include: [spi-device.yaml, ethernet-controller.yaml]
11 int-gpios:
12 type: phandle-array
14 description: Interrupt pin.
16 The interrupt pin of W5500 is active low.
17 If connected directly the MCU pin should be configured
19 reset-gpios:
20 type: phandle-array
[all …]
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| /Zephyr-latest/dts/bindings/display/ |
| D | solomon,ssd1306fb-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: display-controller.yaml
7 segment-offset:
10 description: 8-bit column start address for Page Addressing Mode
12 page-offset:
17 display-offset:
22 multiplex-ratio:
27 segment-remap:
31 com-invdir:
35 com-sequential:
[all …]
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| /Zephyr-latest/tests/kernel/timer/timer_behavior/ |
| D | Kconfig | 1 # SPDX-License-Identifier: Apache-2.0
28 default 10
43 default 10
45 A value of 10 means 10%.
50 Toggles a GPIO pin, on every period, that can be used by an external
61 connected to a GPIO pin is used to measure time behaviour.
68 connected to a GPIO pin is used to measure time behaviour.
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,ism330dhcx-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 When setting the accel-odr and gyro-odr properties in a .dts or .dtsi file you may include
9 #include <zephyr/dt-bindings/sensor/ism330dhcx.h>
14 accel-odr = <ISM330DHCX_DT_ODR_104Hz>;
15 gyro-odr = <ISM330DHCX_DT_ODR_104Hz>;
18 include: sensor-device.yaml
21 drdy-gpios:
22 type: phandle-array
24 DRDY gpio pin
26 This pin defaults to active high when produced by the sensor.
[all …]
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| D | st,lis2dux12-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 When setting the odr, power-mode, and range properties in a .dts or .dtsi file you may include
8 #include <zephyr/dt-bindings/sensor/st_lis2dux12.h>
11 power-mode = <LIS2DUX12_OPER_MODE_LOW_POWER>;
16 include: sensor-device.yaml
19 int1-gpios:
20 type: phandle-array
22 INT1 pin
24 This pin defaults to active high when produced by the sensor.
27 int2-gpios:
[all …]
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| D | st,lsm6dso-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range,
6 gyro-odr properties in a .dts or .dtsi file you may include lsm6dso.h
10 #include <zephyr/dt-bindings/sensor/lsm6dso.h>
15 accel-pm = <LSM6DSO_DT_XL_ULP_MODE>;
16 accel-range = <LSM6DSO_DT_FS_8G>;
17 accel-odr = <LSM6DSO_DT_ODR_1Hz6>;
18 gyro-pm = <LSM6DSO_DT_GY_NORMAL_MODE>;
19 gyro-range = <LSM6DSO_DT_FS_2000DPS>;
20 gyro-odr = <LSM6DSO_DT_ODR_6667Hz>;
[all …]
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| /Zephyr-latest/tests/drivers/pinctrl/gd32/src/ |
| D | main_af.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 12U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
[all …]
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| D | main_afio.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 14U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
[all …]
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| /Zephyr-latest/dts/bindings/can/ |
| D | microchip,mcp251xfd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
39 The interrupt signal from the controller is active low in push-pull mode.
[all …]
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| /Zephyr-latest/include/zephyr/drivers/pinctrl/ |
| D | pinctrl_rcar_common.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h>
17 uint8_t bank:5; /* bank number 0 - 18 */
18 uint8_t shift:5; /* bit shift 0 - 28 */
22 /** Pull-up, pull-down, or bias disable is requested */
26 /** Select pull-up resistor if set pull-down otherwise */
28 /** Alternate function for the pin is requested */
30 /** Ignore IPSR settings for alternate function pin */
37 /** Type for R-Car pin. */
39 uint16_t pin; member
[all …]
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| /Zephyr-latest/soc/xlnx/zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
118 #define MIO10 10
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
211 #define MIO_GROUP_SMC0_NOR_PINS 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, \
[all …]
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| /Zephyr-latest/dts/bindings/mspi/ |
| D | mspi-controller.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency:
15 "#address-cells":
18 "#size-cells":
22 op-mode:
25 - "MSPI_CONTROLLER"
26 - "MSPI_PERIPHERAL"
34 - "MSPI_HALF_DUPLEX"
35 - "MSPI_FULL_DUPLEX"
41 dqs-support:
[all …]
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
54 /* bit[8] output buffer type: push-pull or open-drain */
67 * bit[10] Alternate output disable. Default==0(alternate output enabled)
69 * Set bit[10]=1 if you wish to control pin output using the parallel
70 * GPIO output register bit for this pin.
72 #define MCHP_GPIO_CTRL_AOD_POS 10
80 /* bits[14:12] pin mux (function) */
106 /* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */
119 * Each GPIO pin implements a second control register.
120 * GPIO Control 2 register selects pin drive strength and slew rate.
[all …]
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