Lines Matching +full:10 +full:- +full:pin
4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
118 #define MIO10 10
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
211 #define MIO_GROUP_SMC0_NOR_PINS 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, \
216 #define MIO_GROUP_SMC0_NAND_PINS 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, \
218 #define MIO_GROUP_CAN0_0_GRP_PINS 10, 11
241 #define MIO_GROUP_UART0_0_GRP_PINS 10, 11
264 #define MIO_GROUP_I2C0_0_GRP_PINS 10, 11
307 #define MIO_GROUP_GPIO0_10_GRP_PINS 10
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t
379 /* Process each pin in group using MIO_GROUP_x_PINS macros defined above */
386 #define Z_PINCTRL_STATE_PIN_CHILD_GROUP_PIN_INIT(pin, node_id) \ argument
387 Z_PINCTRL_STATE_PIN_INIT(node_id, pin)
389 /* Process pin using MIOx macros defines above */
393 /* Process pin functions and special functions (CD, WP) */
394 #define Z_PINCTRL_STATE_PIN_INIT(node_id, pin) \ argument
396 (Z_PINCTRL_STATE_PIN_SPECIAL_INIT(node_id, pin)), \
397 (Z_PINCTRL_STATE_PIN_FUNCTION_INIT(node_id, pin)))
399 /* Determine if pin has special function */
405 /* Populate pinctrl_soc_pin_t for each special function pin */
406 #define Z_PINCTRL_STATE_PIN_SPECIAL_INIT(node_id, pin) \ argument
410 .val = pin << UTIL_CAT(MIO_PIN_SPECIAL_SHIFT_, \
416 /* Populate pinctrl_soc_pin_t for each pin */
417 #define Z_PINCTRL_STATE_PIN_FUNCTION_INIT(node_id, pin) \ argument
421 .offset = pin * sizeof(uint32_t), \