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/Zephyr-latest/boards/arm/v2m_musca_b1/
Dv2m_musca_b1-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 reg = <0x3000 0x1000>;
10 interrupts = <6 3>;
15 reg = <0x4000 0x1000>;
16 interrupts = <7 3>;
20 compatible = "arm,cmsdk-timer";
21 reg = <0x10c000 0x1000>;
22 interrupts = <3 3>;
27 reg = <0x105000 0x1000>;
28 interrupts = <39 3 40 3 41 3 43 3>;
[all …]
/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi2 * Copyright (c) 2019-2020 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
9 reg = <0x3000 0x1000>;
10 interrupts = <6 3>;
15 reg = <0x4000 0x1000>;
16 interrupts = <7 3>;
20 compatible = "arm,cmsdk-timer";
21 reg = <0x10b000 0x1000>;
22 interrupts = <33 3>;
27 reg = <0x101000 0x1000>;
[all …]
/Zephyr-latest/tests/net/lib/lwm2m/interop/pytest/
Dtest_lwm2m.py7 SPDX-License-Identifier: Apache-2.0
11 https://www.openmobilealliance.org/release/LightweightM2M/ETS/OMA-ETS-LightweightM2M-V1_1-20190912-…
15 * Registration Interface [100-199]
16 * Device management & Service Enablement Interface [200-299]
17 * Information Reporting Interface [300-399]
34 """LightweightM2M-1.1-int-102 - Registration Update"""
35 lines = shell.get_filtered_output(shell.exec_command('lwm2m read 1/0/1 -u32'))
36 lifetime = int(lines[0])
39 leshan.write(endpoint, '1/0/1', lifetime)
45 shell.exec_command('lwm2m write 1/0/1 -u32 86400')
[all …]
/Zephyr-latest/modules/hal_nordic/nrfx/
Dnrfx_config_nrf51.h2 * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
18 * Integer value. Minimum: 0 Maximum: 3
21 #define NRFX_DEFAULT_IRQ_PRIORITY 3
27 * Boolean. Accepted values 0 and 1.
30 #define NRFX_ADC_ENABLED 0
36 * Integer value. Minimum: 0 Maximum: 3
45 * Boolean. Accepted values 0 and 1.
48 #define NRFX_ADC_CONFIG_LOG_ENABLED 0
56 * - Off = 0
[all …]
/Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
24 #define BT_UUID_SERVICE_A BT_UUID_DECLARE_16(0xa00a)
29 #define BT_UUID_VALUE_V1 BT_UUID_DECLARE_16(0xb001)
34 #define BT_UUID_VALUE_V2 BT_UUID_DECLARE_16(0xb002)
39 #define BT_UUID_VALUE_V3 BT_UUID_DECLARE_16(0xb003)
41 static uint8_t value_v1_value = 0x01;
43 '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3',
44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4500_F100x1024-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
Dxmc4700_F144x2048-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
/Zephyr-latest/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/
Dmps2_an521-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 sysclk: system-clock {
8 compatible = "fixed-clock";
9 clock-frequency = <25000000>;
10 #clock-cells = <0>;
13 timer0: timer@0 {
14 compatible = "arm,cmsdk-timer";
15 reg = <0x0 0x1000>;
16 interrupts = <3 3>;
20 compatible = "arm,cmsdk-timer";
[all …]
/Zephyr-latest/boards/arm/mps2/
Dmps2_an521-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 sysclk: system-clock {
8 compatible = "fixed-clock";
9 clock-frequency = <25000000>;
10 #clock-cells = <0>;
13 timer0: timer@0 {
14 compatible = "arm,cmsdk-timer";
15 reg = <0x0 0x1000>;
16 interrupts = <3 3>;
20 compatible = "arm,cmsdk-timer";
[all …]
/Zephyr-latest/subsys/net/ip/
Dnet_tc_mapping.h10 * SPDX-License-Identifier: Apache-2.0
19 * according to 802.1Q - table I-2.
23 * 0 (default) BE Best effort
25 * 3 CA Critical applications
36 #if defined(CONFIG_NET_TC_MAPPING_STRICT) && (NET_TC_COUNT > 0)
39 * implementations that do not support the credit-based shaper transmission
41 * Ref: 802.1Q - chapter 8.6.6 - table 8-4
45 static const uint8_t priority2tc_strict_1[] = {0, 0, 0, 0, 0, 0, 0, 0};
48 static const uint8_t priority2tc_strict_2[] = {0, 0, 0, 0, 1, 1, 1, 1};
50 #if NET_TC_TX_COUNT == 3 || NET_TC_RX_COUNT == 3
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
12 /* MIWU table 0 */
14 wui_io80: wui0-1-0 {
15 miwus = <&miwu0 0 0>; /* GPIO80 */
17 wui_io81: wui0-1-1 {
18 miwus = <&miwu0 0 1>; /* GPIO81 */
20 wui_io82: wui0-1-2 {
21 miwus = <&miwu0 0 2>; /* GPIO82 */
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_peci.h4 * SPDX-License-Identifier: Apache-2.0
14 #define MCHP_PECI_WR_DATA_REG_OFS 0u
15 #define MCHP_PECI_WR_DATA_MASK 0xffu
19 #define MCHP_PECI_RD_DATA_MASK 0xffu
23 #define MCHP_PECI_CTRL_MASK 0xe9u
24 #define MCHP_PECI_CTRL_PD_POS 0
26 #define MCHP_PECI_CTRL_RST_POS 3
35 /* Status 1 register. RW1C and read-only bits. */
36 #define MCHP_PECI_STS1_REG_OFS 0x0cu
37 #define MCHP_PECI_STS1_MASK 0xbfu
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32g4_clock.h4 * SPDX-License-Identifier: Apache-2.0
12 #define STM32_CLOCK_BUS_AHB1 0x048
13 #define STM32_CLOCK_BUS_AHB2 0x04c
14 #define STM32_CLOCK_BUS_AHB3 0x050
15 #define STM32_CLOCK_BUS_APB1 0x058
16 #define STM32_CLOCK_BUS_APB1_2 0x05c
17 #define STM32_CLOCK_BUS_APB2 0x060
42 #define STM32_CLOCK_REG_MASK 0xFFU
43 #define STM32_CLOCK_REG_SHIFT 0U
44 #define STM32_CLOCK_SHIFT_MASK 0x1FU
[all …]
Dstm32u5_clock.h5 * SPDX-License-Identifier: Apache-2.0
43 #define STM32_CLOCK_BUS_AHB1 0x088
44 #define STM32_CLOCK_BUS_AHB2 0x08C
45 #define STM32_CLOCK_BUS_AHB2_2 0x090
46 #define STM32_CLOCK_BUS_AHB3 0x094
47 #define STM32_CLOCK_BUS_APB1 0x09C
48 #define STM32_CLOCK_BUS_APB1_2 0x0A0
49 #define STM32_CLOCK_BUS_APB2 0x0A4
50 #define STM32_CLOCK_BUS_APB3 0x0A8
55 #define STM32_CLOCK_REG_MASK 0xFFU
[all …]
Dstm32l4_clock.h4 * SPDX-License-Identifier: Apache-2.0
12 #define STM32_CLOCK_BUS_AHB1 0x048
13 #define STM32_CLOCK_BUS_AHB2 0x04c
14 #define STM32_CLOCK_BUS_AHB3 0x050
15 #define STM32_CLOCK_BUS_APB1 0x058
16 #define STM32_CLOCK_BUS_APB1_2 0x05c
17 #define STM32_CLOCK_BUS_APB2 0x060
40 #define STM32_CLOCK_REG_MASK 0xFFU
41 #define STM32_CLOCK_REG_SHIFT 0U
42 #define STM32_CLOCK_SHIFT_MASK 0x1FU
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dch32v003-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #define CH32V003_PINMUX_PORT_PA 0
18 #define CH32V003_PINMUX_SPI1_RM 0
27 /* Port number with 0-2 */
28 #define CH32V003_PINCTRL_PORT_SHIFT 0
29 /* Pin number 0-15 */
31 /* Base remap bit 0-31 */
33 /* Function remapping ID 0-3 */
42 #define TIM1_ETR_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 0)
45 #define TIM1_ETR_PC2_3 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 3)
[all …]
/Zephyr-latest/boards/arm/mps3/
Dmps3_common_soc_peripheral.dtsi2 * Copyright (c) 2019-2021 Linaro Limited
3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 * SPDX-License-Identifier: Apache-2.0
8 sysclk: system-clock {
9 compatible = "fixed-clock";
10 clock-frequency = <25000000>;
11 #clock-cells = <0>;
15 compatible = "arm,cmsdk-gpio";
16 reg = <0x1100000 0x1000>;
17 interrupts = <69 3>;
[all …]
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
21 zephyr,flash-controller = &flash;
22 zephyr,bt-hci = &esp32_bt_hci;
[all …]
/Zephyr-latest/soc/ene/kb1200/reg/
Dgpio.h4 * SPDX-License-Identifier: Apache-2.0
15 volatile uint32_t Reserved1[3];
17 volatile uint32_t Reserved2[3];
19 volatile uint32_t Reserved3[3];
21 volatile uint32_t Reserved4[3];
23 volatile uint32_t Reserved5[3];
25 volatile uint32_t Reserved6[3];
27 volatile uint32_t Reserved7[3];
29 volatile uint32_t Reserved8[3];
31 volatile uint32_t Reserved9[3];
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 reg = <0x4000fc00 0x200>;
11 compatible = "microchip,xec-pcr";
12 reg = <0x40080100 0x100 0x4000a400 0x100>;
13 reg-names = "pcrr", "vbatr";
14 interrupts = <174 0>;
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
[all …]
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_r8a77951.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
13 { 0x0300, {
21 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
24 { 0x0304, {
32 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
35 { 0x0308, {
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
[all …]
Dpfc_r8a77961.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
13 { 0x0300, {
21 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
24 { 0x0304, {
32 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
35 { 0x0308, {
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
[all …]
Dpfc_r8a779f0.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
14 { 0x80, {
15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
16 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
17 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
18 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
19 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
20 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
21 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6_cm0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
12 cpu@0 {
13 compatible = "arm,cortex-m0+";
16 /delete-node/ cpu@1;
21 /* see cypress,psoc6-int-mux.yaml */
22 compatible = "cypress,psoc6-intmux";
23 reg = <0x40210020 0x20>;
24 ranges = <0x0 0x40210020 0x20>;
26 #address-cells = <1>;
[all …]
/Zephyr-latest/samples/subsys/zbus/msg_subscriber/src/
Dmain.c3 * SPDX-License-Identifier: Apache-2.0
24 total_allocated -= bytes; in on_heap_free()
51 ZBUS_MSG_INIT(.x = 0, .y = 0, .z = 0) /* Initial value */
58 LOG_INF("From listener foo_lis -> Acc x=%d, y=%d, z=%d", acc->x, acc->y, acc->z); in listener_callback_example()
97 LOG_INF("From msg subscriber %s -> Acc x=%d, y=%d, z=%d", zbus_obs_name(subscriber), in msg_subscriber_task()
103 NULL, NULL, 3, 0, 0);
105 NULL, NULL, 3, 0, 0);
107 NULL, NULL, 3, 0, 0);
109 NULL, NULL, 3, 0, 0);
111 NULL, NULL, 3, 0, 0);
[all …]

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