Lines Matching +full:0 +full:- +full:3
5 * SPDX-License-Identifier: Apache-2.0
43 #define STM32_CLOCK_BUS_AHB1 0x088
44 #define STM32_CLOCK_BUS_AHB2 0x08C
45 #define STM32_CLOCK_BUS_AHB2_2 0x090
46 #define STM32_CLOCK_BUS_AHB3 0x094
47 #define STM32_CLOCK_BUS_APB1 0x09C
48 #define STM32_CLOCK_BUS_APB1_2 0x0A0
49 #define STM32_CLOCK_BUS_APB2 0x0A4
50 #define STM32_CLOCK_BUS_APB3 0x0A8
55 #define STM32_CLOCK_REG_MASK 0xFFU
56 #define STM32_CLOCK_REG_SHIFT 0U
57 #define STM32_CLOCK_SHIFT_MASK 0x1FU
59 #define STM32_CLOCK_MASK_MASK 0x7U
61 #define STM32_CLOCK_VAL_MASK 0x7U
67 * - reg (1/2/3) [ 0 : 7 ]
68 * - shift (0..31) [ 8 : 12 ]
69 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
70 * - val (0..7) [ 16 : 18 ]
75 * @param val Clock value (0, 1, ... 7).
84 #define CCIPR1_REG 0xE0
85 #define CCIPR2_REG 0xE4
86 #define CCIPR3_REG 0xE8
89 #define BDCR_REG 0xF0
92 #define CFGR1_REG 0x1C
96 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
97 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
98 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG)
99 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG)
100 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG)
101 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
102 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG)
103 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG)
104 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG)
105 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)
106 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)
107 #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)
108 #define FDCAN1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR1_REG)
109 #define ICKLK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR1_REG)
112 #define MDF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG)
116 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
121 #define OCTOSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
122 #define HSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG)
123 #define I2C5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG)
124 #define I2C6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG)
125 #define OTGHS_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)
127 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)
128 #define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)
129 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG)
130 #define LPTIM34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR3_REG)
131 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG)
136 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
139 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
140 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
143 #define MCO_PRE_DIV_1 0
146 #define MCO_PRE_DIV_8 3