Lines Matching +full:0 +full:- +full:3
2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
13 { 0x0300, {
21 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
24 { 0x0304, {
32 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
35 { 0x0308, {
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
38 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
39 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
42 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
43 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
46 { 0x030c, {
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
48 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
49 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
50 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
51 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
52 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
53 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
54 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
57 { 0x0310, {
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
59 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
60 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
61 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
62 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
63 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
64 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
65 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
68 { 0x0314, {
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
71 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
72 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
73 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
74 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
75 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
76 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
79 { 0x0318, {
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
81 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
82 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
83 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
84 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
85 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
86 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
87 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
90 { 0x031c, {
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
92 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
93 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
94 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
95 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
96 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
97 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
98 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
101 { 0x0320, {
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
103 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
104 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
105 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
106 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
107 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
108 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
109 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
112 { 0x0324, {
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
114 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
115 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
116 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
117 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
118 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
119 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
120 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
123 { 0x0328, {
124 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
125 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
126 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
127 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
128 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
129 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
130 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
131 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
134 { 0x032c, {
135 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
136 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
137 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
138 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
139 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
140 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
142 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
145 { 0x0330, {
152 { 0x0334, {
155 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
156 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
157 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
158 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
159 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
160 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
163 { 0x0338, {
164 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
165 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
166 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
167 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
168 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
169 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
170 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
171 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
174 { 0x033c, {
175 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
176 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
177 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
178 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
179 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
180 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
181 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
182 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
185 { 0x0340, {
186 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
187 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
188 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
189 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
190 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
191 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
192 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
193 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
196 { 0x0344, {
197 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
198 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
199 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
200 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
201 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
202 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
203 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
204 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
207 { 0x0348, {
208 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
209 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
210 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
211 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
212 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
213 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
214 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
215 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
218 { 0x034c, {
219 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
220 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
221 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
222 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
223 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
224 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
225 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
226 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
229 { 0x0350, {
230 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
231 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
232 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
233 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
234 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
235 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
236 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
237 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
240 { 0x0354, {
241 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
242 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
243 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
244 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
245 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
246 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
247 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
248 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
251 { 0x0358, {
252 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
253 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
254 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
255 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
256 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
257 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
258 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
259 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
262 { 0x035c, {
263 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
264 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
265 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
266 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
267 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
268 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
269 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
270 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
273 { 0x0360, {
274 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
275 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
276 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
277 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
278 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
279 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
280 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
291 { PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */
292 [0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
295 [3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
325 { PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */
326 [0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
329 [3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
332 [6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
338 [12] = RCAR_GP_PIN(1, 0), /* A0 */
341 [15] = RCAR_GP_PIN(1, 3), /* A3 */
359 { PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */
360 [0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
363 [3] = RCAR_GP_PIN(1, 22), /* BS_N */
370 [10] = RCAR_GP_PIN(0, 0), /* D0 */
371 [11] = RCAR_GP_PIN(0, 1), /* D1 */
372 [12] = RCAR_GP_PIN(0, 2), /* D2 */
373 [13] = RCAR_GP_PIN(0, 3), /* D3 */
374 [14] = RCAR_GP_PIN(0, 4), /* D4 */
375 [15] = RCAR_GP_PIN(0, 5), /* D5 */
376 [16] = RCAR_GP_PIN(0, 6), /* D6 */
377 [17] = RCAR_GP_PIN(0, 7), /* D7 */
378 [18] = RCAR_GP_PIN(0, 8), /* D8 */
379 [19] = RCAR_GP_PIN(0, 9), /* D9 */
380 [20] = RCAR_GP_PIN(0, 10), /* D10 */
381 [21] = RCAR_GP_PIN(0, 11), /* D11 */
382 [22] = RCAR_GP_PIN(0, 12), /* D12 */
383 [23] = RCAR_GP_PIN(0, 13), /* D13 */
384 [24] = RCAR_GP_PIN(0, 14), /* D14 */
385 [25] = RCAR_GP_PIN(0, 15), /* D15 */
386 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
389 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
393 { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */
394 [0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
397 [3] = PIN_EXTALR, /* EXTALR*/
404 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
405 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
406 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
407 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
408 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
409 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
410 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
411 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
412 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
413 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
414 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
415 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
416 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
419 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
427 { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */
428 [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
431 [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
436 [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
437 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
438 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
439 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
440 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
443 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
461 { PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */
462 [0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
465 [3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
469 [7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
472 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
495 { PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */
496 [0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
499 [3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
543 /* There is only one register on Gen 3 */ in pfc_rcar_get_reg_index()
544 *reg_index = 0; in pfc_rcar_get_reg_index()
545 return 0; in pfc_rcar_get_reg_index()