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4  * SPDX-License-Identifier: Apache-2.0
14 #define MCHP_PECI_WR_DATA_REG_OFS	0u
15 #define MCHP_PECI_WR_DATA_MASK		0xffu
19 #define MCHP_PECI_RD_DATA_MASK		0xffu
23 #define MCHP_PECI_CTRL_MASK		0xe9u
24 #define MCHP_PECI_CTRL_PD_POS		0
26 #define MCHP_PECI_CTRL_RST_POS		3
35 /* Status 1 register. RW1C and read-only bits. */
36 #define MCHP_PECI_STS1_REG_OFS		0x0cu
37 #define MCHP_PECI_STS1_MASK		0xbfu
38 #define MCHP_PECI_STS1_BOF_POS		0
42 /* Error is read-only */
45 /* Ready is read-only */
46 #define MCHP_PECI_STS1_RDY_POS		3
52 /* MINT is read-only */
56 /* Status 2 register. Read-only bits. */
57 #define MCHP_PECI_STS2_REG_OFS		0x10u
58 #define MCHP_PECI_STS2_MASK		0x8fu
59 #define MCHP_PECI_STS2_WFF_POS		0
65 #define MCHP_PECI_STS2_RFE_POS		3
71 #define MCHP_PECI_ERR_REG_OFS		0x14u
72 #define MCHP_PECI_ERR_MASK		0xf3u
73 #define MCHP_PECI_ERR_FERR_POS		0
87 #define MCHP_PECI_IEN1_REG_OFS		0x18u
88 #define MCHP_PECI_IEN1_MASK		0x37u
89 #define MCHP_PECI_IEN1_BIEN_POS		0
101 #define MCHP_PECI_IEN2_REG_OFS		0x1cu
102 #define MCHP_PECI_IEN2_MASK		0x06u
109 #define MCHP_PECI_OPT_BT_LSB_REG_OFS	0x20u
110 #define MCHP_PECI_OPT_BT_LSB_MASK	0xffu
113 #define MCHP_PECI_OPT_BT_MSB_REG_OFS	0x24u
114 #define MCHP_PECI_OPT_BT_MSB_MASK	0xffu
116 /** @brief PECI controller. Size = 76(0x4c) */
119 	uint8_t RSVD1[3];
121 	uint8_t RSVD2[3];
123 	uint8_t RSVD3[3];
125 	uint8_t RSVD4[3];
127 	uint8_t RSVD5[3];
129 	uint8_t RSVD6[3];
131 	uint8_t RSVD7[3];
133 	uint8_t RSVD8[3];
135 	uint8_t RSVD9[3];
137 	uint8_t RSVD10[3];
139 	uint8_t RSVD11[3];
141 	uint8_t RSVD12[3];
143 	uint8_t RSVD13[3];
144 	uint32_t RSVD14[3];
146 	uint8_t RSVD15[3];
148 	uint8_t RSVD16[3];
150 	uint8_t RSVD17[3];