Lines Matching +full:0 +full:- +full:3
4 * SPDX-License-Identifier: Apache-2.0
12 #define STM32_CLOCK_BUS_AHB1 0x048
13 #define STM32_CLOCK_BUS_AHB2 0x04c
14 #define STM32_CLOCK_BUS_AHB3 0x050
15 #define STM32_CLOCK_BUS_APB1 0x058
16 #define STM32_CLOCK_BUS_APB1_2 0x05c
17 #define STM32_CLOCK_BUS_APB2 0x060
42 #define STM32_CLOCK_REG_MASK 0xFFU
43 #define STM32_CLOCK_REG_SHIFT 0U
44 #define STM32_CLOCK_SHIFT_MASK 0x1FU
46 #define STM32_CLOCK_MASK_MASK 0x7U
48 #define STM32_CLOCK_VAL_MASK 0x7U
54 * - reg (1/2/3) [ 0 : 7 ]
55 * - shift (0..31) [ 8 : 12 ]
56 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
57 * - val (0..7) [ 16 : 18 ]
62 * @param val Clock value (0, 1, ... 7).
71 #define CCIPR_REG 0x88
72 #define CCIPR2_REG 0x9C
75 #define BDCR_REG 0x90
79 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
80 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
81 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
82 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
83 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
84 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
85 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
86 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
87 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
88 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
89 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
90 #define I2S23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
91 #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG)
92 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
93 #define ADC12_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
94 #define ADC34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
96 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
97 #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
99 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)