1 /*
2 * Copyright (c) 2023 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #include <errno.h>
9 #include <pinctrl_soc.h>
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
11
12 const struct pfc_drive_reg pfc_drive_regs[] = {
13 /* DRV0CTRL0 */
14 { 0x80, {
15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
16 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
17 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
18 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
19 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
20 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
21 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
22 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
23 } },
24 /* DRV1CTRL0 */
25 { 0x84, {
26 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
27 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
28 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
29 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
30 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
31 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
32 { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
33 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
34 } },
35 /* DRV2CTRL0 */
36 { 0x88, {
37 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
38 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
39 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
40 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
41 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
42 } },
43 /* DRV3CTRL0 is empty */
44 /* DRV0CTRL1 */
45 { 0x80, {
46 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
47 { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
48 { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
49 { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
50 { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
51 { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
52 { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
53 { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
54 } },
55 /* DRV1CTRL1 */
56 { 0x84, {
57 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
58 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
59 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
60 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
61 { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
62 { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
63 { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
64 { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
65 } },
66 /* DRV2CTRL1 */
67 { 0x88, {
68 { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
69 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
70 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
71 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
72 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
73 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
74 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
75 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
76 } },
77 /* DRV3CTRL1 */
78 { 0x8c, {
79 { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
80 } },
81 /* DRV0CTRL2 */
82 { 0x80, {
83 { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
84 { RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */
85 { RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */
86 { RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */
87 { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
88 { RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */
89 { RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */
90 { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
91 } },
92 /* DRV1CTRL2 */
93 { 0x84, {
94 { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
95 { RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */
96 { RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */
97 { RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */
98 { RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */
99 { RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */
100 { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
101 { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
102 } },
103 /* DRV2CTRL2 */
104 { 0x88, {
105 { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
106 } },
107 /* DRV3CTRL2 is empty */
108 /* DRV0CTRL3 */
109 { 0x80, {
110 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
111 { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
112 { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
113 { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
114 { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
115 { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
116 { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
117 { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
118 } },
119 /* DRV1CTRL3 */
120 { 0x84, {
121 { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
122 { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
123 { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
124 { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
125 { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
126 { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
127 { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
128 { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
129 } },
130 /* DRV2CTRL3 */
131 { 0x88, {
132 { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
133 { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
134 { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
135 } },
136 /* DRV3CTRL3 is empty */
137 /* DRV0CTRL4 */
138 { 0x80, {
139 { RCAR_GP_PIN(4, 7), 28, 3 }, /* GP4_07 */
140 { RCAR_GP_PIN(4, 6), 24, 3 }, /* GP4_06 */
141 { RCAR_GP_PIN(4, 5), 20, 3 }, /* GP4_05 */
142 { RCAR_GP_PIN(4, 4), 16, 3 }, /* GP4_04 */
143 { RCAR_GP_PIN(4, 3), 12, 3 }, /* GP4_03 */
144 { RCAR_GP_PIN(4, 2), 8, 3 }, /* GP4_02 */
145 { RCAR_GP_PIN(4, 1), 4, 3 }, /* GP4_01 */
146 { RCAR_GP_PIN(4, 0), 0, 3 }, /* GP4_00 */
147 } },
148 /* DRV1CTRL4 */
149 { 0x84, {
150 { RCAR_GP_PIN(4, 15), 28, 3 }, /* GP4_15 */
151 { RCAR_GP_PIN(4, 14), 24, 3 }, /* GP4_14 */
152 { RCAR_GP_PIN(4, 13), 20, 3 }, /* GP4_13 */
153 { RCAR_GP_PIN(4, 12), 16, 3 }, /* GP4_12 */
154 { RCAR_GP_PIN(4, 11), 12, 3 }, /* GP4_11 */
155 { RCAR_GP_PIN(4, 10), 8, 3 }, /* GP4_10 */
156 { RCAR_GP_PIN(4, 9), 4, 3 }, /* GP4_09 */
157 { RCAR_GP_PIN(4, 8), 0, 3 }, /* GP4_08 */
158 } },
159 /* DRV2CTRL4 */
160 { 0x88, {
161 { RCAR_GP_PIN(4, 23), 28, 3 }, /* MSPI0CSS1 */
162 { RCAR_GP_PIN(4, 22), 24, 3 }, /* MPSI0SO/MSPI0DCS */
163 { RCAR_GP_PIN(4, 21), 20, 3 }, /* MPSI0SI */
164 { RCAR_GP_PIN(4, 20), 16, 3 }, /* MSPI0SC */
165 { RCAR_GP_PIN(4, 19), 12, 3 }, /* GP4_19 */
166 { RCAR_GP_PIN(4, 18), 8, 3 }, /* GP4_18 */
167 { RCAR_GP_PIN(4, 17), 4, 3 }, /* GP4_17 */
168 { RCAR_GP_PIN(4, 16), 0, 3 }, /* GP4_16 */
169 } },
170 /* DRV3CTRL4 */
171 { 0x8c, {
172 { RCAR_GP_PIN(4, 30), 24, 3 }, /* MSPI1CSS1 */
173 { RCAR_GP_PIN(4, 29), 20, 3 }, /* MSPI1CSS2 */
174 { RCAR_GP_PIN(4, 28), 16, 3 }, /* MSPI1SC */
175 { RCAR_GP_PIN(4, 27), 12, 3 }, /* MSPI1CSS0 */
176 { RCAR_GP_PIN(4, 26), 8, 3 }, /* MPSI1SO/MSPI1DCS */
177 { RCAR_GP_PIN(4, 25), 4, 3 }, /* MSPI1SI */
178 { RCAR_GP_PIN(4, 24), 0, 3 }, /* MSPI0CSS0 */
179 } },
180 /* DRV0CTRL5 */
181 { 0x80, {
182 { RCAR_GP_PIN(5, 7), 28, 3 }, /* ETNB0RXD3 */
183 { RCAR_GP_PIN(5, 6), 24, 3 }, /* ETNB0RXER */
184 { RCAR_GP_PIN(5, 5), 20, 3 }, /* ETNB0MDC */
185 { RCAR_GP_PIN(5, 4), 16, 3 }, /* ETNB0LINKSTA */
186 { RCAR_GP_PIN(5, 3), 12, 3 }, /* ETNB0WOL */
187 { RCAR_GP_PIN(5, 2), 8, 3 }, /* ETNB0MD */
188 { RCAR_GP_PIN(5, 1), 4, 3 }, /* RIIC0SDA */
189 { RCAR_GP_PIN(5, 0), 0, 3 }, /* RIIC0SCL */
190 } },
191 /* DRV1CTRL5 */
192 { 0x84, {
193 { RCAR_GP_PIN(5, 15), 28, 3 }, /* ETNB0TXCLK */
194 { RCAR_GP_PIN(5, 14), 24, 3 }, /* ETNB0TXD3 */
195 { RCAR_GP_PIN(5, 13), 20, 3 }, /* ETNB0TXER */
196 { RCAR_GP_PIN(5, 12), 16, 3 }, /* ETNB0RXCLK */
197 { RCAR_GP_PIN(5, 11), 12, 3 }, /* ETNB0RXD0 */
198 { RCAR_GP_PIN(5, 10), 8, 3 }, /* ETNB0RXDV */
199 { RCAR_GP_PIN(5, 9), 4, 3 }, /* ETNB0RXD2 */
200 { RCAR_GP_PIN(5, 8), 0, 3 }, /* ETNB0RXD1 */
201 } },
202 /* DRV2CTRL5 */
203 { 0x88, {
204 { RCAR_GP_PIN(5, 19), 12, 3 }, /* ETNB0TXD0 */
205 { RCAR_GP_PIN(5, 18), 8, 3 }, /* ETNB0TXEN */
206 { RCAR_GP_PIN(5, 17), 4, 3 }, /* ETNB0TXD2 */
207 { RCAR_GP_PIN(5, 16), 0, 3 }, /* ETNB0TXD1 */
208 } },
209 /* DRV3CTRL5 is empty */
210 /* DRV0CTRL6 */
211 { 0x80, {
212 { RCAR_GP_PIN(6, 7), 28, 3 }, /* RLIN34RX/INTP20 */
213 { RCAR_GP_PIN(6, 6), 24, 3 }, /* RLIN34TX */
214 { RCAR_GP_PIN(6, 5), 20, 3 }, /* RLIN35RX/INTP21 */
215 { RCAR_GP_PIN(6, 4), 16, 3 }, /* RLIN35TX */
216 { RCAR_GP_PIN(6, 3), 12, 3 }, /* RLIN36RX/INTP22 */
217 { RCAR_GP_PIN(6, 2), 8, 3 }, /* RLIN36TX */
218 { RCAR_GP_PIN(6, 1), 4, 3 }, /* RLIN37RX/INTP23 */
219 { RCAR_GP_PIN(6, 0), 0, 3 }, /* RLIN37TX */
220 } },
221 /* DRV1CTRL6 */
222 { 0x84, {
223 { RCAR_GP_PIN(6, 15), 28, 3 }, /* RLIN30RX/INTP16 */
224 { RCAR_GP_PIN(6, 14), 24, 3 }, /* RLIN30TX */
225 { RCAR_GP_PIN(6, 13), 20, 3 }, /* RLIN31RX/INTP17 */
226 { RCAR_GP_PIN(6, 12), 16, 3 }, /* RLIN31TX */
227 { RCAR_GP_PIN(6, 11), 12, 3 }, /* RLIN32RX/INTP18 */
228 { RCAR_GP_PIN(6, 10), 8, 3 }, /* RLIN32TX */
229 { RCAR_GP_PIN(6, 9), 4, 3 }, /* RLIN33RX/INTP19 */
230 { RCAR_GP_PIN(6, 8), 0, 3 }, /* RLIN33TX */
231 } },
232 /* DRV2CTRL6 */
233 { 0x88, {
234 { RCAR_GP_PIN(6, 22), 24, 3 }, /* NMI1 */
235 { RCAR_GP_PIN(6, 21), 20, 3 }, /* INTP32 */
236 { RCAR_GP_PIN(6, 20), 16, 3 }, /* INTP33 */
237 { RCAR_GP_PIN(6, 19), 12, 3 }, /* INTP34 */
238 { RCAR_GP_PIN(6, 18), 8, 3 }, /* INTP35 */
239 { RCAR_GP_PIN(6, 17), 4, 3 }, /* INTP36 */
240 { RCAR_GP_PIN(6, 16), 0, 3 }, /* INTP37 */
241 } },
242 /* DRV3CTRL6 */
243 { 0x8c, {
244 { RCAR_GP_PIN(6, 31), 28, 3 }, /* PRESETOUT1# */
245 } },
246 /* DRV0CTRL7 */
247 { 0x80, {
248 { RCAR_GP_PIN(7, 7), 28, 3 }, /* CAN3RX/INTP3 */
249 { RCAR_GP_PIN(7, 6), 24, 3 }, /* CAN3TX */
250 { RCAR_GP_PIN(7, 5), 20, 3 }, /* CAN2RX/INTP2 */
251 { RCAR_GP_PIN(7, 4), 16, 3 }, /* CAN2TX */
252 { RCAR_GP_PIN(7, 3), 12, 3 }, /* CAN1RX/INTP1 */
253 { RCAR_GP_PIN(7, 2), 8, 3 }, /* CAN1TX */
254 { RCAR_GP_PIN(7, 1), 4, 3 }, /* CAN0RX/INTP0 */
255 { RCAR_GP_PIN(7, 0), 0, 3 }, /* CAN0TX */
256 } },
257 /* DRV1CTRL7 */
258 { 0x84, {
259 { RCAR_GP_PIN(7, 15), 28, 3 }, /* CAN7RX/INTP7 */
260 { RCAR_GP_PIN(7, 14), 24, 3 }, /* CAN7TX */
261 { RCAR_GP_PIN(7, 13), 20, 3 }, /* CAN6RX/INTP6 */
262 { RCAR_GP_PIN(7, 12), 16, 3 }, /* CAN6TX */
263 { RCAR_GP_PIN(7, 11), 12, 3 }, /* CAN5RX/INTP5 */
264 { RCAR_GP_PIN(7, 10), 8, 3 }, /* CAN5TX */
265 { RCAR_GP_PIN(7, 9), 4, 3 }, /* CAN4RX/INTP4 */
266 { RCAR_GP_PIN(7, 8), 0, 3 }, /* CAN4TX */
267 } },
268 /* DRV2CTRL7 */
269 { 0x88, {
270 { RCAR_GP_PIN(7, 23), 28, 3 }, /* CAN11RX/INTP11 */
271 { RCAR_GP_PIN(7, 22), 24, 3 }, /* CAN11TX */
272 { RCAR_GP_PIN(7, 21), 20, 3 }, /* CAN10RX/INTP10 */
273 { RCAR_GP_PIN(7, 20), 16, 3 }, /* CAN10TX */
274 { RCAR_GP_PIN(7, 19), 12, 3 }, /* CAN9RX/INTP9 */
275 { RCAR_GP_PIN(7, 18), 8, 3 }, /* CAN9TX */
276 { RCAR_GP_PIN(7, 17), 4, 3 }, /* CAN8RX/INTP8 */
277 { RCAR_GP_PIN(7, 16), 0, 3 }, /* CAN8TX */
278 } },
279 /* DRV3CTRL7 */
280 { 0x8c, {
281 { RCAR_GP_PIN(7, 31), 28, 3 }, /* CAN15RX/INTP15 */
282 { RCAR_GP_PIN(7, 30), 24, 3 }, /* CAN15TX */
283 { RCAR_GP_PIN(7, 29), 20, 3 }, /* CAN14RX/INTP14 */
284 { RCAR_GP_PIN(7, 28), 16, 3 }, /* CAN14TX */
285 { RCAR_GP_PIN(7, 27), 12, 3 }, /* CAN13RX/INTP13 */
286 { RCAR_GP_PIN(7, 26), 8, 3 }, /* CAN13TX */
287 { RCAR_GP_PIN(7, 25), 4, 3 }, /* CAN12RX/INTP12 */
288 { RCAR_GP_PIN(7, 24), 0, 3 }, /* CAN12TX */
289 } },
290 /* DRV0CTRLSYS0 */
291 { 0x80, {
292 { RCAR_GP_PIN(8, 0), 0, 3 }, /* PRESETOUT0# */
293 } },
294 /* DRV1CTRLSYS0 */
295 { 0x84, {
296 { RCAR_GP_PIN(8, 12), 16, 2 }, /* DCUTCK0 */
297 { RCAR_GP_PIN(8, 11), 12, 2 }, /* DCUTDO0 */
298 { RCAR_GP_PIN(8, 10), 8, 2 }, /* DCUTDI0 */
299 { RCAR_GP_PIN(8, 9), 4, 2 }, /* DCUTDY0# */
300 { RCAR_GP_PIN(8, 8), 0, 2 }, /* DCUTMS0 */
301 } },
302 { },
303 };
304
305 #define PFC_BIAS_REG(r1, r2) \
306 .puen = r1, \
307 .pud = r2, \
308 .pins =
309
310 const struct pfc_bias_reg pfc_bias_regs[] = {
311 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN0, PUD0 */
312 [0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
313 [1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
314 [2] = RCAR_GP_PIN(0, 2), /* HRX0 */
315 [3] = RCAR_GP_PIN(0, 3), /* HTX0 */
316 [4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
317 [5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
318 [6] = RCAR_GP_PIN(0, 6), /* RX0 */
319 [7] = RCAR_GP_PIN(0, 7), /* TX0 */
320 [8] = RCAR_GP_PIN(0, 8), /* SCK0 */
321 [9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
322 [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
323 [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
324 [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
325 [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
326 [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
327 [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
328 [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
329 [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
330 [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
331 [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
332 [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
333 [21] = PIN_NONE,
334 [22] = PIN_NONE,
335 [23] = PIN_NONE,
336 [24] = PIN_NONE,
337 [25] = PIN_NONE,
338 [26] = PIN_NONE,
339 [27] = PIN_NONE,
340 [28] = PIN_NONE,
341 [29] = PIN_NONE,
342 [30] = PIN_NONE,
343 [31] = PIN_NONE,
344 } },
345 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN1, PUD1 */
346 [0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
347 [1] = RCAR_GP_PIN(1, 1), /* GP1_01 */
348 [2] = RCAR_GP_PIN(1, 2), /* GP1_02 */
349 [3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
350 [4] = RCAR_GP_PIN(1, 4), /* GP1_04 */
351 [5] = RCAR_GP_PIN(1, 5), /* GP1_05 */
352 [6] = RCAR_GP_PIN(1, 6), /* GP1_06 */
353 [7] = RCAR_GP_PIN(1, 7), /* GP1_07 */
354 [8] = RCAR_GP_PIN(1, 8), /* GP1_08 */
355 [9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
356 [10] = RCAR_GP_PIN(1, 10), /* GP1_10 */
357 [11] = RCAR_GP_PIN(1, 11), /* GP1_11 */
358 [12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */
359 [13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */
360 [14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */
361 [15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */
362 [16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */
363 [17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */
364 [18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */
365 [19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */
366 [20] = RCAR_GP_PIN(1, 20), /* MMC_DS */
367 [21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */
368 [22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */
369 [23] = RCAR_GP_PIN(1, 23), /* SD_CD */
370 [24] = RCAR_GP_PIN(1, 24), /* SD_WP */
371 [25] = PIN_NONE,
372 [26] = PIN_NONE,
373 [27] = PIN_NONE,
374 [28] = PIN_NONE,
375 [29] = PIN_NONE,
376 [30] = PIN_NONE,
377 [31] = PIN_NONE,
378 } },
379 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN2, PUD2 */
380 [0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
381 [1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */
382 [2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */
383 [3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
384 [4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */
385 [5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */
386 [6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */
387 [7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */
388 [8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */
389 [9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
390 [10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */
391 [11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */
392 [12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */
393 [13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */
394 [14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */
395 [15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */
396 [16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */
397 [17] = PIN_NONE,
398 [18] = PIN_NONE,
399 [19] = PIN_NONE,
400 [20] = PIN_NONE,
401 [21] = PIN_NONE,
402 [22] = PIN_NONE,
403 [23] = PIN_NONE,
404 [24] = PIN_NONE,
405 [25] = PIN_NONE,
406 [26] = PIN_NONE,
407 [27] = PIN_NONE,
408 [28] = PIN_NONE,
409 [29] = PIN_NONE,
410 [30] = PIN_NONE,
411 [31] = PIN_NONE,
412 } },
413 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN3, PUD3 */
414 [0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
415 [1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
416 [2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
417 [3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
418 [4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
419 [5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
420 [6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
421 [7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
422 [8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
423 [9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
424 [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
425 [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
426 [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
427 [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
428 [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
429 [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
430 [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
431 [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
432 [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */
433 [19] = PIN_NONE,
434 [20] = PIN_NONE,
435 [21] = PIN_NONE,
436 [22] = PIN_NONE,
437 [23] = PIN_NONE,
438 [24] = PIN_NONE,
439 [25] = PIN_NONE,
440 [26] = PIN_NONE,
441 [27] = PIN_NONE,
442 [28] = PIN_NONE,
443 [29] = PIN_NONE,
444 [30] = PIN_NONE,
445 [31] = PIN_NONE,
446 } },
447 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN4, PUD4 */
448 [0] = RCAR_GP_PIN(4, 0), /* GP4_00 */
449 [1] = RCAR_GP_PIN(4, 1), /* GP4_01 */
450 [2] = RCAR_GP_PIN(4, 2), /* GP4_02 */
451 [3] = RCAR_GP_PIN(4, 3), /* GP4_03 */
452 [4] = RCAR_GP_PIN(4, 4), /* GP4_04 */
453 [5] = RCAR_GP_PIN(4, 5), /* GP4_05 */
454 [6] = RCAR_GP_PIN(4, 6), /* GP4_06 */
455 [7] = RCAR_GP_PIN(4, 7), /* GP4_07 */
456 [8] = RCAR_GP_PIN(4, 8), /* GP4_08 */
457 [9] = RCAR_GP_PIN(4, 9), /* GP4_09 */
458 [10] = RCAR_GP_PIN(4, 10), /* GP4_10 */
459 [11] = RCAR_GP_PIN(4, 11), /* GP4_11 */
460 [12] = RCAR_GP_PIN(4, 12), /* GP4_12 */
461 [13] = RCAR_GP_PIN(4, 13), /* GP4_13 */
462 [14] = RCAR_GP_PIN(4, 14), /* GP4_14 */
463 [15] = RCAR_GP_PIN(4, 15), /* GP4_15 */
464 [16] = RCAR_GP_PIN(4, 16), /* GP4_16 */
465 [17] = RCAR_GP_PIN(4, 17), /* GP4_17 */
466 [18] = RCAR_GP_PIN(4, 18), /* GP4_18 */
467 [19] = RCAR_GP_PIN(4, 19), /* GP4_19 */
468 [20] = RCAR_GP_PIN(4, 20), /* MSPI0SC */
469 [21] = RCAR_GP_PIN(4, 21), /* MSPI0SI */
470 [22] = RCAR_GP_PIN(4, 22), /* MSPI0SO/MSPI0DCS */
471 [23] = RCAR_GP_PIN(4, 23), /* MSPI0CSS1 */
472 [24] = RCAR_GP_PIN(4, 24), /* MSPI0CSS0 */
473 [25] = RCAR_GP_PIN(4, 25), /* MSPI1SI */
474 [26] = RCAR_GP_PIN(4, 26), /* MSPI1SO/MSPI1DCS */
475 [27] = RCAR_GP_PIN(4, 27), /* MSPI1CSS0 */
476 [28] = RCAR_GP_PIN(4, 28), /* MSPI1SC */
477 [29] = RCAR_GP_PIN(4, 29), /* MSPI1CSS2 */
478 [30] = RCAR_GP_PIN(4, 30), /* MSPI1CSS1 */
479 [31] = PIN_NONE,
480 } },
481 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN5, PUD5 */
482 [0] = RCAR_GP_PIN(5, 0), /* RIIC0SCL */
483 [1] = RCAR_GP_PIN(5, 1), /* RIIC0SDA */
484 [2] = RCAR_GP_PIN(5, 2), /* ETNB0MD */
485 [3] = RCAR_GP_PIN(5, 3), /* ETNB0WOL */
486 [4] = RCAR_GP_PIN(5, 4), /* ETNB0LINKSTA */
487 [5] = RCAR_GP_PIN(5, 5), /* ETNB0MDC */
488 [6] = RCAR_GP_PIN(5, 6), /* ETNB0RXER */
489 [7] = RCAR_GP_PIN(5, 7), /* ETNB0RXD3 */
490 [8] = RCAR_GP_PIN(5, 8), /* ETNB0RXD1 */
491 [9] = RCAR_GP_PIN(5, 9), /* ETNB0RXD2 */
492 [10] = RCAR_GP_PIN(5, 10), /* ETNB0RXDV */
493 [11] = RCAR_GP_PIN(5, 11), /* ETNB0RXD0 */
494 [12] = RCAR_GP_PIN(5, 12), /* ETNB0RXCLK */
495 [13] = RCAR_GP_PIN(5, 13), /* ETNB0TXER */
496 [14] = RCAR_GP_PIN(5, 14), /* ETNB0TXD3 */
497 [15] = RCAR_GP_PIN(5, 15), /* ETNB0TXCLK */
498 [16] = RCAR_GP_PIN(5, 16), /* ETNB0TXD1 */
499 [17] = RCAR_GP_PIN(5, 17), /* ETNB0TXD2 */
500 [18] = RCAR_GP_PIN(5, 18), /* ETNB0TXEN */
501 [19] = RCAR_GP_PIN(5, 19), /* ETNB0TXD0 */
502 [20] = PIN_NONE,
503 [21] = PIN_NONE,
504 [22] = PIN_NONE,
505 [23] = PIN_NONE,
506 [24] = PIN_NONE,
507 [25] = PIN_NONE,
508 [26] = PIN_NONE,
509 [27] = PIN_NONE,
510 [28] = PIN_NONE,
511 [29] = PIN_NONE,
512 [30] = PIN_NONE,
513 [31] = PIN_NONE,
514 } },
515 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN6, PUD6 */
516 [0] = RCAR_GP_PIN(6, 0), /* RLIN37TX */
517 [1] = RCAR_GP_PIN(6, 1), /* RLIN37RX/INTP23 */
518 [2] = RCAR_GP_PIN(6, 2), /* RLIN36TX */
519 [3] = RCAR_GP_PIN(6, 3), /* RLIN36RX/INTP22 */
520 [4] = RCAR_GP_PIN(6, 4), /* RLIN35TX */
521 [5] = RCAR_GP_PIN(6, 5), /* RLIN35RX/INTP21 */
522 [6] = RCAR_GP_PIN(6, 6), /* RLIN34TX */
523 [7] = RCAR_GP_PIN(6, 7), /* RLIN34RX/INTP20 */
524 [8] = RCAR_GP_PIN(6, 8), /* RLIN33TX */
525 [9] = RCAR_GP_PIN(6, 9), /* RLIN33RX/INTP19 */
526 [10] = RCAR_GP_PIN(6, 10), /* RLIN32TX */
527 [11] = RCAR_GP_PIN(6, 11), /* RLIN32RX/INTP18 */
528 [12] = RCAR_GP_PIN(6, 12), /* RLIN31TX */
529 [13] = RCAR_GP_PIN(6, 13), /* RLIN31RX/INTP17 */
530 [14] = RCAR_GP_PIN(6, 14), /* RLIN30TX */
531 [15] = RCAR_GP_PIN(6, 15), /* RLIN30RX/INTP16 */
532 [16] = RCAR_GP_PIN(6, 16), /* INTP37 */
533 [17] = RCAR_GP_PIN(6, 17), /* INTP36 */
534 [18] = RCAR_GP_PIN(6, 18), /* INTP35 */
535 [19] = RCAR_GP_PIN(6, 19), /* INTP34 */
536 [20] = RCAR_GP_PIN(6, 20), /* INTP33 */
537 [21] = RCAR_GP_PIN(6, 21), /* INTP32 */
538 [22] = RCAR_GP_PIN(6, 22), /* NMI1 */
539 [23] = PIN_NONE,
540 [24] = PIN_NONE,
541 [25] = PIN_NONE,
542 [26] = PIN_NONE,
543 [27] = PIN_NONE,
544 [28] = PIN_NONE,
545 [29] = PIN_NONE,
546 [30] = PIN_NONE,
547 [31] = PIN_NONE,
548 } },
549 { PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN7, PUD7 */
550 [0] = RCAR_GP_PIN(7, 0), /* CAN0TX */
551 [1] = RCAR_GP_PIN(7, 1), /* CAN0RX/INTP0 */
552 [2] = RCAR_GP_PIN(7, 2), /* CAN1TX */
553 [3] = RCAR_GP_PIN(7, 3), /* CAN1RX/INTP1 */
554 [4] = RCAR_GP_PIN(7, 4), /* CAN2TX */
555 [5] = RCAR_GP_PIN(7, 5), /* CAN2RX/INTP2 */
556 [6] = RCAR_GP_PIN(7, 6), /* CAN3TX */
557 [7] = RCAR_GP_PIN(7, 7), /* CAN3RX/INTP3 */
558 [8] = RCAR_GP_PIN(7, 8), /* CAN4TX */
559 [9] = RCAR_GP_PIN(7, 9), /* CAN4RX/INTP4 */
560 [10] = RCAR_GP_PIN(7, 10), /* CAN5TX */
561 [11] = RCAR_GP_PIN(7, 11), /* CAN5RX/INTP5 */
562 [12] = RCAR_GP_PIN(7, 12), /* CAN6TX */
563 [13] = RCAR_GP_PIN(7, 13), /* CAN6RX/INTP6 */
564 [14] = RCAR_GP_PIN(7, 14), /* CAN7TX */
565 [15] = RCAR_GP_PIN(7, 15), /* CAN7RX/INTP7 */
566 [16] = RCAR_GP_PIN(7, 16), /* CAN8TX */
567 [17] = RCAR_GP_PIN(7, 17), /* CAN8RX/INTP8 */
568 [18] = RCAR_GP_PIN(7, 18), /* CAN9TX */
569 [19] = RCAR_GP_PIN(7, 19), /* CAN9RX/INTP9 */
570 [20] = RCAR_GP_PIN(7, 20), /* CAN10TX */
571 [21] = RCAR_GP_PIN(7, 21), /* CAN10RX/INTP10 */
572 [22] = RCAR_GP_PIN(7, 22), /* CAN11TX */
573 [23] = RCAR_GP_PIN(7, 23), /* CAN11RX/INTP11 */
574 [24] = RCAR_GP_PIN(7, 24), /* CAN12TX */
575 [25] = RCAR_GP_PIN(7, 25), /* CAN12RX/INTP12 */
576 [26] = RCAR_GP_PIN(7, 26), /* CAN13TX */
577 [27] = RCAR_GP_PIN(7, 27), /* CAN13RX/INTP13 */
578 [28] = RCAR_GP_PIN(7, 28), /* CAN14TX */
579 [29] = RCAR_GP_PIN(7, 29), /* CAN14RX/INTP14 */
580 [30] = RCAR_GP_PIN(7, 30), /* CAN15TX */
581 [31] = RCAR_GP_PIN(7, 31), /* CAN15RX/INTP15 */
582 } },
583 { /* sentinel */ },
584 };
585
pfc_rcar_get_bias_regs(void)586 const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
587 {
588 return pfc_bias_regs;
589 }
590
pfc_rcar_get_drive_regs(void)591 const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
592 {
593 return pfc_drive_regs;
594 }
595
pfc_rcar_get_reg_index(uint8_t pin,uint8_t * reg_index)596 int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
597 {
598 if (RCAR_IS_GP_PIN(pin) == false) {
599 return -EINVAL;
600 }
601
602 *reg_index = pin / 32;
603
604 return 0;
605 }
606
