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Searched refs:TIM_ECR_FIDX (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h1531 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4744 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4757 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4770 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
4830 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h1418 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4595 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4608 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4621 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
4681 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h1624 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4877 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4890 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4903 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
4963 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_tim.h1781 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
5058 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
5071 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
5084 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
5142 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c3139 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3153 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2963 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
2977 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c3053 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3067 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3308 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3322 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9083 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
Dstm32wba52xx.h13246 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
Dstm32wba54xx.h13953 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
Dstm32wba55xx.h13971 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
/hal_stm32-3.5.0/stm32cube/stm32g4xx/soc/
Dstm32gbk1cb.h10787 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g431xx.h10815 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g441xx.h11045 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g471xx.h11548 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g4a1xx.h11555 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g473xx.h12116 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g491xx.h11325 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g483xx.h12346 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g484xx.h15925 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g474xx.h15695 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
/hal_stm32-3.5.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7916 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
/hal_stm32-3.5.0/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11052 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
Dstm32u535xx.h10652 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro

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