1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 * + Timer encoder index configuration
16 ******************************************************************************
17 * @attention
18 *
19 * Copyright (c) 2021 STMicroelectronics.
20 * All rights reserved.
21 *
22 * This software is licensed under terms that can be found in the LICENSE file
23 * in the root directory of this software component.
24 * If no LICENSE file comes with this software, it is provided AS-IS.
25 *
26 ******************************************************************************
27 @verbatim
28 ==============================================================================
29 ##### TIMER Extended features #####
30 ==============================================================================
31 [..]
32 The Timer Extended features include:
33 (#) Complementary outputs with programmable dead-time for :
34 (++) Output Compare
35 (++) PWM generation (Edge and Center-aligned Mode)
36 (++) One-pulse mode output
37 (#) Synchronization circuit to control the timer with external signals and to
38 interconnect several timers together.
39 (#) Break input to put the timer output signals in reset state or in a known state.
40 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
41 positioning purposes
42 (#) In case of Pulse on compare, configure pulse length and delay
43 (#) Encoder index configuration
44
45 ##### How to use this driver #####
46 ==============================================================================
47 [..]
48 (#) Initialize the TIM low level resources by implementing the following functions
49 depending on the selected feature:
50 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
51
52 (#) Initialize the TIM low level resources :
53 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
54 (##) TIM pins configuration
55 (+++) Enable the clock for the TIM GPIOs using the following function:
56 __HAL_RCC_GPIOx_CLK_ENABLE();
57 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
58
59 (#) The external Clock can be configured, if needed (the default clock is the
60 internal clock from the APBx), using the following function:
61 HAL_TIM_ConfigClockSource, the clock configuration should be done before
62 any start function.
63
64 (#) Configure the TIM in the desired functioning mode using one of the
65 initialization function of this driver:
66 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
67 Timer Hall Sensor Interface and the commutation event with the corresponding
68 Interrupt and DMA request if needed (Note that One Timer is used to interface
69 with the Hall sensor Interface and another Timer should be used to use
70 the commutation event).
71 (#) In case of Pulse On Compare:
72 (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
73
74
75 (#) Activate the TIM peripheral using one of the start functions:
76 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
77 HAL_TIMEx_OCN_Start_IT()
78 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
79 HAL_TIMEx_PWMN_Start_IT()
80 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
81 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
82 HAL_TIMEx_HallSensor_Start_IT().
83
84 @endverbatim
85 ******************************************************************************
86 */
87
88 /* Includes ------------------------------------------------------------------*/
89 #include "stm32u5xx_hal.h"
90
91 /** @addtogroup STM32U5xx_HAL_Driver
92 * @{
93 */
94
95 /** @defgroup TIMEx TIMEx
96 * @brief TIM Extended HAL module driver
97 * @{
98 */
99
100 #ifdef HAL_TIM_MODULE_ENABLED
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
106 * @{
107 */
108 /* Timeout for break input rearm */
109 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
110 /**
111 * @}
112 */
113 /* End of private constants --------------------------------------------------*/
114
115 /* Private macros ------------------------------------------------------------*/
116 /* Private variables ---------------------------------------------------------*/
117 /* Private function prototypes -----------------------------------------------*/
118 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
119 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
120 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
124 * @{
125 */
126
127 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
128 * @brief Timer Hall Sensor functions
129 *
130 @verbatim
131 ==============================================================================
132 ##### Timer Hall Sensor functions #####
133 ==============================================================================
134 [..]
135 This section provides functions allowing to:
136 (+) Initialize and configure TIM HAL Sensor.
137 (+) De-initialize TIM HAL Sensor.
138 (+) Start the Hall Sensor Interface.
139 (+) Stop the Hall Sensor Interface.
140 (+) Start the Hall Sensor Interface and enable interrupts.
141 (+) Stop the Hall Sensor Interface and disable interrupts.
142 (+) Start the Hall Sensor Interface and enable DMA transfers.
143 (+) Stop the Hall Sensor Interface and disable DMA transfers.
144
145 @endverbatim
146 * @{
147 */
148 /**
149 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
150 * @note When the timer instance is initialized in Hall Sensor Interface mode,
151 * timer channels 1 and channel 2 are reserved and cannot be used for
152 * other purpose.
153 * @param htim TIM Hall Sensor Interface handle
154 * @param sConfig TIM Hall Sensor configuration structure
155 * @retval HAL status
156 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
158 {
159 TIM_OC_InitTypeDef OC_Config;
160
161 /* Check the TIM handle allocation */
162 if (htim == NULL)
163 {
164 return HAL_ERROR;
165 }
166
167 /* Check the parameters */
168 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
169 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
170 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
171 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
172 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
173 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
176
177 if (htim->State == HAL_TIM_STATE_RESET)
178 {
179 /* Allocate lock resource and initialize it */
180 htim->Lock = HAL_UNLOCKED;
181
182 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
183 /* Reset interrupt callbacks to legacy week callbacks */
184 TIM_ResetCallback(htim);
185
186 if (htim->HallSensor_MspInitCallback == NULL)
187 {
188 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
189 }
190 /* Init the low level hardware : GPIO, CLOCK, NVIC */
191 htim->HallSensor_MspInitCallback(htim);
192 #else
193 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
194 HAL_TIMEx_HallSensor_MspInit(htim);
195 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
196 }
197
198 /* Set the TIM state */
199 htim->State = HAL_TIM_STATE_BUSY;
200
201 /* Configure the Time base in the Encoder Mode */
202 TIM_Base_SetConfig(htim->Instance, &htim->Init);
203
204 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
205 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
206
207 /* Reset the IC1PSC Bits */
208 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
209 /* Set the IC1PSC value */
210 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
211
212 /* Enable the Hall sensor interface (XOR function of the three inputs) */
213 htim->Instance->CR2 |= TIM_CR2_TI1S;
214
215 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
216 htim->Instance->SMCR &= ~TIM_SMCR_TS;
217 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
218
219 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
220 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
221 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
222
223 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
224 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
225 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
226 OC_Config.OCMode = TIM_OCMODE_PWM2;
227 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
228 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
229 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
230 OC_Config.Pulse = sConfig->Commutation_Delay;
231
232 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
233
234 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
235 register to 101 */
236 htim->Instance->CR2 &= ~TIM_CR2_MMS;
237 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
238
239 /* Initialize the DMA burst operation state */
240 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
241
242 /* Initialize the TIM channels state */
243 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
244 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
245 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
247
248 /* Initialize the TIM state*/
249 htim->State = HAL_TIM_STATE_READY;
250
251 return HAL_OK;
252 }
253
254 /**
255 * @brief DeInitializes the TIM Hall Sensor interface
256 * @param htim TIM Hall Sensor Interface handle
257 * @retval HAL status
258 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)259 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
260 {
261 /* Check the parameters */
262 assert_param(IS_TIM_INSTANCE(htim->Instance));
263
264 htim->State = HAL_TIM_STATE_BUSY;
265
266 /* Disable the TIM Peripheral Clock */
267 __HAL_TIM_DISABLE(htim);
268
269 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
270 if (htim->HallSensor_MspDeInitCallback == NULL)
271 {
272 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
273 }
274 /* DeInit the low level hardware */
275 htim->HallSensor_MspDeInitCallback(htim);
276 #else
277 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
278 HAL_TIMEx_HallSensor_MspDeInit(htim);
279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
280
281 /* Change the DMA burst operation state */
282 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
283
284 /* Change the TIM channels state */
285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
289
290 /* Change TIM state */
291 htim->State = HAL_TIM_STATE_RESET;
292
293 /* Release Lock */
294 __HAL_UNLOCK(htim);
295
296 return HAL_OK;
297 }
298
299 /**
300 * @brief Initializes the TIM Hall Sensor MSP.
301 * @param htim TIM Hall Sensor Interface handle
302 * @retval None
303 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)304 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
305 {
306 /* Prevent unused argument(s) compilation warning */
307 UNUSED(htim);
308
309 /* NOTE : This function should not be modified, when the callback is needed,
310 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
311 */
312 }
313
314 /**
315 * @brief DeInitializes TIM Hall Sensor MSP.
316 * @param htim TIM Hall Sensor Interface handle
317 * @retval None
318 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)319 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
320 {
321 /* Prevent unused argument(s) compilation warning */
322 UNUSED(htim);
323
324 /* NOTE : This function should not be modified, when the callback is needed,
325 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
326 */
327 }
328
329 /**
330 * @brief Starts the TIM Hall Sensor Interface.
331 * @param htim TIM Hall Sensor Interface handle
332 * @retval HAL status
333 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
335 {
336 uint32_t tmpsmcr;
337 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
338 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
339 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
340 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
341
342 /* Check the parameters */
343 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
344
345 /* Check the TIM channels state */
346 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
347 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
348 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
349 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
350 {
351 return HAL_ERROR;
352 }
353
354 /* Set the TIM channels state */
355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
356 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
357 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
358 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
359
360 /* Enable the Input Capture channel 1
361 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
362 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
363 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
364
365 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
366 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
367 {
368 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
369 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
370 {
371 __HAL_TIM_ENABLE(htim);
372 }
373 }
374 else
375 {
376 __HAL_TIM_ENABLE(htim);
377 }
378
379 /* Return function status */
380 return HAL_OK;
381 }
382
383 /**
384 * @brief Stops the TIM Hall sensor Interface.
385 * @param htim TIM Hall Sensor Interface handle
386 * @retval HAL status
387 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
389 {
390 /* Check the parameters */
391 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
392
393 /* Disable the Input Capture channels 1, 2 and 3
394 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
395 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
397
398 /* Disable the Peripheral */
399 __HAL_TIM_DISABLE(htim);
400
401 /* Set the TIM channels state */
402 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
405 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
413 * @param htim TIM Hall Sensor Interface handle
414 * @retval HAL status
415 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)416 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
417 {
418 uint32_t tmpsmcr;
419 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
420 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
421 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
422 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
423
424 /* Check the parameters */
425 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
426
427 /* Check the TIM channels state */
428 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
429 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
430 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
431 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
432 {
433 return HAL_ERROR;
434 }
435
436 /* Set the TIM channels state */
437 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
438 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
440 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
441
442 /* Enable the capture compare Interrupts 1 event */
443 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
444
445 /* Enable the Input Capture channel 1
446 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
447 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
449
450 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
451 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
452 {
453 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
454 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
455 {
456 __HAL_TIM_ENABLE(htim);
457 }
458 }
459 else
460 {
461 __HAL_TIM_ENABLE(htim);
462 }
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
470 * @param htim TIM Hall Sensor Interface handle
471 * @retval HAL status
472 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
474 {
475 /* Check the parameters */
476 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
477
478 /* Disable the Input Capture channel 1
479 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
480 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
481 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
482
483 /* Disable the capture compare Interrupts event */
484 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
485
486 /* Disable the Peripheral */
487 __HAL_TIM_DISABLE(htim);
488
489 /* Set the TIM channels state */
490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
491 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
492 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
493 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
501 * @param htim TIM Hall Sensor Interface handle
502 * @param pData The destination Buffer address.
503 * @param Length The length of data to be transferred from TIM peripheral to memory.
504 * @retval HAL status
505 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)506 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
507 {
508 uint32_t tmpsmcr;
509 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
510 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
511
512 /* Check the parameters */
513 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
514
515 /* Set the TIM channel state */
516 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
517 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
518 {
519 return HAL_BUSY;
520 }
521 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
522 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
523 {
524 if ((pData == NULL) || (Length == 0U))
525 {
526 return HAL_ERROR;
527 }
528 else
529 {
530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
532 }
533 }
534 else
535 {
536 return HAL_ERROR;
537 }
538
539 /* Enable the Input Capture channel 1
540 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
541 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
543
544 /* Set the DMA Input Capture 1 Callbacks */
545 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
546 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
547 /* Set the DMA error callback */
548 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
549
550 /* Enable the DMA channel for Capture 1*/
551 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
552 {
553 /* Return error status */
554 return HAL_ERROR;
555 }
556 /* Enable the capture compare 1 Interrupt */
557 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
558
559 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
560 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
561 {
562 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
563 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
564 {
565 __HAL_TIM_ENABLE(htim);
566 }
567 }
568 else
569 {
570 __HAL_TIM_ENABLE(htim);
571 }
572
573 /* Return function status */
574 return HAL_OK;
575 }
576
577 /**
578 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
579 * @param htim TIM Hall Sensor Interface handle
580 * @retval HAL status
581 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)582 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
583 {
584 /* Check the parameters */
585 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
586
587 /* Disable the Input Capture channel 1
588 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
589 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
590 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
591
592
593 /* Disable the capture compare Interrupts 1 event */
594 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
595
596 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
597
598 /* Disable the Peripheral */
599 __HAL_TIM_DISABLE(htim);
600
601 /* Set the TIM channel state */
602 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
603 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
604
605 /* Return function status */
606 return HAL_OK;
607 }
608
609 /**
610 * @}
611 */
612
613 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
614 * @brief Timer Complementary Output Compare functions
615 *
616 @verbatim
617 ==============================================================================
618 ##### Timer Complementary Output Compare functions #####
619 ==============================================================================
620 [..]
621 This section provides functions allowing to:
622 (+) Start the Complementary Output Compare/PWM.
623 (+) Stop the Complementary Output Compare/PWM.
624 (+) Start the Complementary Output Compare/PWM and enable interrupts.
625 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
626 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
627 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
628
629 @endverbatim
630 * @{
631 */
632
633 /**
634 * @brief Starts the TIM Output Compare signal generation on the complementary
635 * output.
636 * @param htim TIM Output Compare handle
637 * @param Channel TIM Channel to be enabled
638 * This parameter can be one of the following values:
639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
643 * @retval HAL status
644 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)645 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
646 {
647 uint32_t tmpsmcr;
648
649 /* Check the parameters */
650 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
651
652 /* Check the TIM complementary channel state */
653 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Set the TIM complementary channel state */
659 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
660
661 /* Enable the Capture compare channel N */
662 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
663
664 /* Enable the Main Output */
665 __HAL_TIM_MOE_ENABLE(htim);
666
667 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
668 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
669 {
670 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
671 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
672 {
673 __HAL_TIM_ENABLE(htim);
674 }
675 }
676 else
677 {
678 __HAL_TIM_ENABLE(htim);
679 }
680
681 /* Return function status */
682 return HAL_OK;
683 }
684
685 /**
686 * @brief Stops the TIM Output Compare signal generation on the complementary
687 * output.
688 * @param htim TIM handle
689 * @param Channel TIM Channel to be disabled
690 * This parameter can be one of the following values:
691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
693 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
694 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
695 * @retval HAL status
696 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)697 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
698 {
699 /* Check the parameters */
700 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
701
702 /* Disable the Capture compare channel N */
703 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
704
705 /* Disable the Main Output */
706 __HAL_TIM_MOE_DISABLE(htim);
707
708 /* Disable the Peripheral */
709 __HAL_TIM_DISABLE(htim);
710
711 /* Set the TIM complementary channel state */
712 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
713
714 /* Return function status */
715 return HAL_OK;
716 }
717
718 /**
719 * @brief Starts the TIM Output Compare signal generation in interrupt mode
720 * on the complementary output.
721 * @param htim TIM OC handle
722 * @param Channel TIM Channel to be enabled
723 * This parameter can be one of the following values:
724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
728 * @retval HAL status
729 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)730 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
731 {
732 HAL_StatusTypeDef status = HAL_OK;
733 uint32_t tmpsmcr;
734
735 /* Check the parameters */
736 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
737
738 /* Check the TIM complementary channel state */
739 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
740 {
741 return HAL_ERROR;
742 }
743
744 /* Set the TIM complementary channel state */
745 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
746
747 switch (Channel)
748 {
749 case TIM_CHANNEL_1:
750 {
751 /* Enable the TIM Output Compare interrupt */
752 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
753 break;
754 }
755
756 case TIM_CHANNEL_2:
757 {
758 /* Enable the TIM Output Compare interrupt */
759 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
760 break;
761 }
762
763 case TIM_CHANNEL_3:
764 {
765 /* Enable the TIM Output Compare interrupt */
766 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
767 break;
768 }
769
770
771 case TIM_CHANNEL_4:
772 {
773 /* Enable the TIM Output Compare interrupt */
774 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
775 break;
776 }
777
778 default:
779 status = HAL_ERROR;
780 break;
781 }
782
783 if (status == HAL_OK)
784 {
785 /* Enable the TIM Break interrupt */
786 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
787
788 /* Enable the Capture compare channel N */
789 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
790
791 /* Enable the Main Output */
792 __HAL_TIM_MOE_ENABLE(htim);
793
794 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
795 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
796 {
797 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
798 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
799 {
800 __HAL_TIM_ENABLE(htim);
801 }
802 }
803 else
804 {
805 __HAL_TIM_ENABLE(htim);
806 }
807 }
808
809 /* Return function status */
810 return status;
811 }
812
813 /**
814 * @brief Stops the TIM Output Compare signal generation in interrupt mode
815 * on the complementary output.
816 * @param htim TIM Output Compare handle
817 * @param Channel TIM Channel to be disabled
818 * This parameter can be one of the following values:
819 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
820 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
821 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
822 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
823 * @retval HAL status
824 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)825 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
826 {
827 HAL_StatusTypeDef status = HAL_OK;
828 uint32_t tmpccer;
829
830 /* Check the parameters */
831 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
832
833 switch (Channel)
834 {
835 case TIM_CHANNEL_1:
836 {
837 /* Disable the TIM Output Compare interrupt */
838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
839 break;
840 }
841
842 case TIM_CHANNEL_2:
843 {
844 /* Disable the TIM Output Compare interrupt */
845 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
846 break;
847 }
848
849 case TIM_CHANNEL_3:
850 {
851 /* Disable the TIM Output Compare interrupt */
852 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
853 break;
854 }
855
856 case TIM_CHANNEL_4:
857 {
858 /* Disable the TIM Output Compare interrupt */
859 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
860 break;
861 }
862
863 default:
864 status = HAL_ERROR;
865 break;
866 }
867
868 if (status == HAL_OK)
869 {
870 /* Disable the Capture compare channel N */
871 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
872
873 /* Disable the TIM Break interrupt (only if no more channel is active) */
874 tmpccer = htim->Instance->CCER;
875 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
876 {
877 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
878 }
879
880 /* Disable the Main Output */
881 __HAL_TIM_MOE_DISABLE(htim);
882
883 /* Disable the Peripheral */
884 __HAL_TIM_DISABLE(htim);
885
886 /* Set the TIM complementary channel state */
887 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
888 }
889
890 /* Return function status */
891 return status;
892 }
893
894 /**
895 * @brief Starts the TIM Output Compare signal generation in DMA mode
896 * on the complementary output.
897 * @param htim TIM Output Compare handle
898 * @param Channel TIM Channel to be enabled
899 * This parameter can be one of the following values:
900 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
901 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
902 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
903 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
904 * @param pData The source Buffer address.
905 * @param Length The length of data to be transferred from memory to TIM peripheral
906 * @retval HAL status
907 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)908 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
909 uint16_t Length)
910 {
911 HAL_StatusTypeDef status = HAL_OK;
912 uint32_t tmpsmcr;
913
914 /* Check the parameters */
915 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
916
917 /* Set the TIM complementary channel state */
918 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
919 {
920 return HAL_BUSY;
921 }
922 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
923 {
924 if ((pData == NULL) || (Length == 0U))
925 {
926 return HAL_ERROR;
927 }
928 else
929 {
930 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
931 }
932 }
933 else
934 {
935 return HAL_ERROR;
936 }
937
938 switch (Channel)
939 {
940 case TIM_CHANNEL_1:
941 {
942 /* Set the DMA compare callbacks */
943 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
944 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
945
946 /* Set the DMA error callback */
947 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
948
949 /* Enable the DMA channel */
950 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
951 Length) != HAL_OK)
952 {
953 /* Return error status */
954 return HAL_ERROR;
955 }
956 /* Enable the TIM Output Compare DMA request */
957 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
958 break;
959 }
960
961 case TIM_CHANNEL_2:
962 {
963 /* Set the DMA compare callbacks */
964 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
965 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
966
967 /* Set the DMA error callback */
968 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
969
970 /* Enable the DMA channel */
971 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
972 Length) != HAL_OK)
973 {
974 /* Return error status */
975 return HAL_ERROR;
976 }
977 /* Enable the TIM Output Compare DMA request */
978 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
979 break;
980 }
981
982 case TIM_CHANNEL_3:
983 {
984 /* Set the DMA compare callbacks */
985 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
986 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
987
988 /* Set the DMA error callback */
989 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
990
991 /* Enable the DMA channel */
992 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
993 Length) != HAL_OK)
994 {
995 /* Return error status */
996 return HAL_ERROR;
997 }
998 /* Enable the TIM Output Compare DMA request */
999 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1000 break;
1001 }
1002
1003 case TIM_CHANNEL_4:
1004 {
1005 /* Set the DMA compare callbacks */
1006 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1007 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1008
1009 /* Set the DMA error callback */
1010 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1011
1012 /* Enable the DMA channel */
1013 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1014 Length) != HAL_OK)
1015 {
1016 /* Return error status */
1017 return HAL_ERROR;
1018 }
1019 /* Enable the TIM Output Compare DMA request */
1020 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1021 break;
1022 }
1023
1024 default:
1025 status = HAL_ERROR;
1026 break;
1027 }
1028
1029 if (status == HAL_OK)
1030 {
1031 /* Enable the Capture compare channel N */
1032 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1033
1034 /* Enable the Main Output */
1035 __HAL_TIM_MOE_ENABLE(htim);
1036
1037 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1038 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1039 {
1040 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1041 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1042 {
1043 __HAL_TIM_ENABLE(htim);
1044 }
1045 }
1046 else
1047 {
1048 __HAL_TIM_ENABLE(htim);
1049 }
1050 }
1051
1052 /* Return function status */
1053 return status;
1054 }
1055
1056 /**
1057 * @brief Stops the TIM Output Compare signal generation in DMA mode
1058 * on the complementary output.
1059 * @param htim TIM Output Compare handle
1060 * @param Channel TIM Channel to be disabled
1061 * This parameter can be one of the following values:
1062 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1063 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1064 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1065 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1066 * @retval HAL status
1067 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1068 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1069 {
1070 HAL_StatusTypeDef status = HAL_OK;
1071
1072 /* Check the parameters */
1073 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1074
1075 switch (Channel)
1076 {
1077 case TIM_CHANNEL_1:
1078 {
1079 /* Disable the TIM Output Compare DMA request */
1080 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1081 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1082 break;
1083 }
1084
1085 case TIM_CHANNEL_2:
1086 {
1087 /* Disable the TIM Output Compare DMA request */
1088 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1089 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1090 break;
1091 }
1092
1093 case TIM_CHANNEL_3:
1094 {
1095 /* Disable the TIM Output Compare DMA request */
1096 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1097 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1098 break;
1099 }
1100
1101 case TIM_CHANNEL_4:
1102 {
1103 /* Disable the TIM Output Compare interrupt */
1104 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1105 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1106 break;
1107 }
1108
1109 default:
1110 status = HAL_ERROR;
1111 break;
1112 }
1113
1114 if (status == HAL_OK)
1115 {
1116 /* Disable the Capture compare channel N */
1117 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1118
1119 /* Disable the Main Output */
1120 __HAL_TIM_MOE_DISABLE(htim);
1121
1122 /* Disable the Peripheral */
1123 __HAL_TIM_DISABLE(htim);
1124
1125 /* Set the TIM complementary channel state */
1126 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1127 }
1128
1129 /* Return function status */
1130 return status;
1131 }
1132
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1138 * @brief Timer Complementary PWM functions
1139 *
1140 @verbatim
1141 ==============================================================================
1142 ##### Timer Complementary PWM functions #####
1143 ==============================================================================
1144 [..]
1145 This section provides functions allowing to:
1146 (+) Start the Complementary PWM.
1147 (+) Stop the Complementary PWM.
1148 (+) Start the Complementary PWM and enable interrupts.
1149 (+) Stop the Complementary PWM and disable interrupts.
1150 (+) Start the Complementary PWM and enable DMA transfers.
1151 (+) Stop the Complementary PWM and disable DMA transfers.
1152 (+) Start the Complementary Input Capture measurement.
1153 (+) Stop the Complementary Input Capture.
1154 (+) Start the Complementary Input Capture and enable interrupts.
1155 (+) Stop the Complementary Input Capture and disable interrupts.
1156 (+) Start the Complementary Input Capture and enable DMA transfers.
1157 (+) Stop the Complementary Input Capture and disable DMA transfers.
1158 (+) Start the Complementary One Pulse generation.
1159 (+) Stop the Complementary One Pulse.
1160 (+) Start the Complementary One Pulse and enable interrupts.
1161 (+) Stop the Complementary One Pulse and disable interrupts.
1162
1163 @endverbatim
1164 * @{
1165 */
1166
1167 /**
1168 * @brief Starts the PWM signal generation on the complementary output.
1169 * @param htim TIM handle
1170 * @param Channel TIM Channel to be enabled
1171 * This parameter can be one of the following values:
1172 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1173 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1174 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1175 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1176 * @retval HAL status
1177 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1178 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1179 {
1180 uint32_t tmpsmcr;
1181
1182 /* Check the parameters */
1183 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1184
1185 /* Check the TIM complementary channel state */
1186 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1187 {
1188 return HAL_ERROR;
1189 }
1190
1191 /* Set the TIM complementary channel state */
1192 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1193
1194 /* Enable the complementary PWM output */
1195 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1196
1197 /* Enable the Main Output */
1198 __HAL_TIM_MOE_ENABLE(htim);
1199
1200 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1201 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1202 {
1203 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1204 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1205 {
1206 __HAL_TIM_ENABLE(htim);
1207 }
1208 }
1209 else
1210 {
1211 __HAL_TIM_ENABLE(htim);
1212 }
1213
1214 /* Return function status */
1215 return HAL_OK;
1216 }
1217
1218 /**
1219 * @brief Stops the PWM signal generation on the complementary output.
1220 * @param htim TIM handle
1221 * @param Channel TIM Channel to be disabled
1222 * This parameter can be one of the following values:
1223 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1224 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1225 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1226 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1227 * @retval HAL status
1228 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1229 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1230 {
1231 /* Check the parameters */
1232 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1233
1234 /* Disable the complementary PWM output */
1235 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1236
1237 /* Disable the Main Output */
1238 __HAL_TIM_MOE_DISABLE(htim);
1239
1240 /* Disable the Peripheral */
1241 __HAL_TIM_DISABLE(htim);
1242
1243 /* Set the TIM complementary channel state */
1244 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1245
1246 /* Return function status */
1247 return HAL_OK;
1248 }
1249
1250 /**
1251 * @brief Starts the PWM signal generation in interrupt mode on the
1252 * complementary output.
1253 * @param htim TIM handle
1254 * @param Channel TIM Channel to be disabled
1255 * This parameter can be one of the following values:
1256 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1257 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1258 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1259 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1260 * @retval HAL status
1261 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1262 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1263 {
1264 HAL_StatusTypeDef status = HAL_OK;
1265 uint32_t tmpsmcr;
1266
1267 /* Check the parameters */
1268 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1269
1270 /* Check the TIM complementary channel state */
1271 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1272 {
1273 return HAL_ERROR;
1274 }
1275
1276 /* Set the TIM complementary channel state */
1277 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1278
1279 switch (Channel)
1280 {
1281 case TIM_CHANNEL_1:
1282 {
1283 /* Enable the TIM Capture/Compare 1 interrupt */
1284 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1285 break;
1286 }
1287
1288 case TIM_CHANNEL_2:
1289 {
1290 /* Enable the TIM Capture/Compare 2 interrupt */
1291 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1292 break;
1293 }
1294
1295 case TIM_CHANNEL_3:
1296 {
1297 /* Enable the TIM Capture/Compare 3 interrupt */
1298 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1299 break;
1300 }
1301
1302 case TIM_CHANNEL_4:
1303 {
1304 /* Enable the TIM Capture/Compare 4 interrupt */
1305 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1306 break;
1307 }
1308
1309 default:
1310 status = HAL_ERROR;
1311 break;
1312 }
1313
1314 if (status == HAL_OK)
1315 {
1316 /* Enable the TIM Break interrupt */
1317 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1318
1319 /* Enable the complementary PWM output */
1320 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1321
1322 /* Enable the Main Output */
1323 __HAL_TIM_MOE_ENABLE(htim);
1324
1325 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1326 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1327 {
1328 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1329 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1330 {
1331 __HAL_TIM_ENABLE(htim);
1332 }
1333 }
1334 else
1335 {
1336 __HAL_TIM_ENABLE(htim);
1337 }
1338 }
1339
1340 /* Return function status */
1341 return status;
1342 }
1343
1344 /**
1345 * @brief Stops the PWM signal generation in interrupt mode on the
1346 * complementary output.
1347 * @param htim TIM handle
1348 * @param Channel TIM Channel to be disabled
1349 * This parameter can be one of the following values:
1350 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1351 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1352 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1353 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1354 * @retval HAL status
1355 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1356 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1357 {
1358 HAL_StatusTypeDef status = HAL_OK;
1359 uint32_t tmpccer;
1360
1361 /* Check the parameters */
1362 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1363
1364 switch (Channel)
1365 {
1366 case TIM_CHANNEL_1:
1367 {
1368 /* Disable the TIM Capture/Compare 1 interrupt */
1369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1370 break;
1371 }
1372
1373 case TIM_CHANNEL_2:
1374 {
1375 /* Disable the TIM Capture/Compare 2 interrupt */
1376 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1377 break;
1378 }
1379
1380 case TIM_CHANNEL_3:
1381 {
1382 /* Disable the TIM Capture/Compare 3 interrupt */
1383 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1384 break;
1385 }
1386
1387 case TIM_CHANNEL_4:
1388 {
1389 /* Disable the TIM Capture/Compare 4 interrupt */
1390 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1391 break;
1392 }
1393
1394 default:
1395 status = HAL_ERROR;
1396 break;
1397 }
1398
1399 if (status == HAL_OK)
1400 {
1401 /* Disable the complementary PWM output */
1402 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1403
1404 /* Disable the TIM Break interrupt (only if no more channel is active) */
1405 tmpccer = htim->Instance->CCER;
1406 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
1407 {
1408 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1409 }
1410
1411 /* Disable the Main Output */
1412 __HAL_TIM_MOE_DISABLE(htim);
1413
1414 /* Disable the Peripheral */
1415 __HAL_TIM_DISABLE(htim);
1416
1417 /* Set the TIM complementary channel state */
1418 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1419 }
1420
1421 /* Return function status */
1422 return status;
1423 }
1424
1425 /**
1426 * @brief Starts the TIM PWM signal generation in DMA mode on the
1427 * complementary output
1428 * @param htim TIM handle
1429 * @param Channel TIM Channel to be enabled
1430 * This parameter can be one of the following values:
1431 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1432 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1433 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1434 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1435 * @param pData The source Buffer address.
1436 * @param Length The length of data to be transferred from memory to TIM peripheral
1437 * @retval HAL status
1438 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1439 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1440 uint16_t Length)
1441 {
1442 HAL_StatusTypeDef status = HAL_OK;
1443 uint32_t tmpsmcr;
1444
1445 /* Check the parameters */
1446 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1447
1448 /* Set the TIM complementary channel state */
1449 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1450 {
1451 return HAL_BUSY;
1452 }
1453 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1454 {
1455 if ((pData == NULL) || (Length == 0U))
1456 {
1457 return HAL_ERROR;
1458 }
1459 else
1460 {
1461 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1462 }
1463 }
1464 else
1465 {
1466 return HAL_ERROR;
1467 }
1468
1469 switch (Channel)
1470 {
1471 case TIM_CHANNEL_1:
1472 {
1473 /* Set the DMA compare callbacks */
1474 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1475 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1476
1477 /* Set the DMA error callback */
1478 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1479
1480 /* Enable the DMA channel */
1481 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1482 Length) != HAL_OK)
1483 {
1484 /* Return error status */
1485 return HAL_ERROR;
1486 }
1487 /* Enable the TIM Capture/Compare 1 DMA request */
1488 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1489 break;
1490 }
1491
1492 case TIM_CHANNEL_2:
1493 {
1494 /* Set the DMA compare callbacks */
1495 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1496 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1497
1498 /* Set the DMA error callback */
1499 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1500
1501 /* Enable the DMA channel */
1502 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1503 Length) != HAL_OK)
1504 {
1505 /* Return error status */
1506 return HAL_ERROR;
1507 }
1508 /* Enable the TIM Capture/Compare 2 DMA request */
1509 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1510 break;
1511 }
1512
1513 case TIM_CHANNEL_3:
1514 {
1515 /* Set the DMA compare callbacks */
1516 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1517 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1518
1519 /* Set the DMA error callback */
1520 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1521
1522 /* Enable the DMA channel */
1523 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1524 Length) != HAL_OK)
1525 {
1526 /* Return error status */
1527 return HAL_ERROR;
1528 }
1529 /* Enable the TIM Capture/Compare 3 DMA request */
1530 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1531 break;
1532 }
1533
1534 case TIM_CHANNEL_4:
1535 {
1536 /* Set the DMA compare callbacks */
1537 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1538 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1539
1540 /* Set the DMA error callback */
1541 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1542
1543 /* Enable the DMA channel */
1544 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1545 Length) != HAL_OK)
1546 {
1547 /* Return error status */
1548 return HAL_ERROR;
1549 }
1550 /* Enable the TIM Capture/Compare 4 DMA request */
1551 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1552 break;
1553 }
1554
1555 default:
1556 status = HAL_ERROR;
1557 break;
1558 }
1559
1560 if (status == HAL_OK)
1561 {
1562 /* Enable the complementary PWM output */
1563 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1564
1565 /* Enable the Main Output */
1566 __HAL_TIM_MOE_ENABLE(htim);
1567
1568 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1569 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1570 {
1571 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1572 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1573 {
1574 __HAL_TIM_ENABLE(htim);
1575 }
1576 }
1577 else
1578 {
1579 __HAL_TIM_ENABLE(htim);
1580 }
1581 }
1582
1583 /* Return function status */
1584 return status;
1585 }
1586
1587 /**
1588 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1589 * output
1590 * @param htim TIM handle
1591 * @param Channel TIM Channel to be disabled
1592 * This parameter can be one of the following values:
1593 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1594 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1595 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1596 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1597 * @retval HAL status
1598 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1599 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1600 {
1601 HAL_StatusTypeDef status = HAL_OK;
1602
1603 /* Check the parameters */
1604 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1605
1606 switch (Channel)
1607 {
1608 case TIM_CHANNEL_1:
1609 {
1610 /* Disable the TIM Capture/Compare 1 DMA request */
1611 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1612 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1613 break;
1614 }
1615
1616 case TIM_CHANNEL_2:
1617 {
1618 /* Disable the TIM Capture/Compare 2 DMA request */
1619 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1620 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1621 break;
1622 }
1623
1624 case TIM_CHANNEL_3:
1625 {
1626 /* Disable the TIM Capture/Compare 3 DMA request */
1627 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1628 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1629 break;
1630 }
1631
1632 case TIM_CHANNEL_4:
1633 {
1634 /* Disable the TIM Capture/Compare 4 DMA request */
1635 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1636 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1637 break;
1638 }
1639
1640 default:
1641 status = HAL_ERROR;
1642 break;
1643 }
1644
1645 if (status == HAL_OK)
1646 {
1647 /* Disable the complementary PWM output */
1648 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1649
1650 /* Disable the Main Output */
1651 __HAL_TIM_MOE_DISABLE(htim);
1652
1653 /* Disable the Peripheral */
1654 __HAL_TIM_DISABLE(htim);
1655
1656 /* Set the TIM complementary channel state */
1657 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1658 }
1659
1660 /* Return function status */
1661 return status;
1662 }
1663
1664 /**
1665 * @}
1666 */
1667
1668 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1669 * @brief Timer Complementary One Pulse functions
1670 *
1671 @verbatim
1672 ==============================================================================
1673 ##### Timer Complementary One Pulse functions #####
1674 ==============================================================================
1675 [..]
1676 This section provides functions allowing to:
1677 (+) Start the Complementary One Pulse generation.
1678 (+) Stop the Complementary One Pulse.
1679 (+) Start the Complementary One Pulse and enable interrupts.
1680 (+) Stop the Complementary One Pulse and disable interrupts.
1681
1682 @endverbatim
1683 * @{
1684 */
1685
1686 /**
1687 * @brief Starts the TIM One Pulse signal generation on the complementary
1688 * output.
1689 * @note OutputChannel must match the pulse output channel chosen when calling
1690 * @ref HAL_TIM_OnePulse_ConfigChannel().
1691 * @param htim TIM One Pulse handle
1692 * @param OutputChannel pulse output channel to enable
1693 * This parameter can be one of the following values:
1694 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1695 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1696 * @retval HAL status
1697 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1698 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1699 {
1700 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1701 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1702 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1703 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1704 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1705
1706 /* Check the parameters */
1707 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1708
1709 /* Check the TIM channels state */
1710 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1711 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1712 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1713 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1714 {
1715 return HAL_ERROR;
1716 }
1717
1718 /* Set the TIM channels state */
1719 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1720 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1721 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1722 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1723
1724 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1725 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1726 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1727
1728 /* Enable the Main Output */
1729 __HAL_TIM_MOE_ENABLE(htim);
1730
1731 /* Return function status */
1732 return HAL_OK;
1733 }
1734
1735 /**
1736 * @brief Stops the TIM One Pulse signal generation on the complementary
1737 * output.
1738 * @note OutputChannel must match the pulse output channel chosen when calling
1739 * @ref HAL_TIM_OnePulse_ConfigChannel().
1740 * @param htim TIM One Pulse handle
1741 * @param OutputChannel pulse output channel to disable
1742 * This parameter can be one of the following values:
1743 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1744 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1745 * @retval HAL status
1746 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1747 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1748 {
1749 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1750
1751 /* Check the parameters */
1752 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1753
1754 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1755 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1756 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1757
1758 /* Disable the Main Output */
1759 __HAL_TIM_MOE_DISABLE(htim);
1760
1761 /* Disable the Peripheral */
1762 __HAL_TIM_DISABLE(htim);
1763
1764 /* Set the TIM channels state */
1765 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1766 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1767 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1768 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1769
1770 /* Return function status */
1771 return HAL_OK;
1772 }
1773
1774 /**
1775 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1776 * complementary channel.
1777 * @note OutputChannel must match the pulse output channel chosen when calling
1778 * @ref HAL_TIM_OnePulse_ConfigChannel().
1779 * @param htim TIM One Pulse handle
1780 * @param OutputChannel pulse output channel to enable
1781 * This parameter can be one of the following values:
1782 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1783 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1784 * @retval HAL status
1785 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1786 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1787 {
1788 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1789 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1790 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1791 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1792 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1793
1794 /* Check the parameters */
1795 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1796
1797 /* Check the TIM channels state */
1798 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1799 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1800 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1801 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1802 {
1803 return HAL_ERROR;
1804 }
1805
1806 /* Set the TIM channels state */
1807 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1808 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1809 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1810 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1811
1812 /* Enable the TIM Capture/Compare 1 interrupt */
1813 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1814
1815 /* Enable the TIM Capture/Compare 2 interrupt */
1816 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1817
1818 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1819 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1820 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1821
1822 /* Enable the Main Output */
1823 __HAL_TIM_MOE_ENABLE(htim);
1824
1825 /* Return function status */
1826 return HAL_OK;
1827 }
1828
1829 /**
1830 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1831 * complementary channel.
1832 * @note OutputChannel must match the pulse output channel chosen when calling
1833 * @ref HAL_TIM_OnePulse_ConfigChannel().
1834 * @param htim TIM One Pulse handle
1835 * @param OutputChannel pulse output channel to disable
1836 * This parameter can be one of the following values:
1837 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1838 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1839 * @retval HAL status
1840 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1841 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1842 {
1843 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1844
1845 /* Check the parameters */
1846 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1847
1848 /* Disable the TIM Capture/Compare 1 interrupt */
1849 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1850
1851 /* Disable the TIM Capture/Compare 2 interrupt */
1852 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1853
1854 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1855 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1856 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1857
1858 /* Disable the Main Output */
1859 __HAL_TIM_MOE_DISABLE(htim);
1860
1861 /* Disable the Peripheral */
1862 __HAL_TIM_DISABLE(htim);
1863
1864 /* Set the TIM channels state */
1865 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1866 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1867 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1868 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1869
1870 /* Return function status */
1871 return HAL_OK;
1872 }
1873
1874 /**
1875 * @}
1876 */
1877
1878 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1879 * @brief Peripheral Control functions
1880 *
1881 @verbatim
1882 ==============================================================================
1883 ##### Peripheral Control functions #####
1884 ==============================================================================
1885 [..]
1886 This section provides functions allowing to:
1887 (+) Configure the commutation event in case of use of the Hall sensor interface.
1888 (+) Configure Output channels for OC and PWM mode.
1889
1890 (+) Configure Complementary channels, break features and dead time.
1891 (+) Configure Master synchronization.
1892 (+) Configure timer remapping capabilities.
1893 (+) Select timer input source.
1894 (+) Enable or disable channel grouping.
1895 (+) Configure Pulse on compare.
1896 (+) Configure Encoder index.
1897
1898 @endverbatim
1899 * @{
1900 */
1901
1902 /**
1903 * @brief Configure the TIM commutation event sequence.
1904 * @note This function is mandatory to use the commutation event in order to
1905 * update the configuration at each commutation detection on the TRGI input of the Timer,
1906 * the typical use of this feature is with the use of another Timer(interface Timer)
1907 * configured in Hall sensor interface, this interface Timer will generate the
1908 * commutation at its TRGO output (connected to Timer used in this function) each time
1909 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1910 * @param htim TIM handle
1911 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1912 * This parameter can be one of the following values:
1913 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1914 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1915 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1916 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1917 * @arg TIM_TS_ITR4: Internal trigger 4 selected
1918 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1919 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1920 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1921 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1922 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1923 * @arg TIM_TS_NONE: No trigger is needed
1924 * @param CommutationSource the Commutation Event source
1925 * This parameter can be one of the following values:
1926 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1927 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1928 * @retval HAL status
1929 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1930 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1931 uint32_t CommutationSource)
1932 {
1933 /* Check the parameters */
1934 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1935 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1936
1937 __HAL_LOCK(htim);
1938
1939 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1940 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1941 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1942 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1943 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
1944 {
1945 /* Select the Input trigger */
1946 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1947 htim->Instance->SMCR |= InputTrigger;
1948 }
1949
1950 /* Select the Capture Compare preload feature */
1951 htim->Instance->CR2 |= TIM_CR2_CCPC;
1952 /* Select the Commutation event source */
1953 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1954 htim->Instance->CR2 |= CommutationSource;
1955
1956 /* Disable Commutation Interrupt */
1957 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1958
1959 /* Disable Commutation DMA request */
1960 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1961
1962 __HAL_UNLOCK(htim);
1963
1964 return HAL_OK;
1965 }
1966
1967 /**
1968 * @brief Configure the TIM commutation event sequence with interrupt.
1969 * @note This function is mandatory to use the commutation event in order to
1970 * update the configuration at each commutation detection on the TRGI input of the Timer,
1971 * the typical use of this feature is with the use of another Timer(interface Timer)
1972 * configured in Hall sensor interface, this interface Timer will generate the
1973 * commutation at its TRGO output (connected to Timer used in this function) each time
1974 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1975 * @param htim TIM handle
1976 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1977 * This parameter can be one of the following values:
1978 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1979 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1980 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1981 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1982 * @arg TIM_TS_ITR4: Internal trigger 4 selected
1983 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1984 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1985 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1986 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1987 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1988 * @arg TIM_TS_NONE: No trigger is needed
1989 * @param CommutationSource the Commutation Event source
1990 * This parameter can be one of the following values:
1991 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1992 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1993 * @retval HAL status
1994 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1995 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1996 uint32_t CommutationSource)
1997 {
1998 /* Check the parameters */
1999 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2000 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2001
2002 __HAL_LOCK(htim);
2003
2004 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2005 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2006 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2007 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2008 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2009 {
2010 /* Select the Input trigger */
2011 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2012 htim->Instance->SMCR |= InputTrigger;
2013 }
2014
2015 /* Select the Capture Compare preload feature */
2016 htim->Instance->CR2 |= TIM_CR2_CCPC;
2017 /* Select the Commutation event source */
2018 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2019 htim->Instance->CR2 |= CommutationSource;
2020
2021 /* Disable Commutation DMA request */
2022 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
2023
2024 /* Enable the Commutation Interrupt */
2025 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
2026
2027 __HAL_UNLOCK(htim);
2028
2029 return HAL_OK;
2030 }
2031
2032 /**
2033 * @brief Configure the TIM commutation event sequence with DMA.
2034 * @note This function is mandatory to use the commutation event in order to
2035 * update the configuration at each commutation detection on the TRGI input of the Timer,
2036 * the typical use of this feature is with the use of another Timer(interface Timer)
2037 * configured in Hall sensor interface, this interface Timer will generate the
2038 * commutation at its TRGO output (connected to Timer used in this function) each time
2039 * the TI1 of the Interface Timer detect a commutation at its input TI1.
2040 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
2041 * @param htim TIM handle
2042 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2043 * This parameter can be one of the following values:
2044 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2045 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2046 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2047 * @arg TIM_TS_ITR3: Internal trigger 3 selected
2048 * @arg TIM_TS_ITR4: Internal trigger 4 selected
2049 * @arg TIM_TS_ITR5: Internal trigger 5 selected
2050 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2051 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2052 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2053 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2054 * @arg TIM_TS_NONE: No trigger is needed
2055 * @param CommutationSource the Commutation Event source
2056 * This parameter can be one of the following values:
2057 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2058 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2059 * @retval HAL status
2060 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2061 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2062 uint32_t CommutationSource)
2063 {
2064 /* Check the parameters */
2065 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2066 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2067
2068 __HAL_LOCK(htim);
2069
2070 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2071 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2072 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2073 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2074 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2075 {
2076 /* Select the Input trigger */
2077 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2078 htim->Instance->SMCR |= InputTrigger;
2079 }
2080
2081 /* Select the Capture Compare preload feature */
2082 htim->Instance->CR2 |= TIM_CR2_CCPC;
2083 /* Select the Commutation event source */
2084 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2085 htim->Instance->CR2 |= CommutationSource;
2086
2087 /* Enable the Commutation DMA Request */
2088 /* Set the DMA Commutation Callback */
2089 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
2090 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
2091 /* Set the DMA error callback */
2092 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
2093
2094 /* Disable Commutation Interrupt */
2095 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
2096
2097 /* Enable the Commutation DMA Request */
2098 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
2099
2100 __HAL_UNLOCK(htim);
2101
2102 return HAL_OK;
2103 }
2104
2105 /**
2106 * @brief Configures the TIM in master mode.
2107 * @param htim TIM handle.
2108 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
2109 * contains the selected trigger output (TRGO) and the Master/Slave
2110 * mode.
2111 * @retval HAL status
2112 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)2113 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2114 const TIM_MasterConfigTypeDef *sMasterConfig)
2115 {
2116 uint32_t tmpcr2;
2117 uint32_t tmpsmcr;
2118
2119 /* Check the parameters */
2120 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2121 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2122 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2123
2124 /* Check input state */
2125 __HAL_LOCK(htim);
2126
2127 /* Change the handler state */
2128 htim->State = HAL_TIM_STATE_BUSY;
2129
2130 /* Get the TIMx CR2 register value */
2131 tmpcr2 = htim->Instance->CR2;
2132
2133 /* Get the TIMx SMCR register value */
2134 tmpsmcr = htim->Instance->SMCR;
2135
2136 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2137 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2138 {
2139 /* Check the parameters */
2140 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2141
2142 /* Clear the MMS2 bits */
2143 tmpcr2 &= ~TIM_CR2_MMS2;
2144 /* Select the TRGO2 source*/
2145 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2146 }
2147
2148 /* Reset the MMS Bits */
2149 tmpcr2 &= ~TIM_CR2_MMS;
2150 /* Select the TRGO source */
2151 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2152
2153 /* Update TIMx CR2 */
2154 htim->Instance->CR2 = tmpcr2;
2155
2156 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2157 {
2158 /* Reset the MSM Bit */
2159 tmpsmcr &= ~TIM_SMCR_MSM;
2160 /* Set master mode */
2161 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2162
2163 /* Update TIMx SMCR */
2164 htim->Instance->SMCR = tmpsmcr;
2165 }
2166
2167 /* Change the htim state */
2168 htim->State = HAL_TIM_STATE_READY;
2169
2170 __HAL_UNLOCK(htim);
2171
2172 return HAL_OK;
2173 }
2174
2175 /**
2176 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2177 * and the AOE(automatic output enable).
2178 * @param htim TIM handle
2179 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2180 * contains the BDTR Register configuration information for the TIM peripheral.
2181 * @note Interrupts can be generated when an active level is detected on the
2182 * break input, the break 2 input or the system break input. Break
2183 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2184 * @retval HAL status
2185 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2186 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2187 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2188 {
2189 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2190 uint32_t tmpbdtr = 0U;
2191
2192 /* Check the parameters */
2193 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2194 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2195 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2196 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2197 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2198 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2199 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2200 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2201 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2202
2203 /* Check input state */
2204 __HAL_LOCK(htim);
2205
2206 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2207 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2208
2209 /* Set the BDTR bits */
2210 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2211 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2212 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2213 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2214 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2215 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2216 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2217 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2218
2219 if (IS_TIM_BREAK_INSTANCE(htim->Instance))
2220 {
2221 /* Check the parameters */
2222 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2223
2224 /* Set BREAK AF mode */
2225 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2226 }
2227
2228 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2229 {
2230 /* Check the parameters */
2231 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2232 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2233 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2234
2235 /* Set the BREAK2 input related BDTR bits */
2236 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2237 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2238 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2239
2240 if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
2241 {
2242 /* Check the parameters */
2243 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2244
2245 /* Set BREAK2 AF mode */
2246 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2247 }
2248 }
2249
2250 /* Set TIMx_BDTR */
2251 htim->Instance->BDTR = tmpbdtr;
2252
2253 __HAL_UNLOCK(htim);
2254
2255 return HAL_OK;
2256 }
2257
2258 /**
2259 * @brief Configures the break input source.
2260 * @param htim TIM handle.
2261 * @param BreakInput Break input to configure
2262 * This parameter can be one of the following values:
2263 * @arg TIM_BREAKINPUT_BRK: Timer break input
2264 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2265 * @param sBreakInputConfig Break input source configuration
2266 * @retval HAL status
2267 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2268 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2269 uint32_t BreakInput,
2270 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2271
2272 {
2273 HAL_StatusTypeDef status = HAL_OK;
2274 uint32_t tmporx;
2275 uint32_t bkin_enable_mask;
2276 uint32_t bkin_polarity_mask;
2277 uint32_t bkin_enable_bitpos;
2278 uint32_t bkin_polarity_bitpos;
2279
2280 /* Check the parameters */
2281 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2282 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2283 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2284 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2285 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_MDF1)
2286 {
2287 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2288 }
2289
2290 /* Check input state */
2291 __HAL_LOCK(htim);
2292
2293 switch (sBreakInputConfig->Source)
2294 {
2295 case TIM_BREAKINPUTSOURCE_BKIN:
2296 {
2297 bkin_enable_mask = TIM1_AF1_BKINE;
2298 bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
2299 bkin_polarity_mask = TIM1_AF1_BKINP;
2300 bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
2301 break;
2302 }
2303 case TIM_BREAKINPUTSOURCE_COMP1:
2304 {
2305 bkin_enable_mask = TIM1_AF1_BKCMP1E;
2306 bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
2307 bkin_polarity_mask = TIM1_AF1_BKCMP1P;
2308 bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
2309 break;
2310 }
2311 case TIM_BREAKINPUTSOURCE_COMP2:
2312 {
2313 bkin_enable_mask = TIM1_AF1_BKCMP2E;
2314 bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
2315 bkin_polarity_mask = TIM1_AF1_BKCMP2P;
2316 bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
2317 break;
2318 }
2319 case TIM_BREAKINPUTSOURCE_MDF1:
2320 {
2321 bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
2322 bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos;
2323 /* No polarity bit for MDF. Variable bkin_polarity_mask keeps its default value 0 */
2324 bkin_polarity_mask = 0U;
2325 bkin_polarity_bitpos = 0U;
2326 break;
2327 }
2328
2329 default:
2330 {
2331 bkin_enable_mask = 0U;
2332 bkin_polarity_mask = 0U;
2333 bkin_enable_bitpos = 0U;
2334 bkin_polarity_bitpos = 0U;
2335 break;
2336 }
2337 }
2338
2339 switch (BreakInput)
2340 {
2341 case TIM_BREAKINPUT_BRK:
2342 {
2343 /* Get the TIMx_AF1 register value */
2344 tmporx = htim->Instance->AF1;
2345
2346 /* Enable the break input */
2347 tmporx &= ~bkin_enable_mask;
2348 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2349
2350 /* Set the break input polarity */
2351 tmporx &= ~bkin_polarity_mask;
2352 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2353
2354 /* Set TIMx_AF1 */
2355 htim->Instance->AF1 = tmporx;
2356 break;
2357 }
2358 case TIM_BREAKINPUT_BRK2:
2359 {
2360 /* Get the TIMx_AF2 register value */
2361 tmporx = htim->Instance->AF2;
2362
2363 /* Enable the break input */
2364 tmporx &= ~bkin_enable_mask;
2365 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2366
2367 /* Set the break input polarity */
2368 tmporx &= ~bkin_polarity_mask;
2369 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2370
2371 /* Set TIMx_AF2 */
2372 htim->Instance->AF2 = tmporx;
2373 break;
2374 }
2375 default:
2376 status = HAL_ERROR;
2377 break;
2378 }
2379
2380 __HAL_UNLOCK(htim);
2381
2382 return status;
2383 }
2384
2385 /**
2386 * @brief Configures the TIMx Remapping input capabilities.
2387 * @param htim TIM handle.
2388 * @param Remap specifies the TIM remapping source.
2389 * For TIM1, the parameter can take one of the following values:
2390 * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
2391 * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output
2392 * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output
2393 * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI
2394 * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS
2395 * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1_ETR is connected to ADC2 AWD2 (*)
2396 * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1_ETR is connected to ADC2 AWD3 (*)
2397 * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
2398 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
2399 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
2400 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1
2401 * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2
2402 * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3
2403 * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1_ETR is connected to ADC2 AWD1 (*)
2404 *
2405 * For TIM2, the parameter can take one of the following values:
2406 * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
2407 * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output
2408 * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output
2409 * @arg TIM_TIM2_ETR_MSIK TIM2 ETR is connected to MSIK
2410 * @arg TIM_TIM2_ETR_HSI TIM2 ETR is connected to HSI
2411 * @arg TIM_TIM2_ETR_MSIS TIM2_ETR is connected to MSIS
2412 * @arg TIM_TIM2_ETR_DCMI_VSYNC TIM2_ETR is connected to DCMI VSYNC (*)
2413 * @arg TIM_TIM2_ETR_LTDC_VSYNC TIM2_ETR is connected to LTDC_VSYNC (*)
2414 * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
2415 * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin
2416 * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin
2417 * @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE
2418 * @arg TIM_TIM2_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*)
2419 * @arg TIM_TIM2_ETR_DCMI_HSYNC TIM2_ETR is connected to DCMI HSYNC (*)
2420 * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2_ETR is connected to LTDC HSYNC (*)
2421 *
2422 * For TIM3, the parameter can take one of the following values:
2423 * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
2424 * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output
2425 * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output
2426 * @arg TIM_TIM3_ETR_MSIK TIM3 ETR is connected to MSIK
2427 * @arg TIM_TIM3_ETR_HSI TIM3 ETR is connected to HSI
2428 * @arg TIM_TIM3_ETR_MSIS TIM3_ETR is connected to MSIS
2429 * @arg TIM_TIM3_ETR_DCMI_VSYNC TIM3_ETR is connected to DCMI VSYNC (*)
2430 * @arg TIM_TIM3_ETR_LTDC_VSYNC TIM3_ETR is connected to LTDC_VSYNC (*)
2431 * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
2432 * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin
2433 * @arg TIM_TIM3_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*)
2434 * @arg TIM_TIM3_ETR_ADC1_AWD1 TIM3 ETR is connected to ADC1 AWD1
2435 * @arg TIM_TIM3_ETR_ADC1_AWD2 TIM3 ETR is connected to ADC1 AWD2
2436 * @arg TIM_TIM3_ETR_ADC1_AWD3 TIM3 ETR is connected to ADC1 AWD3
2437 * @arg TIM_TIM3_ETR_DCMI_HSYNC TIM3_ETR is connected to DCMI HSYNC (*)
2438 * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC (*)
2439 *
2440 * For TIM4, the parameter can take one of the following values:
2441 * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
2442 * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output
2443 * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output
2444 * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK
2445 * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI
2446 * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS
2447 * @arg TIM_TIM4_ETR_DCMI_VSYNC TIM4_ETR is connected to DCMI VSYNC (*)
2448 * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC_VSYNC (*)
2449 * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
2450 * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin
2451 * @arg TIM_TIM4_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*)
2452 * @arg TIM_TIM4_ETR_ADC2_AWD1 TIM4_ETR is connected to ADC2 AWD1 (*)
2453 * @arg TIM_TIM4_ETR_ADC2_AWD2 TIM4_ETR is connected to ADC2 AWD2 (*)
2454 * @arg TIM_TIM4_ETR_ADC2_AWD3 TIM4_ETR is connected to ADC2 AWD3 (*)
2455 * @arg TIM_TIM4_ETR_DCMI_HSYNC TIM4_ETR is connected to DCMI HSYNC (*)
2456 * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC (*)
2457 *
2458 * For TIM5, the parameter can take one of the following values:
2459 * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO
2460 * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output
2461 * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output
2462 * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK
2463 * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI
2464 * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS
2465 * @arg TIM_TIM5_ETR_DCMI_VSYNC TIM5_ETR is connected to DCMI VSYNC (*)
2466 * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC_VSYNC (*)
2467 * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin
2468 * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin
2469 * @arg TIM_TIM5_ETR_DSI_TE TIM5_ETR is connected to DSI_TE (*)
2470 * @arg TIM_TIM5_ETR_DCMI_HSYNC TIM5_ETR is connected to DCMI HSYNC (*)
2471 * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC (*)
2472 *
2473 * For TIM8, the parameter can take one of the following values:
2474 * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
2475 * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output
2476 * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output
2477 * @arg TIM_TIM8_ETR_MSIK TIM8 ETR is connected to MSIK
2478 * @arg TIM_TIM8_ETR_HSI TIM8 ETR is connected to HSI
2479 * @arg TIM_TIM8_ETR_MSIS TIM8_ETR is connected to MSIS
2480 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8_ETR is connected to ADC2 AWD2 (*)
2481 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8_ETR is connected to ADC2 AWD3 (*)
2482 * @arg TIM_TIM8_ETR_ADC1_AWD1 TIM8 ETR is connected to ADC1 AWD1
2483 * @arg TIM_TIM8_ETR_ADC1_AWD2 TIM8 ETR is connected to ADC1 AWD2
2484 * @arg TIM_TIM8_ETR_ADC1_AWD3 TIM8 ETR is connected to ADC1 AWD3
2485 * @arg TIM_TIM8_ETR_ADC4_AWD1 TIM8 ETR is connected to ADC4 AWD1
2486 * @arg TIM_TIM8_ETR_ADC4_AWD2 TIM8 ETR is connected to ADC4 AWD2
2487 * @arg TIM_TIM8_ETR_ADC4_AWD3 TIM8 ETR is connected to ADC4 AWD3
2488 * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8_ETR is connected to ADC2 AWD1 (*)
2489 *
2490 * (*) Value not defined in all devices.
2491 *
2492 * @retval HAL status
2493 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2494 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2495 {
2496 /* Check parameters */
2497 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2498 assert_param(IS_TIM_REMAP(Remap));
2499
2500 __HAL_LOCK(htim);
2501
2502 MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
2503
2504 __HAL_UNLOCK(htim);
2505
2506 return HAL_OK;
2507 }
2508
2509 /**
2510 * @brief Select the timer input source
2511 * @param htim TIM handle.
2512 * @param Channel specifies the TIM Channel
2513 * This parameter can be one of the following values:
2514 * @arg TIM_CHANNEL_1: TI1 input channel
2515 * @arg TIM_CHANNEL_2: TI2 input channel
2516 * @arg TIM_CHANNEL_4: TIM Channel 4
2517 * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
2518 * For TIM1, the parameter is one of the following values:
2519 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2520 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2521 * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output
2522 *
2523 * For TIM2, the parameter is one of the following values:
2524 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2525 * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
2526 * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output
2527 * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
2528 * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
2529 * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output
2530 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2531 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2532 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
2533 *
2534 * For TIM3, the parameter is one of the following values:
2535 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2536 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2537 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
2538 * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
2539 * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
2540 * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP1 output
2541 *
2542 * For TIM4, the parameter is one of the following values:
2543 * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
2544 * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
2545 * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output
2546 * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
2547 * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output
2548 * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output
2549 *
2550 * For TIM5, the parameter is one of the following values:
2551 * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
2552 * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI
2553 * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE
2554 * @arg TIM_TIM5_TI1_RTC_WKUP: TIM5 TI1 is connected to RTC wakeup interrupt
2555 * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output
2556 * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output
2557 * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
2558 * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output
2559 * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output
2560 *
2561 * For TIM8, the parameter is one of the following values:
2562 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
2563 * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
2564 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
2565 *
2566 * For TIM15, the parameter is one of the following values:
2567 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2568 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
2569 * @arg TIM_TIM15_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
2570 * @arg TIM_TIM15_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
2571 * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
2572 * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
2573 * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
2574 * @arg TIM_TIM15_TI2_COMP2: TIM8 TI1 is connected to COMP2 output
2575 *
2576 * For TIM16, the parameter can have the following values:
2577 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2578 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
2579 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2580 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2581 * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt
2582 * @arg TIM_TIM16_TI1_HSE_DIV32: TIM16 TI1 is connected to HSE/32
2583 * @arg TIM_TIM16_TI1_MSIS_1024: TIM16 TI1 is connected to MSIS/1024
2584 * @arg TIM_TIM16_TI1_MSIS_4: TIM16 TI1 is connected to MSIS/4
2585 * @arg TIM_TIM16_TI1_HSI_256: TIM16 TI1 is connected to HSI/256
2586 *
2587 * For TIM17, the parameter can have the following values:
2588 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2589 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
2590 * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI
2591 * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE
2592 * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt
2593 * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32
2594 * @arg TIM_TIM17_TI1_MSIS_1024: TIM17 TI1 is connected to MSIS/024
2595 * @arg TIM_TIM17_TI1_MSIS_4: TIM17 TI1 is connected to MSIS/4
2596 * @arg TIM_TIM17_TI1_HSI_256: TIM17 TI1 is connected to HSI/256
2597 *
2598 * (*) Value not defined in all devices. \n
2599 * @retval HAL status
2600 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2601 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2602 {
2603 HAL_StatusTypeDef status = HAL_OK;
2604
2605 /* Check parameters */
2606 assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
2607 assert_param(IS_TIM_TISEL(TISelection));
2608
2609 __HAL_LOCK(htim);
2610
2611 switch (Channel)
2612 {
2613 case TIM_CHANNEL_1:
2614 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2615 break;
2616 case TIM_CHANNEL_2:
2617 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2618 break;
2619 case TIM_CHANNEL_4:
2620 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
2621 break;
2622 default:
2623 status = HAL_ERROR;
2624 break;
2625 }
2626
2627 __HAL_UNLOCK(htim);
2628
2629 return status;
2630 }
2631
2632 /**
2633 * @brief Group channel 5 and channel 1, 2 or 3
2634 * @param htim TIM handle.
2635 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2636 * This parameter can be any combination of the following values:
2637 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2638 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2639 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2640 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2641 * @retval HAL status
2642 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2643 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2644 {
2645 /* Check parameters */
2646 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2647 assert_param(IS_TIM_GROUPCH5(Channels));
2648
2649 /* Process Locked */
2650 __HAL_LOCK(htim);
2651
2652 htim->State = HAL_TIM_STATE_BUSY;
2653
2654 /* Clear GC5Cx bit fields */
2655 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2656
2657 /* Set GC5Cx bit fields */
2658 htim->Instance->CCR5 |= Channels;
2659
2660 /* Change the htim state */
2661 htim->State = HAL_TIM_STATE_READY;
2662
2663 __HAL_UNLOCK(htim);
2664
2665 return HAL_OK;
2666 }
2667
2668 /**
2669 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2670 * @param htim TIM handle.
2671 * @param BreakInput Break input to disarm
2672 * This parameter can be one of the following values:
2673 * @arg TIM_BREAKINPUT_BRK: Timer break input
2674 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2675 * @note The break input can be disarmed only when it is configured in
2676 * bidirectional mode and when when MOE is reset.
2677 * @note Purpose is to be able to have the input voltage back to high-state,
2678 * whatever the time constant on the output .
2679 * @retval HAL status
2680 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2681 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2682 {
2683 HAL_StatusTypeDef status = HAL_OK;
2684 uint32_t tmpbdtr;
2685
2686 /* Check the parameters */
2687 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2688 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2689
2690 switch (BreakInput)
2691 {
2692 case TIM_BREAKINPUT_BRK:
2693 {
2694 /* Check initial conditions */
2695 tmpbdtr = READ_REG(htim->Instance->BDTR);
2696 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2697 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2698 {
2699 /* Break input BRK is disarmed */
2700 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2701 }
2702 break;
2703 }
2704
2705 case TIM_BREAKINPUT_BRK2:
2706 {
2707 /* Check initial conditions */
2708 tmpbdtr = READ_REG(htim->Instance->BDTR);
2709 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2710 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2711 {
2712 /* Break input BRK is disarmed */
2713 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2714 }
2715 break;
2716 }
2717 default:
2718 status = HAL_ERROR;
2719 break;
2720 }
2721
2722 return status;
2723 }
2724
2725 /**
2726 * @brief Arm the designated break input (when it operates in bidirectional mode).
2727 * @param htim TIM handle.
2728 * @param BreakInput Break input to arm
2729 * This parameter can be one of the following values:
2730 * @arg TIM_BREAKINPUT_BRK: Timer break input
2731 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2732 * @note Arming is possible at anytime, even if fault is present.
2733 * @note Break input is automatically armed as soon as MOE bit is set.
2734 * @retval HAL status
2735 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2736 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2737 {
2738 HAL_StatusTypeDef status = HAL_OK;
2739 uint32_t tickstart;
2740
2741 /* Check the parameters */
2742 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2743 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2744
2745 switch (BreakInput)
2746 {
2747 case TIM_BREAKINPUT_BRK:
2748 {
2749 /* Check initial conditions */
2750 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2751 {
2752 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2753 /* Init tickstart for timeout management */
2754 tickstart = HAL_GetTick();
2755 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2756 {
2757 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2758 {
2759 /* New check to avoid false timeout detection in case of preemption */
2760 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2761 {
2762 return HAL_TIMEOUT;
2763 }
2764 }
2765 }
2766 }
2767 break;
2768 }
2769
2770 case TIM_BREAKINPUT_BRK2:
2771 {
2772 /* Check initial conditions */
2773 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2774 {
2775 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2776 /* Init tickstart for timeout management */
2777 tickstart = HAL_GetTick();
2778 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2779 {
2780 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2781 {
2782 /* New check to avoid false timeout detection in case of preemption */
2783 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2784 {
2785 return HAL_TIMEOUT;
2786 }
2787 }
2788 }
2789 }
2790 break;
2791 }
2792 default:
2793 status = HAL_ERROR;
2794 break;
2795 }
2796
2797 return status;
2798 }
2799
2800 /**
2801 * @brief Enable dithering
2802 * @param htim TIM handle
2803 * @note Main usage is PWM mode
2804 * @note This function must be called when timer is stopped or disabled (CEN =0)
2805 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2806 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2807 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2808 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2809 * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
2810 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2811 * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
2812 * can be used to calculate period (ARR) and delay (CCRx) value.
2813 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2814 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2815 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2816 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2817 * @retval HAL status
2818 */
HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef * htim)2819 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
2820 {
2821 /* Check the parameters */
2822 assert_param(IS_TIM_INSTANCE(htim->Instance));
2823
2824 SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2825 return HAL_OK;
2826 }
2827
2828 /**
2829 * @brief Disable dithering
2830 * @param htim TIM handle
2831 * @note This function must be called when timer is stopped or disabled (CEN =0)
2832 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2833 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2834 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2835 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2836 * - ARR and CCRx values are limited to 0xFFEF in dithering mode
2837 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2838 * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2839 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2840 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2841 * @retval HAL status
2842 */
HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef * htim)2843 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
2844 {
2845 /* Check the parameters */
2846 assert_param(IS_TIM_INSTANCE(htim->Instance));
2847
2848 CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2849 return HAL_OK;
2850 }
2851
2852 /**
2853 * @brief Initializes the pulse on compare pulse width and pulse prescaler
2854 * @param htim TIM Output Compare handle
2855 * @param PulseWidthPrescaler Pulse width prescaler
2856 * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
2857 * @param PulseWidth Pulse width
2858 * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2859 * @retval HAL status
2860 */
HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef * htim,uint32_t PulseWidthPrescaler,uint32_t PulseWidth)2861 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
2862 uint32_t PulseWidthPrescaler,
2863 uint32_t PulseWidth)
2864 {
2865 uint32_t tmpecr;
2866
2867 /* Check the parameters */
2868 assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
2869 assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
2870 assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
2871
2872 /* Process Locked */
2873 __HAL_LOCK(htim);
2874
2875 /* Set the TIM state */
2876 htim->State = HAL_TIM_STATE_BUSY;
2877
2878 /* Get the TIMx ECR register value */
2879 tmpecr = htim->Instance->ECR;
2880 /* Reset the Pulse width prescaler and the Pulse width */
2881 tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
2882 /* Set the Pulse width prescaler and Pulse width*/
2883 tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
2884 tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
2885 /* Write to TIMx ECR */
2886 htim->Instance->ECR = tmpecr;
2887
2888 /* Change the TIM state */
2889 htim->State = HAL_TIM_STATE_READY;
2890
2891 /* Release Lock */
2892 __HAL_UNLOCK(htim);
2893
2894 return HAL_OK;
2895 }
2896
2897 /**
2898 * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
2899 * @param htim TIM handle
2900 * @param Source Source of slave mode selection preload
2901 * This parameter can be one of the following values:
2902 * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
2903 * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
2904 * @retval HAL status
2905 */
HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef * htim,uint32_t Source)2906 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
2907 {
2908 /* Check the parameters */
2909 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2910 assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
2911
2912 MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
2913 return HAL_OK;
2914 }
2915
2916 /**
2917 * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2918 * @param htim TIM handle
2919 * @retval HAL status
2920 */
HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef * htim)2921 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
2922 {
2923 /* Check the parameters */
2924 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2925
2926 SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2927 return HAL_OK;
2928 }
2929
2930 /**
2931 * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2932 * @param htim TIM handle
2933 * @retval HAL status
2934 */
HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef * htim)2935 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
2936 {
2937 /* Check the parameters */
2938 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2939
2940 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2941 return HAL_OK;
2942 }
2943
2944 /**
2945 * @brief Enable deadtime preload
2946 * @param htim TIM handle
2947 * @retval HAL status
2948 */
HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef * htim)2949 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
2950 {
2951 /* Check the parameters */
2952 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2953
2954 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2955 return HAL_OK;
2956 }
2957
2958 /**
2959 * @brief Disable deadtime preload
2960 * @param htim TIM handle
2961 * @retval HAL status
2962 */
HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef * htim)2963 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
2964 {
2965 /* Check the parameters */
2966 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2967
2968 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2969 return HAL_OK;
2970 }
2971
2972 /**
2973 * @brief Configure deadtime
2974 * @param htim TIM handle
2975 * @param Deadtime Deadtime value
2976 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2977 * @retval HAL status
2978 */
HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef * htim,uint32_t Deadtime)2979 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
2980 {
2981 /* Check the parameters */
2982 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2983 assert_param(IS_TIM_DEADTIME(Deadtime));
2984
2985 MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
2986 return HAL_OK;
2987 }
2988
2989 /**
2990 * @brief Configure asymmetrical deadtime
2991 * @param htim TIM handle
2992 * @param FallingDeadtime Falling edge deadtime value
2993 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2994 * @retval HAL status
2995 */
HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef * htim,uint32_t FallingDeadtime)2996 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
2997 {
2998 /* Check the parameters */
2999 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3000 assert_param(IS_TIM_DEADTIME(FallingDeadtime));
3001
3002 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
3003 return HAL_OK;
3004 }
3005
3006 /**
3007 * @brief Enable asymmetrical deadtime
3008 * @param htim TIM handle
3009 * @retval HAL status
3010 */
HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3011 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3012 {
3013 /* Check the parameters */
3014 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3015
3016 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3017 return HAL_OK;
3018 }
3019
3020 /**
3021 * @brief Disable asymmetrical deadtime
3022 * @param htim TIM handle
3023 * @retval HAL status
3024 */
HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3025 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3026 {
3027 /* Check the parameters */
3028 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3029
3030 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3031 return HAL_OK;
3032 }
3033
3034 /**
3035 * @brief Configures the encoder index.
3036 * @note warning in case of encoder mode clock plus direction
3037 * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3038 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
3039 * @param htim TIM handle.
3040 * @param sEncoderIndexConfig Encoder index configuration
3041 * @retval HAL status
3042 */
HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef * htim,TIMEx_EncoderIndexConfigTypeDef * sEncoderIndexConfig)3043 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
3044 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
3045 {
3046 /* Check the parameters */
3047 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3048 assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
3049 assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
3050 assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
3051 assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking));
3052 assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
3053 assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
3054 assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
3055
3056 /* Process Locked */
3057 __HAL_LOCK(htim);
3058
3059 /* Configures the TIMx External Trigger (ETR) which is used as Index input */
3060 TIM_ETR_SetConfig(htim->Instance,
3061 sEncoderIndexConfig->Prescaler,
3062 sEncoderIndexConfig->Polarity,
3063 sEncoderIndexConfig->Filter);
3064
3065 /* Configures the encoder index */
3066 #if defined (STM32U575xx) || defined (STM32U585xx)
3067 if (HAL_GetREVID() >= REV_ID_B) /* supported in cut2 */
3068 {
3069 MODIFY_REG(htim->Instance->ECR,
3070 TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3071 (sEncoderIndexConfig->Direction |
3072 (sEncoderIndexConfig->Blanking) |
3073 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3074 sEncoderIndexConfig->Position |
3075 TIM_ECR_IE));
3076 }
3077 else
3078 {
3079 MODIFY_REG(htim->Instance->ECR,
3080 TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3081 (sEncoderIndexConfig->Direction |
3082 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3083 sEncoderIndexConfig->Position |
3084 TIM_ECR_IE));
3085 }
3086 #else
3087 MODIFY_REG(htim->Instance->ECR,
3088 TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3089 (sEncoderIndexConfig->Direction |
3090 (sEncoderIndexConfig->Blanking) |
3091 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3092 sEncoderIndexConfig->Position |
3093 TIM_ECR_IE));
3094 #endif /* STM32U575xx || STM32U585xx */
3095
3096 __HAL_UNLOCK(htim);
3097
3098 return HAL_OK;
3099 }
3100
3101 /**
3102 * @brief Enable encoder index
3103 * @param htim TIM handle
3104 * @retval HAL status
3105 */
HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef * htim)3106 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
3107 {
3108 /* Check the parameters */
3109 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3110
3111 SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
3112 return HAL_OK;
3113 }
3114
3115 /**
3116 * @brief Disable encoder index
3117 * @param htim TIM handle
3118 * @retval HAL status
3119 */
HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef * htim)3120 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
3121 {
3122 /* Check the parameters */
3123 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3124
3125 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
3126 return HAL_OK;
3127 }
3128
3129 /**
3130 * @brief Enable encoder first index
3131 * @param htim TIM handle
3132 * @retval HAL status
3133 */
HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef * htim)3134 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3135 {
3136 /* Check the parameters */
3137 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3138
3139 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3140 return HAL_OK;
3141 }
3142
3143 /**
3144 * @brief Disable encoder first index
3145 * @param htim TIM handle
3146 * @retval HAL status
3147 */
HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef * htim)3148 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3149 {
3150 /* Check the parameters */
3151 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3152
3153 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3154 return HAL_OK;
3155 }
3156
3157 /**
3158 * @}
3159 */
3160
3161 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
3162 * @brief Extended Callbacks functions
3163 *
3164 @verbatim
3165 ==============================================================================
3166 ##### Extended Callbacks functions #####
3167 ==============================================================================
3168 [..]
3169 This section provides Extended TIM callback functions:
3170 (+) Timer Commutation callback
3171 (+) Timer Break callback
3172
3173 @endverbatim
3174 * @{
3175 */
3176
3177 /**
3178 * @brief Hall commutation changed callback in non-blocking mode
3179 * @param htim TIM handle
3180 * @retval None
3181 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)3182 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
3183 {
3184 /* Prevent unused argument(s) compilation warning */
3185 UNUSED(htim);
3186
3187 /* NOTE : This function should not be modified, when the callback is needed,
3188 the HAL_TIMEx_CommutCallback could be implemented in the user file
3189 */
3190 }
3191 /**
3192 * @brief Hall commutation changed half complete callback in non-blocking mode
3193 * @param htim TIM handle
3194 * @retval None
3195 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)3196 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
3197 {
3198 /* Prevent unused argument(s) compilation warning */
3199 UNUSED(htim);
3200
3201 /* NOTE : This function should not be modified, when the callback is needed,
3202 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
3203 */
3204 }
3205
3206 /**
3207 * @brief Hall Break detection callback in non-blocking mode
3208 * @param htim TIM handle
3209 * @retval None
3210 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)3211 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
3212 {
3213 /* Prevent unused argument(s) compilation warning */
3214 UNUSED(htim);
3215
3216 /* NOTE : This function should not be modified, when the callback is needed,
3217 the HAL_TIMEx_BreakCallback could be implemented in the user file
3218 */
3219 }
3220
3221 /**
3222 * @brief Hall Break2 detection callback in non blocking mode
3223 * @param htim: TIM handle
3224 * @retval None
3225 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)3226 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
3227 {
3228 /* Prevent unused argument(s) compilation warning */
3229 UNUSED(htim);
3230
3231 /* NOTE : This function Should not be modified, when the callback is needed,
3232 the HAL_TIMEx_Break2Callback could be implemented in the user file
3233 */
3234 }
3235
3236 /**
3237 * @brief Encoder index callback in non-blocking mode
3238 * @param htim TIM handle
3239 * @retval None
3240 */
HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef * htim)3241 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
3242 {
3243 /* Prevent unused argument(s) compilation warning */
3244 UNUSED(htim);
3245
3246 /* NOTE : This function should not be modified, when the callback is needed,
3247 the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
3248 */
3249 }
3250
3251 /**
3252 * @brief Direction change callback in non-blocking mode
3253 * @param htim TIM handle
3254 * @retval None
3255 */
HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef * htim)3256 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
3257 {
3258 /* Prevent unused argument(s) compilation warning */
3259 UNUSED(htim);
3260
3261 /* NOTE : This function should not be modified, when the callback is needed,
3262 the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
3263 */
3264 }
3265
3266 /**
3267 * @brief Index error callback in non-blocking mode
3268 * @param htim TIM handle
3269 * @retval None
3270 */
HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef * htim)3271 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
3272 {
3273 /* Prevent unused argument(s) compilation warning */
3274 UNUSED(htim);
3275
3276 /* NOTE : This function should not be modified, when the callback is needed,
3277 the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
3278 */
3279 }
3280
3281 /**
3282 * @brief Transition error callback in non-blocking mode
3283 * @param htim TIM handle
3284 * @retval None
3285 */
HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef * htim)3286 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
3287 {
3288 /* Prevent unused argument(s) compilation warning */
3289 UNUSED(htim);
3290
3291 /* NOTE : This function should not be modified, when the callback is needed,
3292 the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
3293 */
3294 }
3295
3296 /**
3297 * @}
3298 */
3299
3300 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
3301 * @brief Extended Peripheral State functions
3302 *
3303 @verbatim
3304 ==============================================================================
3305 ##### Extended Peripheral State functions #####
3306 ==============================================================================
3307 [..]
3308 This subsection permits to get in run-time the status of the peripheral
3309 and the data flow.
3310
3311 @endverbatim
3312 * @{
3313 */
3314
3315 /**
3316 * @brief Return the TIM Hall Sensor interface handle state.
3317 * @param htim TIM Hall Sensor handle
3318 * @retval HAL state
3319 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)3320 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
3321 {
3322 return htim->State;
3323 }
3324
3325 /**
3326 * @brief Return actual state of the TIM complementary channel.
3327 * @param htim TIM handle
3328 * @param ChannelN TIM Complementary channel
3329 * This parameter can be one of the following values:
3330 * @arg TIM_CHANNEL_1: TIM Channel 1
3331 * @arg TIM_CHANNEL_2: TIM Channel 2
3332 * @arg TIM_CHANNEL_3: TIM Channel 3
3333 * @arg TIM_CHANNEL_4: TIM Channel 4
3334 * @retval TIM Complementary channel state
3335 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)3336 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
3337 {
3338 HAL_TIM_ChannelStateTypeDef channel_state;
3339
3340 /* Check the parameters */
3341 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
3342
3343 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
3344
3345 return channel_state;
3346 }
3347 /**
3348 * @}
3349 */
3350
3351 /**
3352 * @}
3353 */
3354
3355 /* Private functions ---------------------------------------------------------*/
3356 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
3357 * @{
3358 */
3359
3360 /**
3361 * @brief TIM DMA Commutation callback.
3362 * @param hdma pointer to DMA handle.
3363 * @retval None
3364 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)3365 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
3366 {
3367 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3368
3369 /* Change the htim state */
3370 htim->State = HAL_TIM_STATE_READY;
3371
3372 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3373 htim->CommutationCallback(htim);
3374 #else
3375 HAL_TIMEx_CommutCallback(htim);
3376 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3377 }
3378
3379 /**
3380 * @brief TIM DMA Commutation half complete callback.
3381 * @param hdma pointer to DMA handle.
3382 * @retval None
3383 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)3384 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
3385 {
3386 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3387
3388 /* Change the htim state */
3389 htim->State = HAL_TIM_STATE_READY;
3390
3391 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3392 htim->CommutationHalfCpltCallback(htim);
3393 #else
3394 HAL_TIMEx_CommutHalfCpltCallback(htim);
3395 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3396 }
3397
3398
3399 /**
3400 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
3401 * @param hdma pointer to DMA handle.
3402 * @retval None
3403 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)3404 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
3405 {
3406 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3407
3408 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3409 {
3410 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3411 }
3412 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3413 {
3414 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3415 }
3416 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3417 {
3418 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3419 }
3420 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3421 {
3422 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3423 }
3424 else
3425 {
3426 /* nothing to do */
3427 }
3428
3429 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3430 htim->PWM_PulseFinishedCallback(htim);
3431 #else
3432 HAL_TIM_PWM_PulseFinishedCallback(htim);
3433 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3434
3435 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3436 }
3437
3438 /**
3439 * @brief TIM DMA error callback (complementary channel)
3440 * @param hdma pointer to DMA handle.
3441 * @retval None
3442 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)3443 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
3444 {
3445 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3446
3447 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3448 {
3449 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3450 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3451 }
3452 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3453 {
3454 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3455 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3456 }
3457 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3458 {
3459 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3460 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3461 }
3462 else
3463 {
3464 /* nothing to do */
3465 }
3466
3467 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3468 htim->ErrorCallback(htim);
3469 #else
3470 HAL_TIM_ErrorCallback(htim);
3471 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3472
3473 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3474 }
3475
3476 /**
3477 * @brief Enables or disables the TIM Capture Compare Channel xN.
3478 * @param TIMx to select the TIM peripheral
3479 * @param Channel specifies the TIM Channel
3480 * This parameter can be one of the following values:
3481 * @arg TIM_CHANNEL_1: TIM Channel 1
3482 * @arg TIM_CHANNEL_2: TIM Channel 2
3483 * @arg TIM_CHANNEL_3: TIM Channel 3
3484 * @arg TIM_CHANNEL_4: TIM Channel 4
3485 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
3486 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
3487 * @retval None
3488 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)3489 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
3490 {
3491 uint32_t tmp;
3492
3493 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
3494
3495 /* Reset the CCxNE Bit */
3496 TIMx->CCER &= ~tmp;
3497
3498 /* Set or reset the CCxNE Bit */
3499 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
3500 }
3501
3502 /**
3503 * @brief Enable HSE/32 .
3504 * @note This function should be called to enable the HSE/32 when it is selected as TIM17_TI1 or TIM16_TI1 input
3505 * source.
3506 * @param htim TIM handle.
3507 * @retval HAL status.
3508 */
HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef * htim)3509 HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim)
3510 {
3511 /* Check the parameters */
3512 assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance));
3513
3514 #if defined (STM32U575xx) || defined (STM32U585xx)
3515 /* The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16
3516 Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register */
3517 if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */
3518 {
3519 __HAL_RCC_TIM17_CLK_ENABLE();
3520 SET_BIT(TIM17->OR1, TIM_OR1_HSE32EN);
3521 }
3522 else
3523 {
3524 SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3525 }
3526 #else
3527 SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3528 #endif /* STM32U575xx || STM32U585xx */
3529
3530 return HAL_OK;
3531 }
3532
3533 /**
3534 * @brief Disable HSE/32 .
3535 * @note This function should be called to Disable the HSE/32 .
3536 * @param htim TIM handle.
3537 * @retval HAL status.
3538 */
HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef * htim)3539 HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim)
3540 {
3541 /* Check the parameters */
3542 assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance));
3543
3544 #if defined (STM32U575xx) || defined (STM32U585xx)
3545 if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */
3546 {
3547 __HAL_RCC_TIM17_CLK_ENABLE();
3548 CLEAR_BIT(TIM17->OR1, TIM_OR1_HSE32EN);
3549 }
3550 else
3551 {
3552 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3553 }
3554 #else
3555 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN);
3556 #endif /* STM32U575xx || STM32U585xx */
3557
3558 return HAL_OK;
3559 }
3560 /**
3561 * @}
3562 */
3563
3564 #endif /* HAL_TIM_MODULE_ENABLED */
3565 /**
3566 * @}
3567 */
3568
3569 /**
3570 * @}
3571 */
3572
