1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32G4xx_LL_TIM_H
21 #define __STM32G4xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x04U, /* 7: TIMx_CH4N */
55 0x38U, /* 8: TIMx_CH5 */
56 0x38U /* 9: TIMx_CH6 */
57
58 };
59
60 static const uint8_t SHIFT_TAB_OCxx[] =
61 {
62 0U, /* 0: OC1M, OC1FE, OC1PE */
63 0U, /* 1: - NA */
64 8U, /* 2: OC2M, OC2FE, OC2PE */
65 0U, /* 3: - NA */
66 0U, /* 4: OC3M, OC3FE, OC3PE */
67 0U, /* 5: - NA */
68 8U, /* 6: OC4M, OC4FE, OC4PE */
69 0U, /* 7: - NA */
70 0U, /* 8: OC5M, OC5FE, OC5PE */
71 8U /* 9: OC6M, OC6FE, OC6PE */
72 };
73
74 static const uint8_t SHIFT_TAB_ICxx[] =
75 {
76 0U, /* 0: CC1S, IC1PSC, IC1F */
77 0U, /* 1: - NA */
78 8U, /* 2: CC2S, IC2PSC, IC2F */
79 0U, /* 3: - NA */
80 0U, /* 4: CC3S, IC3PSC, IC3F */
81 0U, /* 5: - NA */
82 8U, /* 6: CC4S, IC4PSC, IC4F */
83 0U, /* 7: - NA */
84 0U, /* 8: - NA */
85 0U /* 9: - NA */
86 };
87
88 static const uint8_t SHIFT_TAB_CCxP[] =
89 {
90 0U, /* 0: CC1P */
91 2U, /* 1: CC1NP */
92 4U, /* 2: CC2P */
93 6U, /* 3: CC2NP */
94 8U, /* 4: CC3P */
95 10U, /* 5: CC3NP */
96 12U, /* 6: CC4P */
97 14U, /* 7: CC4NP */
98 16U, /* 8: CC5P */
99 20U /* 9: CC6P */
100 };
101
102 static const uint8_t SHIFT_TAB_OISx[] =
103 {
104 0U, /* 0: OIS1 */
105 1U, /* 1: OIS1N */
106 2U, /* 2: OIS2 */
107 3U, /* 3: OIS2N */
108 4U, /* 4: OIS3 */
109 5U, /* 5: OIS3N */
110 6U, /* 6: OIS4 */
111 7U, /* 7: OIS4N */
112 8U, /* 8: OIS5 */
113 10U /* 9: OIS6 */
114 };
115 /**
116 * @}
117 */
118
119 /* Private constants ---------------------------------------------------------*/
120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
121 * @{
122 */
123
124 /* Defines used for the bit position in the register and perform offsets */
125 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
126
127 /* Generic bit definitions for TIMx_AF1 register */
128 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
129 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
130
131
132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
133 #define DT_DELAY_1 ((uint8_t)0x7F)
134 #define DT_DELAY_2 ((uint8_t)0x3F)
135 #define DT_DELAY_3 ((uint8_t)0x1F)
136 #define DT_DELAY_4 ((uint8_t)0x1F)
137
138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
139 #define DT_RANGE_1 ((uint8_t)0x00)
140 #define DT_RANGE_2 ((uint8_t)0x80)
141 #define DT_RANGE_3 ((uint8_t)0xC0)
142 #define DT_RANGE_4 ((uint8_t)0xE0)
143
144 /** Legacy definitions for compatibility purpose
145 @cond 0
146 */
147 /**
148 @endcond
149 */
150
151 #define OCREF_CLEAR_SELECT_Pos (28U)
152 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */
153 /**
154 * @}
155 */
156
157 /* Private macros ------------------------------------------------------------*/
158 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
159 * @{
160 */
161 /** @brief Convert channel id into channel index.
162 * @param __CHANNEL__ This parameter can be one of the following values:
163 * @arg @ref LL_TIM_CHANNEL_CH1
164 * @arg @ref LL_TIM_CHANNEL_CH1N
165 * @arg @ref LL_TIM_CHANNEL_CH2
166 * @arg @ref LL_TIM_CHANNEL_CH2N
167 * @arg @ref LL_TIM_CHANNEL_CH3
168 * @arg @ref LL_TIM_CHANNEL_CH3N
169 * @arg @ref LL_TIM_CHANNEL_CH4
170 * @arg @ref LL_TIM_CHANNEL_CH4N
171 * @arg @ref LL_TIM_CHANNEL_CH5
172 * @arg @ref LL_TIM_CHANNEL_CH6
173 * @retval none
174 */
175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
176 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
185
186 /** @brief Calculate the deadtime sampling period(in ps).
187 * @param __TIMCLK__ timer input clock frequency (in Hz).
188 * @param __CKD__ This parameter can be one of the following values:
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
192 * @retval none
193 */
194 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
195 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
196 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
197 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
198 /**
199 * @}
200 */
201
202
203 /* Exported types ------------------------------------------------------------*/
204 #if defined(USE_FULL_LL_DRIVER)
205 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
206 * @{
207 */
208
209 /**
210 * @brief TIM Time Base configuration structure definition.
211 */
212 typedef struct
213 {
214 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
215 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
216
217 This feature can be modified afterwards using unitary function
218 @ref LL_TIM_SetPrescaler().*/
219
220 uint32_t CounterMode; /*!< Specifies the counter mode.
221 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetCounterMode().*/
225
226 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
227 Auto-Reload Register at the next update event.
228 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
229 Some timer instances may support 32 bits counters. In that case this parameter must
230 be a number between 0x0000 and 0xFFFFFFFF.
231
232 This feature can be modified afterwards using unitary function
233 @ref LL_TIM_SetAutoReload().*/
234
235 uint32_t ClockDivision; /*!< Specifies the clock division.
236 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetClockDivision().*/
240
241 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
242 reaches zero, an update event is generated and counting restarts
243 from the RCR value (N).
244 This means in PWM mode that (N+1) corresponds to:
245 - the number of PWM periods in edge-aligned mode
246 - the number of half PWM period in center-aligned mode
247 GP timers: this parameter must be a number between Min_Data = 0x00 and
248 Max_Data = 0xFF.
249 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
250 Max_Data = 0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 @ref LL_TIM_SetRepetitionCounter().*/
254 } LL_TIM_InitTypeDef;
255
256 /**
257 * @brief TIM Output Compare configuration structure definition.
258 */
259 typedef struct
260 {
261 uint32_t OCMode; /*!< Specifies the output mode.
262 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetMode().*/
266
267 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
268 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
269
270 This feature can be modified afterwards using unitary functions
271 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
272
273 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
274 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
275
276 This feature can be modified afterwards using unitary functions
277 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
278
279 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
280 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
281
282 This feature can be modified afterwards using unitary function
283 LL_TIM_OC_SetCompareCHx (x=1..6).*/
284
285 uint32_t OCPolarity; /*!< Specifies the output polarity.
286 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
287
288 This feature can be modified afterwards using unitary function
289 @ref LL_TIM_OC_SetPolarity().*/
290
291 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
292 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_OC_SetPolarity().*/
296
297
298 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
299 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
300
301 This feature can be modified afterwards using unitary function
302 @ref LL_TIM_OC_SetIdleState().*/
303
304 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetIdleState().*/
309 } LL_TIM_OC_InitTypeDef;
310
311 /**
312 * @brief TIM Input Capture configuration structure definition.
313 */
314
315 typedef struct
316 {
317
318 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
319 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
320
321 This feature can be modified afterwards using unitary function
322 @ref LL_TIM_IC_SetPolarity().*/
323
324 uint32_t ICActiveInput; /*!< Specifies the input.
325 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
326
327 This feature can be modified afterwards using unitary function
328 @ref LL_TIM_IC_SetActiveInput().*/
329
330 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
331 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetPrescaler().*/
335
336 uint32_t ICFilter; /*!< Specifies the input capture filter.
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetFilter().*/
341 } LL_TIM_IC_InitTypeDef;
342
343
344 /**
345 * @brief TIM Encoder interface configuration structure definition.
346 */
347 typedef struct
348 {
349 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
350 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_SetEncoderMode().*/
354
355 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
356 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetPolarity().*/
360
361 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
362 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetActiveInput().*/
366
367 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
368 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetPrescaler().*/
372
373 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
374 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetFilter().*/
378
379 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
380 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetPolarity().*/
384
385 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
386 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetActiveInput().*/
390
391 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
392 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetPrescaler().*/
396
397 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
398 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetFilter().*/
402
403 } LL_TIM_ENCODER_InitTypeDef;
404
405 /**
406 * @brief TIM Hall sensor interface configuration structure definition.
407 */
408 typedef struct
409 {
410
411 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
412 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
413
414 This feature can be modified afterwards using unitary function
415 @ref LL_TIM_IC_SetPolarity().*/
416
417 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
418 Prescaler must be set to get a maximum counter period longer than the
419 time interval between 2 consecutive changes on the Hall inputs.
420 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
421
422 This feature can be modified afterwards using unitary function
423 @ref LL_TIM_IC_SetPrescaler().*/
424
425 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
426 This parameter can be a value of
427 @ref TIM_LL_EC_IC_FILTER.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_IC_SetFilter().*/
431
432 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
433 A positive pulse (TRGO event) is generated with a programmable delay every time
434 a change occurs on the Hall inputs.
435 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
436
437 This feature can be modified afterwards using unitary function
438 @ref LL_TIM_OC_SetCompareCH2().*/
439 } LL_TIM_HALLSENSOR_InitTypeDef;
440
441 /**
442 * @brief BDTR (Break and Dead Time) structure definition
443 */
444 typedef struct
445 {
446 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
447 This parameter can be a value of @ref TIM_LL_EC_OSSR
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_SetOffStates()
451
452 @note This bit-field cannot be modified as long as LOCK level 2 has been
453 programmed. */
454
455 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
456 This parameter can be a value of @ref TIM_LL_EC_OSSI
457
458 This feature can be modified afterwards using unitary function
459 @ref LL_TIM_SetOffStates()
460
461 @note This bit-field cannot be modified as long as LOCK level 2 has been
462 programmed. */
463
464 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
465 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
466
467 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
468 register has been written, their content is frozen until the next reset.*/
469
470 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
471 switching-on of the outputs.
472 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
473
474 This feature can be modified afterwards using unitary function
475 @ref LL_TIM_OC_SetDeadTime()
476
477 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
478 programmed. */
479
480 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
482
483 This feature can be modified afterwards using unitary functions
484 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been
487 programmed. */
488
489 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
490 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
491
492 This feature can be modified afterwards using unitary function
493 @ref LL_TIM_ConfigBRK()
494
495 @note This bit-field can not be modified as long as LOCK level 1 has been
496 programmed. */
497
498 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
499 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
500
501 This feature can be modified afterwards using unitary function
502 @ref LL_TIM_ConfigBRK()
503
504 @note This bit-field can not be modified as long as LOCK level 1 has been
505 programmed. */
506
507 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
508 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
509
510 This feature can be modified afterwards using unitary functions
511 @ref LL_TIM_ConfigBRK()
512
513 @note Bidirectional break input is only supported by advanced timers instances.
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
523
524 @note This bit-field can not be modified as long as LOCK level 1 has been
525 programmed. */
526
527 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
528 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
529
530 This feature can be modified afterwards using unitary function
531 @ref LL_TIM_ConfigBRK2()
532
533 @note This bit-field can not be modified as long as LOCK level 1 has been
534 programmed. */
535
536 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
537 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
538
539 This feature can be modified afterwards using unitary function
540 @ref LL_TIM_ConfigBRK2()
541
542 @note This bit-field can not be modified as long as LOCK level 1 has been
543 programmed. */
544
545 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
546 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
547
548 This feature can be modified afterwards using unitary functions
549 @ref LL_TIM_ConfigBRK2()
550
551 @note Bidirectional break input is only supported by advanced timers instances.
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
557 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
561
562 @note This bit-field can not be modified as long as LOCK level 1 has been
563 programmed. */
564 } LL_TIM_BDTR_InitTypeDef;
565
566 /**
567 * @}
568 */
569 #endif /* USE_FULL_LL_DRIVER */
570
571 /* Exported constants --------------------------------------------------------*/
572 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
573 * @{
574 */
575
576 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
577 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
578 * @{
579 */
580 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
581 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
582 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
583 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
584 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
585 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
586 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
587 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
588 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
589 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
590 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
591 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
592 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
593 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
594 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
595 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
596 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
597 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
598 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
599 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
600 /**
601 * @}
602 */
603
604 #if defined(USE_FULL_LL_DRIVER)
605 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
606 * @{
607 */
608 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
609 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
615 * @{
616 */
617 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
618 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
624 * @{
625 */
626 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
627 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
628 /**
629 * @}
630 */
631 #endif /* USE_FULL_LL_DRIVER */
632
633 /** @defgroup TIM_LL_EC_IT IT Defines
634 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
635 * @{
636 */
637 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
638 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
639 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
640 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
641 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
642 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
643 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
644 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
645 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
646 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
647 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
648 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
654 * @{
655 */
656 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
657 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
663 * @{
664 */
665 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
666 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
672 * @{
673 */
674 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
675 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
676 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
677 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
678 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
684 * @{
685 */
686 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
687 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
688 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
694 * @{
695 */
696 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
697 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
703 * @{
704 */
705 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
706 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
712 * @{
713 */
714 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
715 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
716 /**
717 * @}
718 */
719
720 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
721 * @{
722 */
723 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
724 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
725 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
726 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_CHANNEL Channel
732 * @{
733 */
734 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
735 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
736 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
737 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
738 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
739 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
740 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
741 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
742 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
743 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
744 /**
745 * @}
746 */
747
748 #if defined(USE_FULL_LL_DRIVER)
749 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
750 * @{
751 */
752 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
753 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
754 /**
755 * @}
756 */
757 #endif /* USE_FULL_LL_DRIVER */
758
759 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
760 * @{
761 */
762 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
763 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
764 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
765 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
766 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
767 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
768 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
769 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
770 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
771 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
772 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
773 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
774 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
775 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
776 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
777 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
783 * @{
784 */
785 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
786 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
792 * @{
793 */
794 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
795 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
801 * @{
802 */
803 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
804 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
805 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
806 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
812 * @{
813 */
814 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
815 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
816 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
817 /**
818 * @}
819 */
820
821 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
822 * @{
823 */
824 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
825 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
826 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
827 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
828 /**
829 * @}
830 */
831
832 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
833 * @{
834 */
835 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
836 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
837 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
838 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
839 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
841 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
842 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
843 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
844 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
845 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
846 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
847 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
848 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
849 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
850 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
856 * @{
857 */
858 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
859 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
860 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
866 * @{
867 */
868 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
869 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
870 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
876 * @{
877 */
878 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
879 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
880 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
881 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
882 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
883 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
884 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
885 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
886 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
887 /**
888 * @}
889 */
890
891 /** @defgroup TIM_LL_EC_TRGO Trigger Output
892 * @{
893 */
894 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
895 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
896 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
897 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
898 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
899 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
900 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
901 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
902 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
903 /**
904 * @}
905 */
906
907 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
908 * @{
909 */
910 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
911 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
912 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
913 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
915 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
916 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
917 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
918 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
919 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
920 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
921 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
922 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
923 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
924 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
926 /**
927 * @}
928 */
929
930 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
931 * @{
932 */
933 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
934 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
935 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
936 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
937 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
938 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
939 the counter are controlled. */
940 /**
941 * @}
942 */
943
944 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
945 * @{
946 */
947 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
948 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
949 /**
950 * @}
951 */
952
953 /** @defgroup TIM_LL_EC_TS Trigger Selection
954 * @{
955 */
956 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
957 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
958 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
959 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
960 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
961 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
962 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
963 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
964 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
965 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
966 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
967 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
968 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
969 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
970 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
971 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
972 /**
973 * @}
974 */
975
976 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
977 * @{
978 */
979 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
980 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
981 /**
982 * @}
983 */
984
985 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
986 * @{
987 */
988 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
989 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
990 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
991 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
992 /**
993 * @}
994 */
995
996 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
997 * @{
998 */
999 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1000 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1001 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1002 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1003 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1004 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1005 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1006 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1007 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
1008 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
1009 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
1010 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1011 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
1012 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1013 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1014 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1020 * @{
1021 */
1022 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1023 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1024 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1025 #define LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1026 #define LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1027 #if defined(COMP5)
1028 #define LL_TIM_TIM1_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1029 #endif /* COMP5 */
1030 #if defined(COMP6)
1031 #define LL_TIM_TIM1_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1032 #endif /* COMP6 */
1033 #if defined(COMP7)
1034 #define LL_TIM_TIM1_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1035 #endif /* COMP7 */
1036 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
1037 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
1038 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
1039 #if defined(ADC4)
1040 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1041 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1042 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1043 #endif /* ADC4 */
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1049 * @{
1050 */
1051 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1052 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1053 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1054 #define LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1055 #define LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1056 #if defined(COMP5)
1057 #define LL_TIM_TIM2_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1058 #endif /* COMP5 */
1059 #if defined(COMP6)
1060 #define LL_TIM_TIM2_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1061 #endif /* COMP6 */
1062 #if defined(COMP7)
1063 #define LL_TIM_TIM2_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1064 #endif /* COMP7 */
1065 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1066 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1067 #if defined(TIM5)
1068 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
1069 #endif /* TIM5 */
1070 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1076 * @{
1077 */
1078 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1079 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1080 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1081 #define LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1082 #define LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1083 #if defined(COMP5)
1084 #define LL_TIM_TIM3_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1085 #endif /* COMP5 */
1086 #if defined(COMP6)
1087 #define LL_TIM_TIM3_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1088 #endif /* COMP6 */
1089 #if defined(COMP7)
1090 #define LL_TIM_TIM3_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1091 #endif /* COMP7 */
1092 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1093 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1094 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
1095 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
1096 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1102 * @{
1103 */
1104 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1105 #define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1106 #define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1107 #define LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1108 #define LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1109 #if defined(COMP5)
1110 #define LL_TIM_TIM4_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1111 #endif /* COMP5 */
1112 #if defined(COMP6)
1113 #define LL_TIM_TIM4_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1114 #endif /* COMP6 */
1115 #if defined(COMP7)
1116 #define LL_TIM_TIM4_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1117 #endif /* COMP7 */
1118 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1119 #if defined(TIM5)
1120 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1121 #endif /* TIM5 */
1122 /**
1123 * @}
1124 */
1125
1126 #if defined(TIM5)
1127 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1128 * @{
1129 */
1130 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1131 #define LL_TIM_TIM5_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1132 #define LL_TIM_TIM5_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1133 #define LL_TIM_TIM5_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1134 #define LL_TIM_TIM5_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1135 #if defined(COMP5)
1136 #define LL_TIM_TIM5_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1137 #endif /* COMP5 */
1138 #if defined(COMP6)
1139 #define LL_TIM_TIM5_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1140 #endif /* COMP6 */
1141 #if defined(COMP7)
1142 #define LL_TIM_TIM5_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1143 #endif /* COMP7 */
1144 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1145 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1146 /**
1147 * @}
1148 */
1149 #endif /* TIM5 */
1150
1151 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1152 * @{
1153 */
1154 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1155 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1156 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1157 #define LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1158 #define LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1159 #if defined(COMP5)
1160 #define LL_TIM_TIM8_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1161 #endif /* COMP5 */
1162 #if defined(COMP6)
1163 #define LL_TIM_TIM8_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1164 #endif /* COMP6 */
1165 #if defined(COMP7)
1166 #define LL_TIM_TIM8_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1167 #endif /* COMP7 */
1168 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */
1169 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
1170 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
1171 #if defined(ADC3)
1172 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
1173 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
1174 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
1175 #endif /* ADC3 */
1176 /**
1177 * @}
1178 */
1179
1180 #if defined(TIM20)
1181 /** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
1182 * @{
1183 */
1184 #define LL_TIM_TIM20_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1185 #define LL_TIM_TIM20_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1186 #define LL_TIM_TIM20_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1187 #define LL_TIM_TIM20_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1188 #define LL_TIM_TIM20_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1189 #if defined(COMP5)
1190 #define LL_TIM_TIM20_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1191 #endif /* COMP5 */
1192 #if defined(COMP6)
1193 #define LL_TIM_TIM20_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1194 #endif /* COMP6 */
1195 #if defined(COMP7)
1196 #define LL_TIM_TIM20_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1197 #endif /* COMP7 */
1198 #if defined(ADC3)
1199 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */
1200 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
1201 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
1202 #endif /* ADC3 */
1203 #if defined(ADC5)
1204 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
1205 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
1206 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
1207 #endif /* ADC5 */
1208 /**
1209 * @}
1210 */
1211 #endif /* TIM20 */
1212
1213 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1214 * @{
1215 */
1216 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1217 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1218 /**
1219 * @}
1220 */
1221
1222 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1223 * @{
1224 */
1225 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1226 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1227 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1228 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1229 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1230 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1231 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1232 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1233 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1234 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1235 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1236 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1237 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1238 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1239 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1240 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1241 /**
1242 * @}
1243 */
1244
1245 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1246 * @{
1247 */
1248 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1249 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1250 /**
1251 * @}
1252 */
1253
1254 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1255 * @{
1256 */
1257 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1258 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1259 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1260 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1261 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1262 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1263 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1264 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1265 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1266 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1267 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1268 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1269 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1270 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1271 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1272 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1273 /**
1274 * @}
1275 */
1276
1277 /** @defgroup TIM_LL_EC_OSSI OSSI
1278 * @{
1279 */
1280 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1281 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1282 /**
1283 * @}
1284 */
1285
1286 /** @defgroup TIM_LL_EC_OSSR OSSR
1287 * @{
1288 */
1289 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1290 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1296 * @{
1297 */
1298 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1299 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1305 * @{
1306 */
1307 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1308 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1309 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1310 #define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
1311 #define LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E /*!< internal signal: COMP4 output */
1312 #if defined(COMP5)
1313 #define LL_TIM_BKIN_SOURCE_BKCOMP5 TIM1_AF1_BKCMP5E /*!< internal signal: COMP5 output */
1314 #endif /* COMP5 */
1315 #if defined(COMP6)
1316 #define LL_TIM_BKIN_SOURCE_BKCOMP6 TIM1_AF1_BKCMP6E /*!< internal signal: COMP6 output */
1317 #endif /* COMP6 */
1318 #if defined(COMP7)
1319 #define LL_TIM_BKIN_SOURCE_BKCOMP7 TIM1_AF1_BKCMP7E /*!< internal signal: COMP7 output */
1320 #endif /* COMP7 */
1321 /**
1322 * @}
1323 */
1324
1325 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1326 * @{
1327 */
1328 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1329 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1330 /**
1331 * @}
1332 */
1333
1334 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1335 * @{
1336 */
1337 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1338 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1339 /**
1340 * @}
1341 */
1342
1343 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1344 * @{
1345 */
1346 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1347 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1348 /**
1349 * @}
1350 */
1351
1352 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1353 * @{
1354 */
1355 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1356 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1357 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1358 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1359 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1360 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1361 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1362 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1363 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1364 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1365 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1366 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1367 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1368 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1369 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1370 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1371 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1372 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1373 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1374 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1375 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1376 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1377 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1378 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1379 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1380 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1381 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst */
1382 /**
1383 * @}
1384 */
1385
1386 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1387 * @{
1388 */
1389 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1390 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1391 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1392 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1393 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1394 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1395 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1396 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1397 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1398 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1399 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1400 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1401 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1402 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1403 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1404 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1405 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1406 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1407 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1408 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1409 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1410 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1411 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1412 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1413 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1414 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1415 /**
1416 * @}
1417 */
1418
1419 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1420 * @{
1421 */
1422 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1423 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
1424 #define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
1425 #define LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
1426 #define LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
1427 /**
1428 * @}
1429 */
1430
1431 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1432 * @{
1433 */
1434 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1435 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
1436 #define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
1437 #define LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
1438 #define LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
1439 #if defined(COMP5)
1440 #define LL_TIM_TIM2_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
1441 #endif /* COMP5 */
1442 /**
1443 * @}
1444 */
1445
1446 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1447 * @{
1448 */
1449 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1450 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
1451 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
1452 #define LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
1453 #define LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
1454 #if defined(COMP6)
1455 #define LL_TIM_TIM2_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
1456 #endif /* COMP6 */
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
1462 * @{
1463 */
1464 #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
1465 #define LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
1466 /**
1467 * @}
1468 */
1469
1470 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1471 * @{
1472 */
1473 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
1474 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
1475 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
1476 /**
1477 * @}
1478 */
1479
1480 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1481 * @{
1482 */
1483 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1484 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
1485 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
1486 #define LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
1487 #define LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
1488 #if defined(COMP5)
1489 #define LL_TIM_TIM3_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
1490 #endif /* COMP5 */
1491 #if defined(COMP6)
1492 #define LL_TIM_TIM3_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
1493 #endif /* COMP6 */
1494 #if defined(COMP7)
1495 #define LL_TIM_TIM3_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
1496 #endif /* COMP7 */
1497 /**
1498 * @}
1499 */
1500
1501 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1502 * @{
1503 */
1504 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1505 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
1506 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
1507 #define LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
1508 #define LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
1509 #if defined(COMP5)
1510 #define LL_TIM_TIM3_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
1511 #endif /* COMP5 */
1512 #if defined(COMP6)
1513 #define LL_TIM_TIM3_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
1514 #endif /* COMP6 */
1515 #if defined(COMP7)
1516 #define LL_TIM_TIM3_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
1517 #endif /* COMP7 */
1518 /**
1519 * @}
1520 */
1521
1522 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
1523 * @{
1524 */
1525 #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
1526 #define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
1527 /**
1528 * @}
1529 */
1530
1531 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
1532 * @{
1533 */
1534 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
1535 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
1536 #define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
1537 #define LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
1538 #define LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
1539 #if defined(COMP5)
1540 #define LL_TIM_TIM4_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
1541 #endif /* COMP5 */
1542 #if defined(COMP6)
1543 #define LL_TIM_TIM4_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
1544 #endif /* COMP6 */
1545 #if defined(COMP7)
1546 #define LL_TIM_TIM4_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
1547 #endif /* COMP7 */
1548 /**
1549 * @}
1550 */
1551
1552 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
1553 * @{
1554 */
1555 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
1556 #define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
1557 #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
1558 #define LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
1559 #define LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
1560 #if defined(COMP5)
1561 #define LL_TIM_TIM4_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
1562 #endif /* COMP5 */
1563 #if defined(COMP6)
1564 #define LL_TIM_TIM4_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
1565 #endif /* COMP6 */
1566 #if defined(COMP7)
1567 #define LL_TIM_TIM4_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
1568 #endif /* COMP7 */
1569 /**
1570 * @}
1571 */
1572
1573 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
1574 * @{
1575 */
1576 #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
1577 #if defined(COMP5)
1578 #define LL_TIM_TIM4_TI3_RMP_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
1579 #endif /* COMP5 */
1580 /**
1581 * @}
1582 */
1583
1584 /** @defgroup TIM_LL_EC_TIM4_TI4_RMP TIM4 Timer Input Ch4 Remap
1585 * @{
1586 */
1587 #define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
1588 #if defined(COMP6)
1589 #define LL_TIM_TIM4_TI4_RMP_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
1590 #endif /* COMP6 */
1591 /**
1592 * @}
1593 */
1594
1595 #if defined(TIM5)
1596 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1597 * @{
1598 */
1599 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
1600 #define LL_TIM_TIM5_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
1601 #define LL_TIM_TIM5_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
1602 #define LL_TIM_TIM5_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
1603 #define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
1604 #define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
1605 #define LL_TIM_TIM5_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
1606 #define LL_TIM_TIM5_TI1_RMP_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
1607 #if defined(COMP5)
1608 #define LL_TIM_TIM5_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
1609 #endif /* COMP5 */
1610 #if defined(COMP6)
1611 #define LL_TIM_TIM5_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
1612 #endif /* COMP6 */
1613 #if defined(COMP7)
1614 #define LL_TIM_TIM5_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
1615 #endif /* COMP7 */
1616 /**
1617 * @}
1618 */
1619
1620 /** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 Timer Input Ch2 Remap
1621 * @{
1622 */
1623 #define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
1624 #define LL_TIM_TIM5_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
1625 #define LL_TIM_TIM5_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
1626 #define LL_TIM_TIM5_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
1627 #define LL_TIM_TIM5_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
1628 #if defined(COMP5)
1629 #define LL_TIM_TIM5_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
1630 #endif /* COMP5 */
1631 #if defined(COMP6)
1632 #define LL_TIM_TIM5_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
1633 #endif /* COMP6 */
1634 #if defined(COMP7)
1635 #define LL_TIM_TIM5_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
1636 #endif /* COMP7 */
1637 /**
1638 * @}
1639 */
1640 #endif /* TIM5 */
1641
1642 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1643 * @{
1644 */
1645 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
1646 #define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
1647 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
1648 #define LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
1649 #define LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
1650 /**
1651 * @}
1652 */
1653
1654 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1655 * @{
1656 */
1657 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1658 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
1659 #define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
1660 #define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
1661 #if defined(COMP5)
1662 #define LL_TIM_TIM15_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
1663 #endif /* COMP5 */
1664 #if defined(COMP7)
1665 #define LL_TIM_TIM15_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
1666 #endif /* COMP7 */
1667 /**
1668 * @}
1669 */
1670
1671 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1672 * @{
1673 */
1674 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1675 #define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
1676 #define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
1677 #if defined(COMP6)
1678 #define LL_TIM_TIM15_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
1679 #endif /* COMP6 */
1680 #if defined(COMP7)
1681 #define LL_TIM_TIM15_TI2_RMP_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
1682 #endif /* COMP7 */
1683 /**
1684 * @}
1685 */
1686
1687 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1688 * @{
1689 */
1690 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1691 #if defined(COMP6)
1692 #define LL_TIM_TIM16_TI1_RMP_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
1693 #endif /* COMP6 */
1694 #define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
1695 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
1696 #define LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
1697 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
1698 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
1699 /**
1700 * @}
1701 */
1702
1703 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1704 * @{
1705 */
1706 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1707 #if defined(COMP5)
1708 #define LL_TIM_TIM17_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
1709 #endif /* COMP5 */
1710 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
1711 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
1712 #define LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
1713 #define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
1714 #define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
1715 /**
1716 * @}
1717 */
1718
1719 #if defined(TIM20)
1720 /** @defgroup TIM_LL_EC_TIM20_TI1_RMP TIM20 Timer Input Ch1 Remap
1721 * @{
1722 */
1723 #define LL_TIM_TIM20_TI1_RMP_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
1724 #define LL_TIM_TIM20_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
1725 #define LL_TIM_TIM20_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
1726 #define LL_TIM_TIM20_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
1727 #define LL_TIM_TIM20_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
1728 /**
1729 * @}
1730 */
1731 #endif /* TIM20 */
1732
1733 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1734 * @{
1735 */
1736 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
1737 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1738 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1739 #define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF clear input is connected to COMP3_OUT */
1740 #define LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP4_OUT */
1741 #if defined(COMP5)
1742 #define LL_TIM_OCREF_CLR_INT_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF clear input is connected to COMP5_OUT */
1743 #endif /* COMP5 */
1744 #if defined(COMP6)
1745 #define LL_TIM_OCREF_CLR_INT_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP6_OUT */
1746 #endif /* COMP6 */
1747 #if defined(COMP7)
1748 #define LL_TIM_OCREF_CLR_INT_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF clear input is connected to COMP7_OUT */
1749 #endif /* COMP7 */
1750 /**
1751 * @}
1752 */
1753
1754 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1755 * @{
1756 */
1757 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1758 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1759 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1760 /**
1761 * @}
1762 */
1763
1764 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1765 * @{
1766 */
1767 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1768 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1769 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1770 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1771 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1772 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1773 /**
1774 * @}
1775 */
1776
1777 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1778 * @{
1779 */
1780 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1781 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1782 /**
1783 * @}
1784 */
1785 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1786 * @{
1787 */
1788 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1789 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1790 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1791 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1792 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1793 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1794 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1795 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1796 /**
1797 * @}
1798 */
1799
1800 /** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
1801 * @{
1802 */
1803 #define LL_TIM_HSE_32_NOT_REQUEST 0x00000000U /*!< Clock HSE/32 not requested */
1804 #define LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
1805 /**
1806 * @}
1807 */
1808
1809 /** Legacy definitions for compatibility purpose
1810 @cond 0
1811 */
1812 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1813 /**
1814 @endcond
1815 */
1816 /**
1817 * @}
1818 */
1819
1820 /* Exported macro ------------------------------------------------------------*/
1821 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1822 * @{
1823 */
1824
1825 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1826 * @{
1827 */
1828 /**
1829 * @brief Write a value in TIM register.
1830 * @param __INSTANCE__ TIM Instance
1831 * @param __REG__ Register to be written
1832 * @param __VALUE__ Value to be written in the register
1833 * @retval None
1834 */
1835 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1836
1837 /**
1838 * @brief Read a value in TIM register.
1839 * @param __INSTANCE__ TIM Instance
1840 * @param __REG__ Register to be read
1841 * @retval Register value
1842 */
1843 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1844 /**
1845 * @}
1846 */
1847
1848 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1849 * @{
1850 */
1851
1852 /**
1853 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1854 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1855 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1856 * to TIMx_CNT register bit 31)
1857 * @param __CNT__ Counter value
1858 * @retval UIF status bit
1859 */
1860 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1861 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1862
1863 /**
1864 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1865 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1866 * @param __TIMCLK__ timer input clock frequency (in Hz)
1867 * @param __CKD__ This parameter can be one of the following values:
1868 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1869 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1870 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1871 * @param __DT__ deadtime duration (in ns)
1872 * @retval DTG[0:7]
1873 */
1874 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1875 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1876 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1877 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1878 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1879 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1880 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1881 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1882 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1883 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1884 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1885 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1886 0U)
1887
1888 /**
1889 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1890 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1891 * @param __TIMCLK__ timer input clock frequency (in Hz)
1892 * @param __CNTCLK__ counter clock frequency (in Hz)
1893 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1894 */
1895 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1896 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1897
1898 /**
1899 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1900 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1901 * @param __TIMCLK__ timer input clock frequency (in Hz)
1902 * @param __PSC__ prescaler
1903 * @param __FREQ__ output signal frequency (in Hz)
1904 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1905 */
1906 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1907 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1908
1909 /**
1910 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1911 * output signal frequency.
1912 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1913 * @param __TIMCLK__ timer input clock frequency (in Hz)
1914 * @param __PSC__ prescaler
1915 * @param __FREQ__ output signal frequency (in Hz)
1916 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1917 */
1918 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1919 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1920 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1921
1922 /**
1923 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1924 * active/inactive delay.
1925 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1926 * @param __TIMCLK__ timer input clock frequency (in Hz)
1927 * @param __PSC__ prescaler
1928 * @param __DELAY__ timer output compare active/inactive delay (in us)
1929 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1930 */
1931 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1932 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1933 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1934
1935 /**
1936 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1937 * output compare active/inactive delay.
1938 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1939 * @param __TIMCLK__ timer input clock frequency (in Hz)
1940 * @param __PSC__ prescaler
1941 * @param __DELAY__ timer output compare active/inactive delay (in us)
1942 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1943 */
1944 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1945 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1946 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1947
1948 /**
1949 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1950 * (when the timer operates in one pulse mode).
1951 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1952 * @param __TIMCLK__ timer input clock frequency (in Hz)
1953 * @param __PSC__ prescaler
1954 * @param __DELAY__ timer output compare active/inactive delay (in us)
1955 * @param __PULSE__ pulse duration (in us)
1956 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1957 */
1958 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1959 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1960 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1961
1962 /**
1963 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1964 * pulse duration (when the timer operates in one pulse mode).
1965 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1966 * @param __TIMCLK__ timer input clock frequency (in Hz)
1967 * @param __PSC__ prescaler
1968 * @param __DELAY__ timer output compare active/inactive delay (in us)
1969 * @param __PULSE__ pulse duration (in us)
1970 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1971 */
1972 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1973 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1974 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1975
1976 /**
1977 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1978 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1979 * @param __ICPSC__ This parameter can be one of the following values:
1980 * @arg @ref LL_TIM_ICPSC_DIV1
1981 * @arg @ref LL_TIM_ICPSC_DIV2
1982 * @arg @ref LL_TIM_ICPSC_DIV4
1983 * @arg @ref LL_TIM_ICPSC_DIV8
1984 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1985 */
1986 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1987 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1988
1989
1990 /**
1991 * @}
1992 */
1993
1994
1995 /**
1996 * @}
1997 */
1998
1999 /* Exported functions --------------------------------------------------------*/
2000 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
2001 * @{
2002 */
2003
2004 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
2005 * @{
2006 */
2007 /**
2008 * @brief Enable timer counter.
2009 * @rmtoll CR1 CEN LL_TIM_EnableCounter
2010 * @param TIMx Timer instance
2011 * @retval None
2012 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)2013 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
2014 {
2015 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
2016 }
2017
2018 /**
2019 * @brief Disable timer counter.
2020 * @rmtoll CR1 CEN LL_TIM_DisableCounter
2021 * @param TIMx Timer instance
2022 * @retval None
2023 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)2024 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
2025 {
2026 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
2027 }
2028
2029 /**
2030 * @brief Indicates whether the timer counter is enabled.
2031 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
2032 * @param TIMx Timer instance
2033 * @retval State of bit (1 or 0).
2034 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)2035 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
2036 {
2037 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
2038 }
2039
2040 /**
2041 * @brief Enable update event generation.
2042 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
2043 * @param TIMx Timer instance
2044 * @retval None
2045 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)2046 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
2047 {
2048 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
2049 }
2050
2051 /**
2052 * @brief Disable update event generation.
2053 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
2054 * @param TIMx Timer instance
2055 * @retval None
2056 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)2057 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
2058 {
2059 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
2060 }
2061
2062 /**
2063 * @brief Indicates whether update event generation is enabled.
2064 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
2065 * @param TIMx Timer instance
2066 * @retval Inverted state of bit (0 or 1).
2067 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)2068 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
2069 {
2070 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
2071 }
2072
2073 /**
2074 * @brief Set update event source
2075 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
2076 * generate an update interrupt or DMA request if enabled:
2077 * - Counter overflow/underflow
2078 * - Setting the UG bit
2079 * - Update generation through the slave mode controller
2080 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
2081 * overflow/underflow generates an update interrupt or DMA request if enabled.
2082 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
2083 * @param TIMx Timer instance
2084 * @param UpdateSource This parameter can be one of the following values:
2085 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2086 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2087 * @retval None
2088 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)2089 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
2090 {
2091 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
2092 }
2093
2094 /**
2095 * @brief Get actual event update source
2096 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
2097 * @param TIMx Timer instance
2098 * @retval Returned value can be one of the following values:
2099 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2100 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2101 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)2102 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
2103 {
2104 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
2105 }
2106
2107 /**
2108 * @brief Set one pulse mode (one shot v.s. repetitive).
2109 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
2110 * @param TIMx Timer instance
2111 * @param OnePulseMode This parameter can be one of the following values:
2112 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2113 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2114 * @retval None
2115 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)2116 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
2117 {
2118 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
2119 }
2120
2121 /**
2122 * @brief Get actual one pulse mode.
2123 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
2124 * @param TIMx Timer instance
2125 * @retval Returned value can be one of the following values:
2126 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2127 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2128 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)2129 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
2130 {
2131 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
2132 }
2133
2134 /**
2135 * @brief Set the timer counter counting mode.
2136 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2137 * check whether or not the counter mode selection feature is supported
2138 * by a timer instance.
2139 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2140 * requires a timer reset to avoid unexpected direction
2141 * due to DIR bit readonly in center aligned mode.
2142 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
2143 * CR1 CMS LL_TIM_SetCounterMode
2144 * @param TIMx Timer instance
2145 * @param CounterMode This parameter can be one of the following values:
2146 * @arg @ref LL_TIM_COUNTERMODE_UP
2147 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2148 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2149 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2150 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2151 * @retval None
2152 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)2153 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
2154 {
2155 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
2156 }
2157
2158 /**
2159 * @brief Get actual counter mode.
2160 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2161 * check whether or not the counter mode selection feature is supported
2162 * by a timer instance.
2163 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
2164 * CR1 CMS LL_TIM_GetCounterMode
2165 * @param TIMx Timer instance
2166 * @retval Returned value can be one of the following values:
2167 * @arg @ref LL_TIM_COUNTERMODE_UP
2168 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2169 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2170 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2171 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2172 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)2173 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
2174 {
2175 uint32_t counter_mode;
2176
2177 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
2178
2179 if (counter_mode == 0U)
2180 {
2181 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2182 }
2183
2184 return counter_mode;
2185 }
2186
2187 /**
2188 * @brief Enable auto-reload (ARR) preload.
2189 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
2190 * @param TIMx Timer instance
2191 * @retval None
2192 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)2193 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
2194 {
2195 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
2196 }
2197
2198 /**
2199 * @brief Disable auto-reload (ARR) preload.
2200 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
2201 * @param TIMx Timer instance
2202 * @retval None
2203 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)2204 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
2205 {
2206 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
2207 }
2208
2209 /**
2210 * @brief Indicates whether auto-reload (ARR) preload is enabled.
2211 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
2212 * @param TIMx Timer instance
2213 * @retval State of bit (1 or 0).
2214 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)2215 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
2216 {
2217 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
2218 }
2219
2220 /**
2221 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
2222 * (when supported) and the digital filters.
2223 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2224 * whether or not the clock division feature is supported by the timer
2225 * instance.
2226 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
2227 * @param TIMx Timer instance
2228 * @param ClockDivision This parameter can be one of the following values:
2229 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2230 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2231 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2232 * @retval None
2233 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)2234 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
2235 {
2236 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
2237 }
2238
2239 /**
2240 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
2241 * generators (when supported) and the digital filters.
2242 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2243 * whether or not the clock division feature is supported by the timer
2244 * instance.
2245 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
2246 * @param TIMx Timer instance
2247 * @retval Returned value can be one of the following values:
2248 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2249 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2250 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2251 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)2252 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
2253 {
2254 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
2255 }
2256
2257 /**
2258 * @brief Set the counter value.
2259 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2260 * whether or not a timer instance supports a 32 bits counter.
2261 * @note If dithering is activated, pay attention to the Counter value interpretation
2262 * @rmtoll CNT CNT LL_TIM_SetCounter
2263 * @param TIMx Timer instance
2264 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2265 * @retval None
2266 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2267 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2268 {
2269 WRITE_REG(TIMx->CNT, Counter);
2270 }
2271
2272 /**
2273 * @brief Get the counter value.
2274 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2275 * whether or not a timer instance supports a 32 bits counter.
2276 * @note If dithering is activated, pay attention to the Counter value interpretation
2277 * @rmtoll CNT CNT LL_TIM_GetCounter
2278 * @param TIMx Timer instance
2279 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2280 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)2281 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
2282 {
2283 return (uint32_t)(READ_REG(TIMx->CNT));
2284 }
2285
2286 /**
2287 * @brief Get the current direction of the counter
2288 * @rmtoll CR1 DIR LL_TIM_GetDirection
2289 * @param TIMx Timer instance
2290 * @retval Returned value can be one of the following values:
2291 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2292 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2293 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)2294 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
2295 {
2296 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2297 }
2298
2299 /**
2300 * @brief Set the prescaler value.
2301 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2302 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2303 * prescaler ratio is taken into account at the next update event.
2304 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2305 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2306 * @param TIMx Timer instance
2307 * @param Prescaler between Min_Data=0 and Max_Data=65535
2308 * @retval None
2309 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2310 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2311 {
2312 WRITE_REG(TIMx->PSC, Prescaler);
2313 }
2314
2315 /**
2316 * @brief Get the prescaler value.
2317 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2318 * @param TIMx Timer instance
2319 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2320 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)2321 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
2322 {
2323 return (uint32_t)(READ_REG(TIMx->PSC));
2324 }
2325
2326 /**
2327 * @brief Set the auto-reload value.
2328 * @note The counter is blocked while the auto-reload value is null.
2329 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2330 * whether or not a timer instance supports a 32 bits counter.
2331 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2332 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2333 * parameter.
2334 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2335 * @param TIMx Timer instance
2336 * @param AutoReload between Min_Data=0 and Max_Data=65535
2337 * @retval None
2338 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2339 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2340 {
2341 WRITE_REG(TIMx->ARR, AutoReload);
2342 }
2343
2344 /**
2345 * @brief Get the auto-reload value.
2346 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2347 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2348 * whether or not a timer instance supports a 32 bits counter.
2349 * @note If dithering is activated, pay attention to the returned value interpretation
2350 * @param TIMx Timer instance
2351 * @retval Auto-reload value
2352 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)2353 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
2354 {
2355 return (uint32_t)(READ_REG(TIMx->ARR));
2356 }
2357
2358 /**
2359 * @brief Set the repetition counter value.
2360 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2361 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2362 * whether or not a timer instance supports a repetition counter.
2363 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2364 * @param TIMx Timer instance
2365 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2366 * @retval None
2367 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2368 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2369 {
2370 WRITE_REG(TIMx->RCR, RepetitionCounter);
2371 }
2372
2373 /**
2374 * @brief Get the repetition counter value.
2375 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2376 * whether or not a timer instance supports a repetition counter.
2377 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2378 * @param TIMx Timer instance
2379 * @retval Repetition counter value
2380 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)2381 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
2382 {
2383 return (uint32_t)(READ_REG(TIMx->RCR));
2384 }
2385
2386 /**
2387 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2388 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2389 * in an atomic way.
2390 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2391 * @param TIMx Timer instance
2392 * @retval None
2393 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2394 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2395 {
2396 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2397 }
2398
2399 /**
2400 * @brief Disable update interrupt flag (UIF) remapping.
2401 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2402 * @param TIMx Timer instance
2403 * @retval None
2404 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2405 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2406 {
2407 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2408 }
2409
2410 /**
2411 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2412 * @param Counter Counter value
2413 * @retval State of bit (1 or 0).
2414 */
LL_TIM_IsActiveUIFCPY(uint32_t Counter)2415 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
2416 {
2417 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2418 }
2419
2420 /**
2421 * @brief Enable dithering.
2422 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2423 * a timer instance provides dithering.
2424 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2425 * @param TIMx Timer instance
2426 * @retval None
2427 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2428 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2429 {
2430 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2431 }
2432
2433 /**
2434 * @brief Disable dithering.
2435 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2436 * a timer instance provides dithering.
2437 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2438 * @param TIMx Timer instance
2439 * @retval None
2440 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2441 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2442 {
2443 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2444 }
2445
2446 /**
2447 * @brief Indicates whether dithering is activated.
2448 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2449 * a timer instance provides dithering.
2450 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2451 * @param TIMx Timer instance
2452 * @retval State of bit (1 or 0).
2453 */
LL_TIM_IsEnabledDithering(TIM_TypeDef * TIMx)2454 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
2455 {
2456 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2457 }
2458
2459 /**
2460 * @}
2461 */
2462
2463 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2464 * @{
2465 */
2466 /**
2467 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2468 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2469 * they are updated only when a commutation event (COM) occurs.
2470 * @note Only on channels that have a complementary output.
2471 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2472 * whether or not a timer instance is able to generate a commutation event.
2473 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2474 * @param TIMx Timer instance
2475 * @retval None
2476 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2477 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2478 {
2479 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2480 }
2481
2482 /**
2483 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2484 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2485 * whether or not a timer instance is able to generate a commutation event.
2486 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2487 * @param TIMx Timer instance
2488 * @retval None
2489 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2490 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2491 {
2492 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2493 }
2494
2495 /**
2496 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2497 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2498 * whether or not a timer instance is able to generate a commutation event.
2499 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2500 * @param TIMx Timer instance
2501 * @param CCUpdateSource This parameter can be one of the following values:
2502 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2503 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2504 * @retval None
2505 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2506 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2507 {
2508 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2509 }
2510
2511 /**
2512 * @brief Set the trigger of the capture/compare DMA request.
2513 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2514 * @param TIMx Timer instance
2515 * @param DMAReqTrigger This parameter can be one of the following values:
2516 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2517 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2518 * @retval None
2519 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2520 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2521 {
2522 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2523 }
2524
2525 /**
2526 * @brief Get actual trigger of the capture/compare DMA request.
2527 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2528 * @param TIMx Timer instance
2529 * @retval Returned value can be one of the following values:
2530 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2531 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2532 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)2533 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
2534 {
2535 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2536 }
2537
2538 /**
2539 * @brief Set the lock level to freeze the
2540 * configuration of several capture/compare parameters.
2541 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2542 * the lock mechanism is supported by a timer instance.
2543 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2544 * @param TIMx Timer instance
2545 * @param LockLevel This parameter can be one of the following values:
2546 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2547 * @arg @ref LL_TIM_LOCKLEVEL_1
2548 * @arg @ref LL_TIM_LOCKLEVEL_2
2549 * @arg @ref LL_TIM_LOCKLEVEL_3
2550 * @retval None
2551 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2552 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2553 {
2554 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2555 }
2556
2557 /**
2558 * @brief Enable capture/compare channels.
2559 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2560 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2561 * CCER CC2E LL_TIM_CC_EnableChannel\n
2562 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2563 * CCER CC3E LL_TIM_CC_EnableChannel\n
2564 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2565 * CCER CC4E LL_TIM_CC_EnableChannel\n
2566 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2567 * CCER CC5E LL_TIM_CC_EnableChannel\n
2568 * CCER CC6E LL_TIM_CC_EnableChannel
2569 * @param TIMx Timer instance
2570 * @param Channels This parameter can be a combination of the following values:
2571 * @arg @ref LL_TIM_CHANNEL_CH1
2572 * @arg @ref LL_TIM_CHANNEL_CH1N
2573 * @arg @ref LL_TIM_CHANNEL_CH2
2574 * @arg @ref LL_TIM_CHANNEL_CH2N
2575 * @arg @ref LL_TIM_CHANNEL_CH3
2576 * @arg @ref LL_TIM_CHANNEL_CH3N
2577 * @arg @ref LL_TIM_CHANNEL_CH4
2578 * @arg @ref LL_TIM_CHANNEL_CH4N
2579 * @arg @ref LL_TIM_CHANNEL_CH5
2580 * @arg @ref LL_TIM_CHANNEL_CH6
2581 * @retval None
2582 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2583 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2584 {
2585 SET_BIT(TIMx->CCER, Channels);
2586 }
2587
2588 /**
2589 * @brief Disable capture/compare channels.
2590 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2591 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2592 * CCER CC2E LL_TIM_CC_DisableChannel\n
2593 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2594 * CCER CC3E LL_TIM_CC_DisableChannel\n
2595 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2596 * CCER CC4E LL_TIM_CC_DisableChannel\n
2597 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2598 * CCER CC5E LL_TIM_CC_DisableChannel\n
2599 * CCER CC6E LL_TIM_CC_DisableChannel
2600 * @param TIMx Timer instance
2601 * @param Channels This parameter can be a combination of the following values:
2602 * @arg @ref LL_TIM_CHANNEL_CH1
2603 * @arg @ref LL_TIM_CHANNEL_CH1N
2604 * @arg @ref LL_TIM_CHANNEL_CH2
2605 * @arg @ref LL_TIM_CHANNEL_CH2N
2606 * @arg @ref LL_TIM_CHANNEL_CH3
2607 * @arg @ref LL_TIM_CHANNEL_CH3N
2608 * @arg @ref LL_TIM_CHANNEL_CH4
2609 * @arg @ref LL_TIM_CHANNEL_CH4N
2610 * @arg @ref LL_TIM_CHANNEL_CH5
2611 * @arg @ref LL_TIM_CHANNEL_CH6
2612 * @retval None
2613 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2614 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2615 {
2616 CLEAR_BIT(TIMx->CCER, Channels);
2617 }
2618
2619 /**
2620 * @brief Indicate whether channel(s) is(are) enabled.
2621 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2622 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2623 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2624 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2625 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2626 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2627 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2628 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2629 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2630 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2631 * @param TIMx Timer instance
2632 * @param Channels This parameter can be a combination of the following values:
2633 * @arg @ref LL_TIM_CHANNEL_CH1
2634 * @arg @ref LL_TIM_CHANNEL_CH1N
2635 * @arg @ref LL_TIM_CHANNEL_CH2
2636 * @arg @ref LL_TIM_CHANNEL_CH2N
2637 * @arg @ref LL_TIM_CHANNEL_CH3
2638 * @arg @ref LL_TIM_CHANNEL_CH3N
2639 * @arg @ref LL_TIM_CHANNEL_CH4
2640 * @arg @ref LL_TIM_CHANNEL_CH4N
2641 * @arg @ref LL_TIM_CHANNEL_CH5
2642 * @arg @ref LL_TIM_CHANNEL_CH6
2643 * @retval State of bit (1 or 0).
2644 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)2645 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2646 {
2647 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2648 }
2649
2650 /**
2651 * @}
2652 */
2653
2654 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2655 * @{
2656 */
2657 /**
2658 * @brief Configure an output channel.
2659 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2660 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2661 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2662 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2663 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2664 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2665 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2666 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2667 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2668 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2669 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2670 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2671 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2672 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2673 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2674 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2675 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2676 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2677 * @param TIMx Timer instance
2678 * @param Channel This parameter can be one of the following values:
2679 * @arg @ref LL_TIM_CHANNEL_CH1
2680 * @arg @ref LL_TIM_CHANNEL_CH2
2681 * @arg @ref LL_TIM_CHANNEL_CH3
2682 * @arg @ref LL_TIM_CHANNEL_CH4
2683 * @arg @ref LL_TIM_CHANNEL_CH5
2684 * @arg @ref LL_TIM_CHANNEL_CH6
2685 * @param Configuration This parameter must be a combination of all the following values:
2686 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2687 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2688 * @retval None
2689 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2690 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2691 {
2692 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2693 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2694 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2695 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2696 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2697 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2698 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2699 }
2700
2701 /**
2702 * @brief Define the behavior of the output reference signal OCxREF from which
2703 * OCx and OCxN (when relevant) are derived.
2704 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2705 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2706 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2707 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2708 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2709 * CCMR3 OC6M LL_TIM_OC_SetMode
2710 * @param TIMx Timer instance
2711 * @param Channel This parameter can be one of the following values:
2712 * @arg @ref LL_TIM_CHANNEL_CH1
2713 * @arg @ref LL_TIM_CHANNEL_CH2
2714 * @arg @ref LL_TIM_CHANNEL_CH3
2715 * @arg @ref LL_TIM_CHANNEL_CH4
2716 * @arg @ref LL_TIM_CHANNEL_CH5
2717 * @arg @ref LL_TIM_CHANNEL_CH6
2718 * @param Mode This parameter can be one of the following values:
2719 * @arg @ref LL_TIM_OCMODE_FROZEN
2720 * @arg @ref LL_TIM_OCMODE_ACTIVE
2721 * @arg @ref LL_TIM_OCMODE_INACTIVE
2722 * @arg @ref LL_TIM_OCMODE_TOGGLE
2723 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2724 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2725 * @arg @ref LL_TIM_OCMODE_PWM1
2726 * @arg @ref LL_TIM_OCMODE_PWM2
2727 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2728 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2729 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2730 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2731 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2732 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2733 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2734 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2735 * @retval None
2736 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2737 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2738 {
2739 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2740 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2741 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2742 }
2743
2744 /**
2745 * @brief Get the output compare mode of an output channel.
2746 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2747 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2748 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2749 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2750 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2751 * CCMR3 OC6M LL_TIM_OC_GetMode
2752 * @param TIMx Timer instance
2753 * @param Channel This parameter can be one of the following values:
2754 * @arg @ref LL_TIM_CHANNEL_CH1
2755 * @arg @ref LL_TIM_CHANNEL_CH2
2756 * @arg @ref LL_TIM_CHANNEL_CH3
2757 * @arg @ref LL_TIM_CHANNEL_CH4
2758 * @arg @ref LL_TIM_CHANNEL_CH5
2759 * @arg @ref LL_TIM_CHANNEL_CH6
2760 * @retval Returned value can be one of the following values:
2761 * @arg @ref LL_TIM_OCMODE_FROZEN
2762 * @arg @ref LL_TIM_OCMODE_ACTIVE
2763 * @arg @ref LL_TIM_OCMODE_INACTIVE
2764 * @arg @ref LL_TIM_OCMODE_TOGGLE
2765 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2766 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2767 * @arg @ref LL_TIM_OCMODE_PWM1
2768 * @arg @ref LL_TIM_OCMODE_PWM2
2769 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2770 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2771 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2772 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2773 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2774 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2775 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2776 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2777 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)2778 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2779 {
2780 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2781 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2782 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2783 }
2784
2785 /**
2786 * @brief Set the polarity of an output channel.
2787 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2788 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2789 * CCER CC2P LL_TIM_OC_SetPolarity\n
2790 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2791 * CCER CC3P LL_TIM_OC_SetPolarity\n
2792 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2793 * CCER CC4P LL_TIM_OC_SetPolarity\n
2794 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2795 * CCER CC5P LL_TIM_OC_SetPolarity\n
2796 * CCER CC6P LL_TIM_OC_SetPolarity
2797 * @param TIMx Timer instance
2798 * @param Channel This parameter can be one of the following values:
2799 * @arg @ref LL_TIM_CHANNEL_CH1
2800 * @arg @ref LL_TIM_CHANNEL_CH1N
2801 * @arg @ref LL_TIM_CHANNEL_CH2
2802 * @arg @ref LL_TIM_CHANNEL_CH2N
2803 * @arg @ref LL_TIM_CHANNEL_CH3
2804 * @arg @ref LL_TIM_CHANNEL_CH3N
2805 * @arg @ref LL_TIM_CHANNEL_CH4
2806 * @arg @ref LL_TIM_CHANNEL_CH4N
2807 * @arg @ref LL_TIM_CHANNEL_CH5
2808 * @arg @ref LL_TIM_CHANNEL_CH6
2809 * @param Polarity This parameter can be one of the following values:
2810 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2811 * @arg @ref LL_TIM_OCPOLARITY_LOW
2812 * @retval None
2813 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2814 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2815 {
2816 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2817 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2818 }
2819
2820 /**
2821 * @brief Get the polarity of an output channel.
2822 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2823 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2824 * CCER CC2P LL_TIM_OC_GetPolarity\n
2825 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2826 * CCER CC3P LL_TIM_OC_GetPolarity\n
2827 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2828 * CCER CC4P LL_TIM_OC_GetPolarity\n
2829 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2830 * CCER CC5P LL_TIM_OC_GetPolarity\n
2831 * CCER CC6P LL_TIM_OC_GetPolarity
2832 * @param TIMx Timer instance
2833 * @param Channel This parameter can be one of the following values:
2834 * @arg @ref LL_TIM_CHANNEL_CH1
2835 * @arg @ref LL_TIM_CHANNEL_CH1N
2836 * @arg @ref LL_TIM_CHANNEL_CH2
2837 * @arg @ref LL_TIM_CHANNEL_CH2N
2838 * @arg @ref LL_TIM_CHANNEL_CH3
2839 * @arg @ref LL_TIM_CHANNEL_CH3N
2840 * @arg @ref LL_TIM_CHANNEL_CH4
2841 * @arg @ref LL_TIM_CHANNEL_CH4N
2842 * @arg @ref LL_TIM_CHANNEL_CH5
2843 * @arg @ref LL_TIM_CHANNEL_CH6
2844 * @retval Returned value can be one of the following values:
2845 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2846 * @arg @ref LL_TIM_OCPOLARITY_LOW
2847 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2848 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2849 {
2850 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2851 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2852 }
2853
2854 /**
2855 * @brief Set the IDLE state of an output channel
2856 * @note This function is significant only for the timer instances
2857 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2858 * can be used to check whether or not a timer instance provides
2859 * a break input.
2860 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2861 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2862 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2863 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2864 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2865 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2866 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2867 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2868 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2869 * CR2 OIS6 LL_TIM_OC_SetIdleState
2870 * @param TIMx Timer instance
2871 * @param Channel This parameter can be one of the following values:
2872 * @arg @ref LL_TIM_CHANNEL_CH1
2873 * @arg @ref LL_TIM_CHANNEL_CH1N
2874 * @arg @ref LL_TIM_CHANNEL_CH2
2875 * @arg @ref LL_TIM_CHANNEL_CH2N
2876 * @arg @ref LL_TIM_CHANNEL_CH3
2877 * @arg @ref LL_TIM_CHANNEL_CH3N
2878 * @arg @ref LL_TIM_CHANNEL_CH4
2879 * @arg @ref LL_TIM_CHANNEL_CH4N
2880 * @arg @ref LL_TIM_CHANNEL_CH5
2881 * @arg @ref LL_TIM_CHANNEL_CH6
2882 * @param IdleState This parameter can be one of the following values:
2883 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2884 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2885 * @retval None
2886 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2887 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2888 {
2889 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2890 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2891 }
2892
2893 /**
2894 * @brief Get the IDLE state of an output channel
2895 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2896 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2897 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2898 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2899 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2900 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2901 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2902 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2903 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2904 * CR2 OIS6 LL_TIM_OC_GetIdleState
2905 * @param TIMx Timer instance
2906 * @param Channel This parameter can be one of the following values:
2907 * @arg @ref LL_TIM_CHANNEL_CH1
2908 * @arg @ref LL_TIM_CHANNEL_CH1N
2909 * @arg @ref LL_TIM_CHANNEL_CH2
2910 * @arg @ref LL_TIM_CHANNEL_CH2N
2911 * @arg @ref LL_TIM_CHANNEL_CH3
2912 * @arg @ref LL_TIM_CHANNEL_CH3N
2913 * @arg @ref LL_TIM_CHANNEL_CH4
2914 * @arg @ref LL_TIM_CHANNEL_CH4N
2915 * @arg @ref LL_TIM_CHANNEL_CH5
2916 * @arg @ref LL_TIM_CHANNEL_CH6
2917 * @retval Returned value can be one of the following values:
2918 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2919 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2920 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)2921 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2922 {
2923 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2924 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2925 }
2926
2927 /**
2928 * @brief Enable fast mode for the output channel.
2929 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2930 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2931 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2932 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2933 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2934 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2935 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2936 * @param TIMx Timer instance
2937 * @param Channel This parameter can be one of the following values:
2938 * @arg @ref LL_TIM_CHANNEL_CH1
2939 * @arg @ref LL_TIM_CHANNEL_CH2
2940 * @arg @ref LL_TIM_CHANNEL_CH3
2941 * @arg @ref LL_TIM_CHANNEL_CH4
2942 * @arg @ref LL_TIM_CHANNEL_CH5
2943 * @arg @ref LL_TIM_CHANNEL_CH6
2944 * @retval None
2945 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2946 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2947 {
2948 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2949 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2950 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2951
2952 }
2953
2954 /**
2955 * @brief Disable fast mode for the output channel.
2956 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2957 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2958 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2959 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2960 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2961 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2962 * @param TIMx Timer instance
2963 * @param Channel This parameter can be one of the following values:
2964 * @arg @ref LL_TIM_CHANNEL_CH1
2965 * @arg @ref LL_TIM_CHANNEL_CH2
2966 * @arg @ref LL_TIM_CHANNEL_CH3
2967 * @arg @ref LL_TIM_CHANNEL_CH4
2968 * @arg @ref LL_TIM_CHANNEL_CH5
2969 * @arg @ref LL_TIM_CHANNEL_CH6
2970 * @retval None
2971 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2972 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2973 {
2974 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2975 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2976 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2977
2978 }
2979
2980 /**
2981 * @brief Indicates whether fast mode is enabled for the output channel.
2982 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2983 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2984 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2985 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2986 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2987 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2988 * @param TIMx Timer instance
2989 * @param Channel This parameter can be one of the following values:
2990 * @arg @ref LL_TIM_CHANNEL_CH1
2991 * @arg @ref LL_TIM_CHANNEL_CH2
2992 * @arg @ref LL_TIM_CHANNEL_CH3
2993 * @arg @ref LL_TIM_CHANNEL_CH4
2994 * @arg @ref LL_TIM_CHANNEL_CH5
2995 * @arg @ref LL_TIM_CHANNEL_CH6
2996 * @retval State of bit (1 or 0).
2997 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2998 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2999 {
3000 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3001 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3002 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
3003 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3004 }
3005
3006 /**
3007 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
3008 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
3009 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
3010 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
3011 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
3012 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
3013 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
3014 * @param TIMx Timer instance
3015 * @param Channel This parameter can be one of the following values:
3016 * @arg @ref LL_TIM_CHANNEL_CH1
3017 * @arg @ref LL_TIM_CHANNEL_CH2
3018 * @arg @ref LL_TIM_CHANNEL_CH3
3019 * @arg @ref LL_TIM_CHANNEL_CH4
3020 * @arg @ref LL_TIM_CHANNEL_CH5
3021 * @arg @ref LL_TIM_CHANNEL_CH6
3022 * @retval None
3023 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)3024 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
3025 {
3026 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3027 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3028 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
3029 }
3030
3031 /**
3032 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
3033 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
3034 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
3035 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
3036 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
3037 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
3038 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
3039 * @param TIMx Timer instance
3040 * @param Channel This parameter can be one of the following values:
3041 * @arg @ref LL_TIM_CHANNEL_CH1
3042 * @arg @ref LL_TIM_CHANNEL_CH2
3043 * @arg @ref LL_TIM_CHANNEL_CH3
3044 * @arg @ref LL_TIM_CHANNEL_CH4
3045 * @arg @ref LL_TIM_CHANNEL_CH5
3046 * @arg @ref LL_TIM_CHANNEL_CH6
3047 * @retval None
3048 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)3049 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
3050 {
3051 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3052 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3053 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
3054 }
3055
3056 /**
3057 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
3058 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
3059 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
3060 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
3061 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
3062 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
3063 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
3064 * @param TIMx Timer instance
3065 * @param Channel This parameter can be one of the following values:
3066 * @arg @ref LL_TIM_CHANNEL_CH1
3067 * @arg @ref LL_TIM_CHANNEL_CH2
3068 * @arg @ref LL_TIM_CHANNEL_CH3
3069 * @arg @ref LL_TIM_CHANNEL_CH4
3070 * @arg @ref LL_TIM_CHANNEL_CH5
3071 * @arg @ref LL_TIM_CHANNEL_CH6
3072 * @retval State of bit (1 or 0).
3073 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)3074 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
3075 {
3076 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3077 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3078 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
3079 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3080 }
3081
3082 /**
3083 * @brief Enable clearing the output channel on an external event.
3084 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3085 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3086 * or not a timer instance can clear the OCxREF signal on an external event.
3087 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
3088 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
3089 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
3090 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
3091 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
3092 * CCMR3 OC6CE LL_TIM_OC_EnableClear
3093 * @param TIMx Timer instance
3094 * @param Channel This parameter can be one of the following values:
3095 * @arg @ref LL_TIM_CHANNEL_CH1
3096 * @arg @ref LL_TIM_CHANNEL_CH2
3097 * @arg @ref LL_TIM_CHANNEL_CH3
3098 * @arg @ref LL_TIM_CHANNEL_CH4
3099 * @arg @ref LL_TIM_CHANNEL_CH5
3100 * @arg @ref LL_TIM_CHANNEL_CH6
3101 * @retval None
3102 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)3103 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3104 {
3105 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3106 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3107 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3108 }
3109
3110 /**
3111 * @brief Disable clearing the output channel on an external event.
3112 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3113 * or not a timer instance can clear the OCxREF signal on an external event.
3114 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
3115 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
3116 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
3117 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
3118 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
3119 * CCMR3 OC6CE LL_TIM_OC_DisableClear
3120 * @param TIMx Timer instance
3121 * @param Channel This parameter can be one of the following values:
3122 * @arg @ref LL_TIM_CHANNEL_CH1
3123 * @arg @ref LL_TIM_CHANNEL_CH2
3124 * @arg @ref LL_TIM_CHANNEL_CH3
3125 * @arg @ref LL_TIM_CHANNEL_CH4
3126 * @arg @ref LL_TIM_CHANNEL_CH5
3127 * @arg @ref LL_TIM_CHANNEL_CH6
3128 * @retval None
3129 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)3130 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3131 {
3132 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3133 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3134 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3135 }
3136
3137 /**
3138 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
3139 * @note This function enables clearing the output channel on an external event.
3140 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3141 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3142 * or not a timer instance can clear the OCxREF signal on an external event.
3143 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
3144 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
3145 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
3146 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
3147 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
3148 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
3149 * @param TIMx Timer instance
3150 * @param Channel This parameter can be one of the following values:
3151 * @arg @ref LL_TIM_CHANNEL_CH1
3152 * @arg @ref LL_TIM_CHANNEL_CH2
3153 * @arg @ref LL_TIM_CHANNEL_CH3
3154 * @arg @ref LL_TIM_CHANNEL_CH4
3155 * @arg @ref LL_TIM_CHANNEL_CH5
3156 * @arg @ref LL_TIM_CHANNEL_CH6
3157 * @retval State of bit (1 or 0).
3158 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)3159 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
3160 {
3161 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3162 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3163 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
3164 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3165 }
3166
3167 /**
3168 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
3169 * the Ocx and OCxN signals).
3170 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3171 * dead-time insertion feature is supported by a timer instance.
3172 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
3173 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
3174 * @param TIMx Timer instance
3175 * @param DeadTime between Min_Data=0 and Max_Data=255
3176 * @retval None
3177 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)3178 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
3179 {
3180 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
3181 }
3182
3183 /**
3184 * @brief Set compare value for output channel 1 (TIMx_CCR1).
3185 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3186 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3187 * whether or not a timer instance supports a 32 bits counter.
3188 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3189 * output channel 1 is supported by a timer instance.
3190 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3191 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
3192 * @param TIMx Timer instance
3193 * @param CompareValue between Min_Data=0 and Max_Data=65535
3194 * @retval None
3195 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)3196 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
3197 {
3198 WRITE_REG(TIMx->CCR1, CompareValue);
3199 }
3200
3201 /**
3202 * @brief Set compare value for output channel 2 (TIMx_CCR2).
3203 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3204 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3205 * whether or not a timer instance supports a 32 bits counter.
3206 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3207 * output channel 2 is supported by a timer instance.
3208 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3209 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
3210 * @param TIMx Timer instance
3211 * @param CompareValue between Min_Data=0 and Max_Data=65535
3212 * @retval None
3213 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)3214 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
3215 {
3216 WRITE_REG(TIMx->CCR2, CompareValue);
3217 }
3218
3219 /**
3220 * @brief Set compare value for output channel 3 (TIMx_CCR3).
3221 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3222 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3223 * whether or not a timer instance supports a 32 bits counter.
3224 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3225 * output channel is supported by a timer instance.
3226 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3227 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
3228 * @param TIMx Timer instance
3229 * @param CompareValue between Min_Data=0 and Max_Data=65535
3230 * @retval None
3231 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)3232 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
3233 {
3234 WRITE_REG(TIMx->CCR3, CompareValue);
3235 }
3236
3237 /**
3238 * @brief Set compare value for output channel 4 (TIMx_CCR4).
3239 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3240 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3241 * whether or not a timer instance supports a 32 bits counter.
3242 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3243 * output channel 4 is supported by a timer instance.
3244 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3245 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
3246 * @param TIMx Timer instance
3247 * @param CompareValue between Min_Data=0 and Max_Data=65535
3248 * @retval None
3249 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)3250 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
3251 {
3252 WRITE_REG(TIMx->CCR4, CompareValue);
3253 }
3254
3255 /**
3256 * @brief Set compare value for output channel 5 (TIMx_CCR5).
3257 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3258 * output channel 5 is supported by a timer instance.
3259 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3260 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3261 * @param TIMx Timer instance
3262 * @param CompareValue between Min_Data=0 and Max_Data=65535
3263 * @retval None
3264 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3265 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3266 {
3267 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3268 }
3269
3270 /**
3271 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3272 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3273 * output channel 6 is supported by a timer instance.
3274 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3275 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3276 * @param TIMx Timer instance
3277 * @param CompareValue between Min_Data=0 and Max_Data=65535
3278 * @retval None
3279 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3280 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3281 {
3282 WRITE_REG(TIMx->CCR6, CompareValue);
3283 }
3284
3285 /**
3286 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3287 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3288 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3289 * whether or not a timer instance supports a 32 bits counter.
3290 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3291 * output channel 1 is supported by a timer instance.
3292 * @note If dithering is activated, pay attention to the returned value interpretation.
3293 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3294 * @param TIMx Timer instance
3295 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3296 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)3297 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
3298 {
3299 return (uint32_t)(READ_REG(TIMx->CCR1));
3300 }
3301
3302 /**
3303 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3304 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3305 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3306 * whether or not a timer instance supports a 32 bits counter.
3307 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3308 * output channel 2 is supported by a timer instance.
3309 * @note If dithering is activated, pay attention to the returned value interpretation.
3310 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3311 * @param TIMx Timer instance
3312 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3313 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)3314 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
3315 {
3316 return (uint32_t)(READ_REG(TIMx->CCR2));
3317 }
3318
3319 /**
3320 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3321 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3322 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3323 * whether or not a timer instance supports a 32 bits counter.
3324 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3325 * output channel 3 is supported by a timer instance.
3326 * @note If dithering is activated, pay attention to the returned value interpretation.
3327 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3328 * @param TIMx Timer instance
3329 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3330 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)3331 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
3332 {
3333 return (uint32_t)(READ_REG(TIMx->CCR3));
3334 }
3335
3336 /**
3337 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3338 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3339 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3340 * whether or not a timer instance supports a 32 bits counter.
3341 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3342 * output channel 4 is supported by a timer instance.
3343 * @note If dithering is activated, pay attention to the returned value interpretation.
3344 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3345 * @param TIMx Timer instance
3346 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3347 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)3348 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
3349 {
3350 return (uint32_t)(READ_REG(TIMx->CCR4));
3351 }
3352
3353 /**
3354 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3355 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3356 * output channel 5 is supported by a timer instance.
3357 * @note If dithering is activated, pay attention to the returned value interpretation.
3358 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3359 * @param TIMx Timer instance
3360 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3361 */
LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)3362 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
3363 {
3364 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3365 }
3366
3367 /**
3368 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3369 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3370 * output channel 6 is supported by a timer instance.
3371 * @note If dithering is activated, pay attention to the returned value interpretation.
3372 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3373 * @param TIMx Timer instance
3374 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3375 */
LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)3376 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
3377 {
3378 return (uint32_t)(READ_REG(TIMx->CCR6));
3379 }
3380
3381 /**
3382 * @brief Select on which reference signal the OC5REF is combined to.
3383 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3384 * whether or not a timer instance supports the combined 3-phase PWM mode.
3385 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3386 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3387 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3388 * @param TIMx Timer instance
3389 * @param GroupCH5 This parameter can be a combination of the following values:
3390 * @arg @ref LL_TIM_GROUPCH5_NONE
3391 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3392 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3393 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3394 * @retval None
3395 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3396 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3397 {
3398 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3399 }
3400
3401 /**
3402 * @brief Set the pulse on compare pulse width prescaler.
3403 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3404 * whether or not the pulse on compare feature is supported by the timer
3405 * instance.
3406 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3407 * @param TIMx Timer instance
3408 * @param PulseWidthPrescaler This parameter can be one of the following values:
3409 * @arg @ref LL_TIM_PWPRSC_X1
3410 * @arg @ref LL_TIM_PWPRSC_X2
3411 * @arg @ref LL_TIM_PWPRSC_X4
3412 * @arg @ref LL_TIM_PWPRSC_X8
3413 * @arg @ref LL_TIM_PWPRSC_X16
3414 * @arg @ref LL_TIM_PWPRSC_X32
3415 * @arg @ref LL_TIM_PWPRSC_X64
3416 * @arg @ref LL_TIM_PWPRSC_X128
3417 * @retval None
3418 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3419 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3420 {
3421 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3422 }
3423
3424 /**
3425 * @brief Get the pulse on compare pulse width prescaler.
3426 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3427 * whether or not the pulse on compare feature is supported by the timer
3428 * instance.
3429 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3430 * @param TIMx Timer instance
3431 * @retval Returned value can be one of the following values:
3432 * @arg @ref LL_TIM_PWPRSC_X1
3433 * @arg @ref LL_TIM_PWPRSC_X2
3434 * @arg @ref LL_TIM_PWPRSC_X4
3435 * @arg @ref LL_TIM_PWPRSC_X8
3436 * @arg @ref LL_TIM_PWPRSC_X16
3437 * @arg @ref LL_TIM_PWPRSC_X32
3438 * @arg @ref LL_TIM_PWPRSC_X64
3439 * @arg @ref LL_TIM_PWPRSC_X128
3440 */
LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef * TIMx)3441 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
3442 {
3443 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3444 }
3445
3446 /**
3447 * @brief Set the pulse on compare pulse width duration.
3448 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3449 * whether or not the pulse on compare feature is supported by the timer
3450 * instance.
3451 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3452 * @param TIMx Timer instance
3453 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3454 * @retval None
3455 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3456 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3457 {
3458 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3459 }
3460
3461 /**
3462 * @brief Get the pulse on compare pulse width duration.
3463 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3464 * whether or not the pulse on compare feature is supported by the timer
3465 * instance.
3466 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3467 * @param TIMx Timer instance
3468 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3469 */
LL_TIM_OC_GetPulseWidth(TIM_TypeDef * TIMx)3470 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
3471 {
3472 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3473 }
3474
3475 /**
3476 * @}
3477 */
3478
3479 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3480 * @{
3481 */
3482 /**
3483 * @brief Configure input channel.
3484 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3485 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3486 * CCMR1 IC1F LL_TIM_IC_Config\n
3487 * CCMR1 CC2S LL_TIM_IC_Config\n
3488 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3489 * CCMR1 IC2F LL_TIM_IC_Config\n
3490 * CCMR2 CC3S LL_TIM_IC_Config\n
3491 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3492 * CCMR2 IC3F LL_TIM_IC_Config\n
3493 * CCMR2 CC4S LL_TIM_IC_Config\n
3494 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3495 * CCMR2 IC4F LL_TIM_IC_Config\n
3496 * CCER CC1P LL_TIM_IC_Config\n
3497 * CCER CC1NP LL_TIM_IC_Config\n
3498 * CCER CC2P LL_TIM_IC_Config\n
3499 * CCER CC2NP LL_TIM_IC_Config\n
3500 * CCER CC3P LL_TIM_IC_Config\n
3501 * CCER CC3NP LL_TIM_IC_Config\n
3502 * CCER CC4P LL_TIM_IC_Config\n
3503 * CCER CC4NP LL_TIM_IC_Config
3504 * @param TIMx Timer instance
3505 * @param Channel This parameter can be one of the following values:
3506 * @arg @ref LL_TIM_CHANNEL_CH1
3507 * @arg @ref LL_TIM_CHANNEL_CH2
3508 * @arg @ref LL_TIM_CHANNEL_CH3
3509 * @arg @ref LL_TIM_CHANNEL_CH4
3510 * @param Configuration This parameter must be a combination of all the following values:
3511 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3512 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3513 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3514 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3515 * @retval None
3516 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3517 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3518 {
3519 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3520 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3521 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3522 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3523 << SHIFT_TAB_ICxx[iChannel]);
3524 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3525 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3526 }
3527
3528 /**
3529 * @brief Set the active input.
3530 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3531 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3532 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3533 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3534 * @param TIMx Timer instance
3535 * @param Channel This parameter can be one of the following values:
3536 * @arg @ref LL_TIM_CHANNEL_CH1
3537 * @arg @ref LL_TIM_CHANNEL_CH2
3538 * @arg @ref LL_TIM_CHANNEL_CH3
3539 * @arg @ref LL_TIM_CHANNEL_CH4
3540 * @param ICActiveInput This parameter can be one of the following values:
3541 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3542 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3543 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3544 * @retval None
3545 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3546 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3547 {
3548 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3549 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3550 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3551 }
3552
3553 /**
3554 * @brief Get the current active input.
3555 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3556 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3557 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3558 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3559 * @param TIMx Timer instance
3560 * @param Channel This parameter can be one of the following values:
3561 * @arg @ref LL_TIM_CHANNEL_CH1
3562 * @arg @ref LL_TIM_CHANNEL_CH2
3563 * @arg @ref LL_TIM_CHANNEL_CH3
3564 * @arg @ref LL_TIM_CHANNEL_CH4
3565 * @retval Returned value can be one of the following values:
3566 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3567 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3568 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3569 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)3570 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
3571 {
3572 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3573 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3574 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3575 }
3576
3577 /**
3578 * @brief Set the prescaler of input channel.
3579 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3580 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3581 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3582 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3583 * @param TIMx Timer instance
3584 * @param Channel This parameter can be one of the following values:
3585 * @arg @ref LL_TIM_CHANNEL_CH1
3586 * @arg @ref LL_TIM_CHANNEL_CH2
3587 * @arg @ref LL_TIM_CHANNEL_CH3
3588 * @arg @ref LL_TIM_CHANNEL_CH4
3589 * @param ICPrescaler This parameter can be one of the following values:
3590 * @arg @ref LL_TIM_ICPSC_DIV1
3591 * @arg @ref LL_TIM_ICPSC_DIV2
3592 * @arg @ref LL_TIM_ICPSC_DIV4
3593 * @arg @ref LL_TIM_ICPSC_DIV8
3594 * @retval None
3595 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3596 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3597 {
3598 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3599 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3600 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3601 }
3602
3603 /**
3604 * @brief Get the current prescaler value acting on an input channel.
3605 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3606 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3607 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3608 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3609 * @param TIMx Timer instance
3610 * @param Channel This parameter can be one of the following values:
3611 * @arg @ref LL_TIM_CHANNEL_CH1
3612 * @arg @ref LL_TIM_CHANNEL_CH2
3613 * @arg @ref LL_TIM_CHANNEL_CH3
3614 * @arg @ref LL_TIM_CHANNEL_CH4
3615 * @retval Returned value can be one of the following values:
3616 * @arg @ref LL_TIM_ICPSC_DIV1
3617 * @arg @ref LL_TIM_ICPSC_DIV2
3618 * @arg @ref LL_TIM_ICPSC_DIV4
3619 * @arg @ref LL_TIM_ICPSC_DIV8
3620 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)3621 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
3622 {
3623 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3624 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3625 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3626 }
3627
3628 /**
3629 * @brief Set the input filter duration.
3630 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3631 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3632 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3633 * CCMR2 IC4F LL_TIM_IC_SetFilter
3634 * @param TIMx Timer instance
3635 * @param Channel This parameter can be one of the following values:
3636 * @arg @ref LL_TIM_CHANNEL_CH1
3637 * @arg @ref LL_TIM_CHANNEL_CH2
3638 * @arg @ref LL_TIM_CHANNEL_CH3
3639 * @arg @ref LL_TIM_CHANNEL_CH4
3640 * @param ICFilter This parameter can be one of the following values:
3641 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3642 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3643 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3644 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3645 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3646 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3647 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3648 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3649 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3650 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3651 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3652 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3653 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3654 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3655 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3656 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3657 * @retval None
3658 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3659 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3660 {
3661 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3662 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3663 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3664 }
3665
3666 /**
3667 * @brief Get the input filter duration.
3668 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3669 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3670 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3671 * CCMR2 IC4F LL_TIM_IC_GetFilter
3672 * @param TIMx Timer instance
3673 * @param Channel This parameter can be one of the following values:
3674 * @arg @ref LL_TIM_CHANNEL_CH1
3675 * @arg @ref LL_TIM_CHANNEL_CH2
3676 * @arg @ref LL_TIM_CHANNEL_CH3
3677 * @arg @ref LL_TIM_CHANNEL_CH4
3678 * @retval Returned value can be one of the following values:
3679 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3680 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3681 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3682 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3683 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3684 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3685 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3686 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3687 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3688 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3689 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3690 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3691 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3692 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3693 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3694 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3695 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)3696 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
3697 {
3698 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3699 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3700 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3701 }
3702
3703 /**
3704 * @brief Set the input channel polarity.
3705 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3706 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3707 * CCER CC2P LL_TIM_IC_SetPolarity\n
3708 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3709 * CCER CC3P LL_TIM_IC_SetPolarity\n
3710 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3711 * CCER CC4P LL_TIM_IC_SetPolarity\n
3712 * CCER CC4NP LL_TIM_IC_SetPolarity
3713 * @param TIMx Timer instance
3714 * @param Channel This parameter can be one of the following values:
3715 * @arg @ref LL_TIM_CHANNEL_CH1
3716 * @arg @ref LL_TIM_CHANNEL_CH2
3717 * @arg @ref LL_TIM_CHANNEL_CH3
3718 * @arg @ref LL_TIM_CHANNEL_CH4
3719 * @param ICPolarity This parameter can be one of the following values:
3720 * @arg @ref LL_TIM_IC_POLARITY_RISING
3721 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3722 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3723 * @retval None
3724 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3725 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3726 {
3727 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3728 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3729 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3730 }
3731
3732 /**
3733 * @brief Get the current input channel polarity.
3734 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3735 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3736 * CCER CC2P LL_TIM_IC_GetPolarity\n
3737 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3738 * CCER CC3P LL_TIM_IC_GetPolarity\n
3739 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3740 * CCER CC4P LL_TIM_IC_GetPolarity\n
3741 * CCER CC4NP LL_TIM_IC_GetPolarity
3742 * @param TIMx Timer instance
3743 * @param Channel This parameter can be one of the following values:
3744 * @arg @ref LL_TIM_CHANNEL_CH1
3745 * @arg @ref LL_TIM_CHANNEL_CH2
3746 * @arg @ref LL_TIM_CHANNEL_CH3
3747 * @arg @ref LL_TIM_CHANNEL_CH4
3748 * @retval Returned value can be one of the following values:
3749 * @arg @ref LL_TIM_IC_POLARITY_RISING
3750 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3751 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3752 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)3753 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
3754 {
3755 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3756 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3757 SHIFT_TAB_CCxP[iChannel]);
3758 }
3759
3760 /**
3761 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3762 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3763 * a timer instance provides an XOR input.
3764 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3765 * @param TIMx Timer instance
3766 * @retval None
3767 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3768 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3769 {
3770 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3771 }
3772
3773 /**
3774 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3775 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3776 * a timer instance provides an XOR input.
3777 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3778 * @param TIMx Timer instance
3779 * @retval None
3780 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3781 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3782 {
3783 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3784 }
3785
3786 /**
3787 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3788 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3789 * a timer instance provides an XOR input.
3790 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3791 * @param TIMx Timer instance
3792 * @retval State of bit (1 or 0).
3793 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3794 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3795 {
3796 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3797 }
3798
3799 /**
3800 * @brief Get captured value for input channel 1.
3801 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3802 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3803 * whether or not a timer instance supports a 32 bits counter.
3804 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3805 * input channel 1 is supported by a timer instance.
3806 * @note If dithering is activated, pay attention to the returned value interpretation.
3807 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3808 * @param TIMx Timer instance
3809 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3810 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)3811 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3812 {
3813 return (uint32_t)(READ_REG(TIMx->CCR1));
3814 }
3815
3816 /**
3817 * @brief Get captured value for input channel 2.
3818 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3819 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3820 * whether or not a timer instance supports a 32 bits counter.
3821 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3822 * input channel 2 is supported by a timer instance.
3823 * @note If dithering is activated, pay attention to the returned value interpretation.
3824 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3825 * @param TIMx Timer instance
3826 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3827 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)3828 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3829 {
3830 return (uint32_t)(READ_REG(TIMx->CCR2));
3831 }
3832
3833 /**
3834 * @brief Get captured value for input channel 3.
3835 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3836 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3837 * whether or not a timer instance supports a 32 bits counter.
3838 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3839 * input channel 3 is supported by a timer instance.
3840 * @note If dithering is activated, pay attention to the returned value interpretation.
3841 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3842 * @param TIMx Timer instance
3843 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3844 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)3845 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3846 {
3847 return (uint32_t)(READ_REG(TIMx->CCR3));
3848 }
3849
3850 /**
3851 * @brief Get captured value for input channel 4.
3852 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3853 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3854 * whether or not a timer instance supports a 32 bits counter.
3855 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3856 * input channel 4 is supported by a timer instance.
3857 * @note If dithering is activated, pay attention to the returned value interpretation.
3858 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3859 * @param TIMx Timer instance
3860 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3861 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)3862 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3863 {
3864 return (uint32_t)(READ_REG(TIMx->CCR4));
3865 }
3866
3867 /**
3868 * @}
3869 */
3870
3871 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3872 * @{
3873 */
3874 /**
3875 * @brief Enable external clock mode 2.
3876 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3877 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3878 * whether or not a timer instance supports external clock mode2.
3879 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3880 * @param TIMx Timer instance
3881 * @retval None
3882 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3883 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3884 {
3885 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3886 }
3887
3888 /**
3889 * @brief Disable external clock mode 2.
3890 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3891 * whether or not a timer instance supports external clock mode2.
3892 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3893 * @param TIMx Timer instance
3894 * @retval None
3895 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3896 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3897 {
3898 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3899 }
3900
3901 /**
3902 * @brief Indicate whether external clock mode 2 is enabled.
3903 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3904 * whether or not a timer instance supports external clock mode2.
3905 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3906 * @param TIMx Timer instance
3907 * @retval State of bit (1 or 0).
3908 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)3909 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3910 {
3911 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3912 }
3913
3914 /**
3915 * @brief Set the clock source of the counter clock.
3916 * @note when selected clock source is external clock mode 1, the timer input
3917 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3918 * function. This timer input must be configured by calling
3919 * the @ref LL_TIM_IC_Config() function.
3920 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3921 * whether or not a timer instance supports external clock mode1.
3922 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3923 * whether or not a timer instance supports external clock mode2.
3924 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3925 * SMCR ECE LL_TIM_SetClockSource
3926 * @param TIMx Timer instance
3927 * @param ClockSource This parameter can be one of the following values:
3928 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3929 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3930 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3931 * @retval None
3932 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3933 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3934 {
3935 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3936 }
3937
3938 /**
3939 * @brief Set the encoder interface mode.
3940 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3941 * whether or not a timer instance supports the encoder mode.
3942 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3943 * @param TIMx Timer instance
3944 * @param EncoderMode This parameter can be one of the following values:
3945 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3946 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3947 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3948 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3949 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3950 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3951 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3952 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3953 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3954 * @retval None
3955 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3956 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3957 {
3958 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3959 }
3960
3961 /**
3962 * @}
3963 */
3964
3965 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3966 * @{
3967 */
3968 /**
3969 * @brief Set the trigger output (TRGO) used for timer synchronization .
3970 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3971 * whether or not a timer instance can operate as a master timer.
3972 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3973 * @param TIMx Timer instance
3974 * @param TimerSynchronization This parameter can be one of the following values:
3975 * @arg @ref LL_TIM_TRGO_RESET
3976 * @arg @ref LL_TIM_TRGO_ENABLE
3977 * @arg @ref LL_TIM_TRGO_UPDATE
3978 * @arg @ref LL_TIM_TRGO_CC1IF
3979 * @arg @ref LL_TIM_TRGO_OC1REF
3980 * @arg @ref LL_TIM_TRGO_OC2REF
3981 * @arg @ref LL_TIM_TRGO_OC3REF
3982 * @arg @ref LL_TIM_TRGO_OC4REF
3983 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3984 * @retval None
3985 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3986 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3987 {
3988 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3989 }
3990
3991 /**
3992 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3993 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3994 * whether or not a timer instance can be used for ADC synchronization.
3995 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3996 * @param TIMx Timer Instance
3997 * @param ADCSynchronization This parameter can be one of the following values:
3998 * @arg @ref LL_TIM_TRGO2_RESET
3999 * @arg @ref LL_TIM_TRGO2_ENABLE
4000 * @arg @ref LL_TIM_TRGO2_UPDATE
4001 * @arg @ref LL_TIM_TRGO2_CC1F
4002 * @arg @ref LL_TIM_TRGO2_OC1
4003 * @arg @ref LL_TIM_TRGO2_OC2
4004 * @arg @ref LL_TIM_TRGO2_OC3
4005 * @arg @ref LL_TIM_TRGO2_OC4
4006 * @arg @ref LL_TIM_TRGO2_OC5
4007 * @arg @ref LL_TIM_TRGO2_OC6
4008 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
4009 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
4010 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
4011 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
4012 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
4013 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
4014 * @retval None
4015 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)4016 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
4017 {
4018 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
4019 }
4020
4021 /**
4022 * @brief Set the synchronization mode of a slave timer.
4023 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4024 * a timer instance can operate as a slave timer.
4025 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
4026 * @param TIMx Timer instance
4027 * @param SlaveMode This parameter can be one of the following values:
4028 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
4029 * @arg @ref LL_TIM_SLAVEMODE_RESET
4030 * @arg @ref LL_TIM_SLAVEMODE_GATED
4031 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
4032 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
4033 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
4034 * @retval None
4035 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)4036 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
4037 {
4038 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
4039 }
4040
4041 /**
4042 * @brief Set the selects the trigger input to be used to synchronize the counter.
4043 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4044 * a timer instance can operate as a slave timer.
4045 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
4046 * @param TIMx Timer instance
4047 * @param TriggerInput This parameter can be one of the following values:
4048 * @arg @ref LL_TIM_TS_ITR0
4049 * @arg @ref LL_TIM_TS_ITR1
4050 * @arg @ref LL_TIM_TS_ITR2
4051 * @arg @ref LL_TIM_TS_ITR3
4052 * @arg @ref LL_TIM_TS_TI1F_ED
4053 * @arg @ref LL_TIM_TS_TI1FP1
4054 * @arg @ref LL_TIM_TS_TI2FP2
4055 * @arg @ref LL_TIM_TS_ETRF
4056 * @arg @ref LL_TIM_TS_ITR4
4057 * @arg @ref LL_TIM_TS_ITR5
4058 * @arg @ref LL_TIM_TS_ITR6
4059 * @arg @ref LL_TIM_TS_ITR7
4060 * @arg @ref LL_TIM_TS_ITR8
4061 * @arg @ref LL_TIM_TS_ITR9
4062 * @arg @ref LL_TIM_TS_ITR10
4063 * @arg @ref LL_TIM_TS_ITR11
4064 * @retval None
4065 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)4066 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
4067 {
4068 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
4069 }
4070
4071 /**
4072 * @brief Enable the Master/Slave mode.
4073 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4074 * a timer instance can operate as a slave timer.
4075 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
4076 * @param TIMx Timer instance
4077 * @retval None
4078 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)4079 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
4080 {
4081 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4082 }
4083
4084 /**
4085 * @brief Disable the Master/Slave mode.
4086 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4087 * a timer instance can operate as a slave timer.
4088 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
4089 * @param TIMx Timer instance
4090 * @retval None
4091 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)4092 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
4093 {
4094 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4095 }
4096
4097 /**
4098 * @brief Indicates whether the Master/Slave mode is enabled.
4099 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4100 * a timer instance can operate as a slave timer.
4101 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
4102 * @param TIMx Timer instance
4103 * @retval State of bit (1 or 0).
4104 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)4105 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
4106 {
4107 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
4108 }
4109
4110 /**
4111 * @brief Configure the external trigger (ETR) input.
4112 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
4113 * a timer instance provides an external trigger input.
4114 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
4115 * SMCR ETPS LL_TIM_ConfigETR\n
4116 * SMCR ETF LL_TIM_ConfigETR
4117 * @param TIMx Timer instance
4118 * @param ETRPolarity This parameter can be one of the following values:
4119 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
4120 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
4121 * @param ETRPrescaler This parameter can be one of the following values:
4122 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
4123 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
4124 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
4125 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
4126 * @param ETRFilter This parameter can be one of the following values:
4127 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
4128 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
4129 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
4130 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
4131 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
4132 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
4133 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
4134 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
4135 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
4136 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
4137 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
4138 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
4139 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
4140 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
4141 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
4142 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
4143 * @retval None
4144 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)4145 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
4146 uint32_t ETRFilter)
4147 {
4148 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
4149 }
4150
4151 /**
4152 * @brief Select the external trigger (ETR) input source.
4153 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
4154 * not a timer instance supports ETR source selection.
4155 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
4156 * @param TIMx Timer instance
4157 * @param ETRSource This parameter can be one of the following values:
4158 *
4159 * TIM1: any combination of ETR_RMP where
4160 *
4161 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
4162 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
4163 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
4164 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
4165 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
4166 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
4167 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
4168 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
4169 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
4170 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
4171 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
4172 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
4173 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
4174 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)
4175 *
4176 * TIM2: any combination of ETR_RMP where
4177 *
4178 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
4179 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
4180 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
4181 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
4182 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
4183 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
4184 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
4185 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
4186 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
4187 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
4188 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
4189 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
4190 *
4191 * TIM3: any combination of ETR_RMP where
4192 *
4193 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
4194 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
4195 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
4196 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
4197 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
4198 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
4199 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
4200 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
4201 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
4202 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
4203 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
4204 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
4205 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
4206 *
4207 * TIM4: any combination of ETR_RMP where
4208 *
4209 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
4210 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
4211 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
4212 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
4213 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
4214 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
4215 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
4216 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
4217 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
4218 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)
4219 *
4220 * TIM5: any combination of ETR_RMP where (**)
4221 *
4222 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*)
4223 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
4224 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
4225 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
4226 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
4227 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
4228 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
4229 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
4230 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
4231 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)
4232 *
4233 * TIM8: any combination of ETR_RMP where
4234 *
4235 * . . ETR_RMP can be one of the following values
4236 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
4237 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
4238 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
4239 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
4240 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
4241 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
4242 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
4243 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
4244 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
4245 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
4246 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
4247 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
4248 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
4249 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
4250 *
4251 * TIM20: any combination of ETR_RMP where (**)
4252 *
4253 * . . ETR_RMP can be one of the following values
4254 * @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*)
4255 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
4256 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
4257 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
4258 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
4259 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
4260 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
4261 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
4262 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
4263 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
4264 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
4265 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
4266 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
4267 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)
4268 *
4269 * (*) Value not defined in all devices. \n
4270 * (**) Register not available in all devices.
4271 * @retval None
4272 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)4273 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
4274 {
4275 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
4276 }
4277
4278 /**
4279 * @brief Enable SMS preload.
4280 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4281 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4282 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
4283 * @param TIMx Timer instance
4284 * @retval None
4285 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)4286 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
4287 {
4288 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4289 }
4290
4291 /**
4292 * @brief Disable SMS preload.
4293 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4294 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4295 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
4296 * @param TIMx Timer instance
4297 * @retval None
4298 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)4299 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
4300 {
4301 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4302 }
4303
4304 /**
4305 * @brief Indicate whether SMS preload is enabled.
4306 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4307 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4308 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
4309 * @param TIMx Timer instance
4310 * @retval State of bit (1 or 0).
4311 */
LL_TIM_IsEnabledSMSPreload(TIM_TypeDef * TIMx)4312 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
4313 {
4314 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4315 }
4316
4317 /**
4318 * @brief Set the preload source of SMS.
4319 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4320 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4321 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4322 * @param TIMx Timer instance
4323 * @param PreloadSource This parameter can be one of the following values:
4324 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4325 * @arg @ref LL_TIM_SMSPS_INDEX
4326 * @retval None
4327 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4328 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4329 {
4330 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4331 }
4332
4333 /**
4334 * @brief Get the preload source of SMS.
4335 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4336 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4337 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4338 * @param TIMx Timer instance
4339 * @retval Returned value can be one of the following values:
4340 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4341 * @arg @ref LL_TIM_SMSPS_INDEX
4342 */
LL_TIM_GetSMSPreloadSource(TIM_TypeDef * TIMx)4343 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
4344 {
4345 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4346 }
4347
4348 /**
4349 * @}
4350 */
4351
4352 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4353 * @{
4354 */
4355 /**
4356 * @brief Enable the break function.
4357 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4358 * a timer instance provides a break input.
4359 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4360 * @param TIMx Timer instance
4361 * @retval None
4362 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4363 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4364 {
4365 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4366 }
4367
4368 /**
4369 * @brief Disable the break function.
4370 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4371 * @param TIMx Timer instance
4372 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4373 * a timer instance provides a break input.
4374 * @retval None
4375 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4376 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4377 {
4378 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4379 }
4380
4381 /**
4382 * @brief Configure the break input.
4383 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4384 * a timer instance provides a break input.
4385 * @note Bidirectional mode is only supported by advanced timer instances.
4386 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4387 * a timer instance is an advanced-control timer.
4388 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4389 * in input mode and in open drain output mode. Any active Break event will
4390 * assert a low logic level on the Break input to indicate an internal break
4391 * event to external devices.
4392 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4393 * LL_TIM_BREAK_AFMODE_INPUT.
4394 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4395 * BDTR BKF LL_TIM_ConfigBRK\n
4396 * BDTR BKBID LL_TIM_ConfigBRK
4397 * @param TIMx Timer instance
4398 * @param BreakPolarity This parameter can be one of the following values:
4399 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4400 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4401 * @param BreakFilter This parameter can be one of the following values:
4402 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4403 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4404 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4405 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4406 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4407 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4408 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4409 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4410 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4411 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4412 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4413 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4414 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4415 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4416 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4417 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4418 * @param BreakAFMode This parameter can be one of the following values:
4419 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4420 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4421 * @retval None
4422 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4423 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4424 uint32_t BreakAFMode)
4425 {
4426 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4427 }
4428
4429 /**
4430 * @brief Disarm the break input (when it operates in bidirectional mode).
4431 * @note The break input can be disarmed only when it is configured in
4432 * bidirectional mode and when when MOE is reset.
4433 * @note Purpose is to be able to have the input voltage back to high-state,
4434 * whatever the time constant on the output .
4435 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4436 * @param TIMx Timer instance
4437 * @retval None
4438 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4439 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4440 {
4441 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4442 }
4443
4444 /**
4445 * @brief Re-arm the break input (when it operates in bidirectional mode).
4446 * @note The Break input is automatically armed as soon as MOE bit is set.
4447 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
4448 * @param TIMx Timer instance
4449 * @retval None
4450 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)4451 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
4452 {
4453 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4454 }
4455
4456 /**
4457 * @brief Enable the break 2 function.
4458 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4459 * a timer instance provides a second break input.
4460 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4461 * @param TIMx Timer instance
4462 * @retval None
4463 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4464 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4465 {
4466 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4467 }
4468
4469 /**
4470 * @brief Disable the break 2 function.
4471 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4472 * a timer instance provides a second break input.
4473 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4474 * @param TIMx Timer instance
4475 * @retval None
4476 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4477 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4478 {
4479 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4480 }
4481
4482 /**
4483 * @brief Configure the break 2 input.
4484 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4485 * a timer instance provides a second break input.
4486 * @note Bidirectional mode is only supported by advanced timer instances.
4487 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4488 * a timer instance is an advanced-control timer.
4489 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4490 * in input mode and in open drain output mode. Any active Break event will
4491 * assert a low logic level on the Break 2 input to indicate an internal break
4492 * event to external devices.
4493 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4494 * LL_TIM_BREAK2_AFMODE_INPUT.
4495 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4496 * BDTR BK2F LL_TIM_ConfigBRK2\n
4497 * BDTR BK2BID LL_TIM_ConfigBRK2
4498 * @param TIMx Timer instance
4499 * @param Break2Polarity This parameter can be one of the following values:
4500 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4501 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4502 * @param Break2Filter This parameter can be one of the following values:
4503 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4504 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4505 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4506 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4507 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4508 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4509 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4510 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4511 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4512 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4513 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4514 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4515 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4516 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4517 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4518 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4519 * @param Break2AFMode This parameter can be one of the following values:
4520 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4521 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4522 * @retval None
4523 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4524 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4525 uint32_t Break2AFMode)
4526 {
4527 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4528 }
4529
4530 /**
4531 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4532 * @note The break 2 input can be disarmed only when it is configured in
4533 * bidirectional mode and when when MOE is reset.
4534 * @note Purpose is to be able to have the input voltage back to high-state,
4535 * whatever the time constant on the output.
4536 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4537 * @param TIMx Timer instance
4538 * @retval None
4539 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4540 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4541 {
4542 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4543 }
4544
4545 /**
4546 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
4547 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
4548 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
4549 * @param TIMx Timer instance
4550 * @retval None
4551 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)4552 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
4553 {
4554 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4555 }
4556
4557 /**
4558 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4559 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4560 * a timer instance provides a break input.
4561 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4562 * BDTR OSSR LL_TIM_SetOffStates
4563 * @param TIMx Timer instance
4564 * @param OffStateIdle This parameter can be one of the following values:
4565 * @arg @ref LL_TIM_OSSI_DISABLE
4566 * @arg @ref LL_TIM_OSSI_ENABLE
4567 * @param OffStateRun This parameter can be one of the following values:
4568 * @arg @ref LL_TIM_OSSR_DISABLE
4569 * @arg @ref LL_TIM_OSSR_ENABLE
4570 * @retval None
4571 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4572 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4573 {
4574 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4575 }
4576
4577 /**
4578 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4579 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4580 * a timer instance provides a break input.
4581 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4582 * @param TIMx Timer instance
4583 * @retval None
4584 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4585 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4586 {
4587 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4588 }
4589
4590 /**
4591 * @brief Disable automatic output (MOE can be set only by software).
4592 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4593 * a timer instance provides a break input.
4594 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4595 * @param TIMx Timer instance
4596 * @retval None
4597 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4598 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4599 {
4600 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4601 }
4602
4603 /**
4604 * @brief Indicate whether automatic output is enabled.
4605 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4606 * a timer instance provides a break input.
4607 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4608 * @param TIMx Timer instance
4609 * @retval State of bit (1 or 0).
4610 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)4611 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
4612 {
4613 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4614 }
4615
4616 /**
4617 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4618 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4619 * software and is reset in case of break or break2 event
4620 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4621 * a timer instance provides a break input.
4622 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4623 * @param TIMx Timer instance
4624 * @retval None
4625 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4626 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4627 {
4628 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4629 }
4630
4631 /**
4632 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4633 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4634 * software and is reset in case of break or break2 event.
4635 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4636 * a timer instance provides a break input.
4637 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4638 * @param TIMx Timer instance
4639 * @retval None
4640 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4641 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4642 {
4643 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4644 }
4645
4646 /**
4647 * @brief Indicates whether outputs are enabled.
4648 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4649 * a timer instance provides a break input.
4650 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4651 * @param TIMx Timer instance
4652 * @retval State of bit (1 or 0).
4653 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)4654 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
4655 {
4656 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4657 }
4658
4659 /**
4660 * @brief Enable the signals connected to the designated timer break input.
4661 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4662 * or not a timer instance allows for break input selection.
4663 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4664 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4665 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4666 * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
4667 * AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n
4668 * AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n
4669 * AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n
4670 * AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n
4671 * AF2 BK2NE LL_TIM_EnableBreakInputSource\n
4672 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4673 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4674 * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
4675 * AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n
4676 * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n
4677 * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n
4678 * AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
4679 * @param TIMx Timer instance
4680 * @param BreakInput This parameter can be one of the following values:
4681 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4682 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4683 * @param Source This parameter can be one of the following values:
4684 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4685 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4686 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4687 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4688 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4689 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4690 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4691 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4692 *
4693 * (*) Value not defined in all devices.
4694 * @retval None
4695 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4696 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4697 {
4698 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4699 SET_BIT(*pReg, Source);
4700 }
4701
4702 /**
4703 * @brief Disable the signals connected to the designated timer break input.
4704 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4705 * or not a timer instance allows for break input selection.
4706 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4707 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4708 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4709 * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
4710 * AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n
4711 * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n
4712 * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n
4713 * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n
4714 * AF2 BKINE LL_TIM_DisableBreakInputSource\n
4715 * AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n
4716 * AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n
4717 * AF2 BKCMP3E LL_TIM_DisableBreakInputSource\n
4718 * AF2 BKCMP4E LL_TIM_DisableBreakInputSource\n
4719 * AF2 BKCMP5E LL_TIM_DisableBreakInputSource\n
4720 * AF2 BKCMP6E LL_TIM_DisableBreakInputSource\n
4721 * AF2 BKCMP7E LL_TIM_DisableBreakInputSource
4722 * @param TIMx Timer instance
4723 * @param BreakInput This parameter can be one of the following values:
4724 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4725 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4726 * @param Source This parameter can be one of the following values:
4727 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4728 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4729 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4730 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4731 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4732 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4733 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4734 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4735 *
4736 * (*) Value not defined in all devices.
4737 * @retval None
4738 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4739 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4740 {
4741 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4742 CLEAR_BIT(*pReg, Source);
4743 }
4744
4745 /**
4746 * @brief Set the polarity of the break signal for the timer break input.
4747 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4748 * or not a timer instance allows for break input selection.
4749 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4750 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4751 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4752 * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
4753 * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n
4754 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4755 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4756 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
4757 * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n
4758 * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity
4759 * @param TIMx Timer instance
4760 * @param BreakInput This parameter can be one of the following values:
4761 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4762 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4763 * @param Source This parameter can be one of the following values:
4764 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4765 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4766 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4767 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4768 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4769 * @param Polarity This parameter can be one of the following values:
4770 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4771 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4772 * @retval None
4773 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4774 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4775 uint32_t Polarity)
4776 {
4777 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4778 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4779 }
4780 /**
4781 * @brief Enable asymmetrical deadtime.
4782 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4783 * a timer instance provides asymmetrical deadtime.
4784 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4785 * @param TIMx Timer instance
4786 * @retval None
4787 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4788 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4789 {
4790 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4791 }
4792
4793 /**
4794 * @brief Disable asymmetrical dead-time.
4795 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4796 * a timer instance provides asymmetrical deadtime.
4797 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4798 * @param TIMx Timer instance
4799 * @retval None
4800 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4801 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4802 {
4803 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4804 }
4805
4806 /**
4807 * @brief Indicates whether asymmetrical deadtime is activated.
4808 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4809 * a timer instance provides asymmetrical deadtime.
4810 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4811 * @param TIMx Timer instance
4812 * @retval State of bit (1 or 0).
4813 */
LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef * TIMx)4814 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4815 {
4816 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4817 }
4818
4819 /**
4820 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4821 * rising edge of OCxN signals).
4822 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4823 * asymmetrical dead-time insertion feature is supported by a timer instance.
4824 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4825 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4826 * (LOCK bits in TIMx_BDTR register).
4827 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4828 * @param TIMx Timer instance
4829 * @param DeadTime between Min_Data=0 and Max_Data=255
4830 * @retval None
4831 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4832 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4833 {
4834 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4835 }
4836
4837 /**
4838 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4839 * the rising edge of OCxN signals).
4840 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4841 * asymmetrical dead-time insertion feature is supported by a timer instance.
4842 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4843 * (LOCK bits in TIMx_BDTR register).
4844 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4845 * @param TIMx Timer instance
4846 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4847 */
LL_TIM_GetFallingDeadTime(TIM_TypeDef * TIMx)4848 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
4849 {
4850 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4851 }
4852
4853 /**
4854 * @brief Enable deadtime preload.
4855 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4856 * a timer instance provides deadtime preload.
4857 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4858 * @param TIMx Timer instance
4859 * @retval None
4860 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4861 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4862 {
4863 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4864 }
4865
4866 /**
4867 * @brief Disable dead-time preload.
4868 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4869 * a timer instance provides deadtime preload.
4870 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4871 * @param TIMx Timer instance
4872 * @retval None
4873 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4874 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4875 {
4876 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4877 }
4878
4879 /**
4880 * @brief Indicates whether deadtime preload is activated.
4881 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4882 * a timer instance provides deadtime preload.
4883 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4884 * @param TIMx Timer instance
4885 * @retval State of bit (1 or 0).
4886 */
LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef * TIMx)4887 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
4888 {
4889 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4890 }
4891
4892 /**
4893 * @}
4894 */
4895
4896 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4897 * @{
4898 */
4899 /**
4900 * @brief Configures the timer DMA burst feature.
4901 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4902 * not a timer instance supports the DMA burst mode.
4903 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4904 * DCR DBA LL_TIM_ConfigDMABurst
4905 * @param TIMx Timer instance
4906 * @param DMABurstBaseAddress This parameter can be one of the following values:
4907 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4908 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4909 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4910 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4911 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4912 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4913 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4914 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4915 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4916 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4917 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4918 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4919 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4920 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4921 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4922 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4923 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4924 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4925 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4926 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4927 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4928 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4929 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4930 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4931 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4932 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4933 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
4934 * @param DMABurstLength This parameter can be one of the following values:
4935 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4936 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4937 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4938 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4939 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4940 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4941 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4942 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4943 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4944 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4945 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4946 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4947 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4948 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4949 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4950 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4951 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4952 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4953 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4954 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4955 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4956 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4957 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4958 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4959 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4960 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4961 * @retval None
4962 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)4963 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
4964 {
4965 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
4966 }
4967
4968 /**
4969 * @}
4970 */
4971
4972 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4973 * @{
4974 */
4975
4976 /**
4977 * @brief Enable encoder index.
4978 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4979 * a timer instance provides an index input.
4980 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4981 * @param TIMx Timer instance
4982 * @retval None
4983 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4984 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4985 {
4986 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4987 }
4988
4989 /**
4990 * @brief Disable encoder index.
4991 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4992 * a timer instance provides an index input.
4993 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4994 * @param TIMx Timer instance
4995 * @retval None
4996 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4997 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4998 {
4999 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
5000 }
5001
5002 /**
5003 * @brief Indicate whether encoder index is enabled.
5004 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5005 * a timer instance provides an index input.
5006 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
5007 * @param TIMx Timer instance
5008 * @retval State of bit (1 or 0).
5009 */
LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef * TIMx)5010 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
5011 {
5012 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
5013 }
5014
5015 /**
5016 * @brief Set index direction
5017 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5018 * a timer instance provides an index input.
5019 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
5020 * @param TIMx Timer instance
5021 * @param IndexDirection This parameter can be one of the following values:
5022 * @arg @ref LL_TIM_INDEX_UP_DOWN
5023 * @arg @ref LL_TIM_INDEX_UP
5024 * @arg @ref LL_TIM_INDEX_DOWN
5025 * @retval None
5026 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)5027 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
5028 {
5029 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
5030 }
5031
5032 /**
5033 * @brief Get actual index direction
5034 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5035 * a timer instance provides an index input.
5036 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
5037 * @param TIMx Timer instance
5038 * @retval Returned value can be one of the following values:
5039 * @arg @ref LL_TIM_INDEX_UP_DOWN
5040 * @arg @ref LL_TIM_INDEX_UP
5041 * @arg @ref LL_TIM_INDEX_DOWN
5042 */
LL_TIM_GetIndexDirection(TIM_TypeDef * TIMx)5043 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
5044 {
5045 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
5046 }
5047
5048 /**
5049 * @brief Enable first index.
5050 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5051 * a timer instance provides an index input.
5052 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
5053 * @param TIMx Timer instance
5054 * @retval None
5055 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)5056 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
5057 {
5058 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
5059 }
5060
5061 /**
5062 * @brief Disable first index.
5063 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5064 * a timer instance provides an index input.
5065 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
5066 * @param TIMx Timer instance
5067 * @retval None
5068 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)5069 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
5070 {
5071 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
5072 }
5073
5074 /**
5075 * @brief Indicates whether first index is enabled.
5076 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5077 * a timer instance provides an index input.
5078 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
5079 * @param TIMx Timer instance
5080 * @retval State of bit (1 or 0).
5081 */
LL_TIM_IsEnabledFirstIndex(TIM_TypeDef * TIMx)5082 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
5083 {
5084 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
5085 }
5086
5087 /**
5088 * @brief Set index positioning
5089 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5090 * a timer instance provides an index input.
5091 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
5092 * @param TIMx Timer instance
5093 * @param IndexPositionning This parameter can be one of the following values:
5094 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5095 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5096 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5097 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5098 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5099 * @arg @ref LL_TIM_INDEX_POSITION_UP
5100 * @retval None
5101 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)5102 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
5103 {
5104 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
5105 }
5106
5107 /**
5108 * @brief Get actual index positioning
5109 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5110 * a timer instance provides an index input.
5111 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
5112 * @param TIMx Timer instance
5113 * @retval Returned value can be one of the following values:
5114 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5115 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5116 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5117 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5118 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5119 * @arg @ref LL_TIM_INDEX_POSITION_UP
5120 */
LL_TIM_GetIndexPositionning(TIM_TypeDef * TIMx)5121 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
5122 {
5123 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
5124 }
5125
5126 /**
5127 * @brief Configure encoder index.
5128 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5129 * a timer instance provides an index input.
5130 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
5131 * ECR FIDX LL_TIM_ConfigIDX\n
5132 * ECR IPOS LL_TIM_ConfigIDX
5133 * @param TIMx Timer instance
5134 * @param Configuration This parameter must be a combination of all the following values:
5135 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
5136 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
5137 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
5138 * @retval None
5139 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)5140 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
5141 {
5142 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
5143 }
5144
5145 /**
5146 * @}
5147 */
5148
5149 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
5150 * @{
5151 */
5152 /**
5153 * @brief Remap TIM inputs (input channel, internal/external triggers).
5154 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
5155 * a some timer inputs can be remapped.
5156 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
5157 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
5158 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
5159 * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
5160 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
5161 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
5162 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
5163 * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
5164 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
5165 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
5166 * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
5167 * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
5168 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
5169 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
5170 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
5171 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
5172 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
5173 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
5174 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
5175 * TIM20_TISEL TI1SEL LL_TIM_SetRemap
5176 * @param TIMx Timer instance
5177 * @param Remap Remap param depends on the TIMx. Description available only
5178 * in CHM version of the User Manual (not in .pdf).
5179 * Otherwise see Reference Manual description of TISEL registers.
5180 *
5181 * Below description summarizes "Timer Instance" and "Remap" param combinations:
5182 *
5183 * TIM1: one of the following values
5184 *
5185 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
5186 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
5187 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
5188 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
5189 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
5190 *
5191 * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
5192 *
5193 * . . TI1_RMP can be one of the following values
5194 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
5195 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
5196 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
5197 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
5198 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
5199 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
5200 *
5201 * . . TI2_RMP can be one of the following values
5202 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
5203 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
5204 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
5205 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
5206 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
5207 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
5208 *
5209 * . . TI3_RMP can be one of the following values
5210 * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
5211 * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
5212 *
5213 * . . TI4_RMP can be one of the following values
5214 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
5215 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
5216 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
5217 *
5218 * TIM3: any combination of TI1_RMP and TI2_RMP where
5219 *
5220 * . . TI1_RMP can be one of the following values
5221 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
5222 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
5223 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
5224 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
5225 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
5226 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
5227 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
5228 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
5229 *
5230 * . . TI2_RMP can be one of the following values
5231 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
5232 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
5233 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
5234 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
5235 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
5236 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
5237 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
5238 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
5239 *
5240 * . . TI3_RMP can be one of the following values
5241 * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
5242 * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
5243 *
5244 * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
5245 *
5246 * . . TI1_RMP can be one of the following values
5247 * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
5248 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
5249 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
5250 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
5251 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
5252 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
5253 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
5254 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
5255 *
5256 * . . TI2_RMP can be one of the following values
5257 * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
5258 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
5259 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
5260 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
5261 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
5262 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
5263 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
5264 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
5265 *
5266 * . . TI3_RMP can be one of the following values
5267 * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
5268 * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
5269 *
5270 * . . TI4_RMP can be one of the following values
5271 * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
5272 * @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
5273 *
5274 * TIM5: any combination of TI1_RMP and TI2_RMP where (**)
5275 *
5276 * . . TI1_RMP can be one of the following values
5277 * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*)
5278 * @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*)
5279 * @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*)
5280 * @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
5281 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*)
5282 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*)
5283 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*)
5284 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*)
5285 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*)
5286 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*)
5287 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*)
5288 *
5289 * . . TI2_RMP can be one of the following values
5290 * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*)
5291 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
5292 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
5293 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
5294 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
5295 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
5296 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
5297 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
5298 *
5299 * TIM8: one of the following values
5300 *
5301 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
5302 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
5303 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
5304 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
5305 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
5306 *
5307 * TIM15: any combination of TI1_RMP and TI2_RMP where
5308 *
5309 * . . TI1_RMP can be one of the following values
5310 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
5311 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
5312 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
5313 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
5314 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
5315 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
5316 *
5317 * . . TI2_RMP can be one of the following values
5318 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
5319 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
5320 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
5321 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
5322 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
5323 *
5324 * TIM16: one of the following values
5325 *
5326 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
5327 * @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
5328 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
5329 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
5330 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
5331 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
5332 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
5333 *
5334 * TIM17: one of the following values
5335 *
5336 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
5337 * @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
5338 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
5339 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
5340 * @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
5341 * @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
5342 * @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
5343 *
5344 * TIM20: one of the following values (**)
5345 *
5346 * @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*)
5347 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
5348 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
5349 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
5350 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
5351 *
5352 * (*) Value not defined in all devices. \n
5353 * (**) Register not available in all devices.
5354 *
5355 *
5356 * @retval None
5357 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)5358 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
5359 {
5360 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
5361 }
5362
5363 /**
5364 * @brief Enable request for HSE/32 clock used for TISEL remap.
5365 * @note Only TIM16 and TIM17 support HSE/32 remap
5366 * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
5367 * @param TIMx Timer instance
5368 * @retval None
5369 */
LL_TIM_EnableHSE32(TIM_TypeDef * TIMx)5370 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
5371 {
5372 SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
5373 }
5374
5375 /**
5376 * @brief Disable request for HSE/32 clock used for TISEL remap.
5377 * @note Only TIM16 and TIM17 support HSE/32 remap
5378 * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
5379 * @param TIMx Timer instance
5380 * @retval None
5381 */
LL_TIM_DisableHSE32(TIM_TypeDef * TIMx)5382 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
5383 {
5384 CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
5385 }
5386
5387 /**
5388 * @brief Indicate whether request for HSE/32 clock is enabled.
5389 * @note Only TIM16 and TIM17 support HSE/32 remap
5390 * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
5391 * @param TIMx Timer instance
5392 * @retval State of bit (1 or 0).
5393 */
LL_TIM_IsEnabledHSE32(TIM_TypeDef * TIMx)5394 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
5395 {
5396 return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
5397 }
5398
5399 /**
5400 * @}
5401 */
5402
5403 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
5404 * @{
5405 */
5406 /**
5407 * @brief Set the OCREF clear input source
5408 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
5409 * @note This function can only be used in Output compare and PWM modes.
5410 * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
5411 * or not a timer instance can configure OCREF clear input source.
5412 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
5413 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
5414 * @param TIMx Timer instance
5415 * @param OCRefClearInputSource This parameter can be one of the following values:
5416 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
5417 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
5418 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
5419 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
5420 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
5421 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
5422 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
5423 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
5424 *
5425 * (*) Value not defined in all devices. \n
5426 * @retval None
5427 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)5428 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
5429 {
5430 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
5431 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
5432 MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
5433 }
5434 /**
5435 * @}
5436 */
5437
5438 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
5439 * @{
5440 */
5441 /**
5442 * @brief Clear the update interrupt flag (UIF).
5443 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5444 * @param TIMx Timer instance
5445 * @retval None
5446 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5447 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5448 {
5449 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5450 }
5451
5452 /**
5453 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5454 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5455 * @param TIMx Timer instance
5456 * @retval State of bit (1 or 0).
5457 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)5458 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
5459 {
5460 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5461 }
5462
5463 /**
5464 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5465 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5466 * @param TIMx Timer instance
5467 * @retval None
5468 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5469 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5470 {
5471 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5472 }
5473
5474 /**
5475 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5476 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5477 * @param TIMx Timer instance
5478 * @retval State of bit (1 or 0).
5479 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)5480 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
5481 {
5482 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5483 }
5484
5485 /**
5486 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5487 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5488 * @param TIMx Timer instance
5489 * @retval None
5490 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5491 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5492 {
5493 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5494 }
5495
5496 /**
5497 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5498 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5499 * @param TIMx Timer instance
5500 * @retval State of bit (1 or 0).
5501 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)5502 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
5503 {
5504 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5505 }
5506
5507 /**
5508 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5509 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5510 * @param TIMx Timer instance
5511 * @retval None
5512 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5513 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5514 {
5515 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5516 }
5517
5518 /**
5519 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5520 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5521 * @param TIMx Timer instance
5522 * @retval State of bit (1 or 0).
5523 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)5524 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
5525 {
5526 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5527 }
5528
5529 /**
5530 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5531 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5532 * @param TIMx Timer instance
5533 * @retval None
5534 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5535 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5536 {
5537 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5538 }
5539
5540 /**
5541 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5542 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5543 * @param TIMx Timer instance
5544 * @retval State of bit (1 or 0).
5545 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)5546 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
5547 {
5548 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5549 }
5550
5551 /**
5552 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5553 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5554 * @param TIMx Timer instance
5555 * @retval None
5556 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5557 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5558 {
5559 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5560 }
5561
5562 /**
5563 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5564 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5565 * @param TIMx Timer instance
5566 * @retval State of bit (1 or 0).
5567 */
LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)5568 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
5569 {
5570 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5571 }
5572
5573 /**
5574 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5575 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5576 * @param TIMx Timer instance
5577 * @retval None
5578 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5579 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5580 {
5581 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5582 }
5583
5584 /**
5585 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5586 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5587 * @param TIMx Timer instance
5588 * @retval State of bit (1 or 0).
5589 */
LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)5590 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
5591 {
5592 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5593 }
5594
5595 /**
5596 * @brief Clear the commutation interrupt flag (COMIF).
5597 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5598 * @param TIMx Timer instance
5599 * @retval None
5600 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5601 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5602 {
5603 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5604 }
5605
5606 /**
5607 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5608 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5609 * @param TIMx Timer instance
5610 * @retval State of bit (1 or 0).
5611 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)5612 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
5613 {
5614 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5615 }
5616
5617 /**
5618 * @brief Clear the trigger interrupt flag (TIF).
5619 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5620 * @param TIMx Timer instance
5621 * @retval None
5622 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5623 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5624 {
5625 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5626 }
5627
5628 /**
5629 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5630 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5631 * @param TIMx Timer instance
5632 * @retval State of bit (1 or 0).
5633 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)5634 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
5635 {
5636 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5637 }
5638
5639 /**
5640 * @brief Clear the break interrupt flag (BIF).
5641 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5642 * @param TIMx Timer instance
5643 * @retval None
5644 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5645 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5646 {
5647 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5648 }
5649
5650 /**
5651 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5652 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5653 * @param TIMx Timer instance
5654 * @retval State of bit (1 or 0).
5655 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)5656 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
5657 {
5658 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5659 }
5660
5661 /**
5662 * @brief Clear the break 2 interrupt flag (B2IF).
5663 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5664 * @param TIMx Timer instance
5665 * @retval None
5666 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5667 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5668 {
5669 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5670 }
5671
5672 /**
5673 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5674 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5675 * @param TIMx Timer instance
5676 * @retval State of bit (1 or 0).
5677 */
LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)5678 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
5679 {
5680 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5681 }
5682
5683 /**
5684 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5685 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5686 * @param TIMx Timer instance
5687 * @retval None
5688 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5689 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5690 {
5691 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5692 }
5693
5694 /**
5695 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5696 * (Capture/Compare 1 interrupt is pending).
5697 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5698 * @param TIMx Timer instance
5699 * @retval State of bit (1 or 0).
5700 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)5701 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
5702 {
5703 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5704 }
5705
5706 /**
5707 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5708 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5709 * @param TIMx Timer instance
5710 * @retval None
5711 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5712 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5713 {
5714 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5715 }
5716
5717 /**
5718 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5719 * (Capture/Compare 2 over-capture interrupt is pending).
5720 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5721 * @param TIMx Timer instance
5722 * @retval State of bit (1 or 0).
5723 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)5724 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
5725 {
5726 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5727 }
5728
5729 /**
5730 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5731 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5732 * @param TIMx Timer instance
5733 * @retval None
5734 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5735 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5736 {
5737 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5738 }
5739
5740 /**
5741 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5742 * (Capture/Compare 3 over-capture interrupt is pending).
5743 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5744 * @param TIMx Timer instance
5745 * @retval State of bit (1 or 0).
5746 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)5747 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
5748 {
5749 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5750 }
5751
5752 /**
5753 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5754 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5755 * @param TIMx Timer instance
5756 * @retval None
5757 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5758 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5759 {
5760 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5761 }
5762
5763 /**
5764 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5765 * (Capture/Compare 4 over-capture interrupt is pending).
5766 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5767 * @param TIMx Timer instance
5768 * @retval State of bit (1 or 0).
5769 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)5770 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
5771 {
5772 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5773 }
5774
5775 /**
5776 * @brief Clear the system break interrupt flag (SBIF).
5777 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5778 * @param TIMx Timer instance
5779 * @retval None
5780 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5781 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5782 {
5783 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5784 }
5785
5786 /**
5787 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5788 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5789 * @param TIMx Timer instance
5790 * @retval State of bit (1 or 0).
5791 */
LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)5792 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
5793 {
5794 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5795 }
5796
5797 /**
5798 * @brief Clear the transition error interrupt flag (TERRF).
5799 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5800 * a timer instance provides encoder error management.
5801 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5802 * @param TIMx Timer instance
5803 * @retval None
5804 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5805 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5806 {
5807 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5808 }
5809
5810 /**
5811 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5812 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5813 * a timer instance provides encoder error management.
5814 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5815 * @param TIMx Timer instance
5816 * @retval State of bit (1 or 0).
5817 */
LL_TIM_IsActiveFlag_TERR(TIM_TypeDef * TIMx)5818 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
5819 {
5820 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5821 }
5822
5823 /**
5824 * @brief Clear the index error interrupt flag (IERRF).
5825 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5826 * a timer instance provides encoder error management.
5827 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5828 * @param TIMx Timer instance
5829 * @retval None
5830 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5831 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5832 {
5833 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5834 }
5835
5836 /**
5837 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5838 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5839 * a timer instance provides encoder error management.
5840 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5841 * @param TIMx Timer instance
5842 * @retval State of bit (1 or 0).
5843 */
LL_TIM_IsActiveFlag_IERR(TIM_TypeDef * TIMx)5844 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
5845 {
5846 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5847 }
5848
5849 /**
5850 * @brief Clear the direction change interrupt flag (DIRF).
5851 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5852 * a timer instance provides encoder interrupt management.
5853 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5854 * @param TIMx Timer instance
5855 * @retval None
5856 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5857 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5858 {
5859 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5860 }
5861
5862 /**
5863 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5864 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5865 * a timer instance provides encoder interrupt management.
5866 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5867 * @param TIMx Timer instance
5868 * @retval State of bit (1 or 0).
5869 */
LL_TIM_IsActiveFlag_DIR(TIM_TypeDef * TIMx)5870 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
5871 {
5872 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5873 }
5874
5875 /**
5876 * @brief Clear the index interrupt flag (IDXF).
5877 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5878 * a timer instance provides encoder interrupt management.
5879 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5880 * @param TIMx Timer instance
5881 * @retval None
5882 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5883 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5884 {
5885 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5886 }
5887
5888 /**
5889 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5890 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5891 * a timer instance provides encoder interrupt management.
5892 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5893 * @param TIMx Timer instance
5894 * @retval State of bit (1 or 0).
5895 */
LL_TIM_IsActiveFlag_IDX(TIM_TypeDef * TIMx)5896 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
5897 {
5898 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5899 }
5900 /**
5901 * @}
5902 */
5903
5904 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5905 * @{
5906 */
5907 /**
5908 * @brief Enable update interrupt (UIE).
5909 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5910 * @param TIMx Timer instance
5911 * @retval None
5912 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5913 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5914 {
5915 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5916 }
5917
5918 /**
5919 * @brief Disable update interrupt (UIE).
5920 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5921 * @param TIMx Timer instance
5922 * @retval None
5923 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5924 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5925 {
5926 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5927 }
5928
5929 /**
5930 * @brief Indicates whether the update interrupt (UIE) is enabled.
5931 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5932 * @param TIMx Timer instance
5933 * @retval State of bit (1 or 0).
5934 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)5935 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
5936 {
5937 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5938 }
5939
5940 /**
5941 * @brief Enable capture/compare 1 interrupt (CC1IE).
5942 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5943 * @param TIMx Timer instance
5944 * @retval None
5945 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5946 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5947 {
5948 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5949 }
5950
5951 /**
5952 * @brief Disable capture/compare 1 interrupt (CC1IE).
5953 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5954 * @param TIMx Timer instance
5955 * @retval None
5956 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5957 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5958 {
5959 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5960 }
5961
5962 /**
5963 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5964 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5965 * @param TIMx Timer instance
5966 * @retval State of bit (1 or 0).
5967 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)5968 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
5969 {
5970 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5971 }
5972
5973 /**
5974 * @brief Enable capture/compare 2 interrupt (CC2IE).
5975 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5976 * @param TIMx Timer instance
5977 * @retval None
5978 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5979 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5980 {
5981 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5982 }
5983
5984 /**
5985 * @brief Disable capture/compare 2 interrupt (CC2IE).
5986 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5987 * @param TIMx Timer instance
5988 * @retval None
5989 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5990 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5991 {
5992 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5993 }
5994
5995 /**
5996 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5997 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5998 * @param TIMx Timer instance
5999 * @retval State of bit (1 or 0).
6000 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)6001 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
6002 {
6003 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
6004 }
6005
6006 /**
6007 * @brief Enable capture/compare 3 interrupt (CC3IE).
6008 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
6009 * @param TIMx Timer instance
6010 * @retval None
6011 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)6012 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
6013 {
6014 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
6015 }
6016
6017 /**
6018 * @brief Disable capture/compare 3 interrupt (CC3IE).
6019 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
6020 * @param TIMx Timer instance
6021 * @retval None
6022 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)6023 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
6024 {
6025 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
6026 }
6027
6028 /**
6029 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
6030 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
6031 * @param TIMx Timer instance
6032 * @retval State of bit (1 or 0).
6033 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)6034 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
6035 {
6036 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
6037 }
6038
6039 /**
6040 * @brief Enable capture/compare 4 interrupt (CC4IE).
6041 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
6042 * @param TIMx Timer instance
6043 * @retval None
6044 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)6045 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
6046 {
6047 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
6048 }
6049
6050 /**
6051 * @brief Disable capture/compare 4 interrupt (CC4IE).
6052 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
6053 * @param TIMx Timer instance
6054 * @retval None
6055 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)6056 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
6057 {
6058 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
6059 }
6060
6061 /**
6062 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
6063 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
6064 * @param TIMx Timer instance
6065 * @retval State of bit (1 or 0).
6066 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)6067 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
6068 {
6069 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
6070 }
6071
6072 /**
6073 * @brief Enable commutation interrupt (COMIE).
6074 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
6075 * @param TIMx Timer instance
6076 * @retval None
6077 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)6078 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
6079 {
6080 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
6081 }
6082
6083 /**
6084 * @brief Disable commutation interrupt (COMIE).
6085 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
6086 * @param TIMx Timer instance
6087 * @retval None
6088 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)6089 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
6090 {
6091 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
6092 }
6093
6094 /**
6095 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
6096 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
6097 * @param TIMx Timer instance
6098 * @retval State of bit (1 or 0).
6099 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)6100 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
6101 {
6102 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
6103 }
6104
6105 /**
6106 * @brief Enable trigger interrupt (TIE).
6107 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
6108 * @param TIMx Timer instance
6109 * @retval None
6110 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)6111 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
6112 {
6113 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
6114 }
6115
6116 /**
6117 * @brief Disable trigger interrupt (TIE).
6118 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
6119 * @param TIMx Timer instance
6120 * @retval None
6121 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)6122 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
6123 {
6124 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
6125 }
6126
6127 /**
6128 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
6129 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
6130 * @param TIMx Timer instance
6131 * @retval State of bit (1 or 0).
6132 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)6133 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
6134 {
6135 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
6136 }
6137
6138 /**
6139 * @brief Enable break interrupt (BIE).
6140 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
6141 * @param TIMx Timer instance
6142 * @retval None
6143 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)6144 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
6145 {
6146 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
6147 }
6148
6149 /**
6150 * @brief Disable break interrupt (BIE).
6151 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
6152 * @param TIMx Timer instance
6153 * @retval None
6154 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)6155 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
6156 {
6157 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
6158 }
6159
6160 /**
6161 * @brief Indicates whether the break interrupt (BIE) is enabled.
6162 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
6163 * @param TIMx Timer instance
6164 * @retval State of bit (1 or 0).
6165 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)6166 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
6167 {
6168 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
6169 }
6170
6171 /**
6172 * @brief Enable transition error interrupt (TERRIE).
6173 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6174 * a timer instance provides encoder error management.
6175 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
6176 * @param TIMx Timer instance
6177 * @retval None
6178 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)6179 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
6180 {
6181 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6182 }
6183
6184 /**
6185 * @brief Disable transition error interrupt (TERRIE).
6186 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6187 * a timer instance provides encoder error management.
6188 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
6189 * @param TIMx Timer instance
6190 * @retval None
6191 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)6192 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
6193 {
6194 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6195 }
6196
6197 /**
6198 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
6199 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6200 * a timer instance provides encoder error management.
6201 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
6202 * @param TIMx Timer instance
6203 * @retval State of bit (1 or 0).
6204 */
LL_TIM_IsEnabledIT_TERR(TIM_TypeDef * TIMx)6205 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
6206 {
6207 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
6208 }
6209
6210 /**
6211 * @brief Enable index error interrupt (IERRIE).
6212 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6213 * a timer instance provides encoder error management.
6214 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
6215 * @param TIMx Timer instance
6216 * @retval None
6217 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)6218 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
6219 {
6220 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6221 }
6222
6223 /**
6224 * @brief Disable index error interrupt (IERRIE).
6225 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6226 * a timer instance provides encoder error management.
6227 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
6228 * @param TIMx Timer instance
6229 * @retval None
6230 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)6231 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
6232 {
6233 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6234 }
6235
6236 /**
6237 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
6238 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6239 * a timer instance provides encoder error management.
6240 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
6241 * @param TIMx Timer instance
6242 * @retval State of bit (1 or 0).
6243 */
LL_TIM_IsEnabledIT_IERR(TIM_TypeDef * TIMx)6244 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
6245 {
6246 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
6247 }
6248
6249 /**
6250 * @brief Enable direction change interrupt (DIRIE).
6251 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6252 * a timer instance provides encoder interrupt management.
6253 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
6254 * @param TIMx Timer instance
6255 * @retval None
6256 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)6257 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
6258 {
6259 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6260 }
6261
6262 /**
6263 * @brief Disable direction change interrupt (DIRIE).
6264 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6265 * a timer instance provides encoder interrupt management.
6266 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
6267 * @param TIMx Timer instance
6268 * @retval None
6269 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)6270 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
6271 {
6272 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6273 }
6274
6275 /**
6276 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
6277 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6278 * a timer instance provides encoder interrupt management.
6279 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
6280 * @param TIMx Timer instance
6281 * @retval State of bit (1 or 0).
6282 */
LL_TIM_IsEnabledIT_DIR(TIM_TypeDef * TIMx)6283 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
6284 {
6285 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
6286 }
6287
6288 /**
6289 * @brief Enable index interrupt (IDXIE).
6290 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6291 * a timer instance provides encoder interrupt management.
6292 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
6293 * @param TIMx Timer instance
6294 * @retval None
6295 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)6296 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
6297 {
6298 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6299 }
6300
6301 /**
6302 * @brief Disable index interrupt (IDXIE).
6303 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6304 * a timer instance provides encoder interrupt management.
6305 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
6306 * @param TIMx Timer instance
6307 * @retval None
6308 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)6309 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
6310 {
6311 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6312 }
6313
6314 /**
6315 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
6316 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6317 * a timer instance provides encoder interrupt management.
6318 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
6319 * @param TIMx Timer instance
6320 * @retval State of bit (1 or 0).
6321 */
LL_TIM_IsEnabledIT_IDX(TIM_TypeDef * TIMx)6322 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
6323 {
6324 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
6325 }
6326
6327 /**
6328 * @}
6329 */
6330
6331 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
6332 * @{
6333 */
6334 /**
6335 * @brief Enable update DMA request (UDE).
6336 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
6337 * @param TIMx Timer instance
6338 * @retval None
6339 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)6340 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6341 {
6342 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
6343 }
6344
6345 /**
6346 * @brief Disable update DMA request (UDE).
6347 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
6348 * @param TIMx Timer instance
6349 * @retval None
6350 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)6351 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6352 {
6353 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
6354 }
6355
6356 /**
6357 * @brief Indicates whether the update DMA request (UDE) is enabled.
6358 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
6359 * @param TIMx Timer instance
6360 * @retval State of bit (1 or 0).
6361 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)6362 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
6363 {
6364 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
6365 }
6366
6367 /**
6368 * @brief Enable capture/compare 1 DMA request (CC1DE).
6369 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
6370 * @param TIMx Timer instance
6371 * @retval None
6372 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)6373 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
6374 {
6375 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6376 }
6377
6378 /**
6379 * @brief Disable capture/compare 1 DMA request (CC1DE).
6380 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
6381 * @param TIMx Timer instance
6382 * @retval None
6383 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)6384 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
6385 {
6386 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6387 }
6388
6389 /**
6390 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
6391 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
6392 * @param TIMx Timer instance
6393 * @retval State of bit (1 or 0).
6394 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)6395 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
6396 {
6397 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
6398 }
6399
6400 /**
6401 * @brief Enable capture/compare 2 DMA request (CC2DE).
6402 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
6403 * @param TIMx Timer instance
6404 * @retval None
6405 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)6406 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
6407 {
6408 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6409 }
6410
6411 /**
6412 * @brief Disable capture/compare 2 DMA request (CC2DE).
6413 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
6414 * @param TIMx Timer instance
6415 * @retval None
6416 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)6417 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
6418 {
6419 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6420 }
6421
6422 /**
6423 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
6424 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
6425 * @param TIMx Timer instance
6426 * @retval State of bit (1 or 0).
6427 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)6428 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
6429 {
6430 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
6431 }
6432
6433 /**
6434 * @brief Enable capture/compare 3 DMA request (CC3DE).
6435 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
6436 * @param TIMx Timer instance
6437 * @retval None
6438 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)6439 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
6440 {
6441 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6442 }
6443
6444 /**
6445 * @brief Disable capture/compare 3 DMA request (CC3DE).
6446 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6447 * @param TIMx Timer instance
6448 * @retval None
6449 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6450 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6451 {
6452 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6453 }
6454
6455 /**
6456 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6457 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6458 * @param TIMx Timer instance
6459 * @retval State of bit (1 or 0).
6460 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)6461 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
6462 {
6463 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6464 }
6465
6466 /**
6467 * @brief Enable capture/compare 4 DMA request (CC4DE).
6468 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6469 * @param TIMx Timer instance
6470 * @retval None
6471 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6472 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6473 {
6474 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6475 }
6476
6477 /**
6478 * @brief Disable capture/compare 4 DMA request (CC4DE).
6479 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6480 * @param TIMx Timer instance
6481 * @retval None
6482 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6483 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6484 {
6485 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6486 }
6487
6488 /**
6489 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6490 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6491 * @param TIMx Timer instance
6492 * @retval State of bit (1 or 0).
6493 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)6494 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
6495 {
6496 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6497 }
6498
6499 /**
6500 * @brief Enable commutation DMA request (COMDE).
6501 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6502 * @param TIMx Timer instance
6503 * @retval None
6504 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6505 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6506 {
6507 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6508 }
6509
6510 /**
6511 * @brief Disable commutation DMA request (COMDE).
6512 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6513 * @param TIMx Timer instance
6514 * @retval None
6515 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6516 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6517 {
6518 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6519 }
6520
6521 /**
6522 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6523 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6524 * @param TIMx Timer instance
6525 * @retval State of bit (1 or 0).
6526 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)6527 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
6528 {
6529 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6530 }
6531
6532 /**
6533 * @brief Enable trigger interrupt (TDE).
6534 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6535 * @param TIMx Timer instance
6536 * @retval None
6537 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6538 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6539 {
6540 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6541 }
6542
6543 /**
6544 * @brief Disable trigger interrupt (TDE).
6545 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6546 * @param TIMx Timer instance
6547 * @retval None
6548 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6549 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6550 {
6551 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6552 }
6553
6554 /**
6555 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6556 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6557 * @param TIMx Timer instance
6558 * @retval State of bit (1 or 0).
6559 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)6560 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
6561 {
6562 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6563 }
6564
6565 /**
6566 * @}
6567 */
6568
6569 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6570 * @{
6571 */
6572 /**
6573 * @brief Generate an update event.
6574 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6575 * @param TIMx Timer instance
6576 * @retval None
6577 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6578 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6579 {
6580 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6581 }
6582
6583 /**
6584 * @brief Generate Capture/Compare 1 event.
6585 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6586 * @param TIMx Timer instance
6587 * @retval None
6588 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6589 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6590 {
6591 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6592 }
6593
6594 /**
6595 * @brief Generate Capture/Compare 2 event.
6596 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6597 * @param TIMx Timer instance
6598 * @retval None
6599 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6600 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6601 {
6602 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6603 }
6604
6605 /**
6606 * @brief Generate Capture/Compare 3 event.
6607 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6608 * @param TIMx Timer instance
6609 * @retval None
6610 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6611 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6612 {
6613 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6614 }
6615
6616 /**
6617 * @brief Generate Capture/Compare 4 event.
6618 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6619 * @param TIMx Timer instance
6620 * @retval None
6621 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6622 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6623 {
6624 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6625 }
6626
6627 /**
6628 * @brief Generate commutation event.
6629 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6630 * @param TIMx Timer instance
6631 * @retval None
6632 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6633 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6634 {
6635 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6636 }
6637
6638 /**
6639 * @brief Generate trigger event.
6640 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6641 * @param TIMx Timer instance
6642 * @retval None
6643 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6644 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6645 {
6646 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6647 }
6648
6649 /**
6650 * @brief Generate break event.
6651 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6652 * @param TIMx Timer instance
6653 * @retval None
6654 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6655 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6656 {
6657 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6658 }
6659
6660 /**
6661 * @brief Generate break 2 event.
6662 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6663 * @param TIMx Timer instance
6664 * @retval None
6665 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6666 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6667 {
6668 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6669 }
6670
6671 /**
6672 * @}
6673 */
6674
6675 #if defined(USE_FULL_LL_DRIVER)
6676 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6677 * @{
6678 */
6679
6680 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
6681 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6682 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
6683 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6684 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6685 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6686 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6687 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6688 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6689 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6690 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6691 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6692 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6693 /**
6694 * @}
6695 */
6696 #endif /* USE_FULL_LL_DRIVER */
6697
6698 /**
6699 * @}
6700 */
6701
6702 /**
6703 * @}
6704 */
6705
6706 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
6707
6708 /**
6709 * @}
6710 */
6711
6712 #ifdef __cplusplus
6713 }
6714 #endif
6715
6716 #endif /* __STM32G4xx_LL_TIM_H */
6717
