1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WBAxx_LL_TIM_H
21 #define __STM32WBAxx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x04U, /* 7: TIMx_CH4N */
55 0x38U, /* 8: TIMx_CH5 */
56 0x38U /* 9: TIMx_CH6 */
57
58 };
59
60 static const uint8_t SHIFT_TAB_OCxx[] =
61 {
62 0U, /* 0: OC1M, OC1FE, OC1PE */
63 0U, /* 1: - NA */
64 8U, /* 2: OC2M, OC2FE, OC2PE */
65 0U, /* 3: - NA */
66 0U, /* 4: OC3M, OC3FE, OC3PE */
67 0U, /* 5: - NA */
68 8U, /* 6: OC4M, OC4FE, OC4PE */
69 0U, /* 7: - NA */
70 0U, /* 8: OC5M, OC5FE, OC5PE */
71 8U /* 9: OC6M, OC6FE, OC6PE */
72 };
73
74 static const uint8_t SHIFT_TAB_ICxx[] =
75 {
76 0U, /* 0: CC1S, IC1PSC, IC1F */
77 0U, /* 1: - NA */
78 8U, /* 2: CC2S, IC2PSC, IC2F */
79 0U, /* 3: - NA */
80 0U, /* 4: CC3S, IC3PSC, IC3F */
81 0U, /* 5: - NA */
82 8U, /* 6: CC4S, IC4PSC, IC4F */
83 0U, /* 7: - NA */
84 0U, /* 8: - NA */
85 0U /* 9: - NA */
86 };
87
88 static const uint8_t SHIFT_TAB_CCxP[] =
89 {
90 0U, /* 0: CC1P */
91 2U, /* 1: CC1NP */
92 4U, /* 2: CC2P */
93 6U, /* 3: CC2NP */
94 8U, /* 4: CC3P */
95 10U, /* 5: CC3NP */
96 12U, /* 6: CC4P */
97 14U, /* 7: CC4NP */
98 16U, /* 8: CC5P */
99 20U /* 9: CC6P */
100 };
101
102 static const uint8_t SHIFT_TAB_OISx[] =
103 {
104 0U, /* 0: OIS1 */
105 1U, /* 1: OIS1N */
106 2U, /* 2: OIS2 */
107 3U, /* 3: OIS2N */
108 4U, /* 4: OIS3 */
109 5U, /* 5: OIS3N */
110 6U, /* 6: OIS4 */
111 7U, /* 7: OIS4N */
112 8U, /* 8: OIS5 */
113 10U /* 9: OIS6 */
114 };
115 /**
116 * @}
117 */
118
119 /* Private constants ---------------------------------------------------------*/
120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
121 * @{
122 */
123
124 /* Defines used for the bit position in the register and perform offsets */
125 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
126
127 /* Generic bit definitions for TIMx_AF1 register */
128 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
129 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
130
131
132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
133 #define DT_DELAY_1 ((uint8_t)0x7F)
134 #define DT_DELAY_2 ((uint8_t)0x3F)
135 #define DT_DELAY_3 ((uint8_t)0x1F)
136 #define DT_DELAY_4 ((uint8_t)0x1F)
137
138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
139 #define DT_RANGE_1 ((uint8_t)0x00)
140 #define DT_RANGE_2 ((uint8_t)0x80)
141 #define DT_RANGE_3 ((uint8_t)0xC0)
142 #define DT_RANGE_4 ((uint8_t)0xE0)
143
144 /** Legacy definitions for compatibility purpose
145 @cond 0
146 */
147 /**
148 @endcond
149 */
150
151 #define OCREF_CLEAR_SELECT_POS (28U)
152 #define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */
153 /**
154 * @}
155 */
156
157 /* Private macros ------------------------------------------------------------*/
158 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
159 * @{
160 */
161 /** @brief Convert channel id into channel index.
162 * @param __CHANNEL__ This parameter can be one of the following values:
163 * @arg @ref LL_TIM_CHANNEL_CH1
164 * @arg @ref LL_TIM_CHANNEL_CH1N
165 * @arg @ref LL_TIM_CHANNEL_CH2
166 * @arg @ref LL_TIM_CHANNEL_CH2N
167 * @arg @ref LL_TIM_CHANNEL_CH3
168 * @arg @ref LL_TIM_CHANNEL_CH3N
169 * @arg @ref LL_TIM_CHANNEL_CH4
170 * @arg @ref LL_TIM_CHANNEL_CH4N
171 * @arg @ref LL_TIM_CHANNEL_CH5
172 * @arg @ref LL_TIM_CHANNEL_CH6
173 * @retval none
174 */
175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
176 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
185
186 /** @brief Calculate the deadtime sampling period(in ps).
187 * @param __TIMCLK__ timer input clock frequency (in Hz).
188 * @param __CKD__ This parameter can be one of the following values:
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
192 * @retval none
193 */
194 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
195 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
196 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
197 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
198 /**
199 * @}
200 */
201
202
203 /* Exported types ------------------------------------------------------------*/
204 #if defined(USE_FULL_LL_DRIVER)
205 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
206 * @{
207 */
208
209 /**
210 * @brief TIM Time Base configuration structure definition.
211 */
212 typedef struct
213 {
214 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
215 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
216
217 This feature can be modified afterwards using unitary function
218 @ref LL_TIM_SetPrescaler().*/
219
220 uint32_t CounterMode; /*!< Specifies the counter mode.
221 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetCounterMode().*/
225
226 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
227 Auto-Reload Register at the next update event.
228 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
229 Some timer instances may support 32 bits counters. In that case this parameter must
230 be a number between 0x0000 and 0xFFFFFFFF.
231
232 This feature can be modified afterwards using unitary function
233 @ref LL_TIM_SetAutoReload().*/
234
235 uint32_t ClockDivision; /*!< Specifies the clock division.
236 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetClockDivision().*/
240
241 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
242 reaches zero, an update event is generated and counting restarts
243 from the RCR value (N).
244 This means in PWM mode that (N+1) corresponds to:
245 - the number of PWM periods in edge-aligned mode
246 - the number of half PWM period in center-aligned mode
247 GP timers: this parameter must be a number between Min_Data = 0x00 and
248 Max_Data = 0xFF.
249 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
250 Max_Data = 0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 @ref LL_TIM_SetRepetitionCounter().*/
254 } LL_TIM_InitTypeDef;
255
256 /**
257 * @brief TIM Output Compare configuration structure definition.
258 */
259 typedef struct
260 {
261 uint32_t OCMode; /*!< Specifies the output mode.
262 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetMode().*/
266
267 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
268 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
269
270 This feature can be modified afterwards using unitary functions
271 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
272
273 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
274 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
275
276 This feature can be modified afterwards using unitary functions
277 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
278
279 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
280 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
281
282 This feature can be modified afterwards using unitary function
283 LL_TIM_OC_SetCompareCHx (x=1..6).*/
284
285 uint32_t OCPolarity; /*!< Specifies the output polarity.
286 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
287
288 This feature can be modified afterwards using unitary function
289 @ref LL_TIM_OC_SetPolarity().*/
290
291 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
292 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_OC_SetPolarity().*/
296
297
298 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
299 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
300
301 This feature can be modified afterwards using unitary function
302 @ref LL_TIM_OC_SetIdleState().*/
303
304 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetIdleState().*/
309 } LL_TIM_OC_InitTypeDef;
310
311 /**
312 * @brief TIM Input Capture configuration structure definition.
313 */
314
315 typedef struct
316 {
317
318 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
319 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
320
321 This feature can be modified afterwards using unitary function
322 @ref LL_TIM_IC_SetPolarity().*/
323
324 uint32_t ICActiveInput; /*!< Specifies the input.
325 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
326
327 This feature can be modified afterwards using unitary function
328 @ref LL_TIM_IC_SetActiveInput().*/
329
330 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
331 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetPrescaler().*/
335
336 uint32_t ICFilter; /*!< Specifies the input capture filter.
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetFilter().*/
341 } LL_TIM_IC_InitTypeDef;
342
343
344 /**
345 * @brief TIM Encoder interface configuration structure definition.
346 */
347 typedef struct
348 {
349 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
350 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_SetEncoderMode().*/
354
355 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
356 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetPolarity().*/
360
361 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
362 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetActiveInput().*/
366
367 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
368 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetPrescaler().*/
372
373 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
374 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetFilter().*/
378
379 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
380 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetPolarity().*/
384
385 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
386 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetActiveInput().*/
390
391 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
392 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetPrescaler().*/
396
397 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
398 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetFilter().*/
402
403 } LL_TIM_ENCODER_InitTypeDef;
404
405 /**
406 * @brief TIM Hall sensor interface configuration structure definition.
407 */
408 typedef struct
409 {
410
411 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
412 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
413
414 This feature can be modified afterwards using unitary function
415 @ref LL_TIM_IC_SetPolarity().*/
416
417 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
418 Prescaler must be set to get a maximum counter period longer than the
419 time interval between 2 consecutive changes on the Hall inputs.
420 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
421
422 This feature can be modified afterwards using unitary function
423 @ref LL_TIM_IC_SetPrescaler().*/
424
425 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
426 This parameter can be a value of
427 @ref TIM_LL_EC_IC_FILTER.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_IC_SetFilter().*/
431
432 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
433 A positive pulse (TRGO event) is generated with a programmable delay every time
434 a change occurs on the Hall inputs.
435 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
436
437 This feature can be modified afterwards using unitary function
438 @ref LL_TIM_OC_SetCompareCH2().*/
439 } LL_TIM_HALLSENSOR_InitTypeDef;
440
441 /**
442 * @brief BDTR (Break and Dead Time) structure definition
443 */
444 typedef struct
445 {
446 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
447 This parameter can be a value of @ref TIM_LL_EC_OSSR
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_SetOffStates()
451
452 @note This bit-field cannot be modified as long as LOCK level 2 has been
453 programmed. */
454
455 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
456 This parameter can be a value of @ref TIM_LL_EC_OSSI
457
458 This feature can be modified afterwards using unitary function
459 @ref LL_TIM_SetOffStates()
460
461 @note This bit-field cannot be modified as long as LOCK level 2 has been
462 programmed. */
463
464 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
465 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
466
467 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
468 register has been written, their content is frozen until the next reset.*/
469
470 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
471 switching-on of the outputs.
472 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
473
474 This feature can be modified afterwards using unitary function
475 @ref LL_TIM_OC_SetDeadTime()
476
477 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
478 programmed. */
479
480 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
482
483 This feature can be modified afterwards using unitary functions
484 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been
487 programmed. */
488
489 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
490 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
491
492 This feature can be modified afterwards using unitary function
493 @ref LL_TIM_ConfigBRK()
494
495 @note This bit-field can not be modified as long as LOCK level 1 has been
496 programmed. */
497
498 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
499 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
500
501 This feature can be modified afterwards using unitary function
502 @ref LL_TIM_ConfigBRK()
503
504 @note This bit-field can not be modified as long as LOCK level 1 has been
505 programmed. */
506
507 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
508 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
509
510 This feature can be modified afterwards using unitary functions
511 @ref LL_TIM_ConfigBRK()
512
513 @note Bidirectional break input is only supported by advanced timers instances.
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
523
524 @note This bit-field can not be modified as long as LOCK level 1 has been
525 programmed. */
526
527 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
528 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
529
530 This feature can be modified afterwards using unitary function
531 @ref LL_TIM_ConfigBRK2()
532
533 @note This bit-field can not be modified as long as LOCK level 1 has been
534 programmed. */
535
536 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
537 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
538
539 This feature can be modified afterwards using unitary function
540 @ref LL_TIM_ConfigBRK2()
541
542 @note This bit-field can not be modified as long as LOCK level 1 has been
543 programmed. */
544
545 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
546 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
547
548 This feature can be modified afterwards using unitary functions
549 @ref LL_TIM_ConfigBRK2()
550
551 @note Bidirectional break input is only supported by advanced timers instances.
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
557 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
561
562 @note This bit-field can not be modified as long as LOCK level 1 has been
563 programmed. */
564 } LL_TIM_BDTR_InitTypeDef;
565
566 /**
567 * @}
568 */
569 #endif /* USE_FULL_LL_DRIVER */
570
571 /* Exported constants --------------------------------------------------------*/
572 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
573 * @{
574 */
575
576 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
577 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
578 * @{
579 */
580 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
581 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
582 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
583 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
584 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
585 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
586 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
587 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
588 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
589 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
590 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
591 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
592 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
593 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
594 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
595 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
596 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
597 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
598 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
599 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
600 /**
601 * @}
602 */
603
604 #if defined(USE_FULL_LL_DRIVER)
605 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
606 * @{
607 */
608 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
609 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
615 * @{
616 */
617 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
618 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
624 * @{
625 */
626 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
627 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
628 /**
629 * @}
630 */
631 #endif /* USE_FULL_LL_DRIVER */
632
633 /** @defgroup TIM_LL_EC_IT IT Defines
634 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
635 * @{
636 */
637 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
638 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
639 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
640 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
641 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
642 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
643 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
644 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
645 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
646 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
647 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
648 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
654 * @{
655 */
656 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
657 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
663 * @{
664 */
665 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
666 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
672 * @{
673 */
674 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
675 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
676 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
677 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
678 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
684 * @{
685 */
686 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
687 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
688 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
694 * @{
695 */
696 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
697 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
703 * @{
704 */
705 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
706 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
712 * @{
713 */
714 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
715 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
716 /**
717 * @}
718 */
719
720 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
721 * @{
722 */
723 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
724 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
725 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
726 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_CHANNEL Channel
732 * @{
733 */
734 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
735 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
736 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
737 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
738 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
739 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
740 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
741 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
742 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
743 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
744 /**
745 * @}
746 */
747
748 #if defined(USE_FULL_LL_DRIVER)
749 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
750 * @{
751 */
752 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
753 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
754 /**
755 * @}
756 */
757 #endif /* USE_FULL_LL_DRIVER */
758
759 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
760 * @{
761 */
762 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
763 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
764 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
765 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
766 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
767 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
768 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
769 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
770 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
771 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
772 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
773 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
774 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
775 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
776 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
777 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
783 * @{
784 */
785 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
786 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
792 * @{
793 */
794 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
795 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
801 * @{
802 */
803 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
804 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
805 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
806 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
812 * @{
813 */
814 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
815 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
816 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
817 /**
818 * @}
819 */
820
821 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
822 * @{
823 */
824 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
825 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
826 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
827 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
828 /**
829 * @}
830 */
831
832 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
833 * @{
834 */
835 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
836 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
837 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
838 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
839 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
841 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
842 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
843 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
844 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
845 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
846 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
847 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
848 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
849 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
850 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
856 * @{
857 */
858 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
859 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
860 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
866 * @{
867 */
868 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
869 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
870 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
876 * @{
877 */
878 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
879 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
880 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
881 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
882 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
883 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
884 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
885 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
886 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
887 /**
888 * @}
889 */
890
891 /** @defgroup TIM_LL_EC_TRGO Trigger Output
892 * @{
893 */
894 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
895 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
896 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
897 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
898 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
899 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
900 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
901 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
902 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
903 /**
904 * @}
905 */
906
907 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
908 * @{
909 */
910 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
911 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
912 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
913 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
915 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
916 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
917 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
918 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
919 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
920 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
921 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
922 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
923 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
924 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
926 /**
927 * @}
928 */
929
930 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
931 * @{
932 */
933 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
934 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
935 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
936 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
937 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
938 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
939 the counter are controlled. */
940 /**
941 * @}
942 */
943
944 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
945 * @{
946 */
947 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
948 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
949 /**
950 * @}
951 */
952
953 /** @defgroup TIM_LL_EC_TS Trigger Selection
954 * @{
955 */
956 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
957 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
958 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
959 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
960 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
961 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
962 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
963 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
964 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
965 /**
966 * @}
967 */
968
969 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
970 * @{
971 */
972 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
973 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
974 /**
975 * @}
976 */
977
978 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
979 * @{
980 */
981 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
982 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
983 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
984 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
985 /**
986 * @}
987 */
988
989 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
990 * @{
991 */
992 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
993 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
994 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
995 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
996 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
997 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
998 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
999 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1000 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1001 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1002 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1003 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1004 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1005 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1006 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1007 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1013 * @{
1014 */
1015 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1016 #if defined(COMP1) && defined(COMP2)
1017 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1018 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1019 #endif /* COMP1 && COMP2 */
1020 #define LL_TIM_TIM1_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1021 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1022 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1023 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1029 * @{
1030 */
1031 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1032 #if defined(COMP1) && defined(COMP2)
1033 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1034 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1035 #endif /* COMP1 && COMP2 */
1036 #define LL_TIM_TIM2_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1037 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1038 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1044 * @{
1045 */
1046 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1047 #if defined(COMP1) && defined(COMP2)
1048 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1049 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1050 #endif /* COMP1 && COMP2 */
1051 #define LL_TIM_TIM3_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1052 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1053 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1054 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
1055 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC1 analog watchdog 2 */
1056 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1062 * @{
1063 */
1064 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1065 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1071 * @{
1072 */
1073 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1074 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1075 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1076 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1077 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1078 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1079 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1080 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1081 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1082 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1083 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1084 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1085 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1086 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1087 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1088 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1089 /**
1090 * @}
1091 */
1092
1093 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1094 * @{
1095 */
1096 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1097 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1098 /**
1099 * @}
1100 */
1101
1102 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1103 * @{
1104 */
1105 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1106 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1107 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1108 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1109 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1110 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1111 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1112 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1113 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1114 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1115 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1116 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1117 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1118 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1119 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1120 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1121 /**
1122 * @}
1123 */
1124
1125 /** @defgroup TIM_LL_EC_OSSI OSSI
1126 * @{
1127 */
1128 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1129 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1130 /**
1131 * @}
1132 */
1133
1134 /** @defgroup TIM_LL_EC_OSSR OSSR
1135 * @{
1136 */
1137 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1138 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1139 /**
1140 * @}
1141 */
1142
1143 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1144 * @{
1145 */
1146 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1147 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1148 /**
1149 * @}
1150 */
1151
1152 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1153 * @{
1154 */
1155 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1156 #if defined(COMP1) && defined(COMP2)
1157 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1158 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1159 #endif /* COMP1 && COMP2 */
1160 /**
1161 * @}
1162 */
1163
1164 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1165 * @{
1166 */
1167 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1168 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1169 /**
1170 * @}
1171 */
1172
1173 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1174 * @{
1175 */
1176 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1177 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1178 /**
1179 * @}
1180 */
1181
1182 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1183 * @{
1184 */
1185 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1186 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1187 /**
1188 * @}
1189 */
1190
1191 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1192 * @{
1193 */
1194 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1195 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1196 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1197 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1198 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1199 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1200 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1201 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1202 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1203 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1204 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1205 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1206 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1207 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1208 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1209 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1210 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1211 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1212 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1213 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1214 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1215 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1216 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1217 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1218 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1219 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1220 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst */
1221 /**
1222 * @}
1223 */
1224
1225 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1226 * @{
1227 */
1228 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1229 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1230 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1231 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1232 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1233 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1234 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1235 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1236 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1237 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1238 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1239 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1240 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1241 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1242 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1243 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1244 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1245 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1246 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1247 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1248 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1249 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1250 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1251 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1252 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1253 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1254 /**
1255 * @}
1256 */
1257
1258 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1259 * @{
1260 */
1261 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1262 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1263 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1264 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1265 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1266 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1267 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1268 /**
1269 * @}
1270 */
1271 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1272 * @{
1273 */
1274 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL /*!< TIM1 TI1 is connected to GPIO */
1275 #if defined(COMP1) && defined(COMP2)
1276 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 TI1 is connected to COMP1 output */
1277 #define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 TI1 is connected to COMP2 output */
1278 #endif /* COMP1 && COMP2 */
1279 /**
1280 * @}
1281 */
1282
1283 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1284 * @{
1285 */
1286 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2 TI1 is connected to GPIO */
1287 #if defined(COMP1) && defined(COMP2)
1288 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 TI1 is connected to COMP1 output */
1289 #define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 TI1 is connected to COMP2 output */
1290 #endif /* COMP1 && COMP2 */
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM16 External Input Ch2 Remap
1296 * @{
1297 */
1298 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2 TI2 is connected to GPIO */
1299 #if defined(COMP1) && defined(COMP2)
1300 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 TI2 is connected to COMP1 output */
1301 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 TI2 is connected to COMP2 output */
1302 #endif /* COMP1 && COMP2 */
1303 /**
1304 * @}
1305 */
1306
1307 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1308 * @{
1309 */
1310 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2 TI4 is connected to COMP1 output */
1311 #if defined(COMP1) && defined(COMP2)
1312 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 TI4 is connected to COMP1 output */
1313 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 TI4 is connected to COMP2 output */
1314 #endif /* COMP1 && COMP2 */
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1320 * @{
1321 */
1322 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3 TI1 is connected to GPIO */
1323 #if defined(COMP1) && defined(COMP2)
1324 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 TI1 is connected to COMP1 output */
1325 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 TI1 is connected to COMP2 output */
1326 #endif /* COMP1 && COMP2 */
1327 /**
1328 * @}
1329 */
1330
1331 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
1332 * @{
1333 */
1334 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3 TI2 is connected to GPIO */
1335 #if defined(COMP1) && defined(COMP2)
1336 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 TI2 is connected to COMP1 output */
1337 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 TI2 is connected to COMP2 output */
1338 #endif /* COMP1 && COMP2 */
1339 /**
1340 * @}
1341 */
1342
1343 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1344 * @{
1345 */
1346 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16 TI1 is connected to GPIO */
1347 #define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to MCO */
1348 #define LL_TIM_TIM16_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSE DIV32 */
1349 #define LL_TIM_TIM16_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM16 TI1 is connected to RTC */
1350 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to LSE */
1351 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to LSI */
1352 #define LL_TIM_TIM16_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSI/256 */
1353 /**
1354 * @}
1355 */
1356
1357 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1358 * @{
1359 */
1360 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17 TI1 is connected to GPIO */
1361 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to MCO */
1362 #define LL_TIM_TIM17_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSE DIV32 */
1363 #define LL_TIM_TIM17_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM17 TI1 is connected to RTC */
1364 #define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to LSE */
1365 #define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to LSI */
1366 #define LL_TIM_TIM17_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSI/256 */
1367 /**
1368 * @}
1369 */
1370
1371 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1372 * @{
1373 */
1374 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
1375 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1376 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1377 /**
1378 * @}
1379 */
1380
1381 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1382 * @{
1383 */
1384 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1385 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1386 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1392 * @{
1393 */
1394 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1395 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1396 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1402 * @{
1403 */
1404 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1405 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1406 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1407 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1408 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1409 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1410 /**
1411 * @}
1412 */
1413
1414 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1415 * @{
1416 */
1417 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1418 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1419 /**
1420 * @}
1421 */
1422 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1423 * @{
1424 */
1425 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1426 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1427 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1428 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1429 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1430 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1431 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1432 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1433 /**
1434 * @}
1435 */
1436
1437 /** Legacy definitions for compatibility purpose
1438 @cond 0
1439 */
1440 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1441 /**
1442 @endcond
1443 */
1444
1445 /**
1446 * @}
1447 */
1448
1449 /* Exported macro ------------------------------------------------------------*/
1450 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1451 * @{
1452 */
1453
1454 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1455 * @{
1456 */
1457 /**
1458 * @brief Write a value in TIM register.
1459 * @param __INSTANCE__ TIM Instance
1460 * @param __REG__ Register to be written
1461 * @param __VALUE__ Value to be written in the register
1462 * @retval None
1463 */
1464 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1465
1466 /**
1467 * @brief Read a value in TIM register.
1468 * @param __INSTANCE__ TIM Instance
1469 * @param __REG__ Register to be read
1470 * @retval Register value
1471 */
1472 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1473 /**
1474 * @}
1475 */
1476
1477 /**
1478 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1479 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1480 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1481 * to TIMx_CNT register bit 31)
1482 * @param __CNT__ Counter value
1483 * @retval UIF status bit
1484 */
1485 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1486 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1487
1488 /**
1489 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1490 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1491 * @param __TIMCLK__ timer input clock frequency (in Hz)
1492 * @param __CKD__ This parameter can be one of the following values:
1493 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1494 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1495 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1496 * @param __DT__ deadtime duration (in ns)
1497 * @retval DTG[0:7]
1498 */
1499 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1500 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1501 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1502 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1503 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1504 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1505 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1506 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1507 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1508 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1509 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1510 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1511 0U)
1512
1513 /**
1514 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1515 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1516 * @param __TIMCLK__ timer input clock frequency (in Hz)
1517 * @param __CNTCLK__ counter clock frequency (in Hz)
1518 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1519 */
1520 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1521 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1522
1523 /**
1524 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1525 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1526 * @param __TIMCLK__ timer input clock frequency (in Hz)
1527 * @param __PSC__ prescaler
1528 * @param __FREQ__ output signal frequency (in Hz)
1529 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1530 */
1531 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1532 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1533
1534 /**
1535 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1536 * output signal frequency.
1537 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1538 * @param __TIMCLK__ timer input clock frequency (in Hz)
1539 * @param __PSC__ prescaler
1540 * @param __FREQ__ output signal frequency (in Hz)
1541 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1542 */
1543 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1544 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1545 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1546
1547 /**
1548 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1549 * active/inactive delay.
1550 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1551 * @param __TIMCLK__ timer input clock frequency (in Hz)
1552 * @param __PSC__ prescaler
1553 * @param __DELAY__ timer output compare active/inactive delay (in us)
1554 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1555 */
1556 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1557 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1558 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1559
1560 /**
1561 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1562 * output compare active/inactive delay.
1563 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1564 * @param __TIMCLK__ timer input clock frequency (in Hz)
1565 * @param __PSC__ prescaler
1566 * @param __DELAY__ timer output compare active/inactive delay (in us)
1567 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1568 */
1569 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1570 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1571 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1572
1573 /**
1574 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1575 * (when the timer operates in one pulse mode).
1576 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1577 * @param __TIMCLK__ timer input clock frequency (in Hz)
1578 * @param __PSC__ prescaler
1579 * @param __DELAY__ timer output compare active/inactive delay (in us)
1580 * @param __PULSE__ pulse duration (in us)
1581 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1582 */
1583 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1584 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1585 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1586
1587 /**
1588 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1589 * pulse duration (when the timer operates in one pulse mode).
1590 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1591 * @param __TIMCLK__ timer input clock frequency (in Hz)
1592 * @param __PSC__ prescaler
1593 * @param __DELAY__ timer output compare active/inactive delay (in us)
1594 * @param __PULSE__ pulse duration (in us)
1595 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1596 */
1597 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1598 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1599 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1600
1601 /**
1602 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1603 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1604 * @param __ICPSC__ This parameter can be one of the following values:
1605 * @arg @ref LL_TIM_ICPSC_DIV1
1606 * @arg @ref LL_TIM_ICPSC_DIV2
1607 * @arg @ref LL_TIM_ICPSC_DIV4
1608 * @arg @ref LL_TIM_ICPSC_DIV8
1609 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1610 */
1611 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1612 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1613
1614
1615 /**
1616 * @}
1617 */
1618
1619 /* Exported functions --------------------------------------------------------*/
1620 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1621 * @{
1622 */
1623
1624 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1625 * @{
1626 */
1627 /**
1628 * @brief Enable timer counter.
1629 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1630 * @param TIMx Timer instance
1631 * @retval None
1632 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1633 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1634 {
1635 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1636 }
1637
1638 /**
1639 * @brief Disable timer counter.
1640 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1641 * @param TIMx Timer instance
1642 * @retval None
1643 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1644 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1645 {
1646 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1647 }
1648
1649 /**
1650 * @brief Indicates whether the timer counter is enabled.
1651 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1652 * @param TIMx Timer instance
1653 * @retval State of bit (1 or 0).
1654 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1655 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1656 {
1657 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1658 }
1659
1660 /**
1661 * @brief Enable update event generation.
1662 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1663 * @param TIMx Timer instance
1664 * @retval None
1665 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1666 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1667 {
1668 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1669 }
1670
1671 /**
1672 * @brief Disable update event generation.
1673 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1674 * @param TIMx Timer instance
1675 * @retval None
1676 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1677 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1678 {
1679 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1680 }
1681
1682 /**
1683 * @brief Indicates whether update event generation is enabled.
1684 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1685 * @param TIMx Timer instance
1686 * @retval Inverted state of bit (0 or 1).
1687 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1688 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1689 {
1690 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Set update event source
1695 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1696 * generate an update interrupt or DMA request if enabled:
1697 * - Counter overflow/underflow
1698 * - Setting the UG bit
1699 * - Update generation through the slave mode controller
1700 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1701 * overflow/underflow generates an update interrupt or DMA request if enabled.
1702 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1703 * @param TIMx Timer instance
1704 * @param UpdateSource This parameter can be one of the following values:
1705 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1706 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1707 * @retval None
1708 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1709 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1710 {
1711 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1712 }
1713
1714 /**
1715 * @brief Get actual event update source
1716 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1717 * @param TIMx Timer instance
1718 * @retval Returned value can be one of the following values:
1719 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1720 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1721 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1722 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1723 {
1724 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1725 }
1726
1727 /**
1728 * @brief Set one pulse mode (one shot v.s. repetitive).
1729 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1730 * @param TIMx Timer instance
1731 * @param OnePulseMode This parameter can be one of the following values:
1732 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1733 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1734 * @retval None
1735 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1736 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1737 {
1738 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1739 }
1740
1741 /**
1742 * @brief Get actual one pulse mode.
1743 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1744 * @param TIMx Timer instance
1745 * @retval Returned value can be one of the following values:
1746 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1747 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1748 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1749 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1750 {
1751 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1752 }
1753
1754 /**
1755 * @brief Set the timer counter counting mode.
1756 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1757 * check whether or not the counter mode selection feature is supported
1758 * by a timer instance.
1759 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1760 * requires a timer reset to avoid unexpected direction
1761 * due to DIR bit readonly in center aligned mode.
1762 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1763 * CR1 CMS LL_TIM_SetCounterMode
1764 * @param TIMx Timer instance
1765 * @param CounterMode This parameter can be one of the following values:
1766 * @arg @ref LL_TIM_COUNTERMODE_UP
1767 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1768 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1769 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1770 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1771 * @retval None
1772 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1773 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1774 {
1775 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1776 }
1777
1778 /**
1779 * @brief Get actual counter mode.
1780 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1781 * check whether or not the counter mode selection feature is supported
1782 * by a timer instance.
1783 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1784 * CR1 CMS LL_TIM_GetCounterMode
1785 * @param TIMx Timer instance
1786 * @retval Returned value can be one of the following values:
1787 * @arg @ref LL_TIM_COUNTERMODE_UP
1788 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1789 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1790 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1791 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1792 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1793 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1794 {
1795 uint32_t counter_mode;
1796
1797 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1798
1799 if (counter_mode == 0U)
1800 {
1801 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1802 }
1803
1804 return counter_mode;
1805 }
1806
1807 /**
1808 * @brief Enable auto-reload (ARR) preload.
1809 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1810 * @param TIMx Timer instance
1811 * @retval None
1812 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1813 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1814 {
1815 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1816 }
1817
1818 /**
1819 * @brief Disable auto-reload (ARR) preload.
1820 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1821 * @param TIMx Timer instance
1822 * @retval None
1823 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1824 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1825 {
1826 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1827 }
1828
1829 /**
1830 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1831 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1832 * @param TIMx Timer instance
1833 * @retval State of bit (1 or 0).
1834 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1835 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1836 {
1837 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1838 }
1839
1840 /**
1841 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1842 * (when supported) and the digital filters.
1843 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1844 * whether or not the clock division feature is supported by the timer
1845 * instance.
1846 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1847 * @param TIMx Timer instance
1848 * @param ClockDivision This parameter can be one of the following values:
1849 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1850 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1851 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1852 * @retval None
1853 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1854 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1855 {
1856 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1857 }
1858
1859 /**
1860 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1861 * generators (when supported) and the digital filters.
1862 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1863 * whether or not the clock division feature is supported by the timer
1864 * instance.
1865 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1866 * @param TIMx Timer instance
1867 * @retval Returned value can be one of the following values:
1868 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1869 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1870 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1871 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1872 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1873 {
1874 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1875 }
1876
1877 /**
1878 * @brief Set the counter value.
1879 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1880 * whether or not a timer instance supports a 32 bits counter.
1881 * @note If dithering is activated, pay attention to the Counter value interpretation
1882 * @rmtoll CNT CNT LL_TIM_SetCounter
1883 * @param TIMx Timer instance
1884 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1885 * @retval None
1886 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1887 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1888 {
1889 WRITE_REG(TIMx->CNT, Counter);
1890 }
1891
1892 /**
1893 * @brief Get the counter value.
1894 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1895 * whether or not a timer instance supports a 32 bits counter.
1896 * @note If dithering is activated, pay attention to the Counter value interpretation
1897 * @rmtoll CNT CNT LL_TIM_GetCounter
1898 * @param TIMx Timer instance
1899 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1900 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1901 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1902 {
1903 return (uint32_t)(READ_REG(TIMx->CNT));
1904 }
1905
1906 /**
1907 * @brief Get the current direction of the counter
1908 * @rmtoll CR1 DIR LL_TIM_GetDirection
1909 * @param TIMx Timer instance
1910 * @retval Returned value can be one of the following values:
1911 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1912 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1913 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1914 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1915 {
1916 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1917 }
1918
1919 /**
1920 * @brief Set the prescaler value.
1921 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1922 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1923 * prescaler ratio is taken into account at the next update event.
1924 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1925 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1926 * @param TIMx Timer instance
1927 * @param Prescaler between Min_Data=0 and Max_Data=65535
1928 * @retval None
1929 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1930 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1931 {
1932 WRITE_REG(TIMx->PSC, Prescaler);
1933 }
1934
1935 /**
1936 * @brief Get the prescaler value.
1937 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1938 * @param TIMx Timer instance
1939 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1940 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1941 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1942 {
1943 return (uint32_t)(READ_REG(TIMx->PSC));
1944 }
1945
1946 /**
1947 * @brief Set the auto-reload value.
1948 * @note The counter is blocked while the auto-reload value is null.
1949 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1950 * whether or not a timer instance supports a 32 bits counter.
1951 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1952 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
1953 * parameter.
1954 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1955 * @param TIMx Timer instance
1956 * @param AutoReload between Min_Data=0 and Max_Data=65535
1957 * @retval None
1958 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1959 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1960 {
1961 WRITE_REG(TIMx->ARR, AutoReload);
1962 }
1963
1964 /**
1965 * @brief Get the auto-reload value.
1966 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1967 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1968 * whether or not a timer instance supports a 32 bits counter.
1969 * @note If dithering is activated, pay attention to the returned value interpretation
1970 * @param TIMx Timer instance
1971 * @retval Auto-reload value
1972 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1973 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1974 {
1975 return (uint32_t)(READ_REG(TIMx->ARR));
1976 }
1977
1978 /**
1979 * @brief Set the repetition counter value.
1980 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1981 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1982 * whether or not a timer instance supports a repetition counter.
1983 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1984 * @param TIMx Timer instance
1985 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1986 * @retval None
1987 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1988 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1989 {
1990 WRITE_REG(TIMx->RCR, RepetitionCounter);
1991 }
1992
1993 /**
1994 * @brief Get the repetition counter value.
1995 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1996 * whether or not a timer instance supports a repetition counter.
1997 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1998 * @param TIMx Timer instance
1999 * @retval Repetition counter value
2000 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2001 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2002 {
2003 return (uint32_t)(READ_REG(TIMx->RCR));
2004 }
2005
2006 /**
2007 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2008 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2009 * in an atomic way.
2010 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2011 * @param TIMx Timer instance
2012 * @retval None
2013 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2014 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2015 {
2016 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2017 }
2018
2019 /**
2020 * @brief Disable update interrupt flag (UIF) remapping.
2021 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2022 * @param TIMx Timer instance
2023 * @retval None
2024 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2025 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2026 {
2027 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2028 }
2029
2030 /**
2031 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2032 * @param Counter Counter value
2033 * @retval State of bit (1 or 0).
2034 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2035 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2036 {
2037 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2038 }
2039
2040 /**
2041 * @brief Enable dithering.
2042 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2043 * a timer instance provides dithering.
2044 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2045 * @param TIMx Timer instance
2046 * @retval None
2047 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2048 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2049 {
2050 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2051 }
2052
2053 /**
2054 * @brief Disable dithering.
2055 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2056 * a timer instance provides dithering.
2057 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2058 * @param TIMx Timer instance
2059 * @retval None
2060 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2061 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2062 {
2063 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2064 }
2065
2066 /**
2067 * @brief Indicates whether dithering is activated.
2068 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2069 * a timer instance provides dithering.
2070 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2071 * @param TIMx Timer instance
2072 * @retval State of bit (1 or 0).
2073 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2074 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2075 {
2076 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2077 }
2078
2079 /**
2080 * @}
2081 */
2082
2083 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2084 * @{
2085 */
2086 /**
2087 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2088 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2089 * they are updated only when a commutation event (COM) occurs.
2090 * @note Only on channels that have a complementary output.
2091 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2092 * whether or not a timer instance is able to generate a commutation event.
2093 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2094 * @param TIMx Timer instance
2095 * @retval None
2096 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2097 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2098 {
2099 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2100 }
2101
2102 /**
2103 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2104 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2105 * whether or not a timer instance is able to generate a commutation event.
2106 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2107 * @param TIMx Timer instance
2108 * @retval None
2109 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2110 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2111 {
2112 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2113 }
2114
2115 /**
2116 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2117 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2118 * whether or not a timer instance is able to generate a commutation event.
2119 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2120 * @param TIMx Timer instance
2121 * @param CCUpdateSource This parameter can be one of the following values:
2122 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2123 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2124 * @retval None
2125 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2126 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2127 {
2128 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2129 }
2130
2131 /**
2132 * @brief Set the trigger of the capture/compare DMA request.
2133 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2134 * @param TIMx Timer instance
2135 * @param DMAReqTrigger This parameter can be one of the following values:
2136 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2137 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2138 * @retval None
2139 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2140 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2141 {
2142 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2143 }
2144
2145 /**
2146 * @brief Get actual trigger of the capture/compare DMA request.
2147 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2148 * @param TIMx Timer instance
2149 * @retval Returned value can be one of the following values:
2150 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2151 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2152 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2153 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2154 {
2155 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2156 }
2157
2158 /**
2159 * @brief Set the lock level to freeze the
2160 * configuration of several capture/compare parameters.
2161 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2162 * the lock mechanism is supported by a timer instance.
2163 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2164 * @param TIMx Timer instance
2165 * @param LockLevel This parameter can be one of the following values:
2166 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2167 * @arg @ref LL_TIM_LOCKLEVEL_1
2168 * @arg @ref LL_TIM_LOCKLEVEL_2
2169 * @arg @ref LL_TIM_LOCKLEVEL_3
2170 * @retval None
2171 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2172 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2173 {
2174 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2175 }
2176
2177 /**
2178 * @brief Enable capture/compare channels.
2179 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2180 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2181 * CCER CC2E LL_TIM_CC_EnableChannel\n
2182 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2183 * CCER CC3E LL_TIM_CC_EnableChannel\n
2184 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2185 * CCER CC4E LL_TIM_CC_EnableChannel\n
2186 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2187 * CCER CC5E LL_TIM_CC_EnableChannel\n
2188 * CCER CC6E LL_TIM_CC_EnableChannel
2189 * @param TIMx Timer instance
2190 * @param Channels This parameter can be a combination of the following values:
2191 * @arg @ref LL_TIM_CHANNEL_CH1
2192 * @arg @ref LL_TIM_CHANNEL_CH1N
2193 * @arg @ref LL_TIM_CHANNEL_CH2
2194 * @arg @ref LL_TIM_CHANNEL_CH2N
2195 * @arg @ref LL_TIM_CHANNEL_CH3
2196 * @arg @ref LL_TIM_CHANNEL_CH3N
2197 * @arg @ref LL_TIM_CHANNEL_CH4
2198 * @arg @ref LL_TIM_CHANNEL_CH4N
2199 * @arg @ref LL_TIM_CHANNEL_CH5
2200 * @arg @ref LL_TIM_CHANNEL_CH6
2201 * @retval None
2202 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2203 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2204 {
2205 SET_BIT(TIMx->CCER, Channels);
2206 }
2207
2208 /**
2209 * @brief Disable capture/compare channels.
2210 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2211 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2212 * CCER CC2E LL_TIM_CC_DisableChannel\n
2213 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2214 * CCER CC3E LL_TIM_CC_DisableChannel\n
2215 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2216 * CCER CC4E LL_TIM_CC_DisableChannel\n
2217 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2218 * CCER CC5E LL_TIM_CC_DisableChannel\n
2219 * CCER CC6E LL_TIM_CC_DisableChannel
2220 * @param TIMx Timer instance
2221 * @param Channels This parameter can be a combination of the following values:
2222 * @arg @ref LL_TIM_CHANNEL_CH1
2223 * @arg @ref LL_TIM_CHANNEL_CH1N
2224 * @arg @ref LL_TIM_CHANNEL_CH2
2225 * @arg @ref LL_TIM_CHANNEL_CH2N
2226 * @arg @ref LL_TIM_CHANNEL_CH3
2227 * @arg @ref LL_TIM_CHANNEL_CH3N
2228 * @arg @ref LL_TIM_CHANNEL_CH4
2229 * @arg @ref LL_TIM_CHANNEL_CH4N
2230 * @arg @ref LL_TIM_CHANNEL_CH5
2231 * @arg @ref LL_TIM_CHANNEL_CH6
2232 * @retval None
2233 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2234 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2235 {
2236 CLEAR_BIT(TIMx->CCER, Channels);
2237 }
2238
2239 /**
2240 * @brief Indicate whether channel(s) is(are) enabled.
2241 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2242 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2243 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2244 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2245 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2246 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2247 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2248 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2249 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2250 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2251 * @param TIMx Timer instance
2252 * @param Channels This parameter can be a combination of the following values:
2253 * @arg @ref LL_TIM_CHANNEL_CH1
2254 * @arg @ref LL_TIM_CHANNEL_CH1N
2255 * @arg @ref LL_TIM_CHANNEL_CH2
2256 * @arg @ref LL_TIM_CHANNEL_CH2N
2257 * @arg @ref LL_TIM_CHANNEL_CH3
2258 * @arg @ref LL_TIM_CHANNEL_CH3N
2259 * @arg @ref LL_TIM_CHANNEL_CH4
2260 * @arg @ref LL_TIM_CHANNEL_CH4N
2261 * @arg @ref LL_TIM_CHANNEL_CH5
2262 * @arg @ref LL_TIM_CHANNEL_CH6
2263 * @retval State of bit (1 or 0).
2264 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2265 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2266 {
2267 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2268 }
2269
2270 /**
2271 * @}
2272 */
2273
2274 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2275 * @{
2276 */
2277 /**
2278 * @brief Configure an output channel.
2279 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2280 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2281 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2282 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2283 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2284 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2285 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2286 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2287 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2288 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2289 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2290 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2291 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2292 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2293 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2294 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2295 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2296 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2297 * @param TIMx Timer instance
2298 * @param Channel This parameter can be one of the following values:
2299 * @arg @ref LL_TIM_CHANNEL_CH1
2300 * @arg @ref LL_TIM_CHANNEL_CH2
2301 * @arg @ref LL_TIM_CHANNEL_CH3
2302 * @arg @ref LL_TIM_CHANNEL_CH4
2303 * @arg @ref LL_TIM_CHANNEL_CH5
2304 * @arg @ref LL_TIM_CHANNEL_CH6
2305 * @param Configuration This parameter must be a combination of all the following values:
2306 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2307 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2308 * @retval None
2309 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2310 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2311 {
2312 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2313 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2314 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2315 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2316 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2317 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2318 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2319 }
2320
2321 /**
2322 * @brief Define the behavior of the output reference signal OCxREF from which
2323 * OCx and OCxN (when relevant) are derived.
2324 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2325 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2326 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2327 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2328 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2329 * CCMR3 OC6M LL_TIM_OC_SetMode
2330 * @param TIMx Timer instance
2331 * @param Channel This parameter can be one of the following values:
2332 * @arg @ref LL_TIM_CHANNEL_CH1
2333 * @arg @ref LL_TIM_CHANNEL_CH2
2334 * @arg @ref LL_TIM_CHANNEL_CH3
2335 * @arg @ref LL_TIM_CHANNEL_CH4
2336 * @arg @ref LL_TIM_CHANNEL_CH5
2337 * @arg @ref LL_TIM_CHANNEL_CH6
2338 * @param Mode This parameter can be one of the following values:
2339 * @arg @ref LL_TIM_OCMODE_FROZEN
2340 * @arg @ref LL_TIM_OCMODE_ACTIVE
2341 * @arg @ref LL_TIM_OCMODE_INACTIVE
2342 * @arg @ref LL_TIM_OCMODE_TOGGLE
2343 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2344 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2345 * @arg @ref LL_TIM_OCMODE_PWM1
2346 * @arg @ref LL_TIM_OCMODE_PWM2
2347 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2348 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2349 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2350 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2351 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2352 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2353 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2354 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2355 * @retval None
2356 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2357 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2358 {
2359 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2361 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2362 }
2363
2364 /**
2365 * @brief Get the output compare mode of an output channel.
2366 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2367 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2368 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2369 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2370 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2371 * CCMR3 OC6M LL_TIM_OC_GetMode
2372 * @param TIMx Timer instance
2373 * @param Channel This parameter can be one of the following values:
2374 * @arg @ref LL_TIM_CHANNEL_CH1
2375 * @arg @ref LL_TIM_CHANNEL_CH2
2376 * @arg @ref LL_TIM_CHANNEL_CH3
2377 * @arg @ref LL_TIM_CHANNEL_CH4
2378 * @arg @ref LL_TIM_CHANNEL_CH5
2379 * @arg @ref LL_TIM_CHANNEL_CH6
2380 * @retval Returned value can be one of the following values:
2381 * @arg @ref LL_TIM_OCMODE_FROZEN
2382 * @arg @ref LL_TIM_OCMODE_ACTIVE
2383 * @arg @ref LL_TIM_OCMODE_INACTIVE
2384 * @arg @ref LL_TIM_OCMODE_TOGGLE
2385 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2386 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2387 * @arg @ref LL_TIM_OCMODE_PWM1
2388 * @arg @ref LL_TIM_OCMODE_PWM2
2389 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2390 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2391 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2392 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2393 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2394 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2395 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2396 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2397 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2398 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2399 {
2400 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2401 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2402 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2403 }
2404
2405 /**
2406 * @brief Set the polarity of an output channel.
2407 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2408 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2409 * CCER CC2P LL_TIM_OC_SetPolarity\n
2410 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2411 * CCER CC3P LL_TIM_OC_SetPolarity\n
2412 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2413 * CCER CC4P LL_TIM_OC_SetPolarity\n
2414 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2415 * CCER CC5P LL_TIM_OC_SetPolarity\n
2416 * CCER CC6P LL_TIM_OC_SetPolarity
2417 * @param TIMx Timer instance
2418 * @param Channel This parameter can be one of the following values:
2419 * @arg @ref LL_TIM_CHANNEL_CH1
2420 * @arg @ref LL_TIM_CHANNEL_CH1N
2421 * @arg @ref LL_TIM_CHANNEL_CH2
2422 * @arg @ref LL_TIM_CHANNEL_CH2N
2423 * @arg @ref LL_TIM_CHANNEL_CH3
2424 * @arg @ref LL_TIM_CHANNEL_CH3N
2425 * @arg @ref LL_TIM_CHANNEL_CH4
2426 * @arg @ref LL_TIM_CHANNEL_CH4N
2427 * @arg @ref LL_TIM_CHANNEL_CH5
2428 * @arg @ref LL_TIM_CHANNEL_CH6
2429 * @param Polarity This parameter can be one of the following values:
2430 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2431 * @arg @ref LL_TIM_OCPOLARITY_LOW
2432 * @retval None
2433 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2434 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2435 {
2436 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2437 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2438 }
2439
2440 /**
2441 * @brief Get the polarity of an output channel.
2442 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2443 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2444 * CCER CC2P LL_TIM_OC_GetPolarity\n
2445 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2446 * CCER CC3P LL_TIM_OC_GetPolarity\n
2447 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2448 * CCER CC4P LL_TIM_OC_GetPolarity\n
2449 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2450 * CCER CC5P LL_TIM_OC_GetPolarity\n
2451 * CCER CC6P LL_TIM_OC_GetPolarity
2452 * @param TIMx Timer instance
2453 * @param Channel This parameter can be one of the following values:
2454 * @arg @ref LL_TIM_CHANNEL_CH1
2455 * @arg @ref LL_TIM_CHANNEL_CH1N
2456 * @arg @ref LL_TIM_CHANNEL_CH2
2457 * @arg @ref LL_TIM_CHANNEL_CH2N
2458 * @arg @ref LL_TIM_CHANNEL_CH3
2459 * @arg @ref LL_TIM_CHANNEL_CH3N
2460 * @arg @ref LL_TIM_CHANNEL_CH4
2461 * @arg @ref LL_TIM_CHANNEL_CH4N
2462 * @arg @ref LL_TIM_CHANNEL_CH5
2463 * @arg @ref LL_TIM_CHANNEL_CH6
2464 * @retval Returned value can be one of the following values:
2465 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2466 * @arg @ref LL_TIM_OCPOLARITY_LOW
2467 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2468 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2469 {
2470 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2471 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2472 }
2473
2474 /**
2475 * @brief Set the IDLE state of an output channel
2476 * @note This function is significant only for the timer instances
2477 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2478 * can be used to check whether or not a timer instance provides
2479 * a break input.
2480 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2481 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2482 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2483 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2484 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2485 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2486 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2487 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2488 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2489 * CR2 OIS6 LL_TIM_OC_SetIdleState
2490 * @param TIMx Timer instance
2491 * @param Channel This parameter can be one of the following values:
2492 * @arg @ref LL_TIM_CHANNEL_CH1
2493 * @arg @ref LL_TIM_CHANNEL_CH1N
2494 * @arg @ref LL_TIM_CHANNEL_CH2
2495 * @arg @ref LL_TIM_CHANNEL_CH2N
2496 * @arg @ref LL_TIM_CHANNEL_CH3
2497 * @arg @ref LL_TIM_CHANNEL_CH3N
2498 * @arg @ref LL_TIM_CHANNEL_CH4
2499 * @arg @ref LL_TIM_CHANNEL_CH4N
2500 * @arg @ref LL_TIM_CHANNEL_CH5
2501 * @arg @ref LL_TIM_CHANNEL_CH6
2502 * @param IdleState This parameter can be one of the following values:
2503 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2504 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2505 * @retval None
2506 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2507 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2508 {
2509 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2510 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2511 }
2512
2513 /**
2514 * @brief Get the IDLE state of an output channel
2515 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2516 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2517 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2518 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2519 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2520 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2521 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2522 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2523 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2524 * CR2 OIS6 LL_TIM_OC_GetIdleState
2525 * @param TIMx Timer instance
2526 * @param Channel This parameter can be one of the following values:
2527 * @arg @ref LL_TIM_CHANNEL_CH1
2528 * @arg @ref LL_TIM_CHANNEL_CH1N
2529 * @arg @ref LL_TIM_CHANNEL_CH2
2530 * @arg @ref LL_TIM_CHANNEL_CH2N
2531 * @arg @ref LL_TIM_CHANNEL_CH3
2532 * @arg @ref LL_TIM_CHANNEL_CH3N
2533 * @arg @ref LL_TIM_CHANNEL_CH4
2534 * @arg @ref LL_TIM_CHANNEL_CH4N
2535 * @arg @ref LL_TIM_CHANNEL_CH5
2536 * @arg @ref LL_TIM_CHANNEL_CH6
2537 * @retval Returned value can be one of the following values:
2538 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2539 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2540 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2541 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2542 {
2543 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2544 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2545 }
2546
2547 /**
2548 * @brief Enable fast mode for the output channel.
2549 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2550 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2551 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2552 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2553 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2554 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2555 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2556 * @param TIMx Timer instance
2557 * @param Channel This parameter can be one of the following values:
2558 * @arg @ref LL_TIM_CHANNEL_CH1
2559 * @arg @ref LL_TIM_CHANNEL_CH2
2560 * @arg @ref LL_TIM_CHANNEL_CH3
2561 * @arg @ref LL_TIM_CHANNEL_CH4
2562 * @arg @ref LL_TIM_CHANNEL_CH5
2563 * @arg @ref LL_TIM_CHANNEL_CH6
2564 * @retval None
2565 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2566 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2567 {
2568 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2569 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2570 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2571
2572 }
2573
2574 /**
2575 * @brief Disable fast mode for the output channel.
2576 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2577 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2578 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2579 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2580 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2581 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2582 * @param TIMx Timer instance
2583 * @param Channel This parameter can be one of the following values:
2584 * @arg @ref LL_TIM_CHANNEL_CH1
2585 * @arg @ref LL_TIM_CHANNEL_CH2
2586 * @arg @ref LL_TIM_CHANNEL_CH3
2587 * @arg @ref LL_TIM_CHANNEL_CH4
2588 * @arg @ref LL_TIM_CHANNEL_CH5
2589 * @arg @ref LL_TIM_CHANNEL_CH6
2590 * @retval None
2591 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2592 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2593 {
2594 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2595 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2596 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2597
2598 }
2599
2600 /**
2601 * @brief Indicates whether fast mode is enabled for the output channel.
2602 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2603 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2604 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2605 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2606 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2607 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2608 * @param TIMx Timer instance
2609 * @param Channel This parameter can be one of the following values:
2610 * @arg @ref LL_TIM_CHANNEL_CH1
2611 * @arg @ref LL_TIM_CHANNEL_CH2
2612 * @arg @ref LL_TIM_CHANNEL_CH3
2613 * @arg @ref LL_TIM_CHANNEL_CH4
2614 * @arg @ref LL_TIM_CHANNEL_CH5
2615 * @arg @ref LL_TIM_CHANNEL_CH6
2616 * @retval State of bit (1 or 0).
2617 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2618 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2619 {
2620 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2621 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2622 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2623 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2624 }
2625
2626 /**
2627 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2628 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2629 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2630 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2631 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2632 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2633 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2634 * @param TIMx Timer instance
2635 * @param Channel This parameter can be one of the following values:
2636 * @arg @ref LL_TIM_CHANNEL_CH1
2637 * @arg @ref LL_TIM_CHANNEL_CH2
2638 * @arg @ref LL_TIM_CHANNEL_CH3
2639 * @arg @ref LL_TIM_CHANNEL_CH4
2640 * @arg @ref LL_TIM_CHANNEL_CH5
2641 * @arg @ref LL_TIM_CHANNEL_CH6
2642 * @retval None
2643 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2644 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2645 {
2646 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2647 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2648 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2649 }
2650
2651 /**
2652 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2653 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2654 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2655 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2656 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2657 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2658 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2659 * @param TIMx Timer instance
2660 * @param Channel This parameter can be one of the following values:
2661 * @arg @ref LL_TIM_CHANNEL_CH1
2662 * @arg @ref LL_TIM_CHANNEL_CH2
2663 * @arg @ref LL_TIM_CHANNEL_CH3
2664 * @arg @ref LL_TIM_CHANNEL_CH4
2665 * @arg @ref LL_TIM_CHANNEL_CH5
2666 * @arg @ref LL_TIM_CHANNEL_CH6
2667 * @retval None
2668 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2669 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2670 {
2671 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2672 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2673 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2674 }
2675
2676 /**
2677 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2678 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2679 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2680 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2681 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2682 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2683 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2684 * @param TIMx Timer instance
2685 * @param Channel This parameter can be one of the following values:
2686 * @arg @ref LL_TIM_CHANNEL_CH1
2687 * @arg @ref LL_TIM_CHANNEL_CH2
2688 * @arg @ref LL_TIM_CHANNEL_CH3
2689 * @arg @ref LL_TIM_CHANNEL_CH4
2690 * @arg @ref LL_TIM_CHANNEL_CH5
2691 * @arg @ref LL_TIM_CHANNEL_CH6
2692 * @retval State of bit (1 or 0).
2693 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2694 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2695 {
2696 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2697 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2698 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2699 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2700 }
2701
2702 /**
2703 * @brief Enable clearing the output channel on an external event.
2704 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2705 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2706 * or not a timer instance can clear the OCxREF signal on an external event.
2707 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2708 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2709 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2710 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2711 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2712 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2713 * @param TIMx Timer instance
2714 * @param Channel This parameter can be one of the following values:
2715 * @arg @ref LL_TIM_CHANNEL_CH1
2716 * @arg @ref LL_TIM_CHANNEL_CH2
2717 * @arg @ref LL_TIM_CHANNEL_CH3
2718 * @arg @ref LL_TIM_CHANNEL_CH4
2719 * @arg @ref LL_TIM_CHANNEL_CH5
2720 * @arg @ref LL_TIM_CHANNEL_CH6
2721 * @retval None
2722 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2723 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2724 {
2725 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2726 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2727 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2728 }
2729
2730 /**
2731 * @brief Disable clearing the output channel on an external event.
2732 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2733 * or not a timer instance can clear the OCxREF signal on an external event.
2734 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2735 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2736 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2737 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2738 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2739 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2740 * @param TIMx Timer instance
2741 * @param Channel This parameter can be one of the following values:
2742 * @arg @ref LL_TIM_CHANNEL_CH1
2743 * @arg @ref LL_TIM_CHANNEL_CH2
2744 * @arg @ref LL_TIM_CHANNEL_CH3
2745 * @arg @ref LL_TIM_CHANNEL_CH4
2746 * @arg @ref LL_TIM_CHANNEL_CH5
2747 * @arg @ref LL_TIM_CHANNEL_CH6
2748 * @retval None
2749 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2750 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2751 {
2752 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2753 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2754 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2755 }
2756
2757 /**
2758 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2759 * @note This function enables clearing the output channel on an external event.
2760 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2761 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2762 * or not a timer instance can clear the OCxREF signal on an external event.
2763 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2764 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2765 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2766 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2767 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2768 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2769 * @param TIMx Timer instance
2770 * @param Channel This parameter can be one of the following values:
2771 * @arg @ref LL_TIM_CHANNEL_CH1
2772 * @arg @ref LL_TIM_CHANNEL_CH2
2773 * @arg @ref LL_TIM_CHANNEL_CH3
2774 * @arg @ref LL_TIM_CHANNEL_CH4
2775 * @arg @ref LL_TIM_CHANNEL_CH5
2776 * @arg @ref LL_TIM_CHANNEL_CH6
2777 * @retval State of bit (1 or 0).
2778 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2779 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2780 {
2781 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2782 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2783 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2784 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2785 }
2786
2787 /**
2788 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2789 * the Ocx and OCxN signals).
2790 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2791 * dead-time insertion feature is supported by a timer instance.
2792 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2793 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2794 * @param TIMx Timer instance
2795 * @param DeadTime between Min_Data=0 and Max_Data=255
2796 * @retval None
2797 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2798 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2799 {
2800 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2801 }
2802
2803 /**
2804 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2805 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2806 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2807 * whether or not a timer instance supports a 32 bits counter.
2808 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2809 * output channel 1 is supported by a timer instance.
2810 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2811 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2812 * @param TIMx Timer instance
2813 * @param CompareValue between Min_Data=0 and Max_Data=65535
2814 * @retval None
2815 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2816 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2817 {
2818 WRITE_REG(TIMx->CCR1, CompareValue);
2819 }
2820
2821 /**
2822 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2823 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2824 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2825 * whether or not a timer instance supports a 32 bits counter.
2826 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2827 * output channel 2 is supported by a timer instance.
2828 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2829 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2830 * @param TIMx Timer instance
2831 * @param CompareValue between Min_Data=0 and Max_Data=65535
2832 * @retval None
2833 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2834 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2835 {
2836 WRITE_REG(TIMx->CCR2, CompareValue);
2837 }
2838
2839 /**
2840 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2841 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2842 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2843 * whether or not a timer instance supports a 32 bits counter.
2844 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2845 * output channel is supported by a timer instance.
2846 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2847 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2848 * @param TIMx Timer instance
2849 * @param CompareValue between Min_Data=0 and Max_Data=65535
2850 * @retval None
2851 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2852 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2853 {
2854 WRITE_REG(TIMx->CCR3, CompareValue);
2855 }
2856
2857 /**
2858 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2859 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2860 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2861 * whether or not a timer instance supports a 32 bits counter.
2862 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2863 * output channel 4 is supported by a timer instance.
2864 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2865 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2866 * @param TIMx Timer instance
2867 * @param CompareValue between Min_Data=0 and Max_Data=65535
2868 * @retval None
2869 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2870 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2871 {
2872 WRITE_REG(TIMx->CCR4, CompareValue);
2873 }
2874
2875 /**
2876 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2877 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2878 * output channel 5 is supported by a timer instance.
2879 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2880 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2881 * @param TIMx Timer instance
2882 * @param CompareValue between Min_Data=0 and Max_Data=65535
2883 * @retval None
2884 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2885 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2886 {
2887 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2888 }
2889
2890 /**
2891 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2892 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2893 * output channel 6 is supported by a timer instance.
2894 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2895 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2896 * @param TIMx Timer instance
2897 * @param CompareValue between Min_Data=0 and Max_Data=65535
2898 * @retval None
2899 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2900 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2901 {
2902 WRITE_REG(TIMx->CCR6, CompareValue);
2903 }
2904
2905 /**
2906 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2907 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2908 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2909 * whether or not a timer instance supports a 32 bits counter.
2910 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2911 * output channel 1 is supported by a timer instance.
2912 * @note If dithering is activated, pay attention to the returned value interpretation.
2913 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2914 * @param TIMx Timer instance
2915 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2916 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2917 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2918 {
2919 return (uint32_t)(READ_REG(TIMx->CCR1));
2920 }
2921
2922 /**
2923 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2924 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2925 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2926 * whether or not a timer instance supports a 32 bits counter.
2927 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2928 * output channel 2 is supported by a timer instance.
2929 * @note If dithering is activated, pay attention to the returned value interpretation.
2930 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2931 * @param TIMx Timer instance
2932 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2933 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2934 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2935 {
2936 return (uint32_t)(READ_REG(TIMx->CCR2));
2937 }
2938
2939 /**
2940 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2941 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2942 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2943 * whether or not a timer instance supports a 32 bits counter.
2944 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2945 * output channel 3 is supported by a timer instance.
2946 * @note If dithering is activated, pay attention to the returned value interpretation.
2947 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2948 * @param TIMx Timer instance
2949 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2950 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2951 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2952 {
2953 return (uint32_t)(READ_REG(TIMx->CCR3));
2954 }
2955
2956 /**
2957 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2958 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2959 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2960 * whether or not a timer instance supports a 32 bits counter.
2961 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2962 * output channel 4 is supported by a timer instance.
2963 * @note If dithering is activated, pay attention to the returned value interpretation.
2964 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2965 * @param TIMx Timer instance
2966 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2967 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2968 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2969 {
2970 return (uint32_t)(READ_REG(TIMx->CCR4));
2971 }
2972
2973 /**
2974 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2975 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2976 * output channel 5 is supported by a timer instance.
2977 * @note If dithering is activated, pay attention to the returned value interpretation.
2978 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2979 * @param TIMx Timer instance
2980 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2981 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2982 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2983 {
2984 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2985 }
2986
2987 /**
2988 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2989 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2990 * output channel 6 is supported by a timer instance.
2991 * @note If dithering is activated, pay attention to the returned value interpretation.
2992 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2993 * @param TIMx Timer instance
2994 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2995 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2996 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2997 {
2998 return (uint32_t)(READ_REG(TIMx->CCR6));
2999 }
3000
3001 /**
3002 * @brief Select on which reference signal the OC5REF is combined to.
3003 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3004 * whether or not a timer instance supports the combined 3-phase PWM mode.
3005 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3006 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3007 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3008 * @param TIMx Timer instance
3009 * @param GroupCH5 This parameter can be a combination of the following values:
3010 * @arg @ref LL_TIM_GROUPCH5_NONE
3011 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3012 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3013 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3014 * @retval None
3015 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3016 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3017 {
3018 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3019 }
3020
3021 /**
3022 * @brief Set the pulse on compare pulse width prescaler.
3023 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3024 * whether or not the pulse on compare feature is supported by the timer
3025 * instance.
3026 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3027 * @param TIMx Timer instance
3028 * @param PulseWidthPrescaler This parameter can be one of the following values:
3029 * @arg @ref LL_TIM_PWPRSC_X1
3030 * @arg @ref LL_TIM_PWPRSC_X2
3031 * @arg @ref LL_TIM_PWPRSC_X4
3032 * @arg @ref LL_TIM_PWPRSC_X8
3033 * @arg @ref LL_TIM_PWPRSC_X16
3034 * @arg @ref LL_TIM_PWPRSC_X32
3035 * @arg @ref LL_TIM_PWPRSC_X64
3036 * @arg @ref LL_TIM_PWPRSC_X128
3037 * @retval None
3038 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3039 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3040 {
3041 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3042 }
3043
3044 /**
3045 * @brief Get the pulse on compare pulse width prescaler.
3046 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3047 * whether or not the pulse on compare feature is supported by the timer
3048 * instance.
3049 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3050 * @param TIMx Timer instance
3051 * @retval Returned value can be one of the following values:
3052 * @arg @ref LL_TIM_PWPRSC_X1
3053 * @arg @ref LL_TIM_PWPRSC_X2
3054 * @arg @ref LL_TIM_PWPRSC_X4
3055 * @arg @ref LL_TIM_PWPRSC_X8
3056 * @arg @ref LL_TIM_PWPRSC_X16
3057 * @arg @ref LL_TIM_PWPRSC_X32
3058 * @arg @ref LL_TIM_PWPRSC_X64
3059 * @arg @ref LL_TIM_PWPRSC_X128
3060 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3061 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3062 {
3063 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3064 }
3065
3066 /**
3067 * @brief Set the pulse on compare pulse width duration.
3068 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3069 * whether or not the pulse on compare feature is supported by the timer
3070 * instance.
3071 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3072 * @param TIMx Timer instance
3073 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3074 * @retval None
3075 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3076 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3077 {
3078 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3079 }
3080
3081 /**
3082 * @brief Get the pulse on compare pulse width duration.
3083 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3084 * whether or not the pulse on compare feature is supported by the timer
3085 * instance.
3086 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3087 * @param TIMx Timer instance
3088 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3089 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3090 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3091 {
3092 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3093 }
3094
3095 /**
3096 * @}
3097 */
3098
3099 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3100 * @{
3101 */
3102 /**
3103 * @brief Configure input channel.
3104 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3105 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3106 * CCMR1 IC1F LL_TIM_IC_Config\n
3107 * CCMR1 CC2S LL_TIM_IC_Config\n
3108 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3109 * CCMR1 IC2F LL_TIM_IC_Config\n
3110 * CCMR2 CC3S LL_TIM_IC_Config\n
3111 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3112 * CCMR2 IC3F LL_TIM_IC_Config\n
3113 * CCMR2 CC4S LL_TIM_IC_Config\n
3114 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3115 * CCMR2 IC4F LL_TIM_IC_Config\n
3116 * CCER CC1P LL_TIM_IC_Config\n
3117 * CCER CC1NP LL_TIM_IC_Config\n
3118 * CCER CC2P LL_TIM_IC_Config\n
3119 * CCER CC2NP LL_TIM_IC_Config\n
3120 * CCER CC3P LL_TIM_IC_Config\n
3121 * CCER CC3NP LL_TIM_IC_Config\n
3122 * CCER CC4P LL_TIM_IC_Config\n
3123 * CCER CC4NP LL_TIM_IC_Config
3124 * @param TIMx Timer instance
3125 * @param Channel This parameter can be one of the following values:
3126 * @arg @ref LL_TIM_CHANNEL_CH1
3127 * @arg @ref LL_TIM_CHANNEL_CH2
3128 * @arg @ref LL_TIM_CHANNEL_CH3
3129 * @arg @ref LL_TIM_CHANNEL_CH4
3130 * @param Configuration This parameter must be a combination of all the following values:
3131 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3132 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3133 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3134 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3135 * @retval None
3136 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3137 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3138 {
3139 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3140 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3141 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3142 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3143 << SHIFT_TAB_ICxx[iChannel]);
3144 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3145 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3146 }
3147
3148 /**
3149 * @brief Set the active input.
3150 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3151 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3152 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3153 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3154 * @param TIMx Timer instance
3155 * @param Channel This parameter can be one of the following values:
3156 * @arg @ref LL_TIM_CHANNEL_CH1
3157 * @arg @ref LL_TIM_CHANNEL_CH2
3158 * @arg @ref LL_TIM_CHANNEL_CH3
3159 * @arg @ref LL_TIM_CHANNEL_CH4
3160 * @param ICActiveInput This parameter can be one of the following values:
3161 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3162 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3163 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3164 * @retval None
3165 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3166 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3167 {
3168 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3169 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3170 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3171 }
3172
3173 /**
3174 * @brief Get the current active input.
3175 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3176 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3177 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3178 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3179 * @param TIMx Timer instance
3180 * @param Channel This parameter can be one of the following values:
3181 * @arg @ref LL_TIM_CHANNEL_CH1
3182 * @arg @ref LL_TIM_CHANNEL_CH2
3183 * @arg @ref LL_TIM_CHANNEL_CH3
3184 * @arg @ref LL_TIM_CHANNEL_CH4
3185 * @retval Returned value can be one of the following values:
3186 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3187 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3188 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3189 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3190 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3191 {
3192 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3193 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3194 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3195 }
3196
3197 /**
3198 * @brief Set the prescaler of input channel.
3199 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3200 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3201 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3202 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3203 * @param TIMx Timer instance
3204 * @param Channel This parameter can be one of the following values:
3205 * @arg @ref LL_TIM_CHANNEL_CH1
3206 * @arg @ref LL_TIM_CHANNEL_CH2
3207 * @arg @ref LL_TIM_CHANNEL_CH3
3208 * @arg @ref LL_TIM_CHANNEL_CH4
3209 * @param ICPrescaler This parameter can be one of the following values:
3210 * @arg @ref LL_TIM_ICPSC_DIV1
3211 * @arg @ref LL_TIM_ICPSC_DIV2
3212 * @arg @ref LL_TIM_ICPSC_DIV4
3213 * @arg @ref LL_TIM_ICPSC_DIV8
3214 * @retval None
3215 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3216 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3217 {
3218 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3219 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3220 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3221 }
3222
3223 /**
3224 * @brief Get the current prescaler value acting on an input channel.
3225 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3226 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3227 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3228 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3229 * @param TIMx Timer instance
3230 * @param Channel This parameter can be one of the following values:
3231 * @arg @ref LL_TIM_CHANNEL_CH1
3232 * @arg @ref LL_TIM_CHANNEL_CH2
3233 * @arg @ref LL_TIM_CHANNEL_CH3
3234 * @arg @ref LL_TIM_CHANNEL_CH4
3235 * @retval Returned value can be one of the following values:
3236 * @arg @ref LL_TIM_ICPSC_DIV1
3237 * @arg @ref LL_TIM_ICPSC_DIV2
3238 * @arg @ref LL_TIM_ICPSC_DIV4
3239 * @arg @ref LL_TIM_ICPSC_DIV8
3240 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3241 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3242 {
3243 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3244 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3245 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3246 }
3247
3248 /**
3249 * @brief Set the input filter duration.
3250 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3251 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3252 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3253 * CCMR2 IC4F LL_TIM_IC_SetFilter
3254 * @param TIMx Timer instance
3255 * @param Channel This parameter can be one of the following values:
3256 * @arg @ref LL_TIM_CHANNEL_CH1
3257 * @arg @ref LL_TIM_CHANNEL_CH2
3258 * @arg @ref LL_TIM_CHANNEL_CH3
3259 * @arg @ref LL_TIM_CHANNEL_CH4
3260 * @param ICFilter This parameter can be one of the following values:
3261 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3262 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3263 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3264 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3265 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3266 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3267 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3268 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3269 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3270 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3271 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3272 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3273 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3274 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3275 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3276 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3277 * @retval None
3278 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3279 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3280 {
3281 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3283 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3284 }
3285
3286 /**
3287 * @brief Get the input filter duration.
3288 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3289 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3290 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3291 * CCMR2 IC4F LL_TIM_IC_GetFilter
3292 * @param TIMx Timer instance
3293 * @param Channel This parameter can be one of the following values:
3294 * @arg @ref LL_TIM_CHANNEL_CH1
3295 * @arg @ref LL_TIM_CHANNEL_CH2
3296 * @arg @ref LL_TIM_CHANNEL_CH3
3297 * @arg @ref LL_TIM_CHANNEL_CH4
3298 * @retval Returned value can be one of the following values:
3299 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3300 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3301 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3302 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3303 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3304 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3305 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3306 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3307 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3308 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3309 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3310 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3311 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3312 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3313 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3314 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3315 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3316 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3317 {
3318 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3319 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3320 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3321 }
3322
3323 /**
3324 * @brief Set the input channel polarity.
3325 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3326 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3327 * CCER CC2P LL_TIM_IC_SetPolarity\n
3328 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3329 * CCER CC3P LL_TIM_IC_SetPolarity\n
3330 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3331 * CCER CC4P LL_TIM_IC_SetPolarity\n
3332 * CCER CC4NP LL_TIM_IC_SetPolarity
3333 * @param TIMx Timer instance
3334 * @param Channel This parameter can be one of the following values:
3335 * @arg @ref LL_TIM_CHANNEL_CH1
3336 * @arg @ref LL_TIM_CHANNEL_CH2
3337 * @arg @ref LL_TIM_CHANNEL_CH3
3338 * @arg @ref LL_TIM_CHANNEL_CH4
3339 * @param ICPolarity This parameter can be one of the following values:
3340 * @arg @ref LL_TIM_IC_POLARITY_RISING
3341 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3342 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3343 * @retval None
3344 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3345 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3346 {
3347 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3348 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3349 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3350 }
3351
3352 /**
3353 * @brief Get the current input channel polarity.
3354 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3355 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3356 * CCER CC2P LL_TIM_IC_GetPolarity\n
3357 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3358 * CCER CC3P LL_TIM_IC_GetPolarity\n
3359 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3360 * CCER CC4P LL_TIM_IC_GetPolarity\n
3361 * CCER CC4NP LL_TIM_IC_GetPolarity
3362 * @param TIMx Timer instance
3363 * @param Channel This parameter can be one of the following values:
3364 * @arg @ref LL_TIM_CHANNEL_CH1
3365 * @arg @ref LL_TIM_CHANNEL_CH2
3366 * @arg @ref LL_TIM_CHANNEL_CH3
3367 * @arg @ref LL_TIM_CHANNEL_CH4
3368 * @retval Returned value can be one of the following values:
3369 * @arg @ref LL_TIM_IC_POLARITY_RISING
3370 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3371 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3372 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3373 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3374 {
3375 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3376 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3377 SHIFT_TAB_CCxP[iChannel]);
3378 }
3379
3380 /**
3381 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3382 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3383 * a timer instance provides an XOR input.
3384 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3385 * @param TIMx Timer instance
3386 * @retval None
3387 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3388 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3389 {
3390 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3391 }
3392
3393 /**
3394 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3395 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3396 * a timer instance provides an XOR input.
3397 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3398 * @param TIMx Timer instance
3399 * @retval None
3400 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3401 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3402 {
3403 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3404 }
3405
3406 /**
3407 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3408 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3409 * a timer instance provides an XOR input.
3410 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3411 * @param TIMx Timer instance
3412 * @retval State of bit (1 or 0).
3413 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3414 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3415 {
3416 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3417 }
3418
3419 /**
3420 * @brief Get captured value for input channel 1.
3421 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3422 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3423 * whether or not a timer instance supports a 32 bits counter.
3424 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3425 * input channel 1 is supported by a timer instance.
3426 * @note If dithering is activated, pay attention to the returned value interpretation.
3427 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3428 * @param TIMx Timer instance
3429 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3430 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3431 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3432 {
3433 return (uint32_t)(READ_REG(TIMx->CCR1));
3434 }
3435
3436 /**
3437 * @brief Get captured value for input channel 2.
3438 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3439 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3440 * whether or not a timer instance supports a 32 bits counter.
3441 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3442 * input channel 2 is supported by a timer instance.
3443 * @note If dithering is activated, pay attention to the returned value interpretation.
3444 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3445 * @param TIMx Timer instance
3446 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3447 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3448 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3449 {
3450 return (uint32_t)(READ_REG(TIMx->CCR2));
3451 }
3452
3453 /**
3454 * @brief Get captured value for input channel 3.
3455 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3456 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3457 * whether or not a timer instance supports a 32 bits counter.
3458 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3459 * input channel 3 is supported by a timer instance.
3460 * @note If dithering is activated, pay attention to the returned value interpretation.
3461 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3462 * @param TIMx Timer instance
3463 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3464 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3465 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3466 {
3467 return (uint32_t)(READ_REG(TIMx->CCR3));
3468 }
3469
3470 /**
3471 * @brief Get captured value for input channel 4.
3472 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3473 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3474 * whether or not a timer instance supports a 32 bits counter.
3475 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3476 * input channel 4 is supported by a timer instance.
3477 * @note If dithering is activated, pay attention to the returned value interpretation.
3478 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3479 * @param TIMx Timer instance
3480 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3481 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3482 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3483 {
3484 return (uint32_t)(READ_REG(TIMx->CCR4));
3485 }
3486
3487 /**
3488 * @}
3489 */
3490
3491 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3492 * @{
3493 */
3494 /**
3495 * @brief Enable external clock mode 2.
3496 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3497 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3498 * whether or not a timer instance supports external clock mode2.
3499 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3500 * @param TIMx Timer instance
3501 * @retval None
3502 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3503 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3504 {
3505 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3506 }
3507
3508 /**
3509 * @brief Disable external clock mode 2.
3510 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3511 * whether or not a timer instance supports external clock mode2.
3512 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3513 * @param TIMx Timer instance
3514 * @retval None
3515 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3516 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3517 {
3518 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3519 }
3520
3521 /**
3522 * @brief Indicate whether external clock mode 2 is enabled.
3523 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3524 * whether or not a timer instance supports external clock mode2.
3525 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3526 * @param TIMx Timer instance
3527 * @retval State of bit (1 or 0).
3528 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3529 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3530 {
3531 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3532 }
3533
3534 /**
3535 * @brief Set the clock source of the counter clock.
3536 * @note when selected clock source is external clock mode 1, the timer input
3537 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3538 * function. This timer input must be configured by calling
3539 * the @ref LL_TIM_IC_Config() function.
3540 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3541 * whether or not a timer instance supports external clock mode1.
3542 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3543 * whether or not a timer instance supports external clock mode2.
3544 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3545 * SMCR ECE LL_TIM_SetClockSource
3546 * @param TIMx Timer instance
3547 * @param ClockSource This parameter can be one of the following values:
3548 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3549 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3550 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3551 * @retval None
3552 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3553 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3554 {
3555 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3556 }
3557
3558 /**
3559 * @brief Set the encoder interface mode.
3560 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3561 * whether or not a timer instance supports the encoder mode.
3562 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3563 * @param TIMx Timer instance
3564 * @param EncoderMode This parameter can be one of the following values:
3565 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3566 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3567 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3568 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3569 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3570 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3571 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3572 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3573 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3574 * @retval None
3575 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3576 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3577 {
3578 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3579 }
3580
3581 /**
3582 * @}
3583 */
3584
3585 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3586 * @{
3587 */
3588 /**
3589 * @brief Set the trigger output (TRGO) used for timer synchronization .
3590 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3591 * whether or not a timer instance can operate as a master timer.
3592 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3593 * @param TIMx Timer instance
3594 * @param TimerSynchronization This parameter can be one of the following values:
3595 * @arg @ref LL_TIM_TRGO_RESET
3596 * @arg @ref LL_TIM_TRGO_ENABLE
3597 * @arg @ref LL_TIM_TRGO_UPDATE
3598 * @arg @ref LL_TIM_TRGO_CC1IF
3599 * @arg @ref LL_TIM_TRGO_OC1REF
3600 * @arg @ref LL_TIM_TRGO_OC2REF
3601 * @arg @ref LL_TIM_TRGO_OC3REF
3602 * @arg @ref LL_TIM_TRGO_OC4REF
3603 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3604 * @retval None
3605 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3606 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3607 {
3608 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3609 }
3610
3611 /**
3612 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3613 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3614 * whether or not a timer instance can be used for ADC synchronization.
3615 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3616 * @param TIMx Timer Instance
3617 * @param ADCSynchronization This parameter can be one of the following values:
3618 * @arg @ref LL_TIM_TRGO2_RESET
3619 * @arg @ref LL_TIM_TRGO2_ENABLE
3620 * @arg @ref LL_TIM_TRGO2_UPDATE
3621 * @arg @ref LL_TIM_TRGO2_CC1F
3622 * @arg @ref LL_TIM_TRGO2_OC1
3623 * @arg @ref LL_TIM_TRGO2_OC2
3624 * @arg @ref LL_TIM_TRGO2_OC3
3625 * @arg @ref LL_TIM_TRGO2_OC4
3626 * @arg @ref LL_TIM_TRGO2_OC5
3627 * @arg @ref LL_TIM_TRGO2_OC6
3628 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3629 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3630 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3631 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3632 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3633 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3634 * @retval None
3635 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3636 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3637 {
3638 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3639 }
3640
3641 /**
3642 * @brief Set the synchronization mode of a slave timer.
3643 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3644 * a timer instance can operate as a slave timer.
3645 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3646 * @param TIMx Timer instance
3647 * @param SlaveMode This parameter can be one of the following values:
3648 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3649 * @arg @ref LL_TIM_SLAVEMODE_RESET
3650 * @arg @ref LL_TIM_SLAVEMODE_GATED
3651 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3652 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3653 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3654 * @retval None
3655 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3656 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3657 {
3658 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3659 }
3660
3661 /**
3662 * @brief Set the selects the trigger input to be used to synchronize the counter.
3663 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3664 * a timer instance can operate as a slave timer.
3665 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3666 * @param TIMx Timer instance
3667 * @param TriggerInput This parameter can be one of the following values:
3668 * @arg @ref LL_TIM_TS_ITR0
3669 * @arg @ref LL_TIM_TS_ITR1
3670 * @arg @ref LL_TIM_TS_ITR2
3671 * @arg @ref LL_TIM_TS_ITR7
3672 * @arg @ref LL_TIM_TS_ITR8
3673 * @arg @ref LL_TIM_TS_TI1F_ED
3674 * @arg @ref LL_TIM_TS_TI1FP1
3675 * @arg @ref LL_TIM_TS_TI2FP2
3676 * @arg @ref LL_TIM_TS_ETRF
3677 * @retval None
3678 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3679 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3680 {
3681 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3682 }
3683
3684 /**
3685 * @brief Enable the Master/Slave mode.
3686 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3687 * a timer instance can operate as a slave timer.
3688 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3689 * @param TIMx Timer instance
3690 * @retval None
3691 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3692 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3693 {
3694 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3695 }
3696
3697 /**
3698 * @brief Disable the Master/Slave mode.
3699 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3700 * a timer instance can operate as a slave timer.
3701 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3702 * @param TIMx Timer instance
3703 * @retval None
3704 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3705 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3706 {
3707 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3708 }
3709
3710 /**
3711 * @brief Indicates whether the Master/Slave mode is enabled.
3712 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3713 * a timer instance can operate as a slave timer.
3714 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3715 * @param TIMx Timer instance
3716 * @retval State of bit (1 or 0).
3717 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3718 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3719 {
3720 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3721 }
3722
3723 /**
3724 * @brief Configure the external trigger (ETR) input.
3725 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3726 * a timer instance provides an external trigger input.
3727 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3728 * SMCR ETPS LL_TIM_ConfigETR\n
3729 * SMCR ETF LL_TIM_ConfigETR
3730 * @param TIMx Timer instance
3731 * @param ETRPolarity This parameter can be one of the following values:
3732 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3733 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3734 * @param ETRPrescaler This parameter can be one of the following values:
3735 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3736 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3737 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3738 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3739 * @param ETRFilter This parameter can be one of the following values:
3740 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3741 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3742 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3743 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3744 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3745 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3746 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3747 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3748 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3749 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3750 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3751 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3752 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3753 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3754 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3755 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3756 * @retval None
3757 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3758 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3759 uint32_t ETRFilter)
3760 {
3761 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3762 }
3763
3764 /**
3765 * @brief Select the external trigger (ETR) input source.
3766 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3767 * not a timer instance supports ETR source selection.
3768 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3769 * @param TIMx Timer instance
3770 * @param ETRSource This parameter can be one of the following values:
3771 *
3772 * For TIM1, the parameter is one of the following values:
3773 *
3774 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3775 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*)
3776 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*)
3777 * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI
3778 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
3779 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
3780 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
3781 *
3782 * For TIM2, the parameter is one of the following values:
3783 *
3784 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3785 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*)
3786 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*)
3787 * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI
3788 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
3789 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
3790 *
3791 * For TIM3, the parameter is one of the following values:
3792 *
3793 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3794 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*)
3795 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*)
3796 * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI
3797 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
3798 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
3799 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1
3800 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2
3801 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3
3802 *
3803 * (*) Value not defined in all devices. \n
3804 * @retval None
3805 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3806 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3807 {
3808 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3809 }
3810
3811 /**
3812 * @brief Enable SMS preload.
3813 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3814 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3815 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
3816 * @param TIMx Timer instance
3817 * @retval None
3818 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)3819 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
3820 {
3821 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3822 }
3823
3824 /**
3825 * @brief Disable SMS preload.
3826 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3827 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3828 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
3829 * @param TIMx Timer instance
3830 * @retval None
3831 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)3832 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
3833 {
3834 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3835 }
3836
3837 /**
3838 * @brief Indicate whether SMS preload is enabled.
3839 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3840 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3841 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
3842 * @param TIMx Timer instance
3843 * @retval State of bit (1 or 0).
3844 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)3845 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
3846 {
3847 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
3848 }
3849
3850 /**
3851 * @brief Set the preload source of SMS.
3852 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3853 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3854 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
3855 * @param TIMx Timer instance
3856 * @param PreloadSource This parameter can be one of the following values:
3857 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
3858 * @arg @ref LL_TIM_SMSPS_INDEX
3859 * @retval None
3860 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)3861 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
3862 {
3863 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
3864 }
3865
3866 /**
3867 * @brief Get the preload source of SMS.
3868 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3869 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3870 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
3871 * @param TIMx Timer instance
3872 * @retval Returned value can be one of the following values:
3873 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
3874 * @arg @ref LL_TIM_SMSPS_INDEX
3875 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)3876 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
3877 {
3878 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
3879 }
3880
3881 /**
3882 * @}
3883 */
3884
3885 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3886 * @{
3887 */
3888 /**
3889 * @brief Enable the break function.
3890 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3891 * a timer instance provides a break input.
3892 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3893 * @param TIMx Timer instance
3894 * @retval None
3895 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3896 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3897 {
3898 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3899 }
3900
3901 /**
3902 * @brief Disable the break function.
3903 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3904 * @param TIMx Timer instance
3905 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3906 * a timer instance provides a break input.
3907 * @retval None
3908 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3909 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3910 {
3911 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3912 }
3913
3914 /**
3915 * @brief Configure the break input.
3916 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3917 * a timer instance provides a break input.
3918 * @note Bidirectional mode is only supported by advanced timer instances.
3919 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3920 * a timer instance is an advanced-control timer.
3921 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3922 * in input mode and in open drain output mode. Any active Break event will
3923 * assert a low logic level on the Break input to indicate an internal break
3924 * event to external devices.
3925 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3926 * LL_TIM_BREAK_AFMODE_INPUT.
3927 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3928 * BDTR BKF LL_TIM_ConfigBRK\n
3929 * BDTR BKBID LL_TIM_ConfigBRK
3930 * @param TIMx Timer instance
3931 * @param BreakPolarity This parameter can be one of the following values:
3932 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3933 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3934 * @param BreakFilter This parameter can be one of the following values:
3935 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3936 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3937 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3938 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3939 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3940 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3941 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3942 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3943 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3944 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3945 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3946 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3947 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3948 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3949 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3950 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3951 * @param BreakAFMode This parameter can be one of the following values:
3952 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3953 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3954 * @retval None
3955 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3956 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3957 uint32_t BreakAFMode)
3958 {
3959 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3960 }
3961
3962 /**
3963 * @brief Disarm the break input (when it operates in bidirectional mode).
3964 * @note The break input can be disarmed only when it is configured in
3965 * bidirectional mode and when when MOE is reset.
3966 * @note Purpose is to be able to have the input voltage back to high-state,
3967 * whatever the time constant on the output .
3968 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3969 * @param TIMx Timer instance
3970 * @retval None
3971 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3972 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3973 {
3974 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3975 }
3976
3977 /**
3978 * @brief Re-arm the break input (when it operates in bidirectional mode).
3979 * @note The Break input is automatically armed as soon as MOE bit is set.
3980 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3981 * @param TIMx Timer instance
3982 * @retval None
3983 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3984 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3985 {
3986 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3987 }
3988
3989 /**
3990 * @brief Enable the break 2 function.
3991 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3992 * a timer instance provides a second break input.
3993 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3994 * @param TIMx Timer instance
3995 * @retval None
3996 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3997 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3998 {
3999 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4000 }
4001
4002 /**
4003 * @brief Disable the break 2 function.
4004 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4005 * a timer instance provides a second break input.
4006 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4007 * @param TIMx Timer instance
4008 * @retval None
4009 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4010 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4011 {
4012 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4013 }
4014
4015 /**
4016 * @brief Configure the break 2 input.
4017 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4018 * a timer instance provides a second break input.
4019 * @note Bidirectional mode is only supported by advanced timer instances.
4020 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4021 * a timer instance is an advanced-control timer.
4022 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4023 * in input mode and in open drain output mode. Any active Break event will
4024 * assert a low logic level on the Break 2 input to indicate an internal break
4025 * event to external devices.
4026 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4027 * LL_TIM_BREAK2_AFMODE_INPUT.
4028 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4029 * BDTR BK2F LL_TIM_ConfigBRK2\n
4030 * BDTR BK2BID LL_TIM_ConfigBRK2
4031 * @param TIMx Timer instance
4032 * @param Break2Polarity This parameter can be one of the following values:
4033 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4034 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4035 * @param Break2Filter This parameter can be one of the following values:
4036 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4037 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4038 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4039 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4040 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4041 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4042 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4043 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4044 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4045 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4046 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4047 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4048 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4049 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4050 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4051 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4052 * @param Break2AFMode This parameter can be one of the following values:
4053 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4054 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4055 * @retval None
4056 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4057 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4058 uint32_t Break2AFMode)
4059 {
4060 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4061 }
4062
4063 /**
4064 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4065 * @note The break 2 input can be disarmed only when it is configured in
4066 * bidirectional mode and when when MOE is reset.
4067 * @note Purpose is to be able to have the input voltage back to high-state,
4068 * whatever the time constant on the output.
4069 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4070 * @param TIMx Timer instance
4071 * @retval None
4072 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4073 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4074 {
4075 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4076 }
4077
4078 /**
4079 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
4080 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
4081 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
4082 * @param TIMx Timer instance
4083 * @retval None
4084 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)4085 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
4086 {
4087 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4088 }
4089
4090 /**
4091 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4092 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4093 * a timer instance provides a break input.
4094 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4095 * BDTR OSSR LL_TIM_SetOffStates
4096 * @param TIMx Timer instance
4097 * @param OffStateIdle This parameter can be one of the following values:
4098 * @arg @ref LL_TIM_OSSI_DISABLE
4099 * @arg @ref LL_TIM_OSSI_ENABLE
4100 * @param OffStateRun This parameter can be one of the following values:
4101 * @arg @ref LL_TIM_OSSR_DISABLE
4102 * @arg @ref LL_TIM_OSSR_ENABLE
4103 * @retval None
4104 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4105 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4106 {
4107 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4108 }
4109
4110 /**
4111 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4112 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4113 * a timer instance provides a break input.
4114 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4115 * @param TIMx Timer instance
4116 * @retval None
4117 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4118 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4119 {
4120 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4121 }
4122
4123 /**
4124 * @brief Disable automatic output (MOE can be set only by software).
4125 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4126 * a timer instance provides a break input.
4127 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4128 * @param TIMx Timer instance
4129 * @retval None
4130 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4131 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4132 {
4133 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4134 }
4135
4136 /**
4137 * @brief Indicate whether automatic output is enabled.
4138 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4139 * a timer instance provides a break input.
4140 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4141 * @param TIMx Timer instance
4142 * @retval State of bit (1 or 0).
4143 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4144 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4145 {
4146 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4147 }
4148
4149 /**
4150 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4151 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4152 * software and is reset in case of break or break2 event
4153 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4154 * a timer instance provides a break input.
4155 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4156 * @param TIMx Timer instance
4157 * @retval None
4158 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4159 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4160 {
4161 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4162 }
4163
4164 /**
4165 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4166 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4167 * software and is reset in case of break or break2 event.
4168 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4169 * a timer instance provides a break input.
4170 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4171 * @param TIMx Timer instance
4172 * @retval None
4173 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4174 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4175 {
4176 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4177 }
4178
4179 /**
4180 * @brief Indicates whether outputs are enabled.
4181 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4182 * a timer instance provides a break input.
4183 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4184 * @param TIMx Timer instance
4185 * @retval State of bit (1 or 0).
4186 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4187 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4188 {
4189 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4190 }
4191
4192 /**
4193 * @brief Enable the signals connected to the designated timer break input.
4194 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4195 * or not a timer instance allows for break input selection.
4196 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4197 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4198 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4199 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4200 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4201 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4202 * @param TIMx Timer instance
4203 * @param BreakInput This parameter can be one of the following values:
4204 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4205 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4206 * @param Source This parameter can be one of the following values:
4207 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4208 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4209 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4210 * @retval None
4211 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4212 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4213 {
4214 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4215 SET_BIT(*pReg, Source);
4216 }
4217
4218 /**
4219 * @brief Disable the signals connected to the designated timer break input.
4220 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4221 * or not a timer instance allows for break input selection.
4222 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4223 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4224 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4225 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4226 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4227 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
4228 * @param TIMx Timer instance
4229 * @param BreakInput This parameter can be one of the following values:
4230 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4231 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4232 * @param Source This parameter can be one of the following values:
4233 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4234 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4235 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4236 * @retval None
4237 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4238 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4239 {
4240 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4241 CLEAR_BIT(*pReg, Source);
4242 }
4243
4244 /**
4245 * @brief Set the polarity of the break signal for the timer break input.
4246 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4247 * or not a timer instance allows for break input selection.
4248 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4249 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4250 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4251 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4252 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4253 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
4254 * @param TIMx Timer instance
4255 * @param BreakInput This parameter can be one of the following values:
4256 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4257 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4258 * @param Source This parameter can be one of the following values:
4259 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4260 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4261 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4262 * @param Polarity This parameter can be one of the following values:
4263 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4264 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4265 * @retval None
4266 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4267 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4268 uint32_t Polarity)
4269 {
4270 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4271 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4272 }
4273 /**
4274 * @brief Enable asymmetrical deadtime.
4275 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4276 * a timer instance provides asymmetrical deadtime.
4277 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4278 * @param TIMx Timer instance
4279 * @retval None
4280 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4281 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4282 {
4283 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4284 }
4285
4286 /**
4287 * @brief Disable asymmetrical dead-time.
4288 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4289 * a timer instance provides asymmetrical deadtime.
4290 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4291 * @param TIMx Timer instance
4292 * @retval None
4293 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4294 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4295 {
4296 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4297 }
4298
4299 /**
4300 * @brief Indicates whether asymmetrical deadtime is activated.
4301 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4302 * a timer instance provides asymmetrical deadtime.
4303 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4304 * @param TIMx Timer instance
4305 * @retval State of bit (1 or 0).
4306 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4307 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4308 {
4309 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4310 }
4311
4312 /**
4313 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4314 * rising edge of OCxN signals).
4315 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4316 * asymmetrical dead-time insertion feature is supported by a timer instance.
4317 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4318 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4319 * (LOCK bits in TIMx_BDTR register).
4320 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4321 * @param TIMx Timer instance
4322 * @param DeadTime between Min_Data=0 and Max_Data=255
4323 * @retval None
4324 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4325 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4326 {
4327 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4328 }
4329
4330 /**
4331 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4332 * the rising edge of OCxN signals).
4333 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4334 * asymmetrical dead-time insertion feature is supported by a timer instance.
4335 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4336 * (LOCK bits in TIMx_BDTR register).
4337 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4338 * @param TIMx Timer instance
4339 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4340 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4341 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4342 {
4343 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4344 }
4345
4346 /**
4347 * @brief Enable deadtime preload.
4348 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4349 * a timer instance provides deadtime preload.
4350 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4351 * @param TIMx Timer instance
4352 * @retval None
4353 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4354 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4355 {
4356 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4357 }
4358
4359 /**
4360 * @brief Disable dead-time preload.
4361 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4362 * a timer instance provides deadtime preload.
4363 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4364 * @param TIMx Timer instance
4365 * @retval None
4366 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4367 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4368 {
4369 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4370 }
4371
4372 /**
4373 * @brief Indicates whether deadtime preload is activated.
4374 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4375 * a timer instance provides deadtime preload.
4376 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4377 * @param TIMx Timer instance
4378 * @retval State of bit (1 or 0).
4379 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4380 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4381 {
4382 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4383 }
4384
4385 /**
4386 * @}
4387 */
4388
4389 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4390 * @{
4391 */
4392 /**
4393 * @brief Configures the timer DMA burst feature.
4394 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4395 * not a timer instance supports the DMA burst mode.
4396 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4397 * DCR DBA LL_TIM_ConfigDMABurst
4398 * @param TIMx Timer instance
4399 * @param DMABurstBaseAddress This parameter can be one of the following values:
4400 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4401 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4402 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4403 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4404 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4405 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4406 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4407 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4408 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4409 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4410 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4411 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4412 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4413 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4414 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4415 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4416 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4417 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4418 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4419 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4420 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4421 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4422 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4423 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4424 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4425 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4426 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
4427 * @param DMABurstLength This parameter can be one of the following values:
4428 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4429 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4430 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4431 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4432 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4433 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4434 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4435 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4436 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4437 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4438 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4439 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4440 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4441 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4442 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4443 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4444 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4445 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4446 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4447 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4448 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4449 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4450 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4451 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4452 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4453 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4454 * @param DMABurstSource This parameter can be one of the following values:
4455 * @arg @ref LL_TIM_DMA_UPDATE
4456 * @arg @ref LL_TIM_DMA_CC1
4457 * @arg @ref LL_TIM_DMA_CC2
4458 * @arg @ref LL_TIM_DMA_CC3
4459 * @arg @ref LL_TIM_DMA_CC4
4460 * @arg @ref LL_TIM_DMA_COM
4461 * @arg @ref LL_TIM_DMA_TRIGGER
4462 * @retval None
4463 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4464 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4465 uint32_t DMABurstSource)
4466 {
4467 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4468 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4469 }
4470
4471 /**
4472 * @}
4473 */
4474
4475 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4476 * @{
4477 */
4478
4479 /**
4480 * @brief Enable encoder index.
4481 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4482 * a timer instance provides an index input.
4483 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4484 * @param TIMx Timer instance
4485 * @retval None
4486 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4487 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4488 {
4489 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4490 }
4491
4492 /**
4493 * @brief Disable encoder index.
4494 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4495 * a timer instance provides an index input.
4496 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4497 * @param TIMx Timer instance
4498 * @retval None
4499 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4500 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4501 {
4502 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4503 }
4504
4505 /**
4506 * @brief Indicate whether encoder index is enabled.
4507 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4508 * a timer instance provides an index input.
4509 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4510 * @param TIMx Timer instance
4511 * @retval State of bit (1 or 0).
4512 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4513 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4514 {
4515 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4516 }
4517
4518 /**
4519 * @brief Set index direction
4520 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4521 * a timer instance provides an index input.
4522 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4523 * @param TIMx Timer instance
4524 * @param IndexDirection This parameter can be one of the following values:
4525 * @arg @ref LL_TIM_INDEX_UP_DOWN
4526 * @arg @ref LL_TIM_INDEX_UP
4527 * @arg @ref LL_TIM_INDEX_DOWN
4528 * @retval None
4529 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4530 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4531 {
4532 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4533 }
4534
4535 /**
4536 * @brief Get actual index direction
4537 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4538 * a timer instance provides an index input.
4539 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4540 * @param TIMx Timer instance
4541 * @retval Returned value can be one of the following values:
4542 * @arg @ref LL_TIM_INDEX_UP_DOWN
4543 * @arg @ref LL_TIM_INDEX_UP
4544 * @arg @ref LL_TIM_INDEX_DOWN
4545 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4546 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4547 {
4548 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4549 }
4550
4551 /**
4552 * @brief Set index blanking
4553 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4554 * a timer instance provides an index input.
4555 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4556 * @param TIMx Timer instance
4557 * @param Indexblanking This parameter can be one of the following values:
4558 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4559 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4560 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4561 * @retval None
4562 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4563 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4564 {
4565 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4566 }
4567
4568 /**
4569 * @brief Get actual index blanking
4570 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4571 * a timer instance provides an index input.
4572 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4573 * @param TIMx Timer instance
4574 * @retval Returned value can be one of the following values:
4575 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4576 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4577 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4578 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4579 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4580 {
4581 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4582 }
4583
4584
4585 /**
4586 * @brief Enable first index.
4587 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4588 * a timer instance provides an index input.
4589 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4590 * @param TIMx Timer instance
4591 * @retval None
4592 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4593 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4594 {
4595 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4596 }
4597
4598 /**
4599 * @brief Disable first index.
4600 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4601 * a timer instance provides an index input.
4602 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4603 * @param TIMx Timer instance
4604 * @retval None
4605 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4606 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4607 {
4608 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4609 }
4610
4611 /**
4612 * @brief Indicates whether first index is enabled.
4613 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4614 * a timer instance provides an index input.
4615 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4616 * @param TIMx Timer instance
4617 * @retval State of bit (1 or 0).
4618 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4619 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4620 {
4621 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4622 }
4623
4624 /**
4625 * @brief Set index positioning
4626 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4627 * a timer instance provides an index input.
4628 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4629 * @param TIMx Timer instance
4630 * @param IndexPositionning This parameter can be one of the following values:
4631 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4632 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4633 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4634 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4635 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4636 * @arg @ref LL_TIM_INDEX_POSITION_UP
4637 * @retval None
4638 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4639 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4640 {
4641 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4642 }
4643
4644 /**
4645 * @brief Get actual index positioning
4646 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4647 * a timer instance provides an index input.
4648 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4649 * @param TIMx Timer instance
4650 * @retval Returned value can be one of the following values:
4651 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4652 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4653 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4654 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4655 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4656 * @arg @ref LL_TIM_INDEX_POSITION_UP
4657 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4658 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4659 {
4660 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
4661 }
4662
4663 /**
4664 * @brief Configure encoder index.
4665 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4666 * a timer instance provides an index input.
4667 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
4668 * ECR IBLK LL_TIM_ConfigIDX\n
4669 * ECR FIDX LL_TIM_ConfigIDX\n
4670 * ECR IPOS LL_TIM_ConfigIDX
4671 * @param TIMx Timer instance
4672 * @param Configuration This parameter must be a combination of all the following values:
4673 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
4674 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
4675 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
4676 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
4677 * @retval None
4678 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)4679 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
4680 {
4681 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
4682 }
4683
4684 /**
4685 * @}
4686 */
4687
4688 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4689 * @{
4690 */
4691 /**
4692 * @brief Remap TIM inputs (input channel, internal/external triggers).
4693 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4694 * a some timer inputs can be remapped.
4695 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
4696 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
4697 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
4698 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
4699 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4700 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
4701 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4702 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
4703 * @param TIMx Timer instance
4704 * @param Remap Remap param depends on the TIMx. Description available only
4705 * in CHM version of the User Manual (not in .pdf).
4706 * Otherwise see Reference Manual description of TISEL registers.
4707 *
4708 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4709 *
4710 * TIM1: one of the following values:
4711 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
4712 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*)
4713 * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*)
4714 *
4715 * TIM2: one of the following values:
4716 * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
4717 * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output (*)
4718 * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output (*)
4719 * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
4720 * @arg LL_TIM_TIM2_TI2_RMP_COMP1: TIM2 TI2 is connected to COMP1 output (*)
4721 * @arg LL_TIM_TIM2_TI2_RMP_COMP2: TIM2 TI2 is connected to COMP2 output (*)
4722 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
4723 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output (*)
4724 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output (*)
4725 *
4726 * TIM3: one of the following values:
4727 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
4728 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*)
4729 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*)
4730 * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
4731 * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*)
4732 * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*)
4733 *
4734 * TIM16: one of the following values:
4735 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
4736 * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO
4737 * @arg LL_TIM_TIM16_TI1_RMP_HSE_DIV32: TIM16 TI1 is connected to HSE DIV32
4738 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC
4739 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
4740 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
4741 * @arg LL_TIM_TIM16_TI1_RMP_HSI_256: TIM16 TI1 is connected to HSI/256
4742 *
4743 * TIM17: one of the following values:
4744 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
4745 * @arg LL_TIM_TIM17_TI1_RMP_MCO: TIM17 TI1 is connected to MCO
4746 * @arg LL_TIM_TIM17_TI1_RMP_HSE_DIV32: TIM17 TI1 is connected to HSE DIV32
4747 * @arg LL_TIM_TIM17_TI1_RMP_RTC: TIM17 TI1 is connected to RTC
4748 * @arg LL_TIM_TIM17_TI1_RMP_LSE: TIM17 TI1 is connected to LSE
4749 * @arg LL_TIM_TIM17_TI1_RMP_LSI: TIM17 TI1 is connected to LSI
4750 * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256
4751 *
4752 * (*) Value not defined in all devices. \n
4753
4754 *
4755 * @retval None
4756 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4757 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4758 {
4759 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4760 }
4761
4762 /**
4763 * @brief Enable request for HSE/32 clock used for TISEL remap.
4764 * @note Only TIM16 and TIM17 support HSE/32 remap
4765 * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
4766 * @param TIMx Timer instance
4767 * @retval None
4768 */
LL_TIM_EnableHSE32(TIM_TypeDef * TIMx)4769 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
4770 {
4771 SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
4772 }
4773
4774 /**
4775 * @brief Disable request for HSE/32 clock used for TISEL remap.
4776 * @note Only TIM16 and TIM17 support HSE/32 remap
4777 * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
4778 * @param TIMx Timer instance
4779 * @retval None
4780 */
LL_TIM_DisableHSE32(TIM_TypeDef * TIMx)4781 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
4782 {
4783 CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
4784 }
4785
4786 /**
4787 * @brief Indicate whether request for HSE/32 clock is enabled.
4788 * @note Only TIM16 and TIM17 support HSE/32 remap
4789 * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
4790 * @param TIMx Timer instance
4791 * @retval State of bit (1 or 0).
4792 */
LL_TIM_IsEnabledHSE32(const TIM_TypeDef * TIMx)4793 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx)
4794 {
4795 return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
4796 }
4797
4798 /**
4799 * @}
4800 */
4801
4802 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4803 * @{
4804 */
4805 /**
4806 * @brief Set the OCREF clear input source
4807 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4808 * @note This function can only be used in Output compare and PWM modes.
4809 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4810 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
4811 * @param TIMx Timer instance
4812 * @param OCRefClearInputSource This parameter can be one of the following values:
4813 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4814 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
4815 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
4816 * @retval None
4817 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4818 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4819 {
4820 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
4821 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
4822 MODIFY_REG(TIMx->AF2, TIM_AF2_OCRSEL, OCRefClearInputSource);
4823 }
4824 /**
4825 * @}
4826 */
4827
4828 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4829 * @{
4830 */
4831 /**
4832 * @brief Clear the update interrupt flag (UIF).
4833 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4834 * @param TIMx Timer instance
4835 * @retval None
4836 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4837 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4838 {
4839 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4840 }
4841
4842 /**
4843 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4844 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4845 * @param TIMx Timer instance
4846 * @retval State of bit (1 or 0).
4847 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4848 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4849 {
4850 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4851 }
4852
4853 /**
4854 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4855 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4856 * @param TIMx Timer instance
4857 * @retval None
4858 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4859 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4860 {
4861 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4862 }
4863
4864 /**
4865 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4866 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4867 * @param TIMx Timer instance
4868 * @retval State of bit (1 or 0).
4869 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4870 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4871 {
4872 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4873 }
4874
4875 /**
4876 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4877 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4878 * @param TIMx Timer instance
4879 * @retval None
4880 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4881 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4882 {
4883 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4884 }
4885
4886 /**
4887 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4888 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4889 * @param TIMx Timer instance
4890 * @retval State of bit (1 or 0).
4891 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4892 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4893 {
4894 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4895 }
4896
4897 /**
4898 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4899 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4900 * @param TIMx Timer instance
4901 * @retval None
4902 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4903 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4904 {
4905 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4906 }
4907
4908 /**
4909 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4910 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4911 * @param TIMx Timer instance
4912 * @retval State of bit (1 or 0).
4913 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4914 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4915 {
4916 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4917 }
4918
4919 /**
4920 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4921 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4922 * @param TIMx Timer instance
4923 * @retval None
4924 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4925 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4926 {
4927 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4928 }
4929
4930 /**
4931 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4932 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4933 * @param TIMx Timer instance
4934 * @retval State of bit (1 or 0).
4935 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4936 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4937 {
4938 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4939 }
4940
4941 /**
4942 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4943 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4944 * @param TIMx Timer instance
4945 * @retval None
4946 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4947 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4948 {
4949 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4950 }
4951
4952 /**
4953 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4954 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4955 * @param TIMx Timer instance
4956 * @retval State of bit (1 or 0).
4957 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4958 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4959 {
4960 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4961 }
4962
4963 /**
4964 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4965 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4966 * @param TIMx Timer instance
4967 * @retval None
4968 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4969 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4970 {
4971 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4972 }
4973
4974 /**
4975 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4976 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4977 * @param TIMx Timer instance
4978 * @retval State of bit (1 or 0).
4979 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4980 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4981 {
4982 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4983 }
4984
4985 /**
4986 * @brief Clear the commutation interrupt flag (COMIF).
4987 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4988 * @param TIMx Timer instance
4989 * @retval None
4990 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4991 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4992 {
4993 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4994 }
4995
4996 /**
4997 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4998 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4999 * @param TIMx Timer instance
5000 * @retval State of bit (1 or 0).
5001 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5002 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5003 {
5004 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5005 }
5006
5007 /**
5008 * @brief Clear the trigger interrupt flag (TIF).
5009 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5010 * @param TIMx Timer instance
5011 * @retval None
5012 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5013 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5014 {
5015 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5016 }
5017
5018 /**
5019 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5020 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5021 * @param TIMx Timer instance
5022 * @retval State of bit (1 or 0).
5023 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5024 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5025 {
5026 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5027 }
5028
5029 /**
5030 * @brief Clear the break interrupt flag (BIF).
5031 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5032 * @param TIMx Timer instance
5033 * @retval None
5034 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5035 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5036 {
5037 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5038 }
5039
5040 /**
5041 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5042 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5043 * @param TIMx Timer instance
5044 * @retval State of bit (1 or 0).
5045 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5046 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5047 {
5048 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5049 }
5050
5051 /**
5052 * @brief Clear the break 2 interrupt flag (B2IF).
5053 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5054 * @param TIMx Timer instance
5055 * @retval None
5056 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5057 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5058 {
5059 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5060 }
5061
5062 /**
5063 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5064 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5065 * @param TIMx Timer instance
5066 * @retval State of bit (1 or 0).
5067 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5068 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5069 {
5070 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5071 }
5072
5073 /**
5074 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5075 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5076 * @param TIMx Timer instance
5077 * @retval None
5078 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5079 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5080 {
5081 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5082 }
5083
5084 /**
5085 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5086 * (Capture/Compare 1 interrupt is pending).
5087 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5088 * @param TIMx Timer instance
5089 * @retval State of bit (1 or 0).
5090 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5091 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5092 {
5093 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5094 }
5095
5096 /**
5097 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5098 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5099 * @param TIMx Timer instance
5100 * @retval None
5101 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5102 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5103 {
5104 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5105 }
5106
5107 /**
5108 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5109 * (Capture/Compare 2 over-capture interrupt is pending).
5110 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5111 * @param TIMx Timer instance
5112 * @retval State of bit (1 or 0).
5113 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5114 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5115 {
5116 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5117 }
5118
5119 /**
5120 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5121 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5122 * @param TIMx Timer instance
5123 * @retval None
5124 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5125 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5126 {
5127 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5128 }
5129
5130 /**
5131 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5132 * (Capture/Compare 3 over-capture interrupt is pending).
5133 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5134 * @param TIMx Timer instance
5135 * @retval State of bit (1 or 0).
5136 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5137 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5138 {
5139 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5140 }
5141
5142 /**
5143 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5144 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5145 * @param TIMx Timer instance
5146 * @retval None
5147 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5148 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5149 {
5150 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5151 }
5152
5153 /**
5154 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5155 * (Capture/Compare 4 over-capture interrupt is pending).
5156 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5157 * @param TIMx Timer instance
5158 * @retval State of bit (1 or 0).
5159 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5160 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5161 {
5162 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5163 }
5164
5165 /**
5166 * @brief Clear the system break interrupt flag (SBIF).
5167 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5168 * @param TIMx Timer instance
5169 * @retval None
5170 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5171 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5172 {
5173 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5174 }
5175
5176 /**
5177 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5178 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5179 * @param TIMx Timer instance
5180 * @retval State of bit (1 or 0).
5181 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5182 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5183 {
5184 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5185 }
5186
5187 /**
5188 * @brief Clear the transition error interrupt flag (TERRF).
5189 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5190 * a timer instance provides encoder error management.
5191 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5192 * @param TIMx Timer instance
5193 * @retval None
5194 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5195 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5196 {
5197 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5198 }
5199
5200 /**
5201 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5202 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5203 * a timer instance provides encoder error management.
5204 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5205 * @param TIMx Timer instance
5206 * @retval State of bit (1 or 0).
5207 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5208 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5209 {
5210 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5211 }
5212
5213 /**
5214 * @brief Clear the index error interrupt flag (IERRF).
5215 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5216 * a timer instance provides encoder error management.
5217 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5218 * @param TIMx Timer instance
5219 * @retval None
5220 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5221 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5222 {
5223 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5224 }
5225
5226 /**
5227 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5228 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5229 * a timer instance provides encoder error management.
5230 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5231 * @param TIMx Timer instance
5232 * @retval State of bit (1 or 0).
5233 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5234 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5235 {
5236 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5237 }
5238
5239 /**
5240 * @brief Clear the direction change interrupt flag (DIRF).
5241 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5242 * a timer instance provides encoder interrupt management.
5243 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5244 * @param TIMx Timer instance
5245 * @retval None
5246 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5247 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5248 {
5249 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5250 }
5251
5252 /**
5253 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5254 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5255 * a timer instance provides encoder interrupt management.
5256 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5257 * @param TIMx Timer instance
5258 * @retval State of bit (1 or 0).
5259 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5260 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5261 {
5262 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5263 }
5264
5265 /**
5266 * @brief Clear the index interrupt flag (IDXF).
5267 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5268 * a timer instance provides encoder interrupt management.
5269 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5270 * @param TIMx Timer instance
5271 * @retval None
5272 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5273 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5274 {
5275 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5276 }
5277
5278 /**
5279 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5280 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5281 * a timer instance provides encoder interrupt management.
5282 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5283 * @param TIMx Timer instance
5284 * @retval State of bit (1 or 0).
5285 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5286 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5287 {
5288 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5289 }
5290 /**
5291 * @}
5292 */
5293
5294 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5295 * @{
5296 */
5297 /**
5298 * @brief Enable update interrupt (UIE).
5299 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5300 * @param TIMx Timer instance
5301 * @retval None
5302 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5303 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5304 {
5305 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5306 }
5307
5308 /**
5309 * @brief Disable update interrupt (UIE).
5310 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5311 * @param TIMx Timer instance
5312 * @retval None
5313 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5314 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5315 {
5316 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5317 }
5318
5319 /**
5320 * @brief Indicates whether the update interrupt (UIE) is enabled.
5321 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5322 * @param TIMx Timer instance
5323 * @retval State of bit (1 or 0).
5324 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5325 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5326 {
5327 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5328 }
5329
5330 /**
5331 * @brief Enable capture/compare 1 interrupt (CC1IE).
5332 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5333 * @param TIMx Timer instance
5334 * @retval None
5335 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5336 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5337 {
5338 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5339 }
5340
5341 /**
5342 * @brief Disable capture/compare 1 interrupt (CC1IE).
5343 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5344 * @param TIMx Timer instance
5345 * @retval None
5346 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5347 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5348 {
5349 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5350 }
5351
5352 /**
5353 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5354 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5355 * @param TIMx Timer instance
5356 * @retval State of bit (1 or 0).
5357 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5358 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5359 {
5360 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5361 }
5362
5363 /**
5364 * @brief Enable capture/compare 2 interrupt (CC2IE).
5365 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5366 * @param TIMx Timer instance
5367 * @retval None
5368 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5369 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5370 {
5371 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5372 }
5373
5374 /**
5375 * @brief Disable capture/compare 2 interrupt (CC2IE).
5376 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5377 * @param TIMx Timer instance
5378 * @retval None
5379 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5380 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5381 {
5382 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5383 }
5384
5385 /**
5386 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5387 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5388 * @param TIMx Timer instance
5389 * @retval State of bit (1 or 0).
5390 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5391 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5392 {
5393 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5394 }
5395
5396 /**
5397 * @brief Enable capture/compare 3 interrupt (CC3IE).
5398 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5399 * @param TIMx Timer instance
5400 * @retval None
5401 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5402 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5403 {
5404 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5405 }
5406
5407 /**
5408 * @brief Disable capture/compare 3 interrupt (CC3IE).
5409 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5410 * @param TIMx Timer instance
5411 * @retval None
5412 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5413 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5414 {
5415 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5416 }
5417
5418 /**
5419 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5420 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5421 * @param TIMx Timer instance
5422 * @retval State of bit (1 or 0).
5423 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5424 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5425 {
5426 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5427 }
5428
5429 /**
5430 * @brief Enable capture/compare 4 interrupt (CC4IE).
5431 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5432 * @param TIMx Timer instance
5433 * @retval None
5434 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5435 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5436 {
5437 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5438 }
5439
5440 /**
5441 * @brief Disable capture/compare 4 interrupt (CC4IE).
5442 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5443 * @param TIMx Timer instance
5444 * @retval None
5445 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5446 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5447 {
5448 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5449 }
5450
5451 /**
5452 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5453 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5454 * @param TIMx Timer instance
5455 * @retval State of bit (1 or 0).
5456 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5457 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5458 {
5459 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5460 }
5461
5462 /**
5463 * @brief Enable commutation interrupt (COMIE).
5464 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5465 * @param TIMx Timer instance
5466 * @retval None
5467 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5468 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5469 {
5470 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5471 }
5472
5473 /**
5474 * @brief Disable commutation interrupt (COMIE).
5475 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5476 * @param TIMx Timer instance
5477 * @retval None
5478 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5479 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5480 {
5481 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5482 }
5483
5484 /**
5485 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5486 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5487 * @param TIMx Timer instance
5488 * @retval State of bit (1 or 0).
5489 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5490 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5491 {
5492 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5493 }
5494
5495 /**
5496 * @brief Enable trigger interrupt (TIE).
5497 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5498 * @param TIMx Timer instance
5499 * @retval None
5500 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5501 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5502 {
5503 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5504 }
5505
5506 /**
5507 * @brief Disable trigger interrupt (TIE).
5508 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5509 * @param TIMx Timer instance
5510 * @retval None
5511 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5512 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5513 {
5514 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5515 }
5516
5517 /**
5518 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5519 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5520 * @param TIMx Timer instance
5521 * @retval State of bit (1 or 0).
5522 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5523 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5524 {
5525 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5526 }
5527
5528 /**
5529 * @brief Enable break interrupt (BIE).
5530 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5531 * @param TIMx Timer instance
5532 * @retval None
5533 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5534 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5535 {
5536 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5537 }
5538
5539 /**
5540 * @brief Disable break interrupt (BIE).
5541 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5542 * @param TIMx Timer instance
5543 * @retval None
5544 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5545 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5546 {
5547 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5548 }
5549
5550 /**
5551 * @brief Indicates whether the break interrupt (BIE) is enabled.
5552 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5553 * @param TIMx Timer instance
5554 * @retval State of bit (1 or 0).
5555 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5556 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5557 {
5558 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5559 }
5560
5561 /**
5562 * @brief Enable transition error interrupt (TERRIE).
5563 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5564 * a timer instance provides encoder error management.
5565 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5566 * @param TIMx Timer instance
5567 * @retval None
5568 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5569 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5570 {
5571 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5572 }
5573
5574 /**
5575 * @brief Disable transition error interrupt (TERRIE).
5576 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5577 * a timer instance provides encoder error management.
5578 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5579 * @param TIMx Timer instance
5580 * @retval None
5581 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5582 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5583 {
5584 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5585 }
5586
5587 /**
5588 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5589 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5590 * a timer instance provides encoder error management.
5591 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5592 * @param TIMx Timer instance
5593 * @retval State of bit (1 or 0).
5594 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5595 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5596 {
5597 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5598 }
5599
5600 /**
5601 * @brief Enable index error interrupt (IERRIE).
5602 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5603 * a timer instance provides encoder error management.
5604 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5605 * @param TIMx Timer instance
5606 * @retval None
5607 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5608 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5609 {
5610 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5611 }
5612
5613 /**
5614 * @brief Disable index error interrupt (IERRIE).
5615 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5616 * a timer instance provides encoder error management.
5617 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
5618 * @param TIMx Timer instance
5619 * @retval None
5620 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)5621 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
5622 {
5623 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5624 }
5625
5626 /**
5627 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
5628 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5629 * a timer instance provides encoder error management.
5630 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
5631 * @param TIMx Timer instance
5632 * @retval State of bit (1 or 0).
5633 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)5634 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
5635 {
5636 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
5637 }
5638
5639 /**
5640 * @brief Enable direction change interrupt (DIRIE).
5641 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5642 * a timer instance provides encoder interrupt management.
5643 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
5644 * @param TIMx Timer instance
5645 * @retval None
5646 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)5647 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
5648 {
5649 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5650 }
5651
5652 /**
5653 * @brief Disable direction change interrupt (DIRIE).
5654 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5655 * a timer instance provides encoder interrupt management.
5656 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
5657 * @param TIMx Timer instance
5658 * @retval None
5659 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)5660 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
5661 {
5662 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5663 }
5664
5665 /**
5666 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
5667 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5668 * a timer instance provides encoder interrupt management.
5669 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
5670 * @param TIMx Timer instance
5671 * @retval State of bit (1 or 0).
5672 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)5673 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
5674 {
5675 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
5676 }
5677
5678 /**
5679 * @brief Enable index interrupt (IDXIE).
5680 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5681 * a timer instance provides encoder interrupt management.
5682 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
5683 * @param TIMx Timer instance
5684 * @retval None
5685 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)5686 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
5687 {
5688 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5689 }
5690
5691 /**
5692 * @brief Disable index interrupt (IDXIE).
5693 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5694 * a timer instance provides encoder interrupt management.
5695 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
5696 * @param TIMx Timer instance
5697 * @retval None
5698 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)5699 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
5700 {
5701 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5702 }
5703
5704 /**
5705 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
5706 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5707 * a timer instance provides encoder interrupt management.
5708 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
5709 * @param TIMx Timer instance
5710 * @retval State of bit (1 or 0).
5711 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)5712 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
5713 {
5714 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
5715 }
5716
5717 /**
5718 * @}
5719 */
5720
5721 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
5722 * @{
5723 */
5724 /**
5725 * @brief Enable update DMA request (UDE).
5726 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
5727 * @param TIMx Timer instance
5728 * @retval None
5729 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)5730 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5731 {
5732 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
5733 }
5734
5735 /**
5736 * @brief Disable update DMA request (UDE).
5737 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
5738 * @param TIMx Timer instance
5739 * @retval None
5740 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)5741 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5742 {
5743 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
5744 }
5745
5746 /**
5747 * @brief Indicates whether the update DMA request (UDE) is enabled.
5748 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
5749 * @param TIMx Timer instance
5750 * @retval State of bit (1 or 0).
5751 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)5752 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
5753 {
5754 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
5755 }
5756
5757 /**
5758 * @brief Enable capture/compare 1 DMA request (CC1DE).
5759 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
5760 * @param TIMx Timer instance
5761 * @retval None
5762 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)5763 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
5764 {
5765 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5766 }
5767
5768 /**
5769 * @brief Disable capture/compare 1 DMA request (CC1DE).
5770 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
5771 * @param TIMx Timer instance
5772 * @retval None
5773 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)5774 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
5775 {
5776 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5777 }
5778
5779 /**
5780 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
5781 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
5782 * @param TIMx Timer instance
5783 * @retval State of bit (1 or 0).
5784 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)5785 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
5786 {
5787 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
5788 }
5789
5790 /**
5791 * @brief Enable capture/compare 2 DMA request (CC2DE).
5792 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
5793 * @param TIMx Timer instance
5794 * @retval None
5795 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)5796 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
5797 {
5798 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5799 }
5800
5801 /**
5802 * @brief Disable capture/compare 2 DMA request (CC2DE).
5803 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
5804 * @param TIMx Timer instance
5805 * @retval None
5806 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)5807 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
5808 {
5809 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5810 }
5811
5812 /**
5813 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
5814 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
5815 * @param TIMx Timer instance
5816 * @retval State of bit (1 or 0).
5817 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)5818 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
5819 {
5820 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
5821 }
5822
5823 /**
5824 * @brief Enable capture/compare 3 DMA request (CC3DE).
5825 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
5826 * @param TIMx Timer instance
5827 * @retval None
5828 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)5829 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
5830 {
5831 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5832 }
5833
5834 /**
5835 * @brief Disable capture/compare 3 DMA request (CC3DE).
5836 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
5837 * @param TIMx Timer instance
5838 * @retval None
5839 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)5840 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
5841 {
5842 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5843 }
5844
5845 /**
5846 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
5847 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
5848 * @param TIMx Timer instance
5849 * @retval State of bit (1 or 0).
5850 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)5851 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
5852 {
5853 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
5854 }
5855
5856 /**
5857 * @brief Enable capture/compare 4 DMA request (CC4DE).
5858 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
5859 * @param TIMx Timer instance
5860 * @retval None
5861 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)5862 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
5863 {
5864 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5865 }
5866
5867 /**
5868 * @brief Disable capture/compare 4 DMA request (CC4DE).
5869 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
5870 * @param TIMx Timer instance
5871 * @retval None
5872 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)5873 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
5874 {
5875 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5876 }
5877
5878 /**
5879 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
5880 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
5881 * @param TIMx Timer instance
5882 * @retval State of bit (1 or 0).
5883 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)5884 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
5885 {
5886 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
5887 }
5888
5889 /**
5890 * @brief Enable commutation DMA request (COMDE).
5891 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
5892 * @param TIMx Timer instance
5893 * @retval None
5894 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)5895 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
5896 {
5897 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
5898 }
5899
5900 /**
5901 * @brief Disable commutation DMA request (COMDE).
5902 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
5903 * @param TIMx Timer instance
5904 * @retval None
5905 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)5906 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
5907 {
5908 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
5909 }
5910
5911 /**
5912 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
5913 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
5914 * @param TIMx Timer instance
5915 * @retval State of bit (1 or 0).
5916 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)5917 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
5918 {
5919 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
5920 }
5921
5922 /**
5923 * @brief Enable trigger interrupt (TDE).
5924 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
5925 * @param TIMx Timer instance
5926 * @retval None
5927 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)5928 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
5929 {
5930 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
5931 }
5932
5933 /**
5934 * @brief Disable trigger interrupt (TDE).
5935 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
5936 * @param TIMx Timer instance
5937 * @retval None
5938 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)5939 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
5940 {
5941 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
5942 }
5943
5944 /**
5945 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
5946 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
5947 * @param TIMx Timer instance
5948 * @retval State of bit (1 or 0).
5949 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)5950 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
5951 {
5952 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
5953 }
5954
5955 /**
5956 * @}
5957 */
5958
5959 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
5960 * @{
5961 */
5962 /**
5963 * @brief Generate an update event.
5964 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
5965 * @param TIMx Timer instance
5966 * @retval None
5967 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)5968 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
5969 {
5970 SET_BIT(TIMx->EGR, TIM_EGR_UG);
5971 }
5972
5973 /**
5974 * @brief Generate Capture/Compare 1 event.
5975 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
5976 * @param TIMx Timer instance
5977 * @retval None
5978 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)5979 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
5980 {
5981 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
5982 }
5983
5984 /**
5985 * @brief Generate Capture/Compare 2 event.
5986 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
5987 * @param TIMx Timer instance
5988 * @retval None
5989 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)5990 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
5991 {
5992 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
5993 }
5994
5995 /**
5996 * @brief Generate Capture/Compare 3 event.
5997 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
5998 * @param TIMx Timer instance
5999 * @retval None
6000 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6001 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6002 {
6003 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6004 }
6005
6006 /**
6007 * @brief Generate Capture/Compare 4 event.
6008 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6009 * @param TIMx Timer instance
6010 * @retval None
6011 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6012 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6013 {
6014 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6015 }
6016
6017 /**
6018 * @brief Generate commutation event.
6019 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6020 * @param TIMx Timer instance
6021 * @retval None
6022 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6023 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6024 {
6025 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6026 }
6027
6028 /**
6029 * @brief Generate trigger event.
6030 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6031 * @param TIMx Timer instance
6032 * @retval None
6033 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6034 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6035 {
6036 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6037 }
6038
6039 /**
6040 * @brief Generate break event.
6041 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6042 * @param TIMx Timer instance
6043 * @retval None
6044 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6045 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6046 {
6047 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6048 }
6049
6050 /**
6051 * @brief Generate break 2 event.
6052 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6053 * @param TIMx Timer instance
6054 * @retval None
6055 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6056 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6057 {
6058 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6059 }
6060
6061 /**
6062 * @}
6063 */
6064
6065 #if defined(USE_FULL_LL_DRIVER)
6066 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6067 * @{
6068 */
6069
6070 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6071 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6072 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6073 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6074 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6075 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6076 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6077 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6078 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6079 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6080 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6081 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6082 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6083 /**
6084 * @}
6085 */
6086 #endif /* USE_FULL_LL_DRIVER */
6087
6088 /**
6089 * @}
6090 */
6091
6092 /**
6093 * @}
6094 */
6095
6096 #endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */
6097
6098 /**
6099 * @}
6100 */
6101
6102 #ifdef __cplusplus
6103 }
6104 #endif
6105
6106 #endif /* __STM32WBAxx_LL_TIM_H */
6107
