1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 * + Timer encoder index configuration
16 ******************************************************************************
17 * @attention
18 *
19 * Copyright (c) 2019 STMicroelectronics.
20 * All rights reserved.
21 *
22 * This software is licensed under terms that can be found in the LICENSE file
23 * in the root directory of this software component.
24 * If no LICENSE file comes with this software, it is provided AS-IS.
25 *
26 ******************************************************************************
27 @verbatim
28 ==============================================================================
29 ##### TIMER Extended features #####
30 ==============================================================================
31 [..]
32 The Timer Extended features include:
33 (#) Complementary outputs with programmable dead-time for :
34 (++) Output Compare
35 (++) PWM generation (Edge and Center-aligned Mode)
36 (++) One-pulse mode output
37 (#) Synchronization circuit to control the timer with external signals and to
38 interconnect several timers together.
39 (#) Break input to put the timer output signals in reset state or in a known state.
40 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
41 positioning purposes
42 (#) In case of Pulse on compare, configure pulse length and delay
43 (#) Encoder index configuration
44
45 ##### How to use this driver #####
46 ==============================================================================
47 [..]
48 (#) Initialize the TIM low level resources by implementing the following functions
49 depending on the selected feature:
50 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
51
52 (#) Initialize the TIM low level resources :
53 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
54 (##) TIM pins configuration
55 (+++) Enable the clock for the TIM GPIOs using the following function:
56 __HAL_RCC_GPIOx_CLK_ENABLE();
57 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
58
59 (#) The external Clock can be configured, if needed (the default clock is the
60 internal clock from the APBx), using the following function:
61 HAL_TIM_ConfigClockSource, the clock configuration should be done before
62 any start function.
63
64 (#) Configure the TIM in the desired functioning mode using one of the
65 initialization function of this driver:
66 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
67 Timer Hall Sensor Interface and the commutation event with the corresponding
68 Interrupt and DMA request if needed (Note that One Timer is used to interface
69 with the Hall sensor Interface and another Timer should be used to use
70 the commutation event).
71 (#) In case of Pulse On Compare:
72 (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
73
74
75 (#) Activate the TIM peripheral using one of the start functions:
76 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
77 HAL_TIMEx_OCN_Start_IT()
78 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
79 HAL_TIMEx_PWMN_Start_IT()
80 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
81 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
82 HAL_TIMEx_HallSensor_Start_IT().
83
84 @endverbatim
85 ******************************************************************************
86 */
87
88 /* Includes ------------------------------------------------------------------*/
89 #include "stm32g4xx_hal.h"
90
91 /** @addtogroup STM32G4xx_HAL_Driver
92 * @{
93 */
94
95 /** @defgroup TIMEx TIMEx
96 * @brief TIM Extended HAL module driver
97 * @{
98 */
99
100 #ifdef HAL_TIM_MODULE_ENABLED
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
106 * @{
107 */
108 /* Timeout for break input rearm */
109 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
110 /**
111 * @}
112 */
113 /* End of private constants --------------------------------------------------*/
114
115 /* Private macros ------------------------------------------------------------*/
116 /* Private variables ---------------------------------------------------------*/
117 /* Private function prototypes -----------------------------------------------*/
118 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
119 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
120 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
124 * @{
125 */
126
127 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
128 * @brief Timer Hall Sensor functions
129 *
130 @verbatim
131 ==============================================================================
132 ##### Timer Hall Sensor functions #####
133 ==============================================================================
134 [..]
135 This section provides functions allowing to:
136 (+) Initialize and configure TIM HAL Sensor.
137 (+) De-initialize TIM HAL Sensor.
138 (+) Start the Hall Sensor Interface.
139 (+) Stop the Hall Sensor Interface.
140 (+) Start the Hall Sensor Interface and enable interrupts.
141 (+) Stop the Hall Sensor Interface and disable interrupts.
142 (+) Start the Hall Sensor Interface and enable DMA transfers.
143 (+) Stop the Hall Sensor Interface and disable DMA transfers.
144
145 @endverbatim
146 * @{
147 */
148 /**
149 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
150 * @note When the timer instance is initialized in Hall Sensor Interface mode,
151 * timer channels 1 and channel 2 are reserved and cannot be used for
152 * other purpose.
153 * @param htim TIM Hall Sensor Interface handle
154 * @param sConfig TIM Hall Sensor configuration structure
155 * @retval HAL status
156 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,TIM_HallSensor_InitTypeDef * sConfig)157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
158 {
159 TIM_OC_InitTypeDef OC_Config;
160
161 /* Check the TIM handle allocation */
162 if (htim == NULL)
163 {
164 return HAL_ERROR;
165 }
166
167 /* Check the parameters */
168 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
169 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
170 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
171 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
172 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
173 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
174 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
175
176 if (htim->State == HAL_TIM_STATE_RESET)
177 {
178 /* Allocate lock resource and initialize it */
179 htim->Lock = HAL_UNLOCKED;
180
181 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
182 /* Reset interrupt callbacks to legacy week callbacks */
183 TIM_ResetCallback(htim);
184
185 if (htim->HallSensor_MspInitCallback == NULL)
186 {
187 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
188 }
189 /* Init the low level hardware : GPIO, CLOCK, NVIC */
190 htim->HallSensor_MspInitCallback(htim);
191 #else
192 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
193 HAL_TIMEx_HallSensor_MspInit(htim);
194 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
195 }
196
197 /* Set the TIM state */
198 htim->State = HAL_TIM_STATE_BUSY;
199
200 /* Configure the Time base in the Encoder Mode */
201 TIM_Base_SetConfig(htim->Instance, &htim->Init);
202
203 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
204 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
205
206 /* Reset the IC1PSC Bits */
207 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
208 /* Set the IC1PSC value */
209 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
210
211 /* Enable the Hall sensor interface (XOR function of the three inputs) */
212 htim->Instance->CR2 |= TIM_CR2_TI1S;
213
214 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
215 htim->Instance->SMCR &= ~TIM_SMCR_TS;
216 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
217
218 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
219 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
220 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
221
222 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
223 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
224 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
225 OC_Config.OCMode = TIM_OCMODE_PWM2;
226 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
227 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
228 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
229 OC_Config.Pulse = sConfig->Commutation_Delay;
230
231 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
232
233 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
234 register to 101 */
235 htim->Instance->CR2 &= ~TIM_CR2_MMS;
236 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
237
238 /* Initialize the DMA burst operation state */
239 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
240
241 /* Initialize the TIM channels state */
242 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
243 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
244 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
245 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
246
247 /* Initialize the TIM state*/
248 htim->State = HAL_TIM_STATE_READY;
249
250 return HAL_OK;
251 }
252
253 /**
254 * @brief DeInitializes the TIM Hall Sensor interface
255 * @param htim TIM Hall Sensor Interface handle
256 * @retval HAL status
257 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)258 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
259 {
260 /* Check the parameters */
261 assert_param(IS_TIM_INSTANCE(htim->Instance));
262
263 htim->State = HAL_TIM_STATE_BUSY;
264
265 /* Disable the TIM Peripheral Clock */
266 __HAL_TIM_DISABLE(htim);
267
268 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
269 if (htim->HallSensor_MspDeInitCallback == NULL)
270 {
271 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
272 }
273 /* DeInit the low level hardware */
274 htim->HallSensor_MspDeInitCallback(htim);
275 #else
276 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
277 HAL_TIMEx_HallSensor_MspDeInit(htim);
278 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
279
280 /* Change the DMA burst operation state */
281 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
282
283 /* Change the TIM channels state */
284 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
286 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
288
289 /* Change TIM state */
290 htim->State = HAL_TIM_STATE_RESET;
291
292 /* Release Lock */
293 __HAL_UNLOCK(htim);
294
295 return HAL_OK;
296 }
297
298 /**
299 * @brief Initializes the TIM Hall Sensor MSP.
300 * @param htim TIM Hall Sensor Interface handle
301 * @retval None
302 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)303 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
304 {
305 /* Prevent unused argument(s) compilation warning */
306 UNUSED(htim);
307
308 /* NOTE : This function should not be modified, when the callback is needed,
309 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
310 */
311 }
312
313 /**
314 * @brief DeInitializes TIM Hall Sensor MSP.
315 * @param htim TIM Hall Sensor Interface handle
316 * @retval None
317 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)318 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
319 {
320 /* Prevent unused argument(s) compilation warning */
321 UNUSED(htim);
322
323 /* NOTE : This function should not be modified, when the callback is needed,
324 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
325 */
326 }
327
328 /**
329 * @brief Starts the TIM Hall Sensor Interface.
330 * @param htim TIM Hall Sensor Interface handle
331 * @retval HAL status
332 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)333 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
334 {
335 uint32_t tmpsmcr;
336 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
337 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
338 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
339 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
340
341 /* Check the parameters */
342 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
343
344 /* Check the TIM channels state */
345 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
346 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
347 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
348 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
349 {
350 return HAL_ERROR;
351 }
352
353 /* Set the TIM channels state */
354 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
356 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
357 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
358
359 /* Enable the Input Capture channel 1
360 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
361 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
362 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
363
364 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
365 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
366 {
367 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
368 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
369 {
370 __HAL_TIM_ENABLE(htim);
371 }
372 }
373 else
374 {
375 __HAL_TIM_ENABLE(htim);
376 }
377
378 /* Return function status */
379 return HAL_OK;
380 }
381
382 /**
383 * @brief Stops the TIM Hall sensor Interface.
384 * @param htim TIM Hall Sensor Interface handle
385 * @retval HAL status
386 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)387 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
388 {
389 /* Check the parameters */
390 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
391
392 /* Disable the Input Capture channels 1, 2 and 3
393 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
394 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
395 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
396
397 /* Disable the Peripheral */
398 __HAL_TIM_DISABLE(htim);
399
400 /* Set the TIM channels state */
401 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
402 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
403 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
405
406 /* Return function status */
407 return HAL_OK;
408 }
409
410 /**
411 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
412 * @param htim TIM Hall Sensor Interface handle
413 * @retval HAL status
414 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)415 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
416 {
417 uint32_t tmpsmcr;
418 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
419 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
420 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
421 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
422
423 /* Check the parameters */
424 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
425
426 /* Check the TIM channels state */
427 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
428 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
429 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
430 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
431 {
432 return HAL_ERROR;
433 }
434
435 /* Set the TIM channels state */
436 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
437 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
438 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
440
441 /* Enable the capture compare Interrupts 1 event */
442 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
443
444 /* Enable the Input Capture channel 1
445 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
446 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
448
449 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
450 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
451 {
452 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
453 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
454 {
455 __HAL_TIM_ENABLE(htim);
456 }
457 }
458 else
459 {
460 __HAL_TIM_ENABLE(htim);
461 }
462
463 /* Return function status */
464 return HAL_OK;
465 }
466
467 /**
468 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
469 * @param htim TIM Hall Sensor Interface handle
470 * @retval HAL status
471 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)472 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
473 {
474 /* Check the parameters */
475 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
476
477 /* Disable the Input Capture channel 1
478 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
479 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
480 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
481
482 /* Disable the capture compare Interrupts event */
483 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
484
485 /* Disable the Peripheral */
486 __HAL_TIM_DISABLE(htim);
487
488 /* Set the TIM channels state */
489 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
491 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
492 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
493
494 /* Return function status */
495 return HAL_OK;
496 }
497
498 /**
499 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
500 * @param htim TIM Hall Sensor Interface handle
501 * @param pData The destination Buffer address.
502 * @param Length The length of data to be transferred from TIM peripheral to memory.
503 * @retval HAL status
504 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)505 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
506 {
507 uint32_t tmpsmcr;
508 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
509 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
510
511 /* Check the parameters */
512 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
513
514 /* Set the TIM channel state */
515 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
516 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
517 {
518 return HAL_BUSY;
519 }
520 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
521 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
522 {
523 if ((pData == NULL) && (Length > 0U))
524 {
525 return HAL_ERROR;
526 }
527 else
528 {
529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
530 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
531 }
532 }
533 else
534 {
535 return HAL_ERROR;
536 }
537
538 /* Enable the Input Capture channel 1
539 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
540 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
541 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
542
543 /* Set the DMA Input Capture 1 Callbacks */
544 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
545 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
546 /* Set the DMA error callback */
547 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
548
549 /* Enable the DMA channel for Capture 1*/
550 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
551 {
552 /* Return error status */
553 return HAL_ERROR;
554 }
555 /* Enable the capture compare 1 Interrupt */
556 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
557
558 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
559 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
560 {
561 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
562 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
563 {
564 __HAL_TIM_ENABLE(htim);
565 }
566 }
567 else
568 {
569 __HAL_TIM_ENABLE(htim);
570 }
571
572 /* Return function status */
573 return HAL_OK;
574 }
575
576 /**
577 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
578 * @param htim TIM Hall Sensor Interface handle
579 * @retval HAL status
580 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)581 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
582 {
583 /* Check the parameters */
584 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
585
586 /* Disable the Input Capture channel 1
587 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
588 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
589 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
590
591
592 /* Disable the capture compare Interrupts 1 event */
593 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
594
595 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
596
597 /* Disable the Peripheral */
598 __HAL_TIM_DISABLE(htim);
599
600 /* Set the TIM channel state */
601 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
602 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
603
604 /* Return function status */
605 return HAL_OK;
606 }
607
608 /**
609 * @}
610 */
611
612 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
613 * @brief Timer Complementary Output Compare functions
614 *
615 @verbatim
616 ==============================================================================
617 ##### Timer Complementary Output Compare functions #####
618 ==============================================================================
619 [..]
620 This section provides functions allowing to:
621 (+) Start the Complementary Output Compare/PWM.
622 (+) Stop the Complementary Output Compare/PWM.
623 (+) Start the Complementary Output Compare/PWM and enable interrupts.
624 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
625 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
626 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
627
628 @endverbatim
629 * @{
630 */
631
632 /**
633 * @brief Starts the TIM Output Compare signal generation on the complementary
634 * output.
635 * @param htim TIM Output Compare handle
636 * @param Channel TIM Channel to be enabled
637 * This parameter can be one of the following values:
638 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
639 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
640 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
641 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
642 * @retval HAL status
643 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)644 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
645 {
646 uint32_t tmpsmcr;
647
648 /* Check the parameters */
649 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
650
651 /* Check the TIM complementary channel state */
652 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
653 {
654 return HAL_ERROR;
655 }
656
657 /* Set the TIM complementary channel state */
658 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
659
660 /* Enable the Capture compare channel N */
661 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
662
663 /* Enable the Main Output */
664 __HAL_TIM_MOE_ENABLE(htim);
665
666 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
667 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
668 {
669 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
670 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
671 {
672 __HAL_TIM_ENABLE(htim);
673 }
674 }
675 else
676 {
677 __HAL_TIM_ENABLE(htim);
678 }
679
680 /* Return function status */
681 return HAL_OK;
682 }
683
684 /**
685 * @brief Stops the TIM Output Compare signal generation on the complementary
686 * output.
687 * @param htim TIM handle
688 * @param Channel TIM Channel to be disabled
689 * This parameter can be one of the following values:
690 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
691 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
692 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
693 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
694 * @retval HAL status
695 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)696 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
697 {
698 /* Check the parameters */
699 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
700
701 /* Disable the Capture compare channel N */
702 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
703
704 /* Disable the Main Output */
705 __HAL_TIM_MOE_DISABLE(htim);
706
707 /* Disable the Peripheral */
708 __HAL_TIM_DISABLE(htim);
709
710 /* Set the TIM complementary channel state */
711 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
712
713 /* Return function status */
714 return HAL_OK;
715 }
716
717 /**
718 * @brief Starts the TIM Output Compare signal generation in interrupt mode
719 * on the complementary output.
720 * @param htim TIM OC handle
721 * @param Channel TIM Channel to be enabled
722 * This parameter can be one of the following values:
723 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
724 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
725 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
726 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
727 * @retval HAL status
728 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)729 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
730 {
731 HAL_StatusTypeDef status = HAL_OK;
732 uint32_t tmpsmcr;
733
734 /* Check the parameters */
735 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
736
737 /* Check the TIM complementary channel state */
738 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
739 {
740 return HAL_ERROR;
741 }
742
743 /* Set the TIM complementary channel state */
744 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
745
746 switch (Channel)
747 {
748 case TIM_CHANNEL_1:
749 {
750 /* Enable the TIM Output Compare interrupt */
751 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
752 break;
753 }
754
755 case TIM_CHANNEL_2:
756 {
757 /* Enable the TIM Output Compare interrupt */
758 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
759 break;
760 }
761
762 case TIM_CHANNEL_3:
763 {
764 /* Enable the TIM Output Compare interrupt */
765 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
766 break;
767 }
768
769
770 case TIM_CHANNEL_4:
771 {
772 /* Enable the TIM Output Compare interrupt */
773 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
774 break;
775 }
776
777 default:
778 status = HAL_ERROR;
779 break;
780 }
781
782 if (status == HAL_OK)
783 {
784 /* Enable the TIM Break interrupt */
785 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
786
787 /* Enable the Capture compare channel N */
788 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
789
790 /* Enable the Main Output */
791 __HAL_TIM_MOE_ENABLE(htim);
792
793 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
794 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
795 {
796 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
797 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
798 {
799 __HAL_TIM_ENABLE(htim);
800 }
801 }
802 else
803 {
804 __HAL_TIM_ENABLE(htim);
805 }
806 }
807
808 /* Return function status */
809 return status;
810 }
811
812 /**
813 * @brief Stops the TIM Output Compare signal generation in interrupt mode
814 * on the complementary output.
815 * @param htim TIM Output Compare handle
816 * @param Channel TIM Channel to be disabled
817 * This parameter can be one of the following values:
818 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
819 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
820 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
821 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
822 * @retval HAL status
823 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)824 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
825 {
826 HAL_StatusTypeDef status = HAL_OK;
827 uint32_t tmpccer;
828
829 /* Check the parameters */
830 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
831
832 switch (Channel)
833 {
834 case TIM_CHANNEL_1:
835 {
836 /* Disable the TIM Output Compare interrupt */
837 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
838 break;
839 }
840
841 case TIM_CHANNEL_2:
842 {
843 /* Disable the TIM Output Compare interrupt */
844 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
845 break;
846 }
847
848 case TIM_CHANNEL_3:
849 {
850 /* Disable the TIM Output Compare interrupt */
851 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
852 break;
853 }
854
855 case TIM_CHANNEL_4:
856 {
857 /* Disable the TIM Output Compare interrupt */
858 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
859 break;
860 }
861
862 default:
863 status = HAL_ERROR;
864 break;
865 }
866
867 if (status == HAL_OK)
868 {
869 /* Disable the Capture compare channel N */
870 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
871
872 /* Disable the TIM Break interrupt (only if no more channel is active) */
873 tmpccer = htim->Instance->CCER;
874 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
875 {
876 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
877 }
878
879 /* Disable the Main Output */
880 __HAL_TIM_MOE_DISABLE(htim);
881
882 /* Disable the Peripheral */
883 __HAL_TIM_DISABLE(htim);
884
885 /* Set the TIM complementary channel state */
886 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
887 }
888
889 /* Return function status */
890 return status;
891 }
892
893 /**
894 * @brief Starts the TIM Output Compare signal generation in DMA mode
895 * on the complementary output.
896 * @param htim TIM Output Compare handle
897 * @param Channel TIM Channel to be enabled
898 * This parameter can be one of the following values:
899 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
900 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
901 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
902 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
903 * @param pData The source Buffer address.
904 * @param Length The length of data to be transferred from memory to TIM peripheral
905 * @retval HAL status
906 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)907 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
908 {
909 HAL_StatusTypeDef status = HAL_OK;
910 uint32_t tmpsmcr;
911
912 /* Check the parameters */
913 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
914
915 /* Set the TIM complementary channel state */
916 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
917 {
918 return HAL_BUSY;
919 }
920 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
921 {
922 if ((pData == NULL) && (Length > 0U))
923 {
924 return HAL_ERROR;
925 }
926 else
927 {
928 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
929 }
930 }
931 else
932 {
933 return HAL_ERROR;
934 }
935
936 switch (Channel)
937 {
938 case TIM_CHANNEL_1:
939 {
940 /* Set the DMA compare callbacks */
941 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
942 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
943
944 /* Set the DMA error callback */
945 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
946
947 /* Enable the DMA channel */
948 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
949 Length) != HAL_OK)
950 {
951 /* Return error status */
952 return HAL_ERROR;
953 }
954 /* Enable the TIM Output Compare DMA request */
955 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
956 break;
957 }
958
959 case TIM_CHANNEL_2:
960 {
961 /* Set the DMA compare callbacks */
962 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
963 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
964
965 /* Set the DMA error callback */
966 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
967
968 /* Enable the DMA channel */
969 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
970 Length) != HAL_OK)
971 {
972 /* Return error status */
973 return HAL_ERROR;
974 }
975 /* Enable the TIM Output Compare DMA request */
976 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
977 break;
978 }
979
980 case TIM_CHANNEL_3:
981 {
982 /* Set the DMA compare callbacks */
983 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
984 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
985
986 /* Set the DMA error callback */
987 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
988
989 /* Enable the DMA channel */
990 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
991 Length) != HAL_OK)
992 {
993 /* Return error status */
994 return HAL_ERROR;
995 }
996 /* Enable the TIM Output Compare DMA request */
997 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
998 break;
999 }
1000
1001 case TIM_CHANNEL_4:
1002 {
1003 /* Set the DMA compare callbacks */
1004 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1005 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1006
1007 /* Set the DMA error callback */
1008 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1009
1010 /* Enable the DMA channel */
1011 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1012 Length) != HAL_OK)
1013 {
1014 /* Return error status */
1015 return HAL_ERROR;
1016 }
1017 /* Enable the TIM Output Compare DMA request */
1018 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1019 break;
1020 }
1021
1022 default:
1023 status = HAL_ERROR;
1024 break;
1025 }
1026
1027 if (status == HAL_OK)
1028 {
1029 /* Enable the Capture compare channel N */
1030 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1031
1032 /* Enable the Main Output */
1033 __HAL_TIM_MOE_ENABLE(htim);
1034
1035 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1036 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1037 {
1038 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1039 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1040 {
1041 __HAL_TIM_ENABLE(htim);
1042 }
1043 }
1044 else
1045 {
1046 __HAL_TIM_ENABLE(htim);
1047 }
1048 }
1049
1050 /* Return function status */
1051 return status;
1052 }
1053
1054 /**
1055 * @brief Stops the TIM Output Compare signal generation in DMA mode
1056 * on the complementary output.
1057 * @param htim TIM Output Compare handle
1058 * @param Channel TIM Channel to be disabled
1059 * This parameter can be one of the following values:
1060 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1061 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1062 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1063 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1064 * @retval HAL status
1065 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1066 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1067 {
1068 HAL_StatusTypeDef status = HAL_OK;
1069
1070 /* Check the parameters */
1071 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1072
1073 switch (Channel)
1074 {
1075 case TIM_CHANNEL_1:
1076 {
1077 /* Disable the TIM Output Compare DMA request */
1078 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1079 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1080 break;
1081 }
1082
1083 case TIM_CHANNEL_2:
1084 {
1085 /* Disable the TIM Output Compare DMA request */
1086 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1087 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1088 break;
1089 }
1090
1091 case TIM_CHANNEL_3:
1092 {
1093 /* Disable the TIM Output Compare DMA request */
1094 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1095 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1096 break;
1097 }
1098
1099 case TIM_CHANNEL_4:
1100 {
1101 /* Disable the TIM Output Compare interrupt */
1102 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1103 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1104 break;
1105 }
1106
1107 default:
1108 status = HAL_ERROR;
1109 break;
1110 }
1111
1112 if (status == HAL_OK)
1113 {
1114 /* Disable the Capture compare channel N */
1115 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1116
1117 /* Disable the Main Output */
1118 __HAL_TIM_MOE_DISABLE(htim);
1119
1120 /* Disable the Peripheral */
1121 __HAL_TIM_DISABLE(htim);
1122
1123 /* Set the TIM complementary channel state */
1124 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1125 }
1126
1127 /* Return function status */
1128 return status;
1129 }
1130
1131 /**
1132 * @}
1133 */
1134
1135 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1136 * @brief Timer Complementary PWM functions
1137 *
1138 @verbatim
1139 ==============================================================================
1140 ##### Timer Complementary PWM functions #####
1141 ==============================================================================
1142 [..]
1143 This section provides functions allowing to:
1144 (+) Start the Complementary PWM.
1145 (+) Stop the Complementary PWM.
1146 (+) Start the Complementary PWM and enable interrupts.
1147 (+) Stop the Complementary PWM and disable interrupts.
1148 (+) Start the Complementary PWM and enable DMA transfers.
1149 (+) Stop the Complementary PWM and disable DMA transfers.
1150 (+) Start the Complementary Input Capture measurement.
1151 (+) Stop the Complementary Input Capture.
1152 (+) Start the Complementary Input Capture and enable interrupts.
1153 (+) Stop the Complementary Input Capture and disable interrupts.
1154 (+) Start the Complementary Input Capture and enable DMA transfers.
1155 (+) Stop the Complementary Input Capture and disable DMA transfers.
1156 (+) Start the Complementary One Pulse generation.
1157 (+) Stop the Complementary One Pulse.
1158 (+) Start the Complementary One Pulse and enable interrupts.
1159 (+) Stop the Complementary One Pulse and disable interrupts.
1160
1161 @endverbatim
1162 * @{
1163 */
1164
1165 /**
1166 * @brief Starts the PWM signal generation on the complementary output.
1167 * @param htim TIM handle
1168 * @param Channel TIM Channel to be enabled
1169 * This parameter can be one of the following values:
1170 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1171 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1172 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1173 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1174 * @retval HAL status
1175 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1176 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1177 {
1178 uint32_t tmpsmcr;
1179
1180 /* Check the parameters */
1181 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1182
1183 /* Check the TIM complementary channel state */
1184 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1185 {
1186 return HAL_ERROR;
1187 }
1188
1189 /* Set the TIM complementary channel state */
1190 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1191
1192 /* Enable the complementary PWM output */
1193 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1194
1195 /* Enable the Main Output */
1196 __HAL_TIM_MOE_ENABLE(htim);
1197
1198 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1199 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1200 {
1201 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1202 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1203 {
1204 __HAL_TIM_ENABLE(htim);
1205 }
1206 }
1207 else
1208 {
1209 __HAL_TIM_ENABLE(htim);
1210 }
1211
1212 /* Return function status */
1213 return HAL_OK;
1214 }
1215
1216 /**
1217 * @brief Stops the PWM signal generation on the complementary output.
1218 * @param htim TIM handle
1219 * @param Channel TIM Channel to be disabled
1220 * This parameter can be one of the following values:
1221 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1222 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1223 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1224 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1225 * @retval HAL status
1226 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1227 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1228 {
1229 /* Check the parameters */
1230 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1231
1232 /* Disable the complementary PWM output */
1233 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1234
1235 /* Disable the Main Output */
1236 __HAL_TIM_MOE_DISABLE(htim);
1237
1238 /* Disable the Peripheral */
1239 __HAL_TIM_DISABLE(htim);
1240
1241 /* Set the TIM complementary channel state */
1242 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1243
1244 /* Return function status */
1245 return HAL_OK;
1246 }
1247
1248 /**
1249 * @brief Starts the PWM signal generation in interrupt mode on the
1250 * complementary output.
1251 * @param htim TIM handle
1252 * @param Channel TIM Channel to be disabled
1253 * This parameter can be one of the following values:
1254 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1255 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1256 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1257 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1258 * @retval HAL status
1259 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1260 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1261 {
1262 HAL_StatusTypeDef status = HAL_OK;
1263 uint32_t tmpsmcr;
1264
1265 /* Check the parameters */
1266 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1267
1268 /* Check the TIM complementary channel state */
1269 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1270 {
1271 return HAL_ERROR;
1272 }
1273
1274 /* Set the TIM complementary channel state */
1275 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1276
1277 switch (Channel)
1278 {
1279 case TIM_CHANNEL_1:
1280 {
1281 /* Enable the TIM Capture/Compare 1 interrupt */
1282 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1283 break;
1284 }
1285
1286 case TIM_CHANNEL_2:
1287 {
1288 /* Enable the TIM Capture/Compare 2 interrupt */
1289 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1290 break;
1291 }
1292
1293 case TIM_CHANNEL_3:
1294 {
1295 /* Enable the TIM Capture/Compare 3 interrupt */
1296 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1297 break;
1298 }
1299
1300 case TIM_CHANNEL_4:
1301 {
1302 /* Enable the TIM Capture/Compare 4 interrupt */
1303 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1304 break;
1305 }
1306
1307 default:
1308 status = HAL_ERROR;
1309 break;
1310 }
1311
1312 if (status == HAL_OK)
1313 {
1314 /* Enable the TIM Break interrupt */
1315 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1316
1317 /* Enable the complementary PWM output */
1318 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1319
1320 /* Enable the Main Output */
1321 __HAL_TIM_MOE_ENABLE(htim);
1322
1323 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1324 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1325 {
1326 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1327 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1328 {
1329 __HAL_TIM_ENABLE(htim);
1330 }
1331 }
1332 else
1333 {
1334 __HAL_TIM_ENABLE(htim);
1335 }
1336 }
1337
1338 /* Return function status */
1339 return status;
1340 }
1341
1342 /**
1343 * @brief Stops the PWM signal generation in interrupt mode on the
1344 * complementary output.
1345 * @param htim TIM handle
1346 * @param Channel TIM Channel to be disabled
1347 * This parameter can be one of the following values:
1348 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1349 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1350 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1351 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1352 * @retval HAL status
1353 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1354 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1355 {
1356 HAL_StatusTypeDef status = HAL_OK;
1357 uint32_t tmpccer;
1358
1359 /* Check the parameters */
1360 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1361
1362 switch (Channel)
1363 {
1364 case TIM_CHANNEL_1:
1365 {
1366 /* Disable the TIM Capture/Compare 1 interrupt */
1367 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1368 break;
1369 }
1370
1371 case TIM_CHANNEL_2:
1372 {
1373 /* Disable the TIM Capture/Compare 2 interrupt */
1374 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1375 break;
1376 }
1377
1378 case TIM_CHANNEL_3:
1379 {
1380 /* Disable the TIM Capture/Compare 3 interrupt */
1381 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1382 break;
1383 }
1384
1385 case TIM_CHANNEL_4:
1386 {
1387 /* Disable the TIM Capture/Compare 4 interrupt */
1388 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1389 break;
1390 }
1391
1392 default:
1393 status = HAL_ERROR;
1394 break;
1395 }
1396
1397 if (status == HAL_OK)
1398 {
1399 /* Disable the complementary PWM output */
1400 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1401
1402 /* Disable the TIM Break interrupt (only if no more channel is active) */
1403 tmpccer = htim->Instance->CCER;
1404 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
1405 {
1406 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1407 }
1408
1409 /* Disable the Main Output */
1410 __HAL_TIM_MOE_DISABLE(htim);
1411
1412 /* Disable the Peripheral */
1413 __HAL_TIM_DISABLE(htim);
1414
1415 /* Set the TIM complementary channel state */
1416 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1417 }
1418
1419 /* Return function status */
1420 return status;
1421 }
1422
1423 /**
1424 * @brief Starts the TIM PWM signal generation in DMA mode on the
1425 * complementary output
1426 * @param htim TIM handle
1427 * @param Channel TIM Channel to be enabled
1428 * This parameter can be one of the following values:
1429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1431 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1432 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1433 * @param pData The source Buffer address.
1434 * @param Length The length of data to be transferred from memory to TIM peripheral
1435 * @retval HAL status
1436 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1437 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1438 {
1439 HAL_StatusTypeDef status = HAL_OK;
1440 uint32_t tmpsmcr;
1441
1442 /* Check the parameters */
1443 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1444
1445 /* Set the TIM complementary channel state */
1446 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1447 {
1448 return HAL_BUSY;
1449 }
1450 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1451 {
1452 if ((pData == NULL) && (Length > 0U))
1453 {
1454 return HAL_ERROR;
1455 }
1456 else
1457 {
1458 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1459 }
1460 }
1461 else
1462 {
1463 return HAL_ERROR;
1464 }
1465
1466 switch (Channel)
1467 {
1468 case TIM_CHANNEL_1:
1469 {
1470 /* Set the DMA compare callbacks */
1471 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1472 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1473
1474 /* Set the DMA error callback */
1475 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1476
1477 /* Enable the DMA channel */
1478 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1479 Length) != HAL_OK)
1480 {
1481 /* Return error status */
1482 return HAL_ERROR;
1483 }
1484 /* Enable the TIM Capture/Compare 1 DMA request */
1485 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1486 break;
1487 }
1488
1489 case TIM_CHANNEL_2:
1490 {
1491 /* Set the DMA compare callbacks */
1492 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1493 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1494
1495 /* Set the DMA error callback */
1496 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1497
1498 /* Enable the DMA channel */
1499 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1500 Length) != HAL_OK)
1501 {
1502 /* Return error status */
1503 return HAL_ERROR;
1504 }
1505 /* Enable the TIM Capture/Compare 2 DMA request */
1506 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1507 break;
1508 }
1509
1510 case TIM_CHANNEL_3:
1511 {
1512 /* Set the DMA compare callbacks */
1513 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1514 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1515
1516 /* Set the DMA error callback */
1517 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1518
1519 /* Enable the DMA channel */
1520 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1521 Length) != HAL_OK)
1522 {
1523 /* Return error status */
1524 return HAL_ERROR;
1525 }
1526 /* Enable the TIM Capture/Compare 3 DMA request */
1527 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1528 break;
1529 }
1530
1531 case TIM_CHANNEL_4:
1532 {
1533 /* Set the DMA compare callbacks */
1534 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1535 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1536
1537 /* Set the DMA error callback */
1538 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1539
1540 /* Enable the DMA channel */
1541 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1542 Length) != HAL_OK)
1543 {
1544 /* Return error status */
1545 return HAL_ERROR;
1546 }
1547 /* Enable the TIM Capture/Compare 4 DMA request */
1548 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1549 break;
1550 }
1551
1552 default:
1553 status = HAL_ERROR;
1554 break;
1555 }
1556
1557 if (status == HAL_OK)
1558 {
1559 /* Enable the complementary PWM output */
1560 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1561
1562 /* Enable the Main Output */
1563 __HAL_TIM_MOE_ENABLE(htim);
1564
1565 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1566 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1567 {
1568 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1569 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1570 {
1571 __HAL_TIM_ENABLE(htim);
1572 }
1573 }
1574 else
1575 {
1576 __HAL_TIM_ENABLE(htim);
1577 }
1578 }
1579
1580 /* Return function status */
1581 return status;
1582 }
1583
1584 /**
1585 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1586 * output
1587 * @param htim TIM handle
1588 * @param Channel TIM Channel to be disabled
1589 * This parameter can be one of the following values:
1590 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1591 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1592 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1593 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1594 * @retval HAL status
1595 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1596 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1597 {
1598 HAL_StatusTypeDef status = HAL_OK;
1599
1600 /* Check the parameters */
1601 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1602
1603 switch (Channel)
1604 {
1605 case TIM_CHANNEL_1:
1606 {
1607 /* Disable the TIM Capture/Compare 1 DMA request */
1608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1609 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1610 break;
1611 }
1612
1613 case TIM_CHANNEL_2:
1614 {
1615 /* Disable the TIM Capture/Compare 2 DMA request */
1616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1617 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1618 break;
1619 }
1620
1621 case TIM_CHANNEL_3:
1622 {
1623 /* Disable the TIM Capture/Compare 3 DMA request */
1624 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1625 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1626 break;
1627 }
1628
1629 case TIM_CHANNEL_4:
1630 {
1631 /* Disable the TIM Capture/Compare 4 DMA request */
1632 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1633 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1634 break;
1635 }
1636
1637 default:
1638 status = HAL_ERROR;
1639 break;
1640 }
1641
1642 if (status == HAL_OK)
1643 {
1644 /* Disable the complementary PWM output */
1645 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1646
1647 /* Disable the Main Output */
1648 __HAL_TIM_MOE_DISABLE(htim);
1649
1650 /* Disable the Peripheral */
1651 __HAL_TIM_DISABLE(htim);
1652
1653 /* Set the TIM complementary channel state */
1654 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1655 }
1656
1657 /* Return function status */
1658 return status;
1659 }
1660
1661 /**
1662 * @}
1663 */
1664
1665 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1666 * @brief Timer Complementary One Pulse functions
1667 *
1668 @verbatim
1669 ==============================================================================
1670 ##### Timer Complementary One Pulse functions #####
1671 ==============================================================================
1672 [..]
1673 This section provides functions allowing to:
1674 (+) Start the Complementary One Pulse generation.
1675 (+) Stop the Complementary One Pulse.
1676 (+) Start the Complementary One Pulse and enable interrupts.
1677 (+) Stop the Complementary One Pulse and disable interrupts.
1678
1679 @endverbatim
1680 * @{
1681 */
1682
1683 /**
1684 * @brief Starts the TIM One Pulse signal generation on the complementary
1685 * output.
1686 * @note OutputChannel must match the pulse output channel chosen when calling
1687 * @ref HAL_TIM_OnePulse_ConfigChannel().
1688 * @param htim TIM One Pulse handle
1689 * @param OutputChannel pulse output channel to enable
1690 * This parameter can be one of the following values:
1691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1693 * @retval HAL status
1694 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1695 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1696 {
1697 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1698 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1699 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1700 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1701 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1702
1703 /* Check the parameters */
1704 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1705
1706 /* Check the TIM channels state */
1707 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1708 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1709 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1710 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1711 {
1712 return HAL_ERROR;
1713 }
1714
1715 /* Set the TIM channels state */
1716 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1717 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1718 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1719 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1720
1721 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1722 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1723 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1724
1725 /* Enable the Main Output */
1726 __HAL_TIM_MOE_ENABLE(htim);
1727
1728 /* Return function status */
1729 return HAL_OK;
1730 }
1731
1732 /**
1733 * @brief Stops the TIM One Pulse signal generation on the complementary
1734 * output.
1735 * @note OutputChannel must match the pulse output channel chosen when calling
1736 * @ref HAL_TIM_OnePulse_ConfigChannel().
1737 * @param htim TIM One Pulse handle
1738 * @param OutputChannel pulse output channel to disable
1739 * This parameter can be one of the following values:
1740 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1741 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1742 * @retval HAL status
1743 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1744 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1745 {
1746 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1747
1748 /* Check the parameters */
1749 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1750
1751 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1752 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1753 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1754
1755 /* Disable the Main Output */
1756 __HAL_TIM_MOE_DISABLE(htim);
1757
1758 /* Disable the Peripheral */
1759 __HAL_TIM_DISABLE(htim);
1760
1761 /* Set the TIM channels state */
1762 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1763 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1764 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1765 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1766
1767 /* Return function status */
1768 return HAL_OK;
1769 }
1770
1771 /**
1772 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1773 * complementary channel.
1774 * @note OutputChannel must match the pulse output channel chosen when calling
1775 * @ref HAL_TIM_OnePulse_ConfigChannel().
1776 * @param htim TIM One Pulse handle
1777 * @param OutputChannel pulse output channel to enable
1778 * This parameter can be one of the following values:
1779 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1780 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1781 * @retval HAL status
1782 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1783 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1784 {
1785 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1786 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1787 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1788 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1789 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1790
1791 /* Check the parameters */
1792 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1793
1794 /* Check the TIM channels state */
1795 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1796 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1797 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1798 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1799 {
1800 return HAL_ERROR;
1801 }
1802
1803 /* Set the TIM channels state */
1804 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1805 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1806 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1807 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1808
1809 /* Enable the TIM Capture/Compare 1 interrupt */
1810 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1811
1812 /* Enable the TIM Capture/Compare 2 interrupt */
1813 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1814
1815 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1816 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1817 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1818
1819 /* Enable the Main Output */
1820 __HAL_TIM_MOE_ENABLE(htim);
1821
1822 /* Return function status */
1823 return HAL_OK;
1824 }
1825
1826 /**
1827 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1828 * complementary channel.
1829 * @note OutputChannel must match the pulse output channel chosen when calling
1830 * @ref HAL_TIM_OnePulse_ConfigChannel().
1831 * @param htim TIM One Pulse handle
1832 * @param OutputChannel pulse output channel to disable
1833 * This parameter can be one of the following values:
1834 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1835 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1836 * @retval HAL status
1837 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1838 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1839 {
1840 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1841
1842 /* Check the parameters */
1843 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1844
1845 /* Disable the TIM Capture/Compare 1 interrupt */
1846 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1847
1848 /* Disable the TIM Capture/Compare 2 interrupt */
1849 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1850
1851 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1852 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1853 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1854
1855 /* Disable the Main Output */
1856 __HAL_TIM_MOE_DISABLE(htim);
1857
1858 /* Disable the Peripheral */
1859 __HAL_TIM_DISABLE(htim);
1860
1861 /* Set the TIM channels state */
1862 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1863 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1864 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1865 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1866
1867 /* Return function status */
1868 return HAL_OK;
1869 }
1870
1871 /**
1872 * @}
1873 */
1874
1875 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1876 * @brief Peripheral Control functions
1877 *
1878 @verbatim
1879 ==============================================================================
1880 ##### Peripheral Control functions #####
1881 ==============================================================================
1882 [..]
1883 This section provides functions allowing to:
1884 (+) Configure the commutation event in case of use of the Hall sensor interface.
1885 (+) Configure Output channels for OC and PWM mode.
1886
1887 (+) Configure Complementary channels, break features and dead time.
1888 (+) Configure Master synchronization.
1889 (+) Configure timer remapping capabilities.
1890 (+) Select timer input source.
1891 (+) Enable or disable channel grouping.
1892 (+) Configure Pulse on compare.
1893 (+) Configure Encoder index.
1894
1895 @endverbatim
1896 * @{
1897 */
1898
1899 /**
1900 * @brief Configure the TIM commutation event sequence.
1901 * @note This function is mandatory to use the commutation event in order to
1902 * update the configuration at each commutation detection on the TRGI input of the Timer,
1903 * the typical use of this feature is with the use of another Timer(interface Timer)
1904 * configured in Hall sensor interface, this interface Timer will generate the
1905 * commutation at its TRGO output (connected to Timer used in this function) each time
1906 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1907 * @param htim TIM handle
1908 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1909 * This parameter can be one of the following values:
1910 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1911 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1912 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1913 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1914 * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
1915 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1916 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1917 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1918 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1919 * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
1920 * @arg TIM_TS_ITR10: Internal trigger 10 selected
1921 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1922 * @arg TIM_TS_NONE: No trigger is needed
1923 *
1924 * (*) Value not defined in all devices.
1925 *
1926 * @param CommutationSource the Commutation Event source
1927 * This parameter can be one of the following values:
1928 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1929 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1930 * @retval HAL status
1931 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1932 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1933 uint32_t CommutationSource)
1934 {
1935 /* Check the parameters */
1936 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1937 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1938
1939 __HAL_LOCK(htim);
1940
1941 #if defined(TIM5) && defined(TIM20)
1942 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1943 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1944 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1945 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1946 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
1947 (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
1948 #elif defined(TIM5)
1949 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1950 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1951 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1952 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1953 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
1954 #elif defined(TIM20)
1955 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1956 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1957 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
1958 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
1959 (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
1960 #else
1961 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1962 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1963 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
1964 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
1965 (InputTrigger == TIM_TS_ITR11))
1966 #endif /* TIM5 && TIM20 */
1967 {
1968 /* Select the Input trigger */
1969 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1970 htim->Instance->SMCR |= InputTrigger;
1971 }
1972
1973 /* Select the Capture Compare preload feature */
1974 htim->Instance->CR2 |= TIM_CR2_CCPC;
1975 /* Select the Commutation event source */
1976 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1977 htim->Instance->CR2 |= CommutationSource;
1978
1979 /* Disable Commutation Interrupt */
1980 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1981
1982 /* Disable Commutation DMA request */
1983 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1984
1985 __HAL_UNLOCK(htim);
1986
1987 return HAL_OK;
1988 }
1989
1990 /**
1991 * @brief Configure the TIM commutation event sequence with interrupt.
1992 * @note This function is mandatory to use the commutation event in order to
1993 * update the configuration at each commutation detection on the TRGI input of the Timer,
1994 * the typical use of this feature is with the use of another Timer(interface Timer)
1995 * configured in Hall sensor interface, this interface Timer will generate the
1996 * commutation at its TRGO output (connected to Timer used in this function) each time
1997 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1998 * @param htim TIM handle
1999 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2000 * This parameter can be one of the following values:
2001 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2002 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2003 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2004 * @arg TIM_TS_ITR3: Internal trigger 3 selected
2005 * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
2006 * @arg TIM_TS_ITR5: Internal trigger 5 selected
2007 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2008 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2009 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2010 * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
2011 * @arg TIM_TS_ITR10: Internal trigger 10 selected
2012 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2013 * @arg TIM_TS_NONE: No trigger is needed
2014 *
2015 * (*) Value not defined in all devices.
2016 *
2017 * @param CommutationSource the Commutation Event source
2018 * This parameter can be one of the following values:
2019 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2020 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2021 * @retval HAL status
2022 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2023 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2024 uint32_t CommutationSource)
2025 {
2026 /* Check the parameters */
2027 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2028 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2029
2030 __HAL_LOCK(htim);
2031
2032 #if defined(TIM5) && defined(TIM20)
2033 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2034 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2035 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2036 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2037 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
2038 (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
2039 #elif defined(TIM5)
2040 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2041 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2042 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2043 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2044 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2045 #elif defined(TIM20)
2046 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2047 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2048 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2049 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2050 (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
2051 #else
2052 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2053 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2054 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2055 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2056 (InputTrigger == TIM_TS_ITR11))
2057 #endif /* TIM5 && TIM20 */
2058 {
2059 /* Select the Input trigger */
2060 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2061 htim->Instance->SMCR |= InputTrigger;
2062 }
2063
2064 /* Select the Capture Compare preload feature */
2065 htim->Instance->CR2 |= TIM_CR2_CCPC;
2066 /* Select the Commutation event source */
2067 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2068 htim->Instance->CR2 |= CommutationSource;
2069
2070 /* Disable Commutation DMA request */
2071 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
2072
2073 /* Enable the Commutation Interrupt */
2074 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
2075
2076 __HAL_UNLOCK(htim);
2077
2078 return HAL_OK;
2079 }
2080
2081 /**
2082 * @brief Configure the TIM commutation event sequence with DMA.
2083 * @note This function is mandatory to use the commutation event in order to
2084 * update the configuration at each commutation detection on the TRGI input of the Timer,
2085 * the typical use of this feature is with the use of another Timer(interface Timer)
2086 * configured in Hall sensor interface, this interface Timer will generate the
2087 * commutation at its TRGO output (connected to Timer used in this function) each time
2088 * the TI1 of the Interface Timer detect a commutation at its input TI1.
2089 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
2090 * @param htim TIM handle
2091 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2092 * This parameter can be one of the following values:
2093 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2094 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2095 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2096 * @arg TIM_TS_ITR3: Internal trigger 3 selected
2097 * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
2098 * @arg TIM_TS_ITR5: Internal trigger 5 selected
2099 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2100 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2101 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2102 * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
2103 * @arg TIM_TS_ITR10: Internal trigger 10 selected
2104 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2105 * @arg TIM_TS_NONE: No trigger is needed
2106 *
2107 * (*) Value not defined in all devices.
2108 *
2109 * @param CommutationSource the Commutation Event source
2110 * This parameter can be one of the following values:
2111 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2112 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2113 * @retval HAL status
2114 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2115 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2116 uint32_t CommutationSource)
2117 {
2118 /* Check the parameters */
2119 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2120 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2121
2122 __HAL_LOCK(htim);
2123
2124 #if defined(TIM5) && defined(TIM20)
2125 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2126 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2127 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2128 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2129 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
2130 (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
2131 #elif defined(TIM5)
2132 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2133 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2134 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2135 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2136 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2137 #elif defined(TIM20)
2138 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2139 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2140 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2141 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2142 (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
2143 #else
2144 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2145 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2146 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2147 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2148 (InputTrigger == TIM_TS_ITR11))
2149 #endif /* TIM5 && TIM20 */
2150 {
2151 /* Select the Input trigger */
2152 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2153 htim->Instance->SMCR |= InputTrigger;
2154 }
2155
2156 /* Select the Capture Compare preload feature */
2157 htim->Instance->CR2 |= TIM_CR2_CCPC;
2158 /* Select the Commutation event source */
2159 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2160 htim->Instance->CR2 |= CommutationSource;
2161
2162 /* Enable the Commutation DMA Request */
2163 /* Set the DMA Commutation Callback */
2164 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
2165 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
2166 /* Set the DMA error callback */
2167 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
2168
2169 /* Disable Commutation Interrupt */
2170 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
2171
2172 /* Enable the Commutation DMA Request */
2173 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
2174
2175 __HAL_UNLOCK(htim);
2176
2177 return HAL_OK;
2178 }
2179
2180 /**
2181 * @brief Configures the TIM in master mode.
2182 * @param htim TIM handle.
2183 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
2184 * contains the selected trigger output (TRGO) and the Master/Slave
2185 * mode.
2186 * @retval HAL status
2187 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,TIM_MasterConfigTypeDef * sMasterConfig)2188 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2189 TIM_MasterConfigTypeDef *sMasterConfig)
2190 {
2191 uint32_t tmpcr2;
2192 uint32_t tmpsmcr;
2193
2194 /* Check the parameters */
2195 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2196 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2197 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2198
2199 /* Check input state */
2200 __HAL_LOCK(htim);
2201
2202 /* Change the handler state */
2203 htim->State = HAL_TIM_STATE_BUSY;
2204
2205 /* Get the TIMx CR2 register value */
2206 tmpcr2 = htim->Instance->CR2;
2207
2208 /* Get the TIMx SMCR register value */
2209 tmpsmcr = htim->Instance->SMCR;
2210
2211 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2212 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2213 {
2214 /* Check the parameters */
2215 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2216
2217 /* Clear the MMS2 bits */
2218 tmpcr2 &= ~TIM_CR2_MMS2;
2219 /* Select the TRGO2 source*/
2220 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2221 }
2222
2223 /* Reset the MMS Bits */
2224 tmpcr2 &= ~TIM_CR2_MMS;
2225 /* Select the TRGO source */
2226 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2227
2228 /* Update TIMx CR2 */
2229 htim->Instance->CR2 = tmpcr2;
2230
2231 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2232 {
2233 /* Reset the MSM Bit */
2234 tmpsmcr &= ~TIM_SMCR_MSM;
2235 /* Set master mode */
2236 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2237
2238 /* Update TIMx SMCR */
2239 htim->Instance->SMCR = tmpsmcr;
2240 }
2241
2242 /* Change the htim state */
2243 htim->State = HAL_TIM_STATE_READY;
2244
2245 __HAL_UNLOCK(htim);
2246
2247 return HAL_OK;
2248 }
2249
2250 /**
2251 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2252 * and the AOE(automatic output enable).
2253 * @param htim TIM handle
2254 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2255 * contains the BDTR Register configuration information for the TIM peripheral.
2256 * @note Interrupts can be generated when an active level is detected on the
2257 * break input, the break 2 input or the system break input. Break
2258 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2259 * @retval HAL status
2260 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2261 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2262 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2263 {
2264 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2265 uint32_t tmpbdtr = 0U;
2266
2267 /* Check the parameters */
2268 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2269 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2270 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2271 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2272 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2273 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2274 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2275 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2276 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2277
2278 /* Check input state */
2279 __HAL_LOCK(htim);
2280
2281 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2282 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2283
2284 /* Set the BDTR bits */
2285 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2286 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2287 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2288 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2289 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2290 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2291 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2292 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2293
2294 if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
2295 {
2296 /* Check the parameters */
2297 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2298
2299 /* Set BREAK AF mode */
2300 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2301 }
2302
2303 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2304 {
2305 /* Check the parameters */
2306 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2307 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2308 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2309
2310 /* Set the BREAK2 input related BDTR bits */
2311 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2312 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2313 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2314
2315 if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
2316 {
2317 /* Check the parameters */
2318 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2319
2320 /* Set BREAK2 AF mode */
2321 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2322 }
2323 }
2324
2325 /* Set TIMx_BDTR */
2326 htim->Instance->BDTR = tmpbdtr;
2327
2328 __HAL_UNLOCK(htim);
2329
2330 return HAL_OK;
2331 }
2332
2333 /**
2334 * @brief Configures the break input source.
2335 * @param htim TIM handle.
2336 * @param BreakInput Break input to configure
2337 * This parameter can be one of the following values:
2338 * @arg TIM_BREAKINPUT_BRK: Timer break input
2339 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2340 * @param sBreakInputConfig Break input source configuration
2341 * @retval HAL status
2342 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2343 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2344 uint32_t BreakInput,
2345 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2346
2347 {
2348 HAL_StatusTypeDef status = HAL_OK;
2349 uint32_t tmporx;
2350 uint32_t bkin_enable_mask;
2351 uint32_t bkin_polarity_mask;
2352 uint32_t bkin_enable_bitpos;
2353 uint32_t bkin_polarity_bitpos;
2354
2355 /* Check the parameters */
2356 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2357 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2358 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2359 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2360 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2361
2362 /* Check input state */
2363 __HAL_LOCK(htim);
2364
2365 switch (sBreakInputConfig->Source)
2366 {
2367 case TIM_BREAKINPUTSOURCE_BKIN:
2368 {
2369 bkin_enable_mask = TIM1_AF1_BKINE;
2370 bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
2371 bkin_polarity_mask = TIM1_AF1_BKINP;
2372 bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
2373 break;
2374 }
2375 case TIM_BREAKINPUTSOURCE_COMP1:
2376 {
2377 bkin_enable_mask = TIM1_AF1_BKCMP1E;
2378 bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
2379 bkin_polarity_mask = TIM1_AF1_BKCMP1P;
2380 bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
2381 break;
2382 }
2383 case TIM_BREAKINPUTSOURCE_COMP2:
2384 {
2385 bkin_enable_mask = TIM1_AF1_BKCMP2E;
2386 bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
2387 bkin_polarity_mask = TIM1_AF1_BKCMP2P;
2388 bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
2389 break;
2390 }
2391 case TIM_BREAKINPUTSOURCE_COMP3:
2392 {
2393 bkin_enable_mask = TIM1_AF1_BKCMP3E;
2394 bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
2395 bkin_polarity_mask = TIM1_AF1_BKCMP3P;
2396 bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
2397 break;
2398 }
2399 case TIM_BREAKINPUTSOURCE_COMP4:
2400 {
2401 bkin_enable_mask = TIM1_AF1_BKCMP4E;
2402 bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
2403 bkin_polarity_mask = TIM1_AF1_BKCMP4P;
2404 bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
2405 break;
2406 }
2407 #if defined (COMP5)
2408 case TIM_BREAKINPUTSOURCE_COMP5:
2409 {
2410 bkin_enable_mask = TIM1_AF1_BKCMP5E;
2411 bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
2412 /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
2413 bkin_polarity_mask = 0U;
2414 bkin_polarity_bitpos = 0U;
2415 break;
2416 }
2417 #endif /* COMP5 */
2418 #if defined (COMP6)
2419 case TIM_BREAKINPUTSOURCE_COMP6:
2420 {
2421 bkin_enable_mask = TIM1_AF1_BKCMP6E;
2422 bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
2423 /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
2424 bkin_polarity_mask = 0U;
2425 bkin_polarity_bitpos = 0U;
2426 break;
2427 }
2428 #endif /* COMP7 */
2429 #if defined (COMP7)
2430 case TIM_BREAKINPUTSOURCE_COMP7:
2431 {
2432 bkin_enable_mask = TIM1_AF1_BKCMP7E;
2433 bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
2434 /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
2435 bkin_polarity_mask = 0U;
2436 bkin_polarity_bitpos = 0U;
2437 break;
2438 }
2439 #endif /* COMP7 */
2440
2441 default:
2442 {
2443 bkin_enable_mask = 0U;
2444 bkin_polarity_mask = 0U;
2445 bkin_enable_bitpos = 0U;
2446 bkin_polarity_bitpos = 0U;
2447 break;
2448 }
2449 }
2450
2451 switch (BreakInput)
2452 {
2453 case TIM_BREAKINPUT_BRK:
2454 {
2455 /* Get the TIMx_AF1 register value */
2456 tmporx = htim->Instance->AF1;
2457
2458 /* Enable the break input */
2459 tmporx &= ~bkin_enable_mask;
2460 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2461
2462 /* Set the break input polarity */
2463 tmporx &= ~bkin_polarity_mask;
2464 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2465
2466 /* Set TIMx_AF1 */
2467 htim->Instance->AF1 = tmporx;
2468 break;
2469 }
2470 case TIM_BREAKINPUT_BRK2:
2471 {
2472 /* Get the TIMx_AF2 register value */
2473 tmporx = htim->Instance->AF2;
2474
2475 /* Enable the break input */
2476 tmporx &= ~bkin_enable_mask;
2477 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2478
2479 /* Set the break input polarity */
2480 tmporx &= ~bkin_polarity_mask;
2481 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2482
2483 /* Set TIMx_AF2 */
2484 htim->Instance->AF2 = tmporx;
2485 break;
2486 }
2487 default:
2488 status = HAL_ERROR;
2489 break;
2490 }
2491
2492 __HAL_UNLOCK(htim);
2493
2494 return status;
2495 }
2496
2497 /**
2498 * @brief Configures the TIMx Remapping input capabilities.
2499 * @param htim TIM handle.
2500 * @param Remap specifies the TIM remapping source.
2501 * For TIM1, the parameter can take one of the following values:
2502 * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
2503 * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output
2504 * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output
2505 * @arg TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3 output
2506 * @arg TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4 output
2507 * @arg TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5 output (*)
2508 * @arg TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6 output (*)
2509 * @arg TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7 output (*)
2510 * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
2511 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
2512 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
2513 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 (*)
2514 * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 (*)
2515 * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 (*)
2516 *
2517 * For TIM2, the parameter can take one of the following values:
2518 * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
2519 * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output
2520 * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output
2521 * @arg TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3 output
2522 * @arg TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4 output
2523 * @arg TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5 output (*)
2524 * @arg TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6 output (*)
2525 * @arg TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7 output (*)
2526 * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
2527 * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin
2528 * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*)
2529 * @arg TIM_TIM2_ETR_LSE
2530 *
2531 * For TIM3, the parameter can take one of the following values:
2532 * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
2533 * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output
2534 * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output
2535 * @arg TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3 output
2536 * @arg TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4 output
2537 * @arg TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5 output (*)
2538 * @arg TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6 output (*)
2539 * @arg TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7 output (*)
2540 * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
2541 * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin
2542 * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1
2543 * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2
2544 * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3
2545 *
2546 * For TIM4, the parameter can take one of the following values:
2547 * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
2548 * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output
2549 * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output
2550 * @arg TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3 output
2551 * @arg TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4 output
2552 * @arg TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5 output (*)
2553 * @arg TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6 output (*)
2554 * @arg TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7 output (*)
2555 * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
2556 * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin (*)
2557 *
2558 * For TIM5, the parameter can take one of the following values: (**)
2559 * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*)
2560 * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*)
2561 * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*)
2562 * @arg TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3 output (*)
2563 * @arg TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4 output (*)
2564 * @arg TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5 output (*)
2565 * @arg TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6 output (*)
2566 * @arg TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7 output (*)
2567 * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin (*)
2568 * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin (*)
2569 *
2570 * For TIM8, the parameter can take one of the following values:
2571 * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
2572 * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output
2573 * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output
2574 * @arg TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3 output
2575 * @arg TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4 output
2576 * @arg TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5 output (*)
2577 * @arg TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6 output (*)
2578 * @arg TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7 output (*)
2579 * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1
2580 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2
2581 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3
2582 * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*)
2583 * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*)
2584 * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*)
2585 *
2586 * For TIM20, the parameter can take one of the following values: (**)
2587 * @arg TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO
2588 * @arg TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1 output (*)
2589 * @arg TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2 output (*)
2590 * @arg TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3 output (*)
2591 * @arg TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4 output (*)
2592 * @arg TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5 output (*)
2593 * @arg TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6 output (*)
2594 * @arg TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7 output (*)
2595 * @arg TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3 AWD1 (*)
2596 * @arg TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3 AWD2 (*)
2597 * @arg TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3 AWD3 (*)
2598 * @arg TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5 AWD1 (*)
2599 * @arg TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5 AWD2 (*)
2600 * @arg TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5 AWD3 (*)
2601 *
2602 * (*) Value not defined in all devices. \n
2603 * (**) Register not available in all devices.
2604 *
2605 * @retval HAL status
2606 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2607 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2608 {
2609 /* Check parameters */
2610 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2611 assert_param(IS_TIM_REMAP(Remap));
2612
2613 __HAL_LOCK(htim);
2614
2615 MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
2616
2617 __HAL_UNLOCK(htim);
2618
2619 return HAL_OK;
2620 }
2621
2622 /**
2623 * @brief Select the timer input source
2624 * @param htim TIM handle.
2625 * @param Channel specifies the TIM Channel
2626 * This parameter can be one of the following values:
2627 * @arg TIM_CHANNEL_1: TI1 input channel
2628 * @arg TIM_CHANNEL_2: TI2 input channel
2629 * @arg TIM_CHANNEL_3: TI3 input channel
2630 * @arg TIM_CHANNEL_4: TI4 input channel
2631 * @param TISelection specifies the timer input source
2632 * For TIM1 this parameter can be one of the following values:
2633 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2634 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2635 * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output
2636 * @arg TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to COMP3 output
2637 * @arg TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to COMP4 output
2638 *
2639 * For TIM2 this parameter can be one of the following values:
2640 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2641 * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
2642 * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output
2643 * @arg TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to COMP3 output
2644 * @arg TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to COMP4 output
2645 * @arg TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to COMP5 output (*)
2646 *
2647 * @arg TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to GPIO
2648 * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
2649 * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output
2650 * @arg TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to COMP3 output
2651 * @arg TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to COMP4 output
2652 * @arg TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to COMP6 output (*)
2653 *
2654 * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO
2655 * @arg TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to COMP4 output
2656 *
2657 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2658 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2659 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
2660 *
2661 * For TIM3 this parameter can be one of the following values:
2662 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2663 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2664 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
2665 * @arg TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to COMP3 output
2666 * @arg TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to COMP4 output
2667 * @arg TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to COMP5 output (*)
2668 * @arg TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to COMP6 output (*)
2669 * @arg TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to COMP7 output (*)
2670 *
2671 * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
2672 * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
2673 * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output
2674 * @arg TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to COMP3 output
2675 * @arg TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to COMP4 output
2676 * @arg TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to COMP5 output (*)
2677 * @arg TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to COMP6 output (*)
2678 * @arg TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to COMP7 output (*)
2679 *
2680 * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO
2681 * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output
2682
2683 * For TIM4 this parameter can be one of the following values:
2684 * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
2685 * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
2686 * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output
2687 * @arg TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to COMP3 output
2688 * @arg TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to COMP4 output
2689 * @arg TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to COMP5 output (*)
2690 * @arg TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to COMP6 output (*)
2691 * @arg TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to COMP7 output (*)
2692 *
2693 * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
2694 * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output
2695 * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output
2696 * @arg TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to COMP3 output
2697 * @arg TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to COMP4 output
2698 * @arg TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to COMP5 output (*)
2699 * @arg TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to COMP6 output (*)
2700 * @arg TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to COMP7 output (*)
2701 *
2702 * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO
2703 * @arg TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to COMP5 output (*)
2704 *
2705 * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO
2706 * @arg TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to COMP6 output (*)
2707 *
2708 * For TIM5 this parameter can be one of the following values: (**)
2709 * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
2710 * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI clock (*)
2711 * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE clock (*)
2712 * @arg TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to RTC Wakeup (*)
2713 * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output (*)
2714 * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*)
2715 * @arg TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to COMP3 output (*)
2716 * @arg TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to COMP4 output (*)
2717 * @arg TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to COMP5 output (*)
2718 * @arg TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to COMP6 output (*)
2719 * @arg TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to COMP7 output (*)
2720 *
2721 * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
2722 * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output
2723 * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output
2724 * @arg TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to COMP3 output
2725 * @arg TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to COMP4 output
2726 * @arg TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to COMP5 output (*)
2727 * @arg TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to COMP6 output (*)
2728 * @arg TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to COMP7 output (*)
2729 *
2730 * For TIM8 this parameter can be one of the following values:
2731 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
2732 * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
2733 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
2734 * @arg TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to COMP3 output
2735 * @arg TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to COMP4 output
2736 *
2737 * For TIM15 this parameter can be one of the following values:
2738 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2739 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE clock
2740 * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output
2741 * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output
2742 * @arg TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to COMP5 output (*)
2743 * @arg TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to COMP7 output (*)
2744 *
2745 * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
2746 * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output
2747 * @arg TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to COMP3 output
2748 * @arg TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to COMP6 output (*)
2749 * @arg TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to COMP7 output (*)
2750 *
2751 * For TIM16 this parameter can be one of the following values:
2752 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2753 * @arg TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to COMP6 output (*)
2754 * @arg TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to MCO output
2755 * @arg TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to HSE div 32
2756 * @arg TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to RTC wakeup
2757 * @arg TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to LSE clock
2758 * @arg TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to LSI clock
2759 *
2760 * For TIM17 this parameter can be one of the following values:
2761 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2762 * @arg TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to COMP5 output (*)
2763 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO output
2764 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
2765 * @arg TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to RTC wakeup
2766 * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE clock
2767 * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI clock
2768
2769 * For TIM20 this parameter can be one of the following values: (**)
2770 * @arg TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to GPIO
2771 * @arg TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to COMP1 output (*)
2772 * @arg TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to COMP2 output (*)
2773 * @arg TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to COMP3 output (*)
2774 * @arg TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to COMP4 output (*)
2775 *
2776 * (*) Value not defined in all devices. \n
2777 * (**) Register not available in all devices.
2778 *
2779 * @retval HAL status
2780 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2781 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2782 {
2783 HAL_StatusTypeDef status = HAL_OK;
2784
2785 /* Check parameters */
2786 assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
2787 assert_param(IS_TIM_TISEL(TISelection));
2788
2789 __HAL_LOCK(htim);
2790
2791 switch (Channel)
2792 {
2793 case TIM_CHANNEL_1:
2794 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2795
2796 /* If required, set OR bit to request HSE/32 clock */
2797 if (IS_TIM_HSE32_INSTANCE(htim->Instance))
2798 {
2799 SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
2800 }
2801 else
2802 {
2803 CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
2804 }
2805 break;
2806 case TIM_CHANNEL_2:
2807 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2808 break;
2809 case TIM_CHANNEL_3:
2810 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
2811 break;
2812 case TIM_CHANNEL_4:
2813 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
2814 break;
2815 default:
2816 status = HAL_ERROR;
2817 break;
2818 }
2819
2820 __HAL_UNLOCK(htim);
2821
2822 return status;
2823 }
2824
2825 /**
2826 * @brief Group channel 5 and channel 1, 2 or 3
2827 * @param htim TIM handle.
2828 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2829 * This parameter can be any combination of the following values:
2830 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2831 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2832 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2833 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2834 * @retval HAL status
2835 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2836 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2837 {
2838 /* Check parameters */
2839 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2840 assert_param(IS_TIM_GROUPCH5(Channels));
2841
2842 /* Process Locked */
2843 __HAL_LOCK(htim);
2844
2845 htim->State = HAL_TIM_STATE_BUSY;
2846
2847 /* Clear GC5Cx bit fields */
2848 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2849
2850 /* Set GC5Cx bit fields */
2851 htim->Instance->CCR5 |= Channels;
2852
2853 /* Change the htim state */
2854 htim->State = HAL_TIM_STATE_READY;
2855
2856 __HAL_UNLOCK(htim);
2857
2858 return HAL_OK;
2859 }
2860
2861 /**
2862 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2863 * @param htim TIM handle.
2864 * @param BreakInput Break input to disarm
2865 * This parameter can be one of the following values:
2866 * @arg TIM_BREAKINPUT_BRK: Timer break input
2867 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2868 * @note The break input can be disarmed only when it is configured in
2869 * bidirectional mode and when when MOE is reset.
2870 * @note Purpose is to be able to have the input voltage back to high-state,
2871 * whatever the time constant on the output .
2872 * @retval HAL status
2873 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2874 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2875 {
2876 HAL_StatusTypeDef status = HAL_OK;
2877 uint32_t tmpbdtr;
2878
2879 /* Check the parameters */
2880 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
2881 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2882
2883 switch (BreakInput)
2884 {
2885 case TIM_BREAKINPUT_BRK:
2886 {
2887 /* Check initial conditions */
2888 tmpbdtr = READ_REG(htim->Instance->BDTR);
2889 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2890 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2891 {
2892 /* Break input BRK is disarmed */
2893 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2894 }
2895 break;
2896 }
2897
2898 case TIM_BREAKINPUT_BRK2:
2899 {
2900 /* Check initial conditions */
2901 tmpbdtr = READ_REG(htim->Instance->BDTR);
2902 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2903 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2904 {
2905 /* Break input BRK is disarmed */
2906 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2907 }
2908 break;
2909 }
2910 default:
2911 status = HAL_ERROR;
2912 break;
2913 }
2914
2915 return status;
2916 }
2917
2918 /**
2919 * @brief Arm the designated break input (when it operates in bidirectional mode).
2920 * @param htim TIM handle.
2921 * @param BreakInput Break input to arm
2922 * This parameter can be one of the following values:
2923 * @arg TIM_BREAKINPUT_BRK: Timer break input
2924 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2925 * @note Arming is possible at anytime, even if fault is present.
2926 * @note Break input is automatically armed as soon as MOE bit is set.
2927 * @retval HAL status
2928 */
HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2929 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2930 {
2931 HAL_StatusTypeDef status = HAL_OK;
2932 uint32_t tickstart;
2933
2934 /* Check the parameters */
2935 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
2936 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2937
2938 switch (BreakInput)
2939 {
2940 case TIM_BREAKINPUT_BRK:
2941 {
2942 /* Check initial conditions */
2943 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2944 {
2945 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2946 /* Init tickstart for timeout management */
2947 tickstart = HAL_GetTick();
2948 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2949 {
2950 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2951 {
2952 /* New check to avoid false timeout detection in case of preemption */
2953 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2954 {
2955 return HAL_TIMEOUT;
2956 }
2957 }
2958 }
2959 }
2960 break;
2961 }
2962
2963 case TIM_BREAKINPUT_BRK2:
2964 {
2965 /* Check initial conditions */
2966 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2967 {
2968 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2969 /* Init tickstart for timeout management */
2970 tickstart = HAL_GetTick();
2971 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2972 {
2973 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2974 {
2975 /* New check to avoid false timeout detection in case of preemption */
2976 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2977 {
2978 return HAL_TIMEOUT;
2979 }
2980 }
2981 }
2982 }
2983 break;
2984 }
2985 default:
2986 status = HAL_ERROR;
2987 break;
2988 }
2989
2990 return status;
2991 }
2992
2993 /**
2994 * @brief Enable dithering
2995 * @param htim TIM handle
2996 * @note Main usage is PWM mode
2997 * @note This function must be called when timer is stopped or disabled (CEN =0)
2998 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2999 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
3000 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
3001 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
3002 * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
3003 * (corresponds to 4094 for the integer part and 15 for the dithered part).
3004 * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
3005 * can be used to calculate period (ARR) and delay (CCRx) value.
3006 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
3007 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
3008 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
3009 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
3010 * @retval HAL status
3011 */
HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef * htim)3012 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
3013 {
3014 /* Check the parameters */
3015 assert_param(IS_TIM_INSTANCE(htim->Instance));
3016
3017 SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
3018 return HAL_OK;
3019 }
3020
3021 /**
3022 * @brief Disable dithering
3023 * @param htim TIM handle
3024 * @note This function must be called when timer is stopped or disabled (CEN =0)
3025 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
3026 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
3027 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
3028 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
3029 * - ARR and CCRx values are limited to 0xFFEF in dithering mode
3030 * (corresponds to 4094 for the integer part and 15 for the dithered part).
3031 * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
3032 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
3033 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
3034 * @retval HAL status
3035 */
HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef * htim)3036 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
3037 {
3038 /* Check the parameters */
3039 assert_param(IS_TIM_INSTANCE(htim->Instance));
3040
3041 CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
3042 return HAL_OK;
3043 }
3044
3045 /**
3046 * @brief Initializes the pulse on compare pulse width and pulse prescaler
3047 * @param htim TIM Output Compare handle
3048 * @param PulseWidthPrescaler Pulse width prescaler
3049 * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
3050 * @param PulseWidth Pulse width
3051 * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
3052 * @retval HAL status
3053 */
HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef * htim,uint32_t PulseWidthPrescaler,uint32_t PulseWidth)3054 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
3055 uint32_t PulseWidthPrescaler,
3056 uint32_t PulseWidth)
3057 {
3058 uint32_t tmpecr;
3059
3060 /* Check the parameters */
3061 assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
3062 assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
3063 assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
3064
3065 /* Process Locked */
3066 __HAL_LOCK(htim);
3067
3068 /* Set the TIM state */
3069 htim->State = HAL_TIM_STATE_BUSY;
3070
3071 /* Get the TIMx ECR register value */
3072 tmpecr = htim->Instance->ECR;
3073 /* Reset the Pulse width prescaler and the Pulse width */
3074 tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
3075 /* Set the Pulse width prescaler and Pulse width*/
3076 tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
3077 tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
3078 /* Write to TIMx ECR */
3079 htim->Instance->ECR = tmpecr;
3080
3081 /* Change the TIM state */
3082 htim->State = HAL_TIM_STATE_READY;
3083
3084 /* Release Lock */
3085 __HAL_UNLOCK(htim);
3086
3087 return HAL_OK;
3088 }
3089
3090 /**
3091 * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
3092 * @param htim TIM handle
3093 * @param Source Source of slave mode selection preload
3094 * This parameter can be one of the following values:
3095 * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
3096 * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
3097 * @retval HAL status
3098 */
HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef * htim,uint32_t Source)3099 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
3100 {
3101 /* Check the parameters */
3102 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3103 assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
3104
3105 MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
3106 return HAL_OK;
3107 }
3108
3109 /**
3110 * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
3111 * @param htim TIM handle
3112 * @retval HAL status
3113 */
HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef * htim)3114 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
3115 {
3116 /* Check the parameters */
3117 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3118
3119 SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
3120 return HAL_OK;
3121 }
3122
3123 /**
3124 * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
3125 * @param htim TIM handle
3126 * @retval HAL status
3127 */
HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef * htim)3128 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
3129 {
3130 /* Check the parameters */
3131 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3132
3133 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
3134 return HAL_OK;
3135 }
3136
3137 /**
3138 * @brief Enable deadtime preload
3139 * @param htim TIM handle
3140 * @retval HAL status
3141 */
HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef * htim)3142 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
3143 {
3144 /* Check the parameters */
3145 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3146
3147 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
3148 return HAL_OK;
3149 }
3150
3151 /**
3152 * @brief Disable deadtime preload
3153 * @param htim TIM handle
3154 * @retval HAL status
3155 */
HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef * htim)3156 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
3157 {
3158 /* Check the parameters */
3159 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3160
3161 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
3162 return HAL_OK;
3163 }
3164
3165 /**
3166 * @brief Configure deadtime
3167 * @param htim TIM handle
3168 * @param Deadtime Deadtime value
3169 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
3170 * @retval HAL status
3171 */
HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef * htim,uint32_t Deadtime)3172 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
3173 {
3174 /* Check the parameters */
3175 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3176 assert_param(IS_TIM_DEADTIME(Deadtime));
3177
3178 MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
3179 return HAL_OK;
3180 }
3181
3182 /**
3183 * @brief Configure asymmetrical deadtime
3184 * @param htim TIM handle
3185 * @param FallingDeadtime Falling edge deadtime value
3186 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
3187 * @retval HAL status
3188 */
HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef * htim,uint32_t FallingDeadtime)3189 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
3190 {
3191 /* Check the parameters */
3192 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3193 assert_param(IS_TIM_DEADTIME(FallingDeadtime));
3194
3195 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
3196 return HAL_OK;
3197 }
3198
3199 /**
3200 * @brief Enable asymmetrical deadtime
3201 * @param htim TIM handle
3202 * @retval HAL status
3203 */
HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3204 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3205 {
3206 /* Check the parameters */
3207 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3208
3209 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3210 return HAL_OK;
3211 }
3212
3213 /**
3214 * @brief Disable asymmetrical deadtime
3215 * @param htim TIM handle
3216 * @retval HAL status
3217 */
HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3218 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3219 {
3220 /* Check the parameters */
3221 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3222
3223 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3224 return HAL_OK;
3225 }
3226
3227 /**
3228 * @brief Configures the encoder index.
3229 * @note warning in case of encoder mode clock plus direction
3230 * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3231 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
3232 * @param htim TIM handle.
3233 * @param sEncoderIndexConfig Encoder index configuration
3234 * @retval HAL status
3235 */
HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef * htim,TIMEx_EncoderIndexConfigTypeDef * sEncoderIndexConfig)3236 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
3237 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
3238 {
3239 /* Check the parameters */
3240 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3241 assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
3242 assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
3243 assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
3244 assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
3245 assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
3246 assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
3247
3248 /* Process Locked */
3249 __HAL_LOCK(htim);
3250
3251 /* Configures the TIMx External Trigger (ETR) which is used as Index input */
3252 TIM_ETR_SetConfig(htim->Instance,
3253 sEncoderIndexConfig->Prescaler,
3254 sEncoderIndexConfig->Polarity,
3255 sEncoderIndexConfig->Filter);
3256
3257 /* Configures the encoder index */
3258 MODIFY_REG(htim->Instance->ECR,
3259 TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3260 (sEncoderIndexConfig->Direction |
3261 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3262 sEncoderIndexConfig->Position |
3263 TIM_ECR_IE));
3264
3265 __HAL_UNLOCK(htim);
3266
3267 return HAL_OK;
3268 }
3269
3270 /**
3271 * @brief Enable encoder index
3272 * @param htim TIM handle
3273 * @retval HAL status
3274 */
HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef * htim)3275 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
3276 {
3277 /* Check the parameters */
3278 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3279
3280 SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
3281 return HAL_OK;
3282 }
3283
3284 /**
3285 * @brief Disable encoder index
3286 * @param htim TIM handle
3287 * @retval HAL status
3288 */
HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef * htim)3289 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
3290 {
3291 /* Check the parameters */
3292 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3293
3294 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
3295 return HAL_OK;
3296 }
3297
3298 /**
3299 * @brief Enable encoder first index
3300 * @param htim TIM handle
3301 * @retval HAL status
3302 */
HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef * htim)3303 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3304 {
3305 /* Check the parameters */
3306 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3307
3308 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3309 return HAL_OK;
3310 }
3311
3312 /**
3313 * @brief Disable encoder first index
3314 * @param htim TIM handle
3315 * @retval HAL status
3316 */
HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef * htim)3317 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3318 {
3319 /* Check the parameters */
3320 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3321
3322 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3323 return HAL_OK;
3324 }
3325
3326 /**
3327 * @}
3328 */
3329
3330 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
3331 * @brief Extended Callbacks functions
3332 *
3333 @verbatim
3334 ==============================================================================
3335 ##### Extended Callbacks functions #####
3336 ==============================================================================
3337 [..]
3338 This section provides Extended TIM callback functions:
3339 (+) Timer Commutation callback
3340 (+) Timer Break callback
3341
3342 @endverbatim
3343 * @{
3344 */
3345
3346 /**
3347 * @brief Hall commutation changed callback in non-blocking mode
3348 * @param htim TIM handle
3349 * @retval None
3350 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)3351 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
3352 {
3353 /* Prevent unused argument(s) compilation warning */
3354 UNUSED(htim);
3355
3356 /* NOTE : This function should not be modified, when the callback is needed,
3357 the HAL_TIMEx_CommutCallback could be implemented in the user file
3358 */
3359 }
3360 /**
3361 * @brief Hall commutation changed half complete callback in non-blocking mode
3362 * @param htim TIM handle
3363 * @retval None
3364 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)3365 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
3366 {
3367 /* Prevent unused argument(s) compilation warning */
3368 UNUSED(htim);
3369
3370 /* NOTE : This function should not be modified, when the callback is needed,
3371 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
3372 */
3373 }
3374
3375 /**
3376 * @brief Hall Break detection callback in non-blocking mode
3377 * @param htim TIM handle
3378 * @retval None
3379 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)3380 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
3381 {
3382 /* Prevent unused argument(s) compilation warning */
3383 UNUSED(htim);
3384
3385 /* NOTE : This function should not be modified, when the callback is needed,
3386 the HAL_TIMEx_BreakCallback could be implemented in the user file
3387 */
3388 }
3389
3390 /**
3391 * @brief Hall Break2 detection callback in non blocking mode
3392 * @param htim: TIM handle
3393 * @retval None
3394 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)3395 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
3396 {
3397 /* Prevent unused argument(s) compilation warning */
3398 UNUSED(htim);
3399
3400 /* NOTE : This function Should not be modified, when the callback is needed,
3401 the HAL_TIMEx_Break2Callback could be implemented in the user file
3402 */
3403 }
3404
3405 /**
3406 * @brief Encoder index callback in non-blocking mode
3407 * @param htim TIM handle
3408 * @retval None
3409 */
HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef * htim)3410 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
3411 {
3412 /* Prevent unused argument(s) compilation warning */
3413 UNUSED(htim);
3414
3415 /* NOTE : This function should not be modified, when the callback is needed,
3416 the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
3417 */
3418 }
3419
3420 /**
3421 * @brief Direction change callback in non-blocking mode
3422 * @param htim TIM handle
3423 * @retval None
3424 */
HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef * htim)3425 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
3426 {
3427 /* Prevent unused argument(s) compilation warning */
3428 UNUSED(htim);
3429
3430 /* NOTE : This function should not be modified, when the callback is needed,
3431 the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
3432 */
3433 }
3434
3435 /**
3436 * @brief Index error callback in non-blocking mode
3437 * @param htim TIM handle
3438 * @retval None
3439 */
HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef * htim)3440 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
3441 {
3442 /* Prevent unused argument(s) compilation warning */
3443 UNUSED(htim);
3444
3445 /* NOTE : This function should not be modified, when the callback is needed,
3446 the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
3447 */
3448 }
3449
3450 /**
3451 * @brief Transition error callback in non-blocking mode
3452 * @param htim TIM handle
3453 * @retval None
3454 */
HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef * htim)3455 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
3456 {
3457 /* Prevent unused argument(s) compilation warning */
3458 UNUSED(htim);
3459
3460 /* NOTE : This function should not be modified, when the callback is needed,
3461 the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
3462 */
3463 }
3464
3465 /**
3466 * @}
3467 */
3468
3469 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
3470 * @brief Extended Peripheral State functions
3471 *
3472 @verbatim
3473 ==============================================================================
3474 ##### Extended Peripheral State functions #####
3475 ==============================================================================
3476 [..]
3477 This subsection permits to get in run-time the status of the peripheral
3478 and the data flow.
3479
3480 @endverbatim
3481 * @{
3482 */
3483
3484 /**
3485 * @brief Return the TIM Hall Sensor interface handle state.
3486 * @param htim TIM Hall Sensor handle
3487 * @retval HAL state
3488 */
HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef * htim)3489 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
3490 {
3491 return htim->State;
3492 }
3493
3494 /**
3495 * @brief Return actual state of the TIM complementary channel.
3496 * @param htim TIM handle
3497 * @param ChannelN TIM Complementary channel
3498 * This parameter can be one of the following values:
3499 * @arg TIM_CHANNEL_1: TIM Channel 1
3500 * @arg TIM_CHANNEL_2: TIM Channel 2
3501 * @arg TIM_CHANNEL_3: TIM Channel 3
3502 * @arg TIM_CHANNEL_4: TIM Channel 4
3503 * @retval TIM Complementary channel state
3504 */
HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef * htim,uint32_t ChannelN)3505 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
3506 {
3507 HAL_TIM_ChannelStateTypeDef channel_state;
3508
3509 /* Check the parameters */
3510 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
3511
3512 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
3513
3514 return channel_state;
3515 }
3516 /**
3517 * @}
3518 */
3519
3520 /**
3521 * @}
3522 */
3523
3524 /* Private functions ---------------------------------------------------------*/
3525 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
3526 * @{
3527 */
3528
3529 /**
3530 * @brief TIM DMA Commutation callback.
3531 * @param hdma pointer to DMA handle.
3532 * @retval None
3533 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)3534 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
3535 {
3536 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3537
3538 /* Change the htim state */
3539 htim->State = HAL_TIM_STATE_READY;
3540
3541 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3542 htim->CommutationCallback(htim);
3543 #else
3544 HAL_TIMEx_CommutCallback(htim);
3545 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3546 }
3547
3548 /**
3549 * @brief TIM DMA Commutation half complete callback.
3550 * @param hdma pointer to DMA handle.
3551 * @retval None
3552 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)3553 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
3554 {
3555 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3556
3557 /* Change the htim state */
3558 htim->State = HAL_TIM_STATE_READY;
3559
3560 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3561 htim->CommutationHalfCpltCallback(htim);
3562 #else
3563 HAL_TIMEx_CommutHalfCpltCallback(htim);
3564 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3565 }
3566
3567
3568 /**
3569 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
3570 * @param hdma pointer to DMA handle.
3571 * @retval None
3572 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)3573 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
3574 {
3575 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3576
3577 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3578 {
3579 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3580
3581 if (hdma->Init.Mode == DMA_NORMAL)
3582 {
3583 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3584 }
3585 }
3586 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3587 {
3588 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3589
3590 if (hdma->Init.Mode == DMA_NORMAL)
3591 {
3592 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3593 }
3594 }
3595 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3596 {
3597 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3598
3599 if (hdma->Init.Mode == DMA_NORMAL)
3600 {
3601 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3602 }
3603 }
3604 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3605 {
3606 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3607
3608 if (hdma->Init.Mode == DMA_NORMAL)
3609 {
3610 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
3611 }
3612 }
3613 else
3614 {
3615 /* nothing to do */
3616 }
3617
3618 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3619 htim->PWM_PulseFinishedCallback(htim);
3620 #else
3621 HAL_TIM_PWM_PulseFinishedCallback(htim);
3622 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3623
3624 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3625 }
3626
3627 /**
3628 * @brief TIM DMA error callback (complementary channel)
3629 * @param hdma pointer to DMA handle.
3630 * @retval None
3631 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)3632 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
3633 {
3634 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3635
3636 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3637 {
3638 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3639 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3640 }
3641 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3642 {
3643 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3644 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3645 }
3646 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3647 {
3648 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3649 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3650 }
3651 else
3652 {
3653 /* nothing to do */
3654 }
3655
3656 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3657 htim->ErrorCallback(htim);
3658 #else
3659 HAL_TIM_ErrorCallback(htim);
3660 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3661
3662 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3663 }
3664
3665 /**
3666 * @brief Enables or disables the TIM Capture Compare Channel xN.
3667 * @param TIMx to select the TIM peripheral
3668 * @param Channel specifies the TIM Channel
3669 * This parameter can be one of the following values:
3670 * @arg TIM_CHANNEL_1: TIM Channel 1
3671 * @arg TIM_CHANNEL_2: TIM Channel 2
3672 * @arg TIM_CHANNEL_3: TIM Channel 3
3673 * @arg TIM_CHANNEL_4: TIM Channel 4
3674 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
3675 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
3676 * @retval None
3677 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)3678 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
3679 {
3680 uint32_t tmp;
3681
3682 tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
3683
3684 /* Reset the CCxNE Bit */
3685 TIMx->CCER &= ~tmp;
3686
3687 /* Set or reset the CCxNE Bit */
3688 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
3689 }
3690 /**
3691 * @}
3692 */
3693
3694 #endif /* HAL_TIM_MODULE_ENABLED */
3695 /**
3696 * @}
3697 */
3698
3699 /**
3700 * @}
3701 */
3702
