1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32H5xx_LL_TIM_H
21 #define __STM32H5xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM12) \
43 || defined (TIM13) \
44 || defined (TIM14) \
45 || defined (TIM15) \
46 || defined (TIM16) \
47 || defined (TIM17)
48
49 /** @defgroup TIM_LL TIM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
56 * @{
57 */
58 static const uint8_t OFFSET_TAB_CCMRx[] =
59 {
60 0x00U, /* 0: TIMx_CH1 */
61 0x00U, /* 1: TIMx_CH1N */
62 0x00U, /* 2: TIMx_CH2 */
63 0x00U, /* 3: TIMx_CH2N */
64 0x04U, /* 4: TIMx_CH3 */
65 0x04U, /* 5: TIMx_CH3N */
66 0x04U, /* 6: TIMx_CH4 */
67 0x04U, /* 7: TIMx_CH4N */
68 0x38U, /* 8: TIMx_CH5 */
69 0x38U /* 9: TIMx_CH6 */
70
71 };
72
73 static const uint8_t SHIFT_TAB_OCxx[] =
74 {
75 0U, /* 0: OC1M, OC1FE, OC1PE */
76 0U, /* 1: - NA */
77 8U, /* 2: OC2M, OC2FE, OC2PE */
78 0U, /* 3: - NA */
79 0U, /* 4: OC3M, OC3FE, OC3PE */
80 0U, /* 5: - NA */
81 8U, /* 6: OC4M, OC4FE, OC4PE */
82 0U, /* 7: - NA */
83 0U, /* 8: OC5M, OC5FE, OC5PE */
84 8U /* 9: OC6M, OC6FE, OC6PE */
85 };
86
87 static const uint8_t SHIFT_TAB_ICxx[] =
88 {
89 0U, /* 0: CC1S, IC1PSC, IC1F */
90 0U, /* 1: - NA */
91 8U, /* 2: CC2S, IC2PSC, IC2F */
92 0U, /* 3: - NA */
93 0U, /* 4: CC3S, IC3PSC, IC3F */
94 0U, /* 5: - NA */
95 8U, /* 6: CC4S, IC4PSC, IC4F */
96 0U, /* 7: - NA */
97 0U, /* 8: - NA */
98 0U /* 9: - NA */
99 };
100
101 static const uint8_t SHIFT_TAB_CCxP[] =
102 {
103 0U, /* 0: CC1P */
104 2U, /* 1: CC1NP */
105 4U, /* 2: CC2P */
106 6U, /* 3: CC2NP */
107 8U, /* 4: CC3P */
108 10U, /* 5: CC3NP */
109 12U, /* 6: CC4P */
110 14U, /* 7: CC4NP */
111 16U, /* 8: CC5P */
112 20U /* 9: CC6P */
113 };
114
115 static const uint8_t SHIFT_TAB_OISx[] =
116 {
117 0U, /* 0: OIS1 */
118 1U, /* 1: OIS1N */
119 2U, /* 2: OIS2 */
120 3U, /* 3: OIS2N */
121 4U, /* 4: OIS3 */
122 5U, /* 5: OIS3N */
123 6U, /* 6: OIS4 */
124 7U, /* 7: OIS4N */
125 8U, /* 8: OIS5 */
126 10U /* 9: OIS6 */
127 };
128 /**
129 * @}
130 */
131
132 /* Private constants ---------------------------------------------------------*/
133 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
134 * @{
135 */
136
137 /* Defines used for the bit position in the register and perform offsets */
138 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
139
140 /* Generic bit definitions for TIMx_AF1 register */
141 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
142 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
143
144
145 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
146 #define DT_DELAY_1 ((uint8_t)0x7F)
147 #define DT_DELAY_2 ((uint8_t)0x3F)
148 #define DT_DELAY_3 ((uint8_t)0x1F)
149 #define DT_DELAY_4 ((uint8_t)0x1F)
150
151 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
152 #define DT_RANGE_1 ((uint8_t)0x00)
153 #define DT_RANGE_2 ((uint8_t)0x80)
154 #define DT_RANGE_3 ((uint8_t)0xC0)
155 #define DT_RANGE_4 ((uint8_t)0xE0)
156
157 /** Legacy definitions for compatibility purpose
158 @cond 0
159 */
160 /**
161 @endcond
162 */
163
164 /**
165 * @}
166 */
167
168 /* Private macros ------------------------------------------------------------*/
169 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
170 * @{
171 */
172 /** @brief Convert channel id into channel index.
173 * @param __CHANNEL__ This parameter can be one of the following values:
174 * @arg @ref LL_TIM_CHANNEL_CH1
175 * @arg @ref LL_TIM_CHANNEL_CH1N
176 * @arg @ref LL_TIM_CHANNEL_CH2
177 * @arg @ref LL_TIM_CHANNEL_CH2N
178 * @arg @ref LL_TIM_CHANNEL_CH3
179 * @arg @ref LL_TIM_CHANNEL_CH3N
180 * @arg @ref LL_TIM_CHANNEL_CH4
181 * @arg @ref LL_TIM_CHANNEL_CH4N
182 * @arg @ref LL_TIM_CHANNEL_CH5
183 * @arg @ref LL_TIM_CHANNEL_CH6
184 * @retval none
185 */
186 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
187 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
189 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
196
197 /** @brief Calculate the deadtime sampling period(in ps).
198 * @param __TIMCLK__ timer input clock frequency (in Hz).
199 * @param __CKD__ This parameter can be one of the following values:
200 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
201 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
203 * @retval none
204 */
205 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
206 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
207 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
208 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
209 /**
210 * @}
211 */
212
213
214 /* Exported types ------------------------------------------------------------*/
215 #if defined(USE_FULL_LL_DRIVER)
216 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
217 * @{
218 */
219
220 /**
221 * @brief TIM Time Base configuration structure definition.
222 */
223 typedef struct
224 {
225 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
226 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
227
228 This feature can be modified afterwards using unitary function
229 @ref LL_TIM_SetPrescaler().*/
230
231 uint32_t CounterMode; /*!< Specifies the counter mode.
232 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_SetCounterMode().*/
236
237 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
238 Auto-Reload Register at the next update event.
239 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
240 Some timer instances may support 32 bits counters. In that case this parameter must
241 be a number between 0x0000 and 0xFFFFFFFF.
242
243 This feature can be modified afterwards using unitary function
244 @ref LL_TIM_SetAutoReload().*/
245
246 uint32_t ClockDivision; /*!< Specifies the clock division.
247 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
248
249 This feature can be modified afterwards using unitary function
250 @ref LL_TIM_SetClockDivision().*/
251
252 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
253 reaches zero, an update event is generated and counting restarts
254 from the RCR value (N).
255 This means in PWM mode that (N+1) corresponds to:
256 - the number of PWM periods in edge-aligned mode
257 - the number of half PWM period in center-aligned mode
258 GP timers: this parameter must be a number between Min_Data = 0x00 and
259 Max_Data = 0xFF.
260 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
261 Max_Data = 0xFFFF.
262
263 This feature can be modified afterwards using unitary function
264 @ref LL_TIM_SetRepetitionCounter().*/
265 } LL_TIM_InitTypeDef;
266
267 /**
268 * @brief TIM Output Compare configuration structure definition.
269 */
270 typedef struct
271 {
272 uint32_t OCMode; /*!< Specifies the output mode.
273 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
274
275 This feature can be modified afterwards using unitary function
276 @ref LL_TIM_OC_SetMode().*/
277
278 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
279 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
280
281 This feature can be modified afterwards using unitary functions
282 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
283
284 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
285 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
286
287 This feature can be modified afterwards using unitary functions
288 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
289
290 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
291 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
292
293 This feature can be modified afterwards using unitary function
294 LL_TIM_OC_SetCompareCHx (x=1..6).*/
295
296 uint32_t OCPolarity; /*!< Specifies the output polarity.
297 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetPolarity().*/
301
302 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
303 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
304
305 This feature can be modified afterwards using unitary function
306 @ref LL_TIM_OC_SetPolarity().*/
307
308
309 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
310 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
311
312 This feature can be modified afterwards using unitary function
313 @ref LL_TIM_OC_SetIdleState().*/
314
315 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
316 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
317
318 This feature can be modified afterwards using unitary function
319 @ref LL_TIM_OC_SetIdleState().*/
320 } LL_TIM_OC_InitTypeDef;
321
322 /**
323 * @brief TIM Input Capture configuration structure definition.
324 */
325
326 typedef struct
327 {
328
329 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
330 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
331
332 This feature can be modified afterwards using unitary function
333 @ref LL_TIM_IC_SetPolarity().*/
334
335 uint32_t ICActiveInput; /*!< Specifies the input.
336 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
337
338 This feature can be modified afterwards using unitary function
339 @ref LL_TIM_IC_SetActiveInput().*/
340
341 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
342 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
343
344 This feature can be modified afterwards using unitary function
345 @ref LL_TIM_IC_SetPrescaler().*/
346
347 uint32_t ICFilter; /*!< Specifies the input capture filter.
348 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_IC_SetFilter().*/
352 } LL_TIM_IC_InitTypeDef;
353
354
355 /**
356 * @brief TIM Encoder interface configuration structure definition.
357 */
358 typedef struct
359 {
360 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
361 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
362
363 This feature can be modified afterwards using unitary function
364 @ref LL_TIM_SetEncoderMode().*/
365
366 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
367 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
368
369 This feature can be modified afterwards using unitary function
370 @ref LL_TIM_IC_SetPolarity().*/
371
372 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
373 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
374
375 This feature can be modified afterwards using unitary function
376 @ref LL_TIM_IC_SetActiveInput().*/
377
378 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
379 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
380
381 This feature can be modified afterwards using unitary function
382 @ref LL_TIM_IC_SetPrescaler().*/
383
384 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
385 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
386
387 This feature can be modified afterwards using unitary function
388 @ref LL_TIM_IC_SetFilter().*/
389
390 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
391 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetPolarity().*/
395
396 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
397 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetActiveInput().*/
401
402 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
403 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
404
405 This feature can be modified afterwards using unitary function
406 @ref LL_TIM_IC_SetPrescaler().*/
407
408 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
409 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
410
411 This feature can be modified afterwards using unitary function
412 @ref LL_TIM_IC_SetFilter().*/
413
414 } LL_TIM_ENCODER_InitTypeDef;
415
416 /**
417 * @brief TIM Hall sensor interface configuration structure definition.
418 */
419 typedef struct
420 {
421
422 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
423 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
424
425 This feature can be modified afterwards using unitary function
426 @ref LL_TIM_IC_SetPolarity().*/
427
428 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
429 Prescaler must be set to get a maximum counter period longer than the
430 time interval between 2 consecutive changes on the Hall inputs.
431 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
432
433 This feature can be modified afterwards using unitary function
434 @ref LL_TIM_IC_SetPrescaler().*/
435
436 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
437 This parameter can be a value of
438 @ref TIM_LL_EC_IC_FILTER.
439
440 This feature can be modified afterwards using unitary function
441 @ref LL_TIM_IC_SetFilter().*/
442
443 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
444 A positive pulse (TRGO event) is generated with a programmable delay every time
445 a change occurs on the Hall inputs.
446 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
447
448 This feature can be modified afterwards using unitary function
449 @ref LL_TIM_OC_SetCompareCH2().*/
450 } LL_TIM_HALLSENSOR_InitTypeDef;
451
452 /**
453 * @brief BDTR (Break and Dead Time) structure definition
454 */
455 typedef struct
456 {
457 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
458 This parameter can be a value of @ref TIM_LL_EC_OSSR
459
460 This feature can be modified afterwards using unitary function
461 @ref LL_TIM_SetOffStates()
462
463 @note This bit-field cannot be modified as long as LOCK level 2 has been
464 programmed. */
465
466 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
467 This parameter can be a value of @ref TIM_LL_EC_OSSI
468
469 This feature can be modified afterwards using unitary function
470 @ref LL_TIM_SetOffStates()
471
472 @note This bit-field cannot be modified as long as LOCK level 2 has been
473 programmed. */
474
475 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
476 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
477
478 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
479 register has been written, their content is frozen until the next reset.*/
480
481 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
482 switching-on of the outputs.
483 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
484
485 This feature can be modified afterwards using unitary function
486 @ref LL_TIM_OC_SetDeadTime()
487
488 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
489 programmed. */
490
491 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
492 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
493
494 This feature can be modified afterwards using unitary functions
495 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
496
497 @note This bit-field can not be modified as long as LOCK level 1 has been
498 programmed. */
499
500 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
501 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
502
503 This feature can be modified afterwards using unitary function
504 @ref LL_TIM_ConfigBRK()
505
506 @note This bit-field can not be modified as long as LOCK level 1 has been
507 programmed. */
508
509 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
510 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
511
512 This feature can be modified afterwards using unitary function
513 @ref LL_TIM_ConfigBRK()
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_ConfigBRK()
523
524 @note Bidirectional break input is only supported by advanced timers instances.
525
526 @note This bit-field can not be modified as long as LOCK level 1 has been
527 programmed. */
528
529 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
530 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
531
532 This feature can be modified afterwards using unitary functions
533 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
534
535 @note This bit-field can not be modified as long as LOCK level 1 has been
536 programmed. */
537
538 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
539 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
540
541 This feature can be modified afterwards using unitary function
542 @ref LL_TIM_ConfigBRK2()
543
544 @note This bit-field can not be modified as long as LOCK level 1 has been
545 programmed. */
546
547 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
548 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
549
550 This feature can be modified afterwards using unitary function
551 @ref LL_TIM_ConfigBRK2()
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
557 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_ConfigBRK2()
561
562 @note Bidirectional break input is only supported by advanced timers instances.
563
564 @note This bit-field can not be modified as long as LOCK level 1 has been
565 programmed. */
566
567 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
568 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
569
570 This feature can be modified afterwards using unitary functions
571 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
572
573 @note This bit-field can not be modified as long as LOCK level 1 has been
574 programmed. */
575 } LL_TIM_BDTR_InitTypeDef;
576
577 /**
578 * @}
579 */
580 #endif /* USE_FULL_LL_DRIVER */
581
582 /* Exported constants --------------------------------------------------------*/
583 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
584 * @{
585 */
586
587 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
588 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
589 * @{
590 */
591 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
592 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
593 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
594 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
595 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
596 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
597 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
598 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
599 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
600 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
601 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
602 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
603 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
604 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
605 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
606 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
607 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
608 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
609 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
610 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
611 /**
612 * @}
613 */
614
615 #if defined(USE_FULL_LL_DRIVER)
616 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
617 * @{
618 */
619 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
620 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
621 /**
622 * @}
623 */
624
625 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
626 * @{
627 */
628 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
629 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
635 * @{
636 */
637 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
638 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
639 /**
640 * @}
641 */
642 #endif /* USE_FULL_LL_DRIVER */
643
644 /** @defgroup TIM_LL_EC_IT IT Defines
645 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
646 * @{
647 */
648 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
649 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
650 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
651 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
652 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
653 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
654 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
655 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
656 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
657 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
658 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
659 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
665 * @{
666 */
667 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
668 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
669 /**
670 * @}
671 */
672
673 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
674 * @{
675 */
676 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
677 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
683 * @{
684 */
685 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
686 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
687 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
688 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
689 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
690 /**
691 * @}
692 */
693
694 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
695 * @{
696 */
697 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
698 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
699 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
705 * @{
706 */
707 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
708 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
714 * @{
715 */
716 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
717 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
718 /**
719 * @}
720 */
721
722 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
723 * @{
724 */
725 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
726 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
732 * @{
733 */
734 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
735 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
736 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
737 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
738 /**
739 * @}
740 */
741
742 /** @defgroup TIM_LL_EC_CHANNEL Channel
743 * @{
744 */
745 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
746 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
747 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
748 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
749 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
750 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
751 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
752 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
753 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
754 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
755 /**
756 * @}
757 */
758
759 #if defined(USE_FULL_LL_DRIVER)
760 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
761 * @{
762 */
763 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
764 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
765 /**
766 * @}
767 */
768 #endif /* USE_FULL_LL_DRIVER */
769
770 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
771 * @{
772 */
773 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
774 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
775 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
776 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
777 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
778 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
779 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
780 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
781 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
782 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
783 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
784 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
785 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
786 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
787 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
788 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
789 /**
790 * @}
791 */
792
793 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
794 * @{
795 */
796 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
797 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
803 * @{
804 */
805 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
806 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
812 * @{
813 */
814 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
815 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
816 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
817 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
823 * @{
824 */
825 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
826 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
827 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
828 /**
829 * @}
830 */
831
832 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
833 * @{
834 */
835 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
836 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
837 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
838 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
844 * @{
845 */
846 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
847 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
848 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
849 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
850 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
851 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
852 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
853 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
854 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
855 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
856 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
857 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
858 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
859 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
860 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
861 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
862 /**
863 * @}
864 */
865
866 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
867 * @{
868 */
869 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
870 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
871 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
872 /**
873 * @}
874 */
875
876 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
877 * @{
878 */
879 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
880 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
881 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
882 /**
883 * @}
884 */
885
886 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
887 * @{
888 */
889 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
890 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
891 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
892 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
893 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
894 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
895 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
896 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
897 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
898 /**
899 * @}
900 */
901
902 /** @defgroup TIM_LL_EC_TRGO Trigger Output
903 * @{
904 */
905 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
906 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
907 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
908 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
909 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
910 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
911 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
912 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
913 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
914 /**
915 * @}
916 */
917
918 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
919 * @{
920 */
921 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
922 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
923 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
924 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
926 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
927 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
928 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
929 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
930 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
931 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
932 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
933 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
934 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
935 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
936 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
937 /**
938 * @}
939 */
940
941 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
942 * @{
943 */
944 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
945 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
946 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
947 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
948 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
949 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
950 the counter are controlled. */
951 /**
952 * @}
953 */
954
955 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
956 * @{
957 */
958 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
959 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
960 /**
961 * @}
962 */
963
964 /** @defgroup TIM_LL_EC_TS Trigger Selection
965 * @{
966 */
967 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
968 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
969 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
970 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
971 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
972 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
973 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
974 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
975 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
976 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
977 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
978 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
979 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
980 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
981 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
982 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
983 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
984 /**
985 * @}
986 */
987
988 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
989 * @{
990 */
991 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
992 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
993 /**
994 * @}
995 */
996
997 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
998 * @{
999 */
1000 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
1001 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
1002 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1003 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1009 * @{
1010 */
1011 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1012 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1013 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1014 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1015 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1016 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1017 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1018 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1019 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1020 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1021 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1022 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1023 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1024 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1025 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1026 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1027 /**
1028 * @}
1029 */
1030
1031 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1032 * @{
1033 */
1034 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1035 #if defined(COMP1)
1036 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1037 #endif /* COMP1*/
1038 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
1039 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC1 analog watchdog 2 */
1040 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1046 * @{
1047 */
1048 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1049 #if defined(COMP1)
1050 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1051 #endif /* COMP1*/
1052 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to LSE */
1053 #if defined(SAI1)
1054 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to SAI1_FSA */
1055 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_2) /*!< ETR input is connected to SAI1_FSB */
1056 #endif /* SAI1 */
1057 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_3) /*!< ETR input is connected to TIM3 ETR */
1058 #if defined(TIM4)
1059 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_3) /*!< ETR input is connected to TIM4 ETR */
1060 #endif /* TIM4 */
1061 #if defined(TIM5)
1062 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to TIM5 ETR */
1063 #endif /* TIM5 */
1064 #if defined(ETH_NS)
1065 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */
1066 #endif /* ETH_NS */
1067 /**
1068 * @}
1069 */
1070
1071 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1072 * @{
1073 */
1074 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1075 #if defined(COMP1)
1076 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1077 #endif /* COMP1*/
1078 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1079 #if defined(TIM4)
1080 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1081 #endif /* TIM4 */
1082 #if defined(TIM5)
1083 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1084 #endif /* TIM5 */
1085 #if defined(ETH_NS)
1086 #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */
1087 #endif /* ETH_NS */
1088 /**
1089 * @}
1090 */
1091
1092 #if defined(TIM4)
1093 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1094 * @{
1095 */
1096 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1097 #define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1098 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1099 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1100 /**
1101 * @}
1102 */
1103 #endif /* TIM4 */
1104
1105 #if defined(TIM5)
1106 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1107 * @{
1108 */
1109 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1110 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to SAI2_FSA */
1111 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to SAI2_FSB */
1112 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1113 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1114 #define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1115 /**
1116 * @}
1117 */
1118 #endif /* TIM5 */
1119
1120 #if defined(TIM8)
1121 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1122 * @{
1123 */
1124 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1125 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1126 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC4 analog watchdog 2 */
1127 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1128 /**
1129 * @}
1130 */
1131 #endif /* TIM8 */
1132
1133 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1134 * @{
1135 */
1136 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1137 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1138 /**
1139 * @}
1140 */
1141
1142 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1143 * @{
1144 */
1145 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1146 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1147 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1148 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1149 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1150 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1151 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1152 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1153 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1154 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1155 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1156 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1157 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1158 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1159 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1160 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1166 * @{
1167 */
1168 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1169 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1175 * @{
1176 */
1177 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1178 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1179 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1180 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1181 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1182 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1183 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1184 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1185 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1186 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1187 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1188 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1189 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1190 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1191 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1192 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1193 /**
1194 * @}
1195 */
1196
1197 /** @defgroup TIM_LL_EC_OSSI OSSI
1198 * @{
1199 */
1200 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1201 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup TIM_LL_EC_OSSR OSSR
1207 * @{
1208 */
1209 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1210 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1216 * @{
1217 */
1218 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1219 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1225 * @{
1226 */
1227 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1228 #if defined(COMP1)
1229 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1230 #endif /* COMP1 */
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1236 * @{
1237 */
1238 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1239 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1245 * @{
1246 */
1247 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1248 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1254 * @{
1255 */
1256 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1257 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1263 * @{
1264 */
1265 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1266 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1267 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1268 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1269 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1270 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1271 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1272 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1273 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1274 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1275 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1276 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1277 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1278 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1279 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1280 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1281 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1282 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1283 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1284 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1285 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1286 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1287 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1288 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1289 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1290 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1296 * @{
1297 */
1298 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1299 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1300 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1301 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1302 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1303 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1304 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1305 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1306 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1307 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1308 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1309 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1310 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1311 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1312 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1313 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1314 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1315 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1316 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1317 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1318 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1319 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1320 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1321 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1322 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1323 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1329 * @{
1330 */
1331 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1332 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1333 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1334 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1335 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1336 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1337 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1338 /**
1339 * @}
1340 */
1341 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1342 * @{
1343 */
1344 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL
1345 #if defined(COMP1)
1346 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
1347 #endif /* COMP1 */
1348 /**
1349 * @}
1350 */
1351
1352 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1353 * @{
1354 */
1355 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1356 #if defined(STM32H503xx)
1357 #define LL_TIM_TIM2_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to LSI */
1358 #define LL_TIM_TIM2_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to LSE */
1359 #define LL_TIM_TIM2_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to RTC */
1360 #define LL_TIM_TIM2_TI1_RMP_TIM3_TI1 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to TIM3 TI1 */
1361 #endif /* STM32H503xx */
1362 #if defined(ETH_NS)
1363 #define LL_TIM_TIM2_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH_ PPS */
1364 #endif /* ETH_NS */
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 External Input Ch2 Remap
1370 * @{
1371 */
1372 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1373 #if defined(STM32H503xx)
1374 #define LL_TIM_TIM2_TI2_RMP_HSI_1024 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to HSI_1024 */
1375 #define LL_TIM_TIM2_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to CSI_128 */
1376 #define LL_TIM_TIM2_TI2_RMP_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */
1377 #define LL_TIM_TIM2_TI2_RMP_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */
1378 #endif /* STM32H503xx */
1379 /**
1380 * @}
1381 */
1382
1383 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1384 * @{
1385 */
1386 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */
1387 #if defined(COMP1)
1388 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI2 is connected to COMP1 */
1389 #endif /* COMP1 */
1390 /**
1391 * @}
1392 */
1393
1394 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1395 * @{
1396 */
1397 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
1398 #if defined(STM32H503xx)
1399 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 */
1400 #define LL_TIM_TIM3_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to MCO1 */
1401 #define LL_TIM_TIM3_TI1_RMP_TIM2_TI1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to TIM2 TI1 */
1402 #define LL_TIM_TIM3_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to HSE 1MHZ */
1403 #endif /* STM32H503xx */
1404 #if defined(ETH_NS)
1405 #define LL_TIM_TIM3_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */
1406 #endif /* ETH_NS */
1407 /**
1408 * @}
1409 */
1410
1411 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
1412 * @{
1413 */
1414 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */
1415 #if defined(STM32H503xx)
1416 #define LL_TIM_TIM3_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */
1417 #define LL_TIM_TIM3_TI2_RMP_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */
1418 #define LL_TIM_TIM3_TI2_RMP_HSI_1024 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM3_TI2 is connected to HSI 1024 */
1419 #endif /* STM32H503xx */
1420 /**
1421 * @}
1422 */
1423
1424 #if defined(TIM12)
1425 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 External Input Ch1 Remap
1426 * @{
1427 */
1428 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */
1429 #define LL_TIM_TIM12_TI1_RMP_HSI_1024 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to HSI 1024 */
1430 #define LL_TIM_TIM12_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */
1431 /**
1432 * @}
1433 */
1434 #endif /* TIM12 */
1435
1436 #if defined(TIM15)
1437 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1438 * @{
1439 */
1440 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1441 #define LL_TIM_TIM15_TI1_RMP_TIM2 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 */
1442 #define LL_TIM_TIM15_TI1_RMP_TIM3 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 */
1443 #define LL_TIM_TIM15_TI1_RMP_TIM4 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 */
1444 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */
1445 #define LL_TIM_TIM15_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to CSI 128*/
1446 #define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */
1447 /**
1448 * @}
1449 */
1450
1451 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
1452 * @{
1453 */
1454 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1455 #define LL_TIM_TIM15_TI2_RMP_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */
1456 #define LL_TIM_TIM15_TI2_RMP_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */
1457 #define LL_TIM_TIM15_TI2_RMP_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */
1458 /**
1459 * @}
1460 */
1461 #endif /* TIM15 */
1462
1463 #if defined(TIM16)
1464 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1465 * @{
1466 */
1467 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */
1468 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */
1469 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */
1470 #define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */
1471 /**
1472 * @}
1473 */
1474 #endif /* TIM16 */
1475
1476 #if defined(TIM17)
1477 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1478 * @{
1479 */
1480 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
1481 #define LL_TIM_TIM17_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to HSE 1MHZ */
1482 #define LL_TIM_TIM17_TI1_RMP_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */
1483 #endif /* TIM17 */
1484
1485 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1486 * @{
1487 */
1488 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1489 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1490 /**
1491 * @}
1492 */
1493
1494 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1495 * @{
1496 */
1497 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1498 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1499 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1500 /**
1501 * @}
1502 */
1503
1504 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1505 * @{
1506 */
1507 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1508 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1509 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1510 /**
1511 * @}
1512 */
1513
1514 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1515 * @{
1516 */
1517 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1518 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1519 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1520 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1521 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1522 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1523 /**
1524 * @}
1525 */
1526
1527 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1528 * @{
1529 */
1530 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1531 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1532 /**
1533 * @}
1534 */
1535 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1536 * @{
1537 */
1538 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1539 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1540 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1541 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1542 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1543 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1544 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1545 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1546 /**
1547 * @}
1548 */
1549
1550 /** Legacy definitions for compatibility purpose
1551 @cond 0
1552 */
1553 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1554 /**
1555 @endcond
1556 */
1557 /**
1558 * @}
1559 */
1560
1561 /* Exported macro ------------------------------------------------------------*/
1562 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1563 * @{
1564 */
1565
1566 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1567 * @{
1568 */
1569 /**
1570 * @brief Write a value in TIM register.
1571 * @param __INSTANCE__ TIM Instance
1572 * @param __REG__ Register to be written
1573 * @param __VALUE__ Value to be written in the register
1574 * @retval None
1575 */
1576 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1577
1578 /**
1579 * @brief Read a value in TIM register.
1580 * @param __INSTANCE__ TIM Instance
1581 * @param __REG__ Register to be read
1582 * @retval Register value
1583 */
1584 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1585 /**
1586 * @}
1587 */
1588
1589 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1590 * @{
1591 */
1592
1593 /**
1594 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1595 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1596 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1597 * to TIMx_CNT register bit 31)
1598 * @param __CNT__ Counter value
1599 * @retval UIF status bit
1600 */
1601 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1602 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1603
1604 /**
1605 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1606 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1607 * @param __TIMCLK__ timer input clock frequency (in Hz)
1608 * @param __CKD__ This parameter can be one of the following values:
1609 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1610 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1611 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1612 * @param __DT__ deadtime duration (in ns)
1613 * @retval DTG[0:7]
1614 */
1615 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1616 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1617 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1618 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1619 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1620 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1621 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1622 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1623 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1624 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1625 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1626 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1627 0U)
1628
1629 /**
1630 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1631 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1632 * @param __TIMCLK__ timer input clock frequency (in Hz)
1633 * @param __CNTCLK__ counter clock frequency (in Hz)
1634 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1635 */
1636 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1637 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1638
1639 /**
1640 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1641 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1642 * @param __TIMCLK__ timer input clock frequency (in Hz)
1643 * @param __PSC__ prescaler
1644 * @param __FREQ__ output signal frequency (in Hz)
1645 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1646 */
1647 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1648 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1649
1650 /**
1651 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1652 * output signal frequency.
1653 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1654 * @param __TIMCLK__ timer input clock frequency (in Hz)
1655 * @param __PSC__ prescaler
1656 * @param __FREQ__ output signal frequency (in Hz)
1657 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1658 */
1659 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1660 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1661 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1662
1663 /**
1664 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1665 * active/inactive delay.
1666 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1667 * @param __TIMCLK__ timer input clock frequency (in Hz)
1668 * @param __PSC__ prescaler
1669 * @param __DELAY__ timer output compare active/inactive delay (in us)
1670 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1671 */
1672 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1673 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1674 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1675
1676 /**
1677 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1678 * output compare active/inactive delay.
1679 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1680 * @param __TIMCLK__ timer input clock frequency (in Hz)
1681 * @param __PSC__ prescaler
1682 * @param __DELAY__ timer output compare active/inactive delay (in us)
1683 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1684 */
1685 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1686 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1687 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1688
1689 /**
1690 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1691 * (when the timer operates in one pulse mode).
1692 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1693 * @param __TIMCLK__ timer input clock frequency (in Hz)
1694 * @param __PSC__ prescaler
1695 * @param __DELAY__ timer output compare active/inactive delay (in us)
1696 * @param __PULSE__ pulse duration (in us)
1697 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1698 */
1699 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1700 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1701 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1702
1703 /**
1704 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1705 * pulse duration (when the timer operates in one pulse mode).
1706 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1707 * @param __TIMCLK__ timer input clock frequency (in Hz)
1708 * @param __PSC__ prescaler
1709 * @param __DELAY__ timer output compare active/inactive delay (in us)
1710 * @param __PULSE__ pulse duration (in us)
1711 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1712 */
1713 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1714 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1715 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1716
1717 /**
1718 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1719 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1720 * @param __ICPSC__ This parameter can be one of the following values:
1721 * @arg @ref LL_TIM_ICPSC_DIV1
1722 * @arg @ref LL_TIM_ICPSC_DIV2
1723 * @arg @ref LL_TIM_ICPSC_DIV4
1724 * @arg @ref LL_TIM_ICPSC_DIV8
1725 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1726 */
1727 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1728 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1729
1730
1731 /**
1732 * @}
1733 */
1734
1735
1736 /**
1737 * @}
1738 */
1739
1740 /* Exported functions --------------------------------------------------------*/
1741 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1742 * @{
1743 */
1744
1745 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1746 * @{
1747 */
1748 /**
1749 * @brief Enable timer counter.
1750 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1751 * @param TIMx Timer instance
1752 * @retval None
1753 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1754 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1755 {
1756 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1757 }
1758
1759 /**
1760 * @brief Disable timer counter.
1761 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1762 * @param TIMx Timer instance
1763 * @retval None
1764 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1765 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1766 {
1767 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1768 }
1769
1770 /**
1771 * @brief Indicates whether the timer counter is enabled.
1772 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1773 * @param TIMx Timer instance
1774 * @retval State of bit (1 or 0).
1775 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1776 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1777 {
1778 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Enable update event generation.
1783 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1784 * @param TIMx Timer instance
1785 * @retval None
1786 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1787 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1788 {
1789 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1790 }
1791
1792 /**
1793 * @brief Disable update event generation.
1794 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1795 * @param TIMx Timer instance
1796 * @retval None
1797 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1798 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1799 {
1800 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1801 }
1802
1803 /**
1804 * @brief Indicates whether update event generation is enabled.
1805 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1806 * @param TIMx Timer instance
1807 * @retval Inverted state of bit (0 or 1).
1808 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1809 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1810 {
1811 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1812 }
1813
1814 /**
1815 * @brief Set update event source
1816 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1817 * generate an update interrupt or DMA request if enabled:
1818 * - Counter overflow/underflow
1819 * - Setting the UG bit
1820 * - Update generation through the slave mode controller
1821 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1822 * overflow/underflow generates an update interrupt or DMA request if enabled.
1823 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1824 * @param TIMx Timer instance
1825 * @param UpdateSource This parameter can be one of the following values:
1826 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1827 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1828 * @retval None
1829 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1830 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1831 {
1832 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1833 }
1834
1835 /**
1836 * @brief Get actual event update source
1837 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1838 * @param TIMx Timer instance
1839 * @retval Returned value can be one of the following values:
1840 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1841 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1842 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1843 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1844 {
1845 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1846 }
1847
1848 /**
1849 * @brief Set one pulse mode (one shot v.s. repetitive).
1850 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1851 * @param TIMx Timer instance
1852 * @param OnePulseMode This parameter can be one of the following values:
1853 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1854 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1855 * @retval None
1856 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1857 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1858 {
1859 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1860 }
1861
1862 /**
1863 * @brief Get actual one pulse mode.
1864 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1865 * @param TIMx Timer instance
1866 * @retval Returned value can be one of the following values:
1867 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1868 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1869 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1870 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1871 {
1872 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1873 }
1874
1875 /**
1876 * @brief Set the timer counter counting mode.
1877 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1878 * check whether or not the counter mode selection feature is supported
1879 * by a timer instance.
1880 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1881 * requires a timer reset to avoid unexpected direction
1882 * due to DIR bit readonly in center aligned mode.
1883 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1884 * CR1 CMS LL_TIM_SetCounterMode
1885 * @param TIMx Timer instance
1886 * @param CounterMode This parameter can be one of the following values:
1887 * @arg @ref LL_TIM_COUNTERMODE_UP
1888 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1889 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1890 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1891 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1892 * @retval None
1893 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1894 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1895 {
1896 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1897 }
1898
1899 /**
1900 * @brief Get actual counter mode.
1901 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1902 * check whether or not the counter mode selection feature is supported
1903 * by a timer instance.
1904 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1905 * CR1 CMS LL_TIM_GetCounterMode
1906 * @param TIMx Timer instance
1907 * @retval Returned value can be one of the following values:
1908 * @arg @ref LL_TIM_COUNTERMODE_UP
1909 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1910 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1911 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1912 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1913 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1914 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1915 {
1916 uint32_t counter_mode;
1917
1918 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1919
1920 if (counter_mode == 0U)
1921 {
1922 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1923 }
1924
1925 return counter_mode;
1926 }
1927
1928 /**
1929 * @brief Enable auto-reload (ARR) preload.
1930 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1931 * @param TIMx Timer instance
1932 * @retval None
1933 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1934 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1935 {
1936 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1937 }
1938
1939 /**
1940 * @brief Disable auto-reload (ARR) preload.
1941 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1942 * @param TIMx Timer instance
1943 * @retval None
1944 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1945 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1946 {
1947 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1948 }
1949
1950 /**
1951 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1952 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1953 * @param TIMx Timer instance
1954 * @retval State of bit (1 or 0).
1955 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1956 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1957 {
1958 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1959 }
1960
1961 /**
1962 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1963 * (when supported) and the digital filters.
1964 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1965 * whether or not the clock division feature is supported by the timer
1966 * instance.
1967 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1968 * @param TIMx Timer instance
1969 * @param ClockDivision This parameter can be one of the following values:
1970 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1971 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1972 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1973 * @retval None
1974 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1975 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1976 {
1977 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1978 }
1979
1980 /**
1981 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1982 * generators (when supported) and the digital filters.
1983 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1984 * whether or not the clock division feature is supported by the timer
1985 * instance.
1986 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1987 * @param TIMx Timer instance
1988 * @retval Returned value can be one of the following values:
1989 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1990 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1991 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1992 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1993 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1994 {
1995 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1996 }
1997
1998 /**
1999 * @brief Set the counter value.
2000 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2001 * whether or not a timer instance supports a 32 bits counter.
2002 * @note If dithering is activated, pay attention to the Counter value interpretation
2003 * @rmtoll CNT CNT LL_TIM_SetCounter
2004 * @param TIMx Timer instance
2005 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2006 * @retval None
2007 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2008 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2009 {
2010 WRITE_REG(TIMx->CNT, Counter);
2011 }
2012
2013 /**
2014 * @brief Get the counter value.
2015 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2016 * whether or not a timer instance supports a 32 bits counter.
2017 * @note If dithering is activated, pay attention to the Counter value interpretation
2018 * @rmtoll CNT CNT LL_TIM_GetCounter
2019 * @param TIMx Timer instance
2020 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2021 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)2022 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
2023 {
2024 return (uint32_t)(READ_REG(TIMx->CNT));
2025 }
2026
2027 /**
2028 * @brief Get the current direction of the counter
2029 * @rmtoll CR1 DIR LL_TIM_GetDirection
2030 * @param TIMx Timer instance
2031 * @retval Returned value can be one of the following values:
2032 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2033 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2034 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)2035 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
2036 {
2037 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2038 }
2039
2040 /**
2041 * @brief Set the prescaler value.
2042 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2043 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2044 * prescaler ratio is taken into account at the next update event.
2045 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2046 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2047 * @param TIMx Timer instance
2048 * @param Prescaler between Min_Data=0 and Max_Data=65535
2049 * @retval None
2050 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2051 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2052 {
2053 WRITE_REG(TIMx->PSC, Prescaler);
2054 }
2055
2056 /**
2057 * @brief Get the prescaler value.
2058 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2059 * @param TIMx Timer instance
2060 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2061 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)2062 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
2063 {
2064 return (uint32_t)(READ_REG(TIMx->PSC));
2065 }
2066
2067 /**
2068 * @brief Set the auto-reload value.
2069 * @note The counter is blocked while the auto-reload value is null.
2070 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2071 * whether or not a timer instance supports a 32 bits counter.
2072 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2073 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2074 * parameter.
2075 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2076 * @param TIMx Timer instance
2077 * @param AutoReload between Min_Data=0 and Max_Data=65535
2078 * @retval None
2079 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2080 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2081 {
2082 WRITE_REG(TIMx->ARR, AutoReload);
2083 }
2084
2085 /**
2086 * @brief Get the auto-reload value.
2087 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2088 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2089 * whether or not a timer instance supports a 32 bits counter.
2090 * @note If dithering is activated, pay attention to the returned value interpretation
2091 * @param TIMx Timer instance
2092 * @retval Auto-reload value
2093 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2094 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2095 {
2096 return (uint32_t)(READ_REG(TIMx->ARR));
2097 }
2098
2099 /**
2100 * @brief Set the repetition counter value.
2101 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2102 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2103 * whether or not a timer instance supports a repetition counter.
2104 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2105 * @param TIMx Timer instance
2106 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2107 * @retval None
2108 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2109 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2110 {
2111 WRITE_REG(TIMx->RCR, RepetitionCounter);
2112 }
2113
2114 /**
2115 * @brief Get the repetition counter value.
2116 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2117 * whether or not a timer instance supports a repetition counter.
2118 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2119 * @param TIMx Timer instance
2120 * @retval Repetition counter value
2121 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2122 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2123 {
2124 return (uint32_t)(READ_REG(TIMx->RCR));
2125 }
2126
2127 /**
2128 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2129 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2130 * in an atomic way.
2131 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2132 * @param TIMx Timer instance
2133 * @retval None
2134 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2135 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2136 {
2137 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2138 }
2139
2140 /**
2141 * @brief Disable update interrupt flag (UIF) remapping.
2142 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2143 * @param TIMx Timer instance
2144 * @retval None
2145 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2146 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2147 {
2148 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2149 }
2150
2151 /**
2152 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2153 * @param Counter Counter value
2154 * @retval State of bit (1 or 0).
2155 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2156 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2157 {
2158 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2159 }
2160
2161 /**
2162 * @brief Enable dithering.
2163 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2164 * a timer instance provides dithering.
2165 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2166 * @param TIMx Timer instance
2167 * @retval None
2168 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2169 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2170 {
2171 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2172 }
2173
2174 /**
2175 * @brief Disable dithering.
2176 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2177 * a timer instance provides dithering.
2178 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2179 * @param TIMx Timer instance
2180 * @retval None
2181 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2182 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2183 {
2184 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2185 }
2186
2187 /**
2188 * @brief Indicates whether dithering is activated.
2189 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2190 * a timer instance provides dithering.
2191 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2192 * @param TIMx Timer instance
2193 * @retval State of bit (1 or 0).
2194 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2195 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2196 {
2197 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2198 }
2199
2200 /**
2201 * @}
2202 */
2203
2204 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2205 * @{
2206 */
2207 /**
2208 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2209 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2210 * they are updated only when a commutation event (COM) occurs.
2211 * @note Only on channels that have a complementary output.
2212 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2213 * whether or not a timer instance is able to generate a commutation event.
2214 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2215 * @param TIMx Timer instance
2216 * @retval None
2217 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2218 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2219 {
2220 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2221 }
2222
2223 /**
2224 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2225 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2226 * whether or not a timer instance is able to generate a commutation event.
2227 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2228 * @param TIMx Timer instance
2229 * @retval None
2230 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2231 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2232 {
2233 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2234 }
2235
2236 /**
2237 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2238 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2239 * whether or not a timer instance is able to generate a commutation event.
2240 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2241 * @param TIMx Timer instance
2242 * @param CCUpdateSource This parameter can be one of the following values:
2243 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2244 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2245 * @retval None
2246 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2247 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2248 {
2249 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2250 }
2251
2252 /**
2253 * @brief Set the trigger of the capture/compare DMA request.
2254 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2255 * @param TIMx Timer instance
2256 * @param DMAReqTrigger This parameter can be one of the following values:
2257 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2258 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2259 * @retval None
2260 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2261 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2262 {
2263 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2264 }
2265
2266 /**
2267 * @brief Get actual trigger of the capture/compare DMA request.
2268 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2269 * @param TIMx Timer instance
2270 * @retval Returned value can be one of the following values:
2271 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2272 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2273 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2274 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2275 {
2276 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2277 }
2278
2279 /**
2280 * @brief Set the lock level to freeze the
2281 * configuration of several capture/compare parameters.
2282 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2283 * the lock mechanism is supported by a timer instance.
2284 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2285 * @param TIMx Timer instance
2286 * @param LockLevel This parameter can be one of the following values:
2287 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2288 * @arg @ref LL_TIM_LOCKLEVEL_1
2289 * @arg @ref LL_TIM_LOCKLEVEL_2
2290 * @arg @ref LL_TIM_LOCKLEVEL_3
2291 * @retval None
2292 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2293 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2294 {
2295 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2296 }
2297
2298 /**
2299 * @brief Enable capture/compare channels.
2300 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2301 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2302 * CCER CC2E LL_TIM_CC_EnableChannel\n
2303 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2304 * CCER CC3E LL_TIM_CC_EnableChannel\n
2305 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2306 * CCER CC4E LL_TIM_CC_EnableChannel\n
2307 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2308 * CCER CC5E LL_TIM_CC_EnableChannel\n
2309 * CCER CC6E LL_TIM_CC_EnableChannel
2310 * @param TIMx Timer instance
2311 * @param Channels This parameter can be a combination of the following values:
2312 * @arg @ref LL_TIM_CHANNEL_CH1
2313 * @arg @ref LL_TIM_CHANNEL_CH1N
2314 * @arg @ref LL_TIM_CHANNEL_CH2
2315 * @arg @ref LL_TIM_CHANNEL_CH2N
2316 * @arg @ref LL_TIM_CHANNEL_CH3
2317 * @arg @ref LL_TIM_CHANNEL_CH3N
2318 * @arg @ref LL_TIM_CHANNEL_CH4
2319 * @arg @ref LL_TIM_CHANNEL_CH4N
2320 * @arg @ref LL_TIM_CHANNEL_CH5
2321 * @arg @ref LL_TIM_CHANNEL_CH6
2322 * @retval None
2323 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2324 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2325 {
2326 SET_BIT(TIMx->CCER, Channels);
2327 }
2328
2329 /**
2330 * @brief Disable capture/compare channels.
2331 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2332 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2333 * CCER CC2E LL_TIM_CC_DisableChannel\n
2334 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2335 * CCER CC3E LL_TIM_CC_DisableChannel\n
2336 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2337 * CCER CC4E LL_TIM_CC_DisableChannel\n
2338 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2339 * CCER CC5E LL_TIM_CC_DisableChannel\n
2340 * CCER CC6E LL_TIM_CC_DisableChannel
2341 * @param TIMx Timer instance
2342 * @param Channels This parameter can be a combination of the following values:
2343 * @arg @ref LL_TIM_CHANNEL_CH1
2344 * @arg @ref LL_TIM_CHANNEL_CH1N
2345 * @arg @ref LL_TIM_CHANNEL_CH2
2346 * @arg @ref LL_TIM_CHANNEL_CH2N
2347 * @arg @ref LL_TIM_CHANNEL_CH3
2348 * @arg @ref LL_TIM_CHANNEL_CH3N
2349 * @arg @ref LL_TIM_CHANNEL_CH4
2350 * @arg @ref LL_TIM_CHANNEL_CH4N
2351 * @arg @ref LL_TIM_CHANNEL_CH5
2352 * @arg @ref LL_TIM_CHANNEL_CH6
2353 * @retval None
2354 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2355 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2356 {
2357 CLEAR_BIT(TIMx->CCER, Channels);
2358 }
2359
2360 /**
2361 * @brief Indicate whether channel(s) is(are) enabled.
2362 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2363 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2364 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2365 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2366 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2367 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2368 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2369 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2370 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2371 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2372 * @param TIMx Timer instance
2373 * @param Channels This parameter can be a combination of the following values:
2374 * @arg @ref LL_TIM_CHANNEL_CH1
2375 * @arg @ref LL_TIM_CHANNEL_CH1N
2376 * @arg @ref LL_TIM_CHANNEL_CH2
2377 * @arg @ref LL_TIM_CHANNEL_CH2N
2378 * @arg @ref LL_TIM_CHANNEL_CH3
2379 * @arg @ref LL_TIM_CHANNEL_CH3N
2380 * @arg @ref LL_TIM_CHANNEL_CH4
2381 * @arg @ref LL_TIM_CHANNEL_CH4N
2382 * @arg @ref LL_TIM_CHANNEL_CH5
2383 * @arg @ref LL_TIM_CHANNEL_CH6
2384 * @retval State of bit (1 or 0).
2385 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)2386 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2387 {
2388 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2389 }
2390
2391 /**
2392 * @}
2393 */
2394
2395 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2396 * @{
2397 */
2398 /**
2399 * @brief Configure an output channel.
2400 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2401 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2402 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2403 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2404 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2405 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2406 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2407 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2408 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2409 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2410 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2411 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2412 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2413 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2414 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2415 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2416 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2417 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2418 * @param TIMx Timer instance
2419 * @param Channel This parameter can be one of the following values:
2420 * @arg @ref LL_TIM_CHANNEL_CH1
2421 * @arg @ref LL_TIM_CHANNEL_CH2
2422 * @arg @ref LL_TIM_CHANNEL_CH3
2423 * @arg @ref LL_TIM_CHANNEL_CH4
2424 * @arg @ref LL_TIM_CHANNEL_CH5
2425 * @arg @ref LL_TIM_CHANNEL_CH6
2426 * @param Configuration This parameter must be a combination of all the following values:
2427 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2428 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2429 * @retval None
2430 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2431 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2432 {
2433 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2434 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2435 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2436 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2437 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2438 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2439 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2440 }
2441
2442 /**
2443 * @brief Define the behavior of the output reference signal OCxREF from which
2444 * OCx and OCxN (when relevant) are derived.
2445 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2446 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2447 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2448 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2449 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2450 * CCMR3 OC6M LL_TIM_OC_SetMode
2451 * @param TIMx Timer instance
2452 * @param Channel This parameter can be one of the following values:
2453 * @arg @ref LL_TIM_CHANNEL_CH1
2454 * @arg @ref LL_TIM_CHANNEL_CH2
2455 * @arg @ref LL_TIM_CHANNEL_CH3
2456 * @arg @ref LL_TIM_CHANNEL_CH4
2457 * @arg @ref LL_TIM_CHANNEL_CH5
2458 * @arg @ref LL_TIM_CHANNEL_CH6
2459 * @param Mode This parameter can be one of the following values:
2460 * @arg @ref LL_TIM_OCMODE_FROZEN
2461 * @arg @ref LL_TIM_OCMODE_ACTIVE
2462 * @arg @ref LL_TIM_OCMODE_INACTIVE
2463 * @arg @ref LL_TIM_OCMODE_TOGGLE
2464 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2465 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2466 * @arg @ref LL_TIM_OCMODE_PWM1
2467 * @arg @ref LL_TIM_OCMODE_PWM2
2468 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2469 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2470 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2471 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2472 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2473 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2474 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2475 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2476 * @retval None
2477 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2478 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2479 {
2480 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2481 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2482 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2483 }
2484
2485 /**
2486 * @brief Get the output compare mode of an output channel.
2487 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2488 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2489 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2490 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2491 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2492 * CCMR3 OC6M LL_TIM_OC_GetMode
2493 * @param TIMx Timer instance
2494 * @param Channel This parameter can be one of the following values:
2495 * @arg @ref LL_TIM_CHANNEL_CH1
2496 * @arg @ref LL_TIM_CHANNEL_CH2
2497 * @arg @ref LL_TIM_CHANNEL_CH3
2498 * @arg @ref LL_TIM_CHANNEL_CH4
2499 * @arg @ref LL_TIM_CHANNEL_CH5
2500 * @arg @ref LL_TIM_CHANNEL_CH6
2501 * @retval Returned value can be one of the following values:
2502 * @arg @ref LL_TIM_OCMODE_FROZEN
2503 * @arg @ref LL_TIM_OCMODE_ACTIVE
2504 * @arg @ref LL_TIM_OCMODE_INACTIVE
2505 * @arg @ref LL_TIM_OCMODE_TOGGLE
2506 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2507 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2508 * @arg @ref LL_TIM_OCMODE_PWM1
2509 * @arg @ref LL_TIM_OCMODE_PWM2
2510 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2511 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2512 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2513 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2514 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2515 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2516 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2517 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2518 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2519 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2520 {
2521 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2522 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2523 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2524 }
2525
2526 /**
2527 * @brief Set the polarity of an output channel.
2528 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2529 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2530 * CCER CC2P LL_TIM_OC_SetPolarity\n
2531 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2532 * CCER CC3P LL_TIM_OC_SetPolarity\n
2533 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2534 * CCER CC4P LL_TIM_OC_SetPolarity\n
2535 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2536 * CCER CC5P LL_TIM_OC_SetPolarity\n
2537 * CCER CC6P LL_TIM_OC_SetPolarity
2538 * @param TIMx Timer instance
2539 * @param Channel This parameter can be one of the following values:
2540 * @arg @ref LL_TIM_CHANNEL_CH1
2541 * @arg @ref LL_TIM_CHANNEL_CH1N
2542 * @arg @ref LL_TIM_CHANNEL_CH2
2543 * @arg @ref LL_TIM_CHANNEL_CH2N
2544 * @arg @ref LL_TIM_CHANNEL_CH3
2545 * @arg @ref LL_TIM_CHANNEL_CH3N
2546 * @arg @ref LL_TIM_CHANNEL_CH4
2547 * @arg @ref LL_TIM_CHANNEL_CH4N
2548 * @arg @ref LL_TIM_CHANNEL_CH5
2549 * @arg @ref LL_TIM_CHANNEL_CH6
2550 * @param Polarity This parameter can be one of the following values:
2551 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2552 * @arg @ref LL_TIM_OCPOLARITY_LOW
2553 * @retval None
2554 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2555 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2556 {
2557 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2558 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2559 }
2560
2561 /**
2562 * @brief Get the polarity of an output channel.
2563 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2564 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2565 * CCER CC2P LL_TIM_OC_GetPolarity\n
2566 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2567 * CCER CC3P LL_TIM_OC_GetPolarity\n
2568 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2569 * CCER CC4P LL_TIM_OC_GetPolarity\n
2570 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2571 * CCER CC5P LL_TIM_OC_GetPolarity\n
2572 * CCER CC6P LL_TIM_OC_GetPolarity
2573 * @param TIMx Timer instance
2574 * @param Channel This parameter can be one of the following values:
2575 * @arg @ref LL_TIM_CHANNEL_CH1
2576 * @arg @ref LL_TIM_CHANNEL_CH1N
2577 * @arg @ref LL_TIM_CHANNEL_CH2
2578 * @arg @ref LL_TIM_CHANNEL_CH2N
2579 * @arg @ref LL_TIM_CHANNEL_CH3
2580 * @arg @ref LL_TIM_CHANNEL_CH3N
2581 * @arg @ref LL_TIM_CHANNEL_CH4
2582 * @arg @ref LL_TIM_CHANNEL_CH4N
2583 * @arg @ref LL_TIM_CHANNEL_CH5
2584 * @arg @ref LL_TIM_CHANNEL_CH6
2585 * @retval Returned value can be one of the following values:
2586 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2587 * @arg @ref LL_TIM_OCPOLARITY_LOW
2588 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2589 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2590 {
2591 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2592 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2593 }
2594
2595 /**
2596 * @brief Set the IDLE state of an output channel
2597 * @note This function is significant only for the timer instances
2598 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2599 * can be used to check whether or not a timer instance provides
2600 * a break input.
2601 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2602 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2603 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2604 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2605 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2606 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2607 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2608 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2609 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2610 * CR2 OIS6 LL_TIM_OC_SetIdleState
2611 * @param TIMx Timer instance
2612 * @param Channel This parameter can be one of the following values:
2613 * @arg @ref LL_TIM_CHANNEL_CH1
2614 * @arg @ref LL_TIM_CHANNEL_CH1N
2615 * @arg @ref LL_TIM_CHANNEL_CH2
2616 * @arg @ref LL_TIM_CHANNEL_CH2N
2617 * @arg @ref LL_TIM_CHANNEL_CH3
2618 * @arg @ref LL_TIM_CHANNEL_CH3N
2619 * @arg @ref LL_TIM_CHANNEL_CH4
2620 * @arg @ref LL_TIM_CHANNEL_CH4N
2621 * @arg @ref LL_TIM_CHANNEL_CH5
2622 * @arg @ref LL_TIM_CHANNEL_CH6
2623 * @param IdleState This parameter can be one of the following values:
2624 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2625 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2626 * @retval None
2627 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2628 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2629 {
2630 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2631 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2632 }
2633
2634 /**
2635 * @brief Get the IDLE state of an output channel
2636 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2637 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2638 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2639 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2640 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2641 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2642 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2643 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2644 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2645 * CR2 OIS6 LL_TIM_OC_GetIdleState
2646 * @param TIMx Timer instance
2647 * @param Channel This parameter can be one of the following values:
2648 * @arg @ref LL_TIM_CHANNEL_CH1
2649 * @arg @ref LL_TIM_CHANNEL_CH1N
2650 * @arg @ref LL_TIM_CHANNEL_CH2
2651 * @arg @ref LL_TIM_CHANNEL_CH2N
2652 * @arg @ref LL_TIM_CHANNEL_CH3
2653 * @arg @ref LL_TIM_CHANNEL_CH3N
2654 * @arg @ref LL_TIM_CHANNEL_CH4
2655 * @arg @ref LL_TIM_CHANNEL_CH4N
2656 * @arg @ref LL_TIM_CHANNEL_CH5
2657 * @arg @ref LL_TIM_CHANNEL_CH6
2658 * @retval Returned value can be one of the following values:
2659 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2660 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2661 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2662 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2663 {
2664 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2665 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2666 }
2667
2668 /**
2669 * @brief Enable fast mode for the output channel.
2670 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2671 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2672 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2673 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2674 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2675 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2676 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2677 * @param TIMx Timer instance
2678 * @param Channel This parameter can be one of the following values:
2679 * @arg @ref LL_TIM_CHANNEL_CH1
2680 * @arg @ref LL_TIM_CHANNEL_CH2
2681 * @arg @ref LL_TIM_CHANNEL_CH3
2682 * @arg @ref LL_TIM_CHANNEL_CH4
2683 * @arg @ref LL_TIM_CHANNEL_CH5
2684 * @arg @ref LL_TIM_CHANNEL_CH6
2685 * @retval None
2686 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2687 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2688 {
2689 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2690 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2691 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2692
2693 }
2694
2695 /**
2696 * @brief Disable fast mode for the output channel.
2697 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2698 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2699 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2700 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2701 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2702 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2703 * @param TIMx Timer instance
2704 * @param Channel This parameter can be one of the following values:
2705 * @arg @ref LL_TIM_CHANNEL_CH1
2706 * @arg @ref LL_TIM_CHANNEL_CH2
2707 * @arg @ref LL_TIM_CHANNEL_CH3
2708 * @arg @ref LL_TIM_CHANNEL_CH4
2709 * @arg @ref LL_TIM_CHANNEL_CH5
2710 * @arg @ref LL_TIM_CHANNEL_CH6
2711 * @retval None
2712 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2713 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2714 {
2715 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2716 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2717 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2718
2719 }
2720
2721 /**
2722 * @brief Indicates whether fast mode is enabled for the output channel.
2723 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2724 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2725 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2726 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2727 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2728 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2729 * @param TIMx Timer instance
2730 * @param Channel This parameter can be one of the following values:
2731 * @arg @ref LL_TIM_CHANNEL_CH1
2732 * @arg @ref LL_TIM_CHANNEL_CH2
2733 * @arg @ref LL_TIM_CHANNEL_CH3
2734 * @arg @ref LL_TIM_CHANNEL_CH4
2735 * @arg @ref LL_TIM_CHANNEL_CH5
2736 * @arg @ref LL_TIM_CHANNEL_CH6
2737 * @retval State of bit (1 or 0).
2738 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2739 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2740 {
2741 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2742 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2743 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2744 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2745 }
2746
2747 /**
2748 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2749 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2750 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2751 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2752 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2753 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2754 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2755 * @param TIMx Timer instance
2756 * @param Channel This parameter can be one of the following values:
2757 * @arg @ref LL_TIM_CHANNEL_CH1
2758 * @arg @ref LL_TIM_CHANNEL_CH2
2759 * @arg @ref LL_TIM_CHANNEL_CH3
2760 * @arg @ref LL_TIM_CHANNEL_CH4
2761 * @arg @ref LL_TIM_CHANNEL_CH5
2762 * @arg @ref LL_TIM_CHANNEL_CH6
2763 * @retval None
2764 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2765 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2766 {
2767 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2768 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2769 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2770 }
2771
2772 /**
2773 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2774 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2775 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2776 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2777 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2778 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2779 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2780 * @param TIMx Timer instance
2781 * @param Channel This parameter can be one of the following values:
2782 * @arg @ref LL_TIM_CHANNEL_CH1
2783 * @arg @ref LL_TIM_CHANNEL_CH2
2784 * @arg @ref LL_TIM_CHANNEL_CH3
2785 * @arg @ref LL_TIM_CHANNEL_CH4
2786 * @arg @ref LL_TIM_CHANNEL_CH5
2787 * @arg @ref LL_TIM_CHANNEL_CH6
2788 * @retval None
2789 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2790 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2791 {
2792 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2793 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2794 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2795 }
2796
2797 /**
2798 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2799 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2800 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2801 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2802 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2803 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2804 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2805 * @param TIMx Timer instance
2806 * @param Channel This parameter can be one of the following values:
2807 * @arg @ref LL_TIM_CHANNEL_CH1
2808 * @arg @ref LL_TIM_CHANNEL_CH2
2809 * @arg @ref LL_TIM_CHANNEL_CH3
2810 * @arg @ref LL_TIM_CHANNEL_CH4
2811 * @arg @ref LL_TIM_CHANNEL_CH5
2812 * @arg @ref LL_TIM_CHANNEL_CH6
2813 * @retval State of bit (1 or 0).
2814 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2815 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2816 {
2817 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2818 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2819 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2820 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2821 }
2822
2823 /**
2824 * @brief Enable clearing the output channel on an external event.
2825 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2826 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2827 * or not a timer instance can clear the OCxREF signal on an external event.
2828 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2829 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2830 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2831 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2832 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2833 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2834 * @param TIMx Timer instance
2835 * @param Channel This parameter can be one of the following values:
2836 * @arg @ref LL_TIM_CHANNEL_CH1
2837 * @arg @ref LL_TIM_CHANNEL_CH2
2838 * @arg @ref LL_TIM_CHANNEL_CH3
2839 * @arg @ref LL_TIM_CHANNEL_CH4
2840 * @arg @ref LL_TIM_CHANNEL_CH5
2841 * @arg @ref LL_TIM_CHANNEL_CH6
2842 * @retval None
2843 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2844 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2845 {
2846 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2847 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2848 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2849 }
2850
2851 /**
2852 * @brief Disable clearing the output channel on an external event.
2853 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2854 * or not a timer instance can clear the OCxREF signal on an external event.
2855 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2856 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2857 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2858 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2859 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2860 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2861 * @param TIMx Timer instance
2862 * @param Channel This parameter can be one of the following values:
2863 * @arg @ref LL_TIM_CHANNEL_CH1
2864 * @arg @ref LL_TIM_CHANNEL_CH2
2865 * @arg @ref LL_TIM_CHANNEL_CH3
2866 * @arg @ref LL_TIM_CHANNEL_CH4
2867 * @arg @ref LL_TIM_CHANNEL_CH5
2868 * @arg @ref LL_TIM_CHANNEL_CH6
2869 * @retval None
2870 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2871 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2872 {
2873 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2874 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2875 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2876 }
2877
2878 /**
2879 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2880 * @note This function enables clearing the output channel on an external event.
2881 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2882 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2883 * or not a timer instance can clear the OCxREF signal on an external event.
2884 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2885 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2886 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2887 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2888 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2889 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2890 * @param TIMx Timer instance
2891 * @param Channel This parameter can be one of the following values:
2892 * @arg @ref LL_TIM_CHANNEL_CH1
2893 * @arg @ref LL_TIM_CHANNEL_CH2
2894 * @arg @ref LL_TIM_CHANNEL_CH3
2895 * @arg @ref LL_TIM_CHANNEL_CH4
2896 * @arg @ref LL_TIM_CHANNEL_CH5
2897 * @arg @ref LL_TIM_CHANNEL_CH6
2898 * @retval State of bit (1 or 0).
2899 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2900 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2901 {
2902 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2903 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2904 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2905 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2906 }
2907
2908 /**
2909 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2910 * the Ocx and OCxN signals).
2911 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2912 * dead-time insertion feature is supported by a timer instance.
2913 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2914 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2915 * @param TIMx Timer instance
2916 * @param DeadTime between Min_Data=0 and Max_Data=255
2917 * @retval None
2918 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2919 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2920 {
2921 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2922 }
2923
2924 /**
2925 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2926 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2927 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2928 * whether or not a timer instance supports a 32 bits counter.
2929 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2930 * output channel 1 is supported by a timer instance.
2931 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2932 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2933 * @param TIMx Timer instance
2934 * @param CompareValue between Min_Data=0 and Max_Data=65535
2935 * @retval None
2936 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2937 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2938 {
2939 WRITE_REG(TIMx->CCR1, CompareValue);
2940 }
2941
2942 /**
2943 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2944 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2945 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2946 * whether or not a timer instance supports a 32 bits counter.
2947 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2948 * output channel 2 is supported by a timer instance.
2949 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2950 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2951 * @param TIMx Timer instance
2952 * @param CompareValue between Min_Data=0 and Max_Data=65535
2953 * @retval None
2954 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2955 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2956 {
2957 WRITE_REG(TIMx->CCR2, CompareValue);
2958 }
2959
2960 /**
2961 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2962 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2963 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2964 * whether or not a timer instance supports a 32 bits counter.
2965 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2966 * output channel is supported by a timer instance.
2967 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2968 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2969 * @param TIMx Timer instance
2970 * @param CompareValue between Min_Data=0 and Max_Data=65535
2971 * @retval None
2972 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2973 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2974 {
2975 WRITE_REG(TIMx->CCR3, CompareValue);
2976 }
2977
2978 /**
2979 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2980 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2981 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2982 * whether or not a timer instance supports a 32 bits counter.
2983 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2984 * output channel 4 is supported by a timer instance.
2985 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2986 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2987 * @param TIMx Timer instance
2988 * @param CompareValue between Min_Data=0 and Max_Data=65535
2989 * @retval None
2990 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2991 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2992 {
2993 WRITE_REG(TIMx->CCR4, CompareValue);
2994 }
2995
2996 /**
2997 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2998 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2999 * output channel 5 is supported by a timer instance.
3000 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3001 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3002 * @param TIMx Timer instance
3003 * @param CompareValue between Min_Data=0 and Max_Data=65535
3004 * @retval None
3005 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3006 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3007 {
3008 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3009 }
3010
3011 /**
3012 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3013 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3014 * output channel 6 is supported by a timer instance.
3015 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3016 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3017 * @param TIMx Timer instance
3018 * @param CompareValue between Min_Data=0 and Max_Data=65535
3019 * @retval None
3020 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3021 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3022 {
3023 WRITE_REG(TIMx->CCR6, CompareValue);
3024 }
3025
3026 /**
3027 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3028 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3029 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3030 * whether or not a timer instance supports a 32 bits counter.
3031 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3032 * output channel 1 is supported by a timer instance.
3033 * @note If dithering is activated, pay attention to the returned value interpretation.
3034 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3035 * @param TIMx Timer instance
3036 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3037 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)3038 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
3039 {
3040 return (uint32_t)(READ_REG(TIMx->CCR1));
3041 }
3042
3043 /**
3044 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3045 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3046 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3047 * whether or not a timer instance supports a 32 bits counter.
3048 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3049 * output channel 2 is supported by a timer instance.
3050 * @note If dithering is activated, pay attention to the returned value interpretation.
3051 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3052 * @param TIMx Timer instance
3053 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3054 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)3055 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
3056 {
3057 return (uint32_t)(READ_REG(TIMx->CCR2));
3058 }
3059
3060 /**
3061 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3062 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3063 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3064 * whether or not a timer instance supports a 32 bits counter.
3065 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3066 * output channel 3 is supported by a timer instance.
3067 * @note If dithering is activated, pay attention to the returned value interpretation.
3068 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3069 * @param TIMx Timer instance
3070 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3071 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)3072 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
3073 {
3074 return (uint32_t)(READ_REG(TIMx->CCR3));
3075 }
3076
3077 /**
3078 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3079 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3080 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3081 * whether or not a timer instance supports a 32 bits counter.
3082 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3083 * output channel 4 is supported by a timer instance.
3084 * @note If dithering is activated, pay attention to the returned value interpretation.
3085 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3086 * @param TIMx Timer instance
3087 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3088 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3089 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3090 {
3091 return (uint32_t)(READ_REG(TIMx->CCR4));
3092 }
3093
3094 /**
3095 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3096 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3097 * output channel 5 is supported by a timer instance.
3098 * @note If dithering is activated, pay attention to the returned value interpretation.
3099 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3100 * @param TIMx Timer instance
3101 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3102 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3103 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3104 {
3105 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3106 }
3107
3108 /**
3109 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3110 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3111 * output channel 6 is supported by a timer instance.
3112 * @note If dithering is activated, pay attention to the returned value interpretation.
3113 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3114 * @param TIMx Timer instance
3115 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3116 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3117 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3118 {
3119 return (uint32_t)(READ_REG(TIMx->CCR6));
3120 }
3121
3122 /**
3123 * @brief Select on which reference signal the OC5REF is combined to.
3124 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3125 * whether or not a timer instance supports the combined 3-phase PWM mode.
3126 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3127 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3128 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3129 * @param TIMx Timer instance
3130 * @param GroupCH5 This parameter can be a combination of the following values:
3131 * @arg @ref LL_TIM_GROUPCH5_NONE
3132 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3133 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3134 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3135 * @retval None
3136 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3137 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3138 {
3139 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3140 }
3141
3142 /**
3143 * @brief Set the pulse on compare pulse width prescaler.
3144 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3145 * whether or not the pulse on compare feature is supported by the timer
3146 * instance.
3147 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3148 * @param TIMx Timer instance
3149 * @param PulseWidthPrescaler This parameter can be one of the following values:
3150 * @arg @ref LL_TIM_PWPRSC_X1
3151 * @arg @ref LL_TIM_PWPRSC_X2
3152 * @arg @ref LL_TIM_PWPRSC_X4
3153 * @arg @ref LL_TIM_PWPRSC_X8
3154 * @arg @ref LL_TIM_PWPRSC_X16
3155 * @arg @ref LL_TIM_PWPRSC_X32
3156 * @arg @ref LL_TIM_PWPRSC_X64
3157 * @arg @ref LL_TIM_PWPRSC_X128
3158 * @retval None
3159 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3160 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3161 {
3162 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3163 }
3164
3165 /**
3166 * @brief Get the pulse on compare pulse width prescaler.
3167 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3168 * whether or not the pulse on compare feature is supported by the timer
3169 * instance.
3170 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3171 * @param TIMx Timer instance
3172 * @retval Returned value can be one of the following values:
3173 * @arg @ref LL_TIM_PWPRSC_X1
3174 * @arg @ref LL_TIM_PWPRSC_X2
3175 * @arg @ref LL_TIM_PWPRSC_X4
3176 * @arg @ref LL_TIM_PWPRSC_X8
3177 * @arg @ref LL_TIM_PWPRSC_X16
3178 * @arg @ref LL_TIM_PWPRSC_X32
3179 * @arg @ref LL_TIM_PWPRSC_X64
3180 * @arg @ref LL_TIM_PWPRSC_X128
3181 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3182 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3183 {
3184 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3185 }
3186
3187 /**
3188 * @brief Set the pulse on compare pulse width duration.
3189 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3190 * whether or not the pulse on compare feature is supported by the timer
3191 * instance.
3192 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3193 * @param TIMx Timer instance
3194 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3195 * @retval None
3196 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3197 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3198 {
3199 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3200 }
3201
3202 /**
3203 * @brief Get the pulse on compare pulse width duration.
3204 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3205 * whether or not the pulse on compare feature is supported by the timer
3206 * instance.
3207 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3208 * @param TIMx Timer instance
3209 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3210 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3211 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3212 {
3213 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3214 }
3215
3216 /**
3217 * @}
3218 */
3219
3220 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3221 * @{
3222 */
3223 /**
3224 * @brief Configure input channel.
3225 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3226 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3227 * CCMR1 IC1F LL_TIM_IC_Config\n
3228 * CCMR1 CC2S LL_TIM_IC_Config\n
3229 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3230 * CCMR1 IC2F LL_TIM_IC_Config\n
3231 * CCMR2 CC3S LL_TIM_IC_Config\n
3232 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3233 * CCMR2 IC3F LL_TIM_IC_Config\n
3234 * CCMR2 CC4S LL_TIM_IC_Config\n
3235 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3236 * CCMR2 IC4F LL_TIM_IC_Config\n
3237 * CCER CC1P LL_TIM_IC_Config\n
3238 * CCER CC1NP LL_TIM_IC_Config\n
3239 * CCER CC2P LL_TIM_IC_Config\n
3240 * CCER CC2NP LL_TIM_IC_Config\n
3241 * CCER CC3P LL_TIM_IC_Config\n
3242 * CCER CC3NP LL_TIM_IC_Config\n
3243 * CCER CC4P LL_TIM_IC_Config\n
3244 * CCER CC4NP LL_TIM_IC_Config
3245 * @param TIMx Timer instance
3246 * @param Channel This parameter can be one of the following values:
3247 * @arg @ref LL_TIM_CHANNEL_CH1
3248 * @arg @ref LL_TIM_CHANNEL_CH2
3249 * @arg @ref LL_TIM_CHANNEL_CH3
3250 * @arg @ref LL_TIM_CHANNEL_CH4
3251 * @param Configuration This parameter must be a combination of all the following values:
3252 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3253 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3254 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3255 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3256 * @retval None
3257 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3258 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3259 {
3260 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3261 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3262 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3263 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3264 << SHIFT_TAB_ICxx[iChannel]);
3265 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3266 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3267 }
3268
3269 /**
3270 * @brief Set the active input.
3271 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3272 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3273 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3274 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3275 * @param TIMx Timer instance
3276 * @param Channel This parameter can be one of the following values:
3277 * @arg @ref LL_TIM_CHANNEL_CH1
3278 * @arg @ref LL_TIM_CHANNEL_CH2
3279 * @arg @ref LL_TIM_CHANNEL_CH3
3280 * @arg @ref LL_TIM_CHANNEL_CH4
3281 * @param ICActiveInput This parameter can be one of the following values:
3282 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3283 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3284 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3285 * @retval None
3286 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3287 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3288 {
3289 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3290 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3291 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3292 }
3293
3294 /**
3295 * @brief Get the current active input.
3296 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3297 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3298 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3299 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3300 * @param TIMx Timer instance
3301 * @param Channel This parameter can be one of the following values:
3302 * @arg @ref LL_TIM_CHANNEL_CH1
3303 * @arg @ref LL_TIM_CHANNEL_CH2
3304 * @arg @ref LL_TIM_CHANNEL_CH3
3305 * @arg @ref LL_TIM_CHANNEL_CH4
3306 * @retval Returned value can be one of the following values:
3307 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3308 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3309 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3310 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3311 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3312 {
3313 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3314 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3315 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3316 }
3317
3318 /**
3319 * @brief Set the prescaler of input channel.
3320 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3321 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3322 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3323 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3324 * @param TIMx Timer instance
3325 * @param Channel This parameter can be one of the following values:
3326 * @arg @ref LL_TIM_CHANNEL_CH1
3327 * @arg @ref LL_TIM_CHANNEL_CH2
3328 * @arg @ref LL_TIM_CHANNEL_CH3
3329 * @arg @ref LL_TIM_CHANNEL_CH4
3330 * @param ICPrescaler This parameter can be one of the following values:
3331 * @arg @ref LL_TIM_ICPSC_DIV1
3332 * @arg @ref LL_TIM_ICPSC_DIV2
3333 * @arg @ref LL_TIM_ICPSC_DIV4
3334 * @arg @ref LL_TIM_ICPSC_DIV8
3335 * @retval None
3336 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3337 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3338 {
3339 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3340 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3341 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3342 }
3343
3344 /**
3345 * @brief Get the current prescaler value acting on an input channel.
3346 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3347 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3348 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3349 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3350 * @param TIMx Timer instance
3351 * @param Channel This parameter can be one of the following values:
3352 * @arg @ref LL_TIM_CHANNEL_CH1
3353 * @arg @ref LL_TIM_CHANNEL_CH2
3354 * @arg @ref LL_TIM_CHANNEL_CH3
3355 * @arg @ref LL_TIM_CHANNEL_CH4
3356 * @retval Returned value can be one of the following values:
3357 * @arg @ref LL_TIM_ICPSC_DIV1
3358 * @arg @ref LL_TIM_ICPSC_DIV2
3359 * @arg @ref LL_TIM_ICPSC_DIV4
3360 * @arg @ref LL_TIM_ICPSC_DIV8
3361 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3362 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3363 {
3364 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3365 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3366 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3367 }
3368
3369 /**
3370 * @brief Set the input filter duration.
3371 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3372 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3373 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3374 * CCMR2 IC4F LL_TIM_IC_SetFilter
3375 * @param TIMx Timer instance
3376 * @param Channel This parameter can be one of the following values:
3377 * @arg @ref LL_TIM_CHANNEL_CH1
3378 * @arg @ref LL_TIM_CHANNEL_CH2
3379 * @arg @ref LL_TIM_CHANNEL_CH3
3380 * @arg @ref LL_TIM_CHANNEL_CH4
3381 * @param ICFilter This parameter can be one of the following values:
3382 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3383 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3384 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3385 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3386 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3387 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3388 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3389 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3390 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3391 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3392 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3393 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3394 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3395 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3396 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3397 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3398 * @retval None
3399 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3400 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3401 {
3402 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3403 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3404 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3405 }
3406
3407 /**
3408 * @brief Get the input filter duration.
3409 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3410 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3411 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3412 * CCMR2 IC4F LL_TIM_IC_GetFilter
3413 * @param TIMx Timer instance
3414 * @param Channel This parameter can be one of the following values:
3415 * @arg @ref LL_TIM_CHANNEL_CH1
3416 * @arg @ref LL_TIM_CHANNEL_CH2
3417 * @arg @ref LL_TIM_CHANNEL_CH3
3418 * @arg @ref LL_TIM_CHANNEL_CH4
3419 * @retval Returned value can be one of the following values:
3420 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3421 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3422 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3423 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3424 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3425 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3426 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3427 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3428 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3429 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3430 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3431 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3432 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3433 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3434 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3435 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3436 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3437 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3438 {
3439 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3440 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3441 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3442 }
3443
3444 /**
3445 * @brief Set the input channel polarity.
3446 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3447 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3448 * CCER CC2P LL_TIM_IC_SetPolarity\n
3449 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3450 * CCER CC3P LL_TIM_IC_SetPolarity\n
3451 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3452 * CCER CC4P LL_TIM_IC_SetPolarity\n
3453 * CCER CC4NP LL_TIM_IC_SetPolarity
3454 * @param TIMx Timer instance
3455 * @param Channel This parameter can be one of the following values:
3456 * @arg @ref LL_TIM_CHANNEL_CH1
3457 * @arg @ref LL_TIM_CHANNEL_CH2
3458 * @arg @ref LL_TIM_CHANNEL_CH3
3459 * @arg @ref LL_TIM_CHANNEL_CH4
3460 * @param ICPolarity This parameter can be one of the following values:
3461 * @arg @ref LL_TIM_IC_POLARITY_RISING
3462 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3463 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3464 * @retval None
3465 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3466 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3467 {
3468 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3469 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3470 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3471 }
3472
3473 /**
3474 * @brief Get the current input channel polarity.
3475 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3476 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3477 * CCER CC2P LL_TIM_IC_GetPolarity\n
3478 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3479 * CCER CC3P LL_TIM_IC_GetPolarity\n
3480 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3481 * CCER CC4P LL_TIM_IC_GetPolarity\n
3482 * CCER CC4NP LL_TIM_IC_GetPolarity
3483 * @param TIMx Timer instance
3484 * @param Channel This parameter can be one of the following values:
3485 * @arg @ref LL_TIM_CHANNEL_CH1
3486 * @arg @ref LL_TIM_CHANNEL_CH2
3487 * @arg @ref LL_TIM_CHANNEL_CH3
3488 * @arg @ref LL_TIM_CHANNEL_CH4
3489 * @retval Returned value can be one of the following values:
3490 * @arg @ref LL_TIM_IC_POLARITY_RISING
3491 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3492 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3493 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3494 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3495 {
3496 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3497 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3498 SHIFT_TAB_CCxP[iChannel]);
3499 }
3500
3501 /**
3502 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3503 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3504 * a timer instance provides an XOR input.
3505 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3506 * @param TIMx Timer instance
3507 * @retval None
3508 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3509 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3510 {
3511 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3512 }
3513
3514 /**
3515 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3516 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3517 * a timer instance provides an XOR input.
3518 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3519 * @param TIMx Timer instance
3520 * @retval None
3521 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3522 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3523 {
3524 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3525 }
3526
3527 /**
3528 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3529 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3530 * a timer instance provides an XOR input.
3531 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3532 * @param TIMx Timer instance
3533 * @retval State of bit (1 or 0).
3534 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3535 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3536 {
3537 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3538 }
3539
3540 /**
3541 * @brief Get captured value for input channel 1.
3542 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3543 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3544 * whether or not a timer instance supports a 32 bits counter.
3545 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3546 * input channel 1 is supported by a timer instance.
3547 * @note If dithering is activated, pay attention to the returned value interpretation.
3548 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3549 * @param TIMx Timer instance
3550 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3551 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3552 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3553 {
3554 return (uint32_t)(READ_REG(TIMx->CCR1));
3555 }
3556
3557 /**
3558 * @brief Get captured value for input channel 2.
3559 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3560 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3561 * whether or not a timer instance supports a 32 bits counter.
3562 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3563 * input channel 2 is supported by a timer instance.
3564 * @note If dithering is activated, pay attention to the returned value interpretation.
3565 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3566 * @param TIMx Timer instance
3567 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3568 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3569 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3570 {
3571 return (uint32_t)(READ_REG(TIMx->CCR2));
3572 }
3573
3574 /**
3575 * @brief Get captured value for input channel 3.
3576 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3577 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3578 * whether or not a timer instance supports a 32 bits counter.
3579 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3580 * input channel 3 is supported by a timer instance.
3581 * @note If dithering is activated, pay attention to the returned value interpretation.
3582 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3583 * @param TIMx Timer instance
3584 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3585 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3586 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3587 {
3588 return (uint32_t)(READ_REG(TIMx->CCR3));
3589 }
3590
3591 /**
3592 * @brief Get captured value for input channel 4.
3593 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3594 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3595 * whether or not a timer instance supports a 32 bits counter.
3596 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3597 * input channel 4 is supported by a timer instance.
3598 * @note If dithering is activated, pay attention to the returned value interpretation.
3599 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3600 * @param TIMx Timer instance
3601 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3602 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3603 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3604 {
3605 return (uint32_t)(READ_REG(TIMx->CCR4));
3606 }
3607
3608 /**
3609 * @}
3610 */
3611
3612 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3613 * @{
3614 */
3615 /**
3616 * @brief Enable external clock mode 2.
3617 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3618 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3619 * whether or not a timer instance supports external clock mode2.
3620 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3621 * @param TIMx Timer instance
3622 * @retval None
3623 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3624 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3625 {
3626 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3627 }
3628
3629 /**
3630 * @brief Disable external clock mode 2.
3631 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3632 * whether or not a timer instance supports external clock mode2.
3633 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3634 * @param TIMx Timer instance
3635 * @retval None
3636 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3637 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3638 {
3639 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3640 }
3641
3642 /**
3643 * @brief Indicate whether external clock mode 2 is enabled.
3644 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3645 * whether or not a timer instance supports external clock mode2.
3646 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3647 * @param TIMx Timer instance
3648 * @retval State of bit (1 or 0).
3649 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3650 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3651 {
3652 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3653 }
3654
3655 /**
3656 * @brief Set the clock source of the counter clock.
3657 * @note when selected clock source is external clock mode 1, the timer input
3658 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3659 * function. This timer input must be configured by calling
3660 * the @ref LL_TIM_IC_Config() function.
3661 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3662 * whether or not a timer instance supports external clock mode1.
3663 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3664 * whether or not a timer instance supports external clock mode2.
3665 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3666 * SMCR ECE LL_TIM_SetClockSource
3667 * @param TIMx Timer instance
3668 * @param ClockSource This parameter can be one of the following values:
3669 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3670 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3671 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3672 * @retval None
3673 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3674 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3675 {
3676 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3677 }
3678
3679 /**
3680 * @brief Set the encoder interface mode.
3681 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3682 * whether or not a timer instance supports the encoder mode.
3683 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3684 * @param TIMx Timer instance
3685 * @param EncoderMode This parameter can be one of the following values:
3686 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3687 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3688 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3689 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3690 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3691 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3692 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3693 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3694 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3695 * @retval None
3696 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3697 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3698 {
3699 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3700 }
3701
3702 /**
3703 * @}
3704 */
3705
3706 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3707 * @{
3708 */
3709 /**
3710 * @brief Set the trigger output (TRGO) used for timer synchronization .
3711 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3712 * whether or not a timer instance can operate as a master timer.
3713 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3714 * @param TIMx Timer instance
3715 * @param TimerSynchronization This parameter can be one of the following values:
3716 * @arg @ref LL_TIM_TRGO_RESET
3717 * @arg @ref LL_TIM_TRGO_ENABLE
3718 * @arg @ref LL_TIM_TRGO_UPDATE
3719 * @arg @ref LL_TIM_TRGO_CC1IF
3720 * @arg @ref LL_TIM_TRGO_OC1REF
3721 * @arg @ref LL_TIM_TRGO_OC2REF
3722 * @arg @ref LL_TIM_TRGO_OC3REF
3723 * @arg @ref LL_TIM_TRGO_OC4REF
3724 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3725 * @retval None
3726 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3727 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3728 {
3729 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3730 }
3731
3732 /**
3733 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3734 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3735 * whether or not a timer instance can be used for ADC synchronization.
3736 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3737 * @param TIMx Timer Instance
3738 * @param ADCSynchronization This parameter can be one of the following values:
3739 * @arg @ref LL_TIM_TRGO2_RESET
3740 * @arg @ref LL_TIM_TRGO2_ENABLE
3741 * @arg @ref LL_TIM_TRGO2_UPDATE
3742 * @arg @ref LL_TIM_TRGO2_CC1F
3743 * @arg @ref LL_TIM_TRGO2_OC1
3744 * @arg @ref LL_TIM_TRGO2_OC2
3745 * @arg @ref LL_TIM_TRGO2_OC3
3746 * @arg @ref LL_TIM_TRGO2_OC4
3747 * @arg @ref LL_TIM_TRGO2_OC5
3748 * @arg @ref LL_TIM_TRGO2_OC6
3749 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3750 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3751 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3752 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3753 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3754 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3755 * @retval None
3756 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3757 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3758 {
3759 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3760 }
3761
3762 /**
3763 * @brief Set the synchronization mode of a slave timer.
3764 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3765 * a timer instance can operate as a slave timer.
3766 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3767 * @param TIMx Timer instance
3768 * @param SlaveMode This parameter can be one of the following values:
3769 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3770 * @arg @ref LL_TIM_SLAVEMODE_RESET
3771 * @arg @ref LL_TIM_SLAVEMODE_GATED
3772 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3773 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3774 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3775 * @retval None
3776 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3777 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3778 {
3779 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3780 }
3781
3782 /**
3783 * @brief Set the selects the trigger input to be used to synchronize the counter.
3784 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3785 * a timer instance can operate as a slave timer.
3786 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3787 * @param TIMx Timer instance
3788 * @param TriggerInput This parameter can be one of the following values:
3789 * @arg @ref LL_TIM_TS_ITR0
3790 * @arg @ref LL_TIM_TS_ITR1
3791 * @arg @ref LL_TIM_TS_ITR2
3792 * @arg @ref LL_TIM_TS_ITR3
3793 * @arg @ref LL_TIM_TS_ITR4
3794 * @arg @ref LL_TIM_TS_ITR5
3795 * @arg @ref LL_TIM_TS_ITR6
3796 * @arg @ref LL_TIM_TS_ITR7
3797 * @arg @ref LL_TIM_TS_ITR8
3798 * @arg @ref LL_TIM_TS_ITR9
3799 * @arg @ref LL_TIM_TS_ITR10
3800 * @arg @ref LL_TIM_TS_ITR11
3801 * @arg @ref LL_TIM_TS_ITR12
3802 * @arg @ref LL_TIM_TS_TI1F_ED
3803 * @arg @ref LL_TIM_TS_TI1FP1
3804 * @arg @ref LL_TIM_TS_TI2FP2
3805 * @arg @ref LL_TIM_TS_ETRF
3806 * @retval None
3807 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3808 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3809 {
3810 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3811 }
3812
3813 /**
3814 * @brief Enable the Master/Slave mode.
3815 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3816 * a timer instance can operate as a slave timer.
3817 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3818 * @param TIMx Timer instance
3819 * @retval None
3820 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3821 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3822 {
3823 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3824 }
3825
3826 /**
3827 * @brief Disable the Master/Slave mode.
3828 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3829 * a timer instance can operate as a slave timer.
3830 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3831 * @param TIMx Timer instance
3832 * @retval None
3833 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3834 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3835 {
3836 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3837 }
3838
3839 /**
3840 * @brief Indicates whether the Master/Slave mode is enabled.
3841 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3842 * a timer instance can operate as a slave timer.
3843 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3844 * @param TIMx Timer instance
3845 * @retval State of bit (1 or 0).
3846 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3847 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3848 {
3849 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3850 }
3851
3852 /**
3853 * @brief Configure the external trigger (ETR) input.
3854 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3855 * a timer instance provides an external trigger input.
3856 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3857 * SMCR ETPS LL_TIM_ConfigETR\n
3858 * SMCR ETF LL_TIM_ConfigETR
3859 * @param TIMx Timer instance
3860 * @param ETRPolarity This parameter can be one of the following values:
3861 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3862 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3863 * @param ETRPrescaler This parameter can be one of the following values:
3864 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3865 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3866 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3867 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3868 * @param ETRFilter This parameter can be one of the following values:
3869 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3870 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3871 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3872 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3873 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3874 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3875 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3876 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3877 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3878 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3879 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3880 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3881 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3882 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3883 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3884 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3885 * @retval None
3886 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3887 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3888 uint32_t ETRFilter)
3889 {
3890 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3891 }
3892
3893 /**
3894 * @brief Select the external trigger (ETR) input source.
3895 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3896 * not a timer instance supports ETR source selection.
3897 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3898 * @param TIMx Timer instance
3899 * @param ETRSource This parameter can be one of the following values:
3900 *
3901 * TIM1: any combination of ETR_RMP where
3902 *
3903 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3904 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*)
3905 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
3906 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
3907 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
3908 *
3909 * TIM2: any combination of ETR_RMP where
3910 *
3911 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3912 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*)
3913 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
3914 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA (*)
3915 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (*)
3916 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
3917 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*)
3918 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
3919 * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS (*)
3920
3921 *
3922 * TIM3: any combination of ETR_RMP where
3923 *
3924 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3925 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*)
3926 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
3927 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*)
3928 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (*)
3929 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS (*)
3930 *
3931 * TIM4: any combination of ETR_RMP where (**)
3932 *
3933 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
3934 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
3935 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
3936 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
3937 *
3938 * TIM5: any combination of ETR_RMP where (**)
3939 *
3940 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
3941 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
3942 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
3943 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
3944 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
3945 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
3946 *
3947 * TIM8: any combination of ETR_RMP where (**)
3948 *
3949 * . . ETR_RMP can be one of the following values
3950 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
3951 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
3952 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
3953 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
3954 *
3955 * (*) Value not defined in all devices. \n
3956 * (**) Timer instance not available on all devices. \n
3957 * @retval None
3958 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3959 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3960 {
3961 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3962 }
3963
3964 /**
3965 * @brief Enable SMS preload.
3966 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3967 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3968 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
3969 * @param TIMx Timer instance
3970 * @retval None
3971 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)3972 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
3973 {
3974 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3975 }
3976
3977 /**
3978 * @brief Disable SMS preload.
3979 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3980 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3981 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
3982 * @param TIMx Timer instance
3983 * @retval None
3984 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)3985 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
3986 {
3987 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3988 }
3989
3990 /**
3991 * @brief Indicate whether SMS preload is enabled.
3992 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3993 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3994 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
3995 * @param TIMx Timer instance
3996 * @retval State of bit (1 or 0).
3997 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)3998 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
3999 {
4000 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4001 }
4002
4003 /**
4004 * @brief Set the preload source of SMS.
4005 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4006 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4007 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4008 * @param TIMx Timer instance
4009 * @param PreloadSource This parameter can be one of the following values:
4010 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4011 * @arg @ref LL_TIM_SMSPS_INDEX
4012 * @retval None
4013 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4014 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4015 {
4016 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4017 }
4018
4019 /**
4020 * @brief Get the preload source of SMS.
4021 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4022 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4023 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4024 * @param TIMx Timer instance
4025 * @retval Returned value can be one of the following values:
4026 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4027 * @arg @ref LL_TIM_SMSPS_INDEX
4028 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)4029 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
4030 {
4031 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4032 }
4033
4034 /**
4035 * @}
4036 */
4037
4038 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4039 * @{
4040 */
4041 /**
4042 * @brief Enable the break function.
4043 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4044 * a timer instance provides a break input.
4045 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4046 * @param TIMx Timer instance
4047 * @retval None
4048 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4049 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4050 {
4051 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4052 }
4053
4054 /**
4055 * @brief Disable the break function.
4056 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4057 * @param TIMx Timer instance
4058 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4059 * a timer instance provides a break input.
4060 * @retval None
4061 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4062 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4063 {
4064 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4065 }
4066
4067 /**
4068 * @brief Configure the break input.
4069 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4070 * a timer instance provides a break input.
4071 * @note Bidirectional mode is only supported by advanced timer instances.
4072 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4073 * a timer instance is an advanced-control timer.
4074 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4075 * in input mode and in open drain output mode. Any active Break event will
4076 * assert a low logic level on the Break input to indicate an internal break
4077 * event to external devices.
4078 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4079 * LL_TIM_BREAK_AFMODE_INPUT.
4080 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4081 * BDTR BKF LL_TIM_ConfigBRK\n
4082 * BDTR BKBID LL_TIM_ConfigBRK
4083 * @param TIMx Timer instance
4084 * @param BreakPolarity This parameter can be one of the following values:
4085 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4086 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4087 * @param BreakFilter This parameter can be one of the following values:
4088 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4089 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4090 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4091 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4092 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4093 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4094 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4095 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4096 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4097 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4098 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4099 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4100 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4101 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4102 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4103 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4104 * @param BreakAFMode This parameter can be one of the following values:
4105 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4106 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4107 * @retval None
4108 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4109 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4110 uint32_t BreakAFMode)
4111 {
4112 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4113 }
4114
4115 /**
4116 * @brief Disarm the break input (when it operates in bidirectional mode).
4117 * @note The break input can be disarmed only when it is configured in
4118 * bidirectional mode and when when MOE is reset.
4119 * @note Purpose is to be able to have the input voltage back to high-state,
4120 * whatever the time constant on the output .
4121 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4122 * @param TIMx Timer instance
4123 * @retval None
4124 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4125 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4126 {
4127 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4128 }
4129
4130 /**
4131 * @brief Re-arm the break input (when it operates in bidirectional mode).
4132 * @note The Break input is automatically armed as soon as MOE bit is set.
4133 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
4134 * @param TIMx Timer instance
4135 * @retval None
4136 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)4137 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
4138 {
4139 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4140 }
4141
4142 /**
4143 * @brief Enable the break 2 function.
4144 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4145 * a timer instance provides a second break input.
4146 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4147 * @param TIMx Timer instance
4148 * @retval None
4149 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4150 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4151 {
4152 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4153 }
4154
4155 /**
4156 * @brief Disable the break 2 function.
4157 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4158 * a timer instance provides a second break input.
4159 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4160 * @param TIMx Timer instance
4161 * @retval None
4162 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4163 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4164 {
4165 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4166 }
4167
4168 /**
4169 * @brief Configure the break 2 input.
4170 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4171 * a timer instance provides a second break input.
4172 * @note Bidirectional mode is only supported by advanced timer instances.
4173 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4174 * a timer instance is an advanced-control timer.
4175 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4176 * in input mode and in open drain output mode. Any active Break event will
4177 * assert a low logic level on the Break 2 input to indicate an internal break
4178 * event to external devices.
4179 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4180 * LL_TIM_BREAK2_AFMODE_INPUT.
4181 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4182 * BDTR BK2F LL_TIM_ConfigBRK2\n
4183 * BDTR BK2BID LL_TIM_ConfigBRK2
4184 * @param TIMx Timer instance
4185 * @param Break2Polarity This parameter can be one of the following values:
4186 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4187 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4188 * @param Break2Filter This parameter can be one of the following values:
4189 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4190 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4191 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4192 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4193 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4194 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4195 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4196 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4197 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4198 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4199 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4200 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4201 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4202 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4203 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4204 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4205 * @param Break2AFMode This parameter can be one of the following values:
4206 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4207 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4208 * @retval None
4209 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4210 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4211 uint32_t Break2AFMode)
4212 {
4213 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4214 }
4215
4216 /**
4217 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4218 * @note The break 2 input can be disarmed only when it is configured in
4219 * bidirectional mode and when when MOE is reset.
4220 * @note Purpose is to be able to have the input voltage back to high-state,
4221 * whatever the time constant on the output.
4222 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4223 * @param TIMx Timer instance
4224 * @retval None
4225 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4226 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4227 {
4228 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4229 }
4230
4231 /**
4232 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
4233 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
4234 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
4235 * @param TIMx Timer instance
4236 * @retval None
4237 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)4238 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
4239 {
4240 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4241 }
4242
4243 /**
4244 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4245 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4246 * a timer instance provides a break input.
4247 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4248 * BDTR OSSR LL_TIM_SetOffStates
4249 * @param TIMx Timer instance
4250 * @param OffStateIdle This parameter can be one of the following values:
4251 * @arg @ref LL_TIM_OSSI_DISABLE
4252 * @arg @ref LL_TIM_OSSI_ENABLE
4253 * @param OffStateRun This parameter can be one of the following values:
4254 * @arg @ref LL_TIM_OSSR_DISABLE
4255 * @arg @ref LL_TIM_OSSR_ENABLE
4256 * @retval None
4257 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4258 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4259 {
4260 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4261 }
4262
4263 /**
4264 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4265 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4266 * a timer instance provides a break input.
4267 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4268 * @param TIMx Timer instance
4269 * @retval None
4270 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4271 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4272 {
4273 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4274 }
4275
4276 /**
4277 * @brief Disable automatic output (MOE can be set only by software).
4278 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4279 * a timer instance provides a break input.
4280 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4281 * @param TIMx Timer instance
4282 * @retval None
4283 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4284 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4285 {
4286 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4287 }
4288
4289 /**
4290 * @brief Indicate whether automatic output is enabled.
4291 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4292 * a timer instance provides a break input.
4293 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4294 * @param TIMx Timer instance
4295 * @retval State of bit (1 or 0).
4296 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4297 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4298 {
4299 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4300 }
4301
4302 /**
4303 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4304 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4305 * software and is reset in case of break or break2 event
4306 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4307 * a timer instance provides a break input.
4308 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4309 * @param TIMx Timer instance
4310 * @retval None
4311 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4312 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4313 {
4314 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4315 }
4316
4317 /**
4318 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4319 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4320 * software and is reset in case of break or break2 event.
4321 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4322 * a timer instance provides a break input.
4323 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4324 * @param TIMx Timer instance
4325 * @retval None
4326 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4327 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4328 {
4329 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4330 }
4331
4332 /**
4333 * @brief Indicates whether outputs are enabled.
4334 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4335 * a timer instance provides a break input.
4336 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4337 * @param TIMx Timer instance
4338 * @retval State of bit (1 or 0).
4339 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4340 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4341 {
4342 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4343 }
4344
4345 /**
4346 * @brief Enable the signals connected to the designated timer break input.
4347 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4348 * or not a timer instance allows for break input selection.
4349 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4350 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4351 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4352 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4353 * @param TIMx Timer instance
4354 * @param BreakInput This parameter can be one of the following values:
4355 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4356 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4357 * @param Source This parameter can be one of the following values:
4358 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4359 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4360 *
4361 * (*) Value not defined in all devices.
4362 * @retval None
4363 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4364 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4365 {
4366 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4367 SET_BIT(*pReg, Source);
4368 }
4369
4370 /**
4371 * @brief Disable the signals connected to the designated timer break input.
4372 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4373 * or not a timer instance allows for break input selection.
4374 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4375 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4376 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4377 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4378 * @param TIMx Timer instance
4379 * @param BreakInput This parameter can be one of the following values:
4380 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4381 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4382 * @param Source This parameter can be one of the following values:
4383 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4384 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4385 *
4386 * (*) Value not defined in all devices.
4387 * @retval None
4388 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4389 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4390 {
4391 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4392 CLEAR_BIT(*pReg, Source);
4393 }
4394
4395 /**
4396 * @brief Set the polarity of the break signal for the timer break input.
4397 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4398 * or not a timer instance allows for break input selection.
4399 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4400 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4401 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4402 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4403 * @param TIMx Timer instance
4404 * @param BreakInput This parameter can be one of the following values:
4405 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4406 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4407 * @param Source This parameter can be one of the following values:
4408 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4409 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4410 * @param Polarity This parameter can be one of the following values:
4411 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4412 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4413 *
4414 * (*) Value not defined in all devices.
4415 * @retval None
4416 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4417 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4418 uint32_t Polarity)
4419 {
4420 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4421 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4422 }
4423 /**
4424 * @brief Enable asymmetrical deadtime.
4425 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4426 * a timer instance provides asymmetrical deadtime.
4427 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4428 * @param TIMx Timer instance
4429 * @retval None
4430 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4431 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4432 {
4433 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4434 }
4435
4436 /**
4437 * @brief Disable asymmetrical dead-time.
4438 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4439 * a timer instance provides asymmetrical deadtime.
4440 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4441 * @param TIMx Timer instance
4442 * @retval None
4443 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4444 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4445 {
4446 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4447 }
4448
4449 /**
4450 * @brief Indicates whether asymmetrical deadtime is activated.
4451 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4452 * a timer instance provides asymmetrical deadtime.
4453 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4454 * @param TIMx Timer instance
4455 * @retval State of bit (1 or 0).
4456 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4457 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4458 {
4459 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4460 }
4461
4462 /**
4463 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4464 * rising edge of OCxN signals).
4465 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4466 * asymmetrical dead-time insertion feature is supported by a timer instance.
4467 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4468 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4469 * (LOCK bits in TIMx_BDTR register).
4470 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4471 * @param TIMx Timer instance
4472 * @param DeadTime between Min_Data=0 and Max_Data=255
4473 * @retval None
4474 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4475 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4476 {
4477 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4478 }
4479
4480 /**
4481 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4482 * the rising edge of OCxN signals).
4483 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4484 * asymmetrical dead-time insertion feature is supported by a timer instance.
4485 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4486 * (LOCK bits in TIMx_BDTR register).
4487 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4488 * @param TIMx Timer instance
4489 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4490 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4491 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4492 {
4493 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4494 }
4495
4496 /**
4497 * @brief Enable deadtime preload.
4498 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4499 * a timer instance provides deadtime preload.
4500 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4501 * @param TIMx Timer instance
4502 * @retval None
4503 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4504 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4505 {
4506 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4507 }
4508
4509 /**
4510 * @brief Disable dead-time preload.
4511 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4512 * a timer instance provides deadtime preload.
4513 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4514 * @param TIMx Timer instance
4515 * @retval None
4516 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4517 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4518 {
4519 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4520 }
4521
4522 /**
4523 * @brief Indicates whether deadtime preload is activated.
4524 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4525 * a timer instance provides deadtime preload.
4526 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4527 * @param TIMx Timer instance
4528 * @retval State of bit (1 or 0).
4529 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4530 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4531 {
4532 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4533 }
4534
4535 /**
4536 * @}
4537 */
4538
4539 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4540 * @{
4541 */
4542 /**
4543 * @brief Configures the timer DMA burst feature.
4544 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4545 * not a timer instance supports the DMA burst mode.
4546 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4547 * DCR DBA LL_TIM_ConfigDMABurst
4548 * @param TIMx Timer instance
4549 * @param DMABurstBaseAddress This parameter can be one of the following values:
4550 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4551 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4552 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4553 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4554 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4555 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4556 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4557 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4558 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4559 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4560 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4561 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4562 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4563 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4564 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4565 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4566 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4567 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4568 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4569 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4570 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4571 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4572 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4573 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4574 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4575 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4576 * @param DMABurstLength This parameter can be one of the following values:
4577 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4578 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4579 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4580 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4581 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4582 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4583 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4584 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4585 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4586 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4587 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4588 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4589 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4590 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4591 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4592 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4593 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4594 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4595 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4596 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4597 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4598 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4599 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4600 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4601 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4602 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4603 * @param DMABurstSource This parameter can be one of the following values:
4604 * @arg @ref LL_TIM_DMA_UPDATE
4605 * @arg @ref LL_TIM_DMA_CC1
4606 * @arg @ref LL_TIM_DMA_CC2
4607 * @arg @ref LL_TIM_DMA_CC3
4608 * @arg @ref LL_TIM_DMA_CC4
4609 * @arg @ref LL_TIM_DMA_COM
4610 * @arg @ref LL_TIM_DMA_TRIGGER
4611 * @retval None
4612 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4613 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4614 uint32_t DMABurstSource)
4615 {
4616 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4617 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4618 }
4619
4620 /**
4621 * @}
4622 */
4623
4624 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4625 * @{
4626 */
4627
4628 /**
4629 * @brief Enable encoder index.
4630 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4631 * a timer instance provides an index input.
4632 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4633 * @param TIMx Timer instance
4634 * @retval None
4635 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4636 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4637 {
4638 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4639 }
4640
4641 /**
4642 * @brief Disable encoder index.
4643 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4644 * a timer instance provides an index input.
4645 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4646 * @param TIMx Timer instance
4647 * @retval None
4648 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4649 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4650 {
4651 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4652 }
4653
4654 /**
4655 * @brief Indicate whether encoder index is enabled.
4656 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4657 * a timer instance provides an index input.
4658 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4659 * @param TIMx Timer instance
4660 * @retval State of bit (1 or 0).
4661 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4662 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4663 {
4664 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4665 }
4666
4667 /**
4668 * @brief Set index direction
4669 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4670 * a timer instance provides an index input.
4671 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4672 * @param TIMx Timer instance
4673 * @param IndexDirection This parameter can be one of the following values:
4674 * @arg @ref LL_TIM_INDEX_UP_DOWN
4675 * @arg @ref LL_TIM_INDEX_UP
4676 * @arg @ref LL_TIM_INDEX_DOWN
4677 * @retval None
4678 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4679 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4680 {
4681 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4682 }
4683
4684 /**
4685 * @brief Get actual index direction
4686 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4687 * a timer instance provides an index input.
4688 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4689 * @param TIMx Timer instance
4690 * @retval Returned value can be one of the following values:
4691 * @arg @ref LL_TIM_INDEX_UP_DOWN
4692 * @arg @ref LL_TIM_INDEX_UP
4693 * @arg @ref LL_TIM_INDEX_DOWN
4694 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4695 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4696 {
4697 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4698 }
4699
4700 /**
4701 * @brief Set index blanking
4702 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4703 * a timer instance provides an index input.
4704 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4705 * @param TIMx Timer instance
4706 * @param Indexblanking This parameter can be one of the following values:
4707 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4708 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4709 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4710 * @retval None
4711 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4712 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4713 {
4714 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4715 }
4716
4717 /**
4718 * @brief Get actual index blanking
4719 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4720 * a timer instance provides an index input.
4721 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4722 * @param TIMx Timer instance
4723 * @retval Returned value can be one of the following values:
4724 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4725 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4726 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4727 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4728 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4729 {
4730 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4731 }
4732
4733
4734 /**
4735 * @brief Enable first index.
4736 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4737 * a timer instance provides an index input.
4738 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4739 * @param TIMx Timer instance
4740 * @retval None
4741 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4742 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4743 {
4744 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4745 }
4746
4747 /**
4748 * @brief Disable first index.
4749 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4750 * a timer instance provides an index input.
4751 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4752 * @param TIMx Timer instance
4753 * @retval None
4754 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4755 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4756 {
4757 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4758 }
4759
4760 /**
4761 * @brief Indicates whether first index is enabled.
4762 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4763 * a timer instance provides an index input.
4764 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4765 * @param TIMx Timer instance
4766 * @retval State of bit (1 or 0).
4767 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4768 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4769 {
4770 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4771 }
4772
4773 /**
4774 * @brief Set index positioning
4775 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4776 * a timer instance provides an index input.
4777 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4778 * @param TIMx Timer instance
4779 * @param IndexPositionning This parameter can be one of the following values:
4780 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4781 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4782 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4783 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4784 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4785 * @arg @ref LL_TIM_INDEX_POSITION_UP
4786 * @retval None
4787 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4788 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4789 {
4790 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4791 }
4792
4793 /**
4794 * @brief Get actual index positioning
4795 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4796 * a timer instance provides an index input.
4797 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4798 * @param TIMx Timer instance
4799 * @retval Returned value can be one of the following values:
4800 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4801 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4802 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4803 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4804 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4805 * @arg @ref LL_TIM_INDEX_POSITION_UP
4806 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4807 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4808 {
4809 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
4810 }
4811
4812 /**
4813 * @brief Configure encoder index.
4814 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4815 * a timer instance provides an index input.
4816 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
4817 * ECR IBLK LL_TIM_ConfigIDX\n
4818 * ECR FIDX LL_TIM_ConfigIDX\n
4819 * ECR IPOS LL_TIM_ConfigIDX
4820 * @param TIMx Timer instance
4821 * @param Configuration This parameter must be a combination of all the following values:
4822 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
4823 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
4824 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
4825 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
4826 * @retval None
4827 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)4828 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
4829 {
4830 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
4831 }
4832
4833 /**
4834 * @}
4835 */
4836
4837 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4838 * @{
4839 */
4840 /**
4841 * @brief Remap TIM inputs (input channel, internal/external triggers).
4842 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4843 * a some timer inputs can be remapped.
4844 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
4845 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
4846 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
4847 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
4848 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4849 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
4850 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
4851 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
4852 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
4853 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
4854 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
4855 * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n
4856 * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n
4857 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
4858 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
4859 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
4860 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4861 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
4862 *
4863 * @param TIMx Timer instance
4864 * @param Remap Remap param depends on the TIMx. Description available only
4865 * in CHM version of the User Manual (not in .pdf).
4866 * Otherwise see Reference Manual description of TISEL registers.
4867 *
4868 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4869 *
4870 * TIM1: one of the following values:
4871 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
4872 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*)
4873 * @arg LL_TIM_TIM1_TI2_RMP_GPIO: TIM1 TI2 is connected to GPIO
4874 * @arg LL_TIM_TIM1_TI3_RMP_GPIO: TIM1 TI3 is connected to GPIO
4875 * @arg LL_TIM_TIM1_TI4_RMP_GPIO: TIM1 TI4 is connected to GPIO
4876 *
4877 * TIM2: one of the following values:
4878 * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
4879 * @arg LL_TIM_TIM2_TI1_RMP_LSI: TIM2 TI1 is connected to LSI (*)
4880 * @arg LL_TIM_TIM2_TI1_RMP_LSE: TIM2 TI1 is connected to LSE (*)
4881 * @arg LL_TIM_TIM2_TI1_RMP_RTC: TIM2 TI1 is connected to RTC (*)
4882 * @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1: TIM2 TI1 is connected to TIM3 TI1 (*)
4883 * @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS: TIM2 TI1 is connected to ETH PPS (*)
4884 * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
4885 * @arg LL_TIM_TIM2_TI2_RMP_HSI_1024: TIM2 TI2 is connected to HSI 1024 (*)
4886 * @arg LL_TIM_TIM2_TI2_RMP_CSI_128: TIM2 TI2 is connected to CSI 128 (*)
4887 * @arg LL_TIM_TIM2_TI2_RMP_MCO2: TIM2 TI2 is connected to MCO2 (*)
4888 * @arg LL_TIM_TIM2_TI2_RMP_MCO1: TIM2 TI2 is connected to MCO1 (*)
4889 * @arg LL_TIM_TIM2_TI3_RMP_GPIO: TIM2 TI3 is connected to GPIO
4890 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
4891 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 (*)
4892 *
4893 * TIM3: one of the following values:
4894 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
4895 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*)
4896 * @arg LL_TIM_TIM3_TI1_RMP_MCO1: TIM3 TI1 is connected to MCO1 (*)
4897 * @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1: TIM3 TI1 is connected to TIM2 TI1 (*)
4898 * @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ: TIM3 TI1 is connected to HSE_1MHZ (*)
4899 * @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS: TIM3 TI1 is connected to ETH PPS (*)
4900 * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
4901 * @arg LL_TIM_TIM3_TI2_RMP_CSI_128: TIM3 TI2 is connected to CSI_128 (*)
4902 * @arg LL_TIM_TIM3_TI2_RMP_MCO2: TIM3 TI2 is connected to MCO2 (*)
4903 * @arg LL_TIM_TIM3_TI2_RMP_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*)
4904 * @arg LL_TIM_TIM3_TI3_RMP_GPIO: TIM3 TI3 is connected to GPIO
4905 * @arg LL_TIM_TIM3_TI4_RMP_GPIO: TIM3 TI4 is connected to GPIO
4906 *
4907 * TIM4: one of the following values: (**)
4908 * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO
4909 * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO
4910 * @arg LL_TIM_TIM4_TI3_RMP_GPIO: TIM4 TI3 is connected to GPIO
4911 * @arg LL_TIM_TIM4_TI4_RMP_GPIO: TIM4 TI4 is connected to GPIO
4912 *
4913 * TIM5: one of the following values: (**)
4914 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
4915 * @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO
4916 * @arg LL_TIM_TIM5_TI3_RMP_GPIO: TIM5 TI3 is connected to GPIO
4917 * @arg LL_TIM_TIM5_TI4_RMP_GPIO: TIM5 TI4 is connected to GPIO
4918 *
4919 * TIM8: one of the following values: (**)
4920 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
4921 * @arg LL_TIM_TIM8_TI2_RMP_GPIO: TIM8 TI2 is connected to GPIO
4922 * @arg LL_TIM_TIM8_TI3_RMP_GPIO: TIM8 TI3 is connected to GPIO
4923 * @arg LL_TIM_TIM8_TI4_RMP_GPIO: TIM8 TI4 is connected to GPIO
4924 *
4925 * TIM12: one of the following values: (**)
4926 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
4927 * @arg LL_TIM_TIM12_TI1_RMP_HSI_1024: TIM12 TI1 is connected to GPIO
4928 * @arg LL_TIM_TIM12_TI1_RMP_CSI_128: TIM12 TI1 is connected to GPIO
4929 *
4930 * TIM13: one of the following values: (**)
4931 * @arg LL_TIM_TIM13_TI1_RMP_GPIO: TIM13 TI1 is connected to GPIO
4932 *
4933 * TIM14: one of the following values: (**)
4934 * @arg LL_TIM_TIM14_TI1_RMP_GPIO: TIM14 TI1 is connected to GPIO
4935 *
4936 * TIM15: one of the following values: (**)
4937 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
4938 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2
4939 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3
4940 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4
4941 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
4942 * @arg LL_TIM_TIM15_TI1_RMP_CSI_128: TIM15 TI1 is connected to CSI/128
4943 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
4944 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI1 is connected to GPIO
4945 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI1 is connected to TIM2
4946 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI1 is connected to TIM3
4947 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI1 is connected to TIM4
4948 *
4949 * TIM16: one of the following values: (**)
4950 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
4951 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
4952 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
4953 * @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP: TIM16 TI1 is connected to RTC_WKUP
4954 *
4955 * TIM17: one of the following values: (**)
4956 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
4957 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ
4958 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
4959 *
4960 * (*) Value not defined in all devices. \n
4961 * (**) Timer instance not available on all devices. \n
4962 *
4963 * @retval None
4964 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4965 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4966 {
4967 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4968 }
4969
4970 /**
4971 * @}
4972 */
4973
4974 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4975 * @{
4976 */
4977 /**
4978 * @brief Set the OCREF clear input source
4979 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4980 * @note This function can only be used in Output compare and PWM modes.
4981 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4982 * @param TIMx Timer instance
4983 * @param OCRefClearInputSource This parameter can be one of the following values:
4984 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
4985 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4986 * @retval None
4987 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4988 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4989 {
4990 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4991 }
4992 /**
4993 * @}
4994 */
4995
4996 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4997 * @{
4998 */
4999 /**
5000 * @brief Clear the update interrupt flag (UIF).
5001 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5002 * @param TIMx Timer instance
5003 * @retval None
5004 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5005 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5006 {
5007 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5008 }
5009
5010 /**
5011 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5012 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5013 * @param TIMx Timer instance
5014 * @retval State of bit (1 or 0).
5015 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)5016 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
5017 {
5018 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5019 }
5020
5021 /**
5022 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5023 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5024 * @param TIMx Timer instance
5025 * @retval None
5026 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5027 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5028 {
5029 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5030 }
5031
5032 /**
5033 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5034 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5035 * @param TIMx Timer instance
5036 * @retval State of bit (1 or 0).
5037 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)5038 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
5039 {
5040 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5041 }
5042
5043 /**
5044 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5045 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5046 * @param TIMx Timer instance
5047 * @retval None
5048 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5049 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5050 {
5051 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5052 }
5053
5054 /**
5055 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5056 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5057 * @param TIMx Timer instance
5058 * @retval State of bit (1 or 0).
5059 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)5060 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
5061 {
5062 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5063 }
5064
5065 /**
5066 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5067 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5068 * @param TIMx Timer instance
5069 * @retval None
5070 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5071 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5072 {
5073 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5074 }
5075
5076 /**
5077 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5078 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5079 * @param TIMx Timer instance
5080 * @retval State of bit (1 or 0).
5081 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)5082 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
5083 {
5084 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5085 }
5086
5087 /**
5088 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5089 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5090 * @param TIMx Timer instance
5091 * @retval None
5092 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5093 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5094 {
5095 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5096 }
5097
5098 /**
5099 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5100 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5101 * @param TIMx Timer instance
5102 * @retval State of bit (1 or 0).
5103 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)5104 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
5105 {
5106 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5107 }
5108
5109 /**
5110 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5111 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5112 * @param TIMx Timer instance
5113 * @retval None
5114 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5115 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5116 {
5117 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5118 }
5119
5120 /**
5121 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5122 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5123 * @param TIMx Timer instance
5124 * @retval State of bit (1 or 0).
5125 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)5126 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
5127 {
5128 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5129 }
5130
5131 /**
5132 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5133 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5134 * @param TIMx Timer instance
5135 * @retval None
5136 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5137 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5138 {
5139 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5140 }
5141
5142 /**
5143 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5144 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5145 * @param TIMx Timer instance
5146 * @retval State of bit (1 or 0).
5147 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)5148 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
5149 {
5150 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5151 }
5152
5153 /**
5154 * @brief Clear the commutation interrupt flag (COMIF).
5155 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5156 * @param TIMx Timer instance
5157 * @retval None
5158 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5159 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5160 {
5161 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5162 }
5163
5164 /**
5165 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5166 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5167 * @param TIMx Timer instance
5168 * @retval State of bit (1 or 0).
5169 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5170 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5171 {
5172 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5173 }
5174
5175 /**
5176 * @brief Clear the trigger interrupt flag (TIF).
5177 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5178 * @param TIMx Timer instance
5179 * @retval None
5180 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5181 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5182 {
5183 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5184 }
5185
5186 /**
5187 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5188 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5189 * @param TIMx Timer instance
5190 * @retval State of bit (1 or 0).
5191 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5192 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5193 {
5194 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5195 }
5196
5197 /**
5198 * @brief Clear the break interrupt flag (BIF).
5199 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5200 * @param TIMx Timer instance
5201 * @retval None
5202 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5203 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5204 {
5205 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5206 }
5207
5208 /**
5209 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5210 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5211 * @param TIMx Timer instance
5212 * @retval State of bit (1 or 0).
5213 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5214 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5215 {
5216 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5217 }
5218
5219 /**
5220 * @brief Clear the break 2 interrupt flag (B2IF).
5221 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5222 * @param TIMx Timer instance
5223 * @retval None
5224 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5225 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5226 {
5227 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5228 }
5229
5230 /**
5231 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5232 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5233 * @param TIMx Timer instance
5234 * @retval State of bit (1 or 0).
5235 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5236 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5237 {
5238 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5239 }
5240
5241 /**
5242 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5243 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5244 * @param TIMx Timer instance
5245 * @retval None
5246 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5247 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5248 {
5249 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5250 }
5251
5252 /**
5253 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5254 * (Capture/Compare 1 interrupt is pending).
5255 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5256 * @param TIMx Timer instance
5257 * @retval State of bit (1 or 0).
5258 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5259 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5260 {
5261 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5262 }
5263
5264 /**
5265 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5266 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5267 * @param TIMx Timer instance
5268 * @retval None
5269 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5270 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5271 {
5272 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5273 }
5274
5275 /**
5276 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5277 * (Capture/Compare 2 over-capture interrupt is pending).
5278 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5279 * @param TIMx Timer instance
5280 * @retval State of bit (1 or 0).
5281 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5282 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5283 {
5284 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5285 }
5286
5287 /**
5288 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5289 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5290 * @param TIMx Timer instance
5291 * @retval None
5292 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5293 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5294 {
5295 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5296 }
5297
5298 /**
5299 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5300 * (Capture/Compare 3 over-capture interrupt is pending).
5301 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5302 * @param TIMx Timer instance
5303 * @retval State of bit (1 or 0).
5304 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5305 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5306 {
5307 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5308 }
5309
5310 /**
5311 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5312 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5313 * @param TIMx Timer instance
5314 * @retval None
5315 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5316 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5317 {
5318 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5319 }
5320
5321 /**
5322 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5323 * (Capture/Compare 4 over-capture interrupt is pending).
5324 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5325 * @param TIMx Timer instance
5326 * @retval State of bit (1 or 0).
5327 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5328 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5329 {
5330 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5331 }
5332
5333 /**
5334 * @brief Clear the system break interrupt flag (SBIF).
5335 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5336 * @param TIMx Timer instance
5337 * @retval None
5338 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5339 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5340 {
5341 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5342 }
5343
5344 /**
5345 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5346 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5347 * @param TIMx Timer instance
5348 * @retval State of bit (1 or 0).
5349 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5350 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5351 {
5352 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5353 }
5354
5355 /**
5356 * @brief Clear the transition error interrupt flag (TERRF).
5357 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5358 * a timer instance provides encoder error management.
5359 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5360 * @param TIMx Timer instance
5361 * @retval None
5362 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5363 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5364 {
5365 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5366 }
5367
5368 /**
5369 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5370 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5371 * a timer instance provides encoder error management.
5372 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5373 * @param TIMx Timer instance
5374 * @retval State of bit (1 or 0).
5375 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5376 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5377 {
5378 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5379 }
5380
5381 /**
5382 * @brief Clear the index error interrupt flag (IERRF).
5383 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5384 * a timer instance provides encoder error management.
5385 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5386 * @param TIMx Timer instance
5387 * @retval None
5388 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5389 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5390 {
5391 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5392 }
5393
5394 /**
5395 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5396 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5397 * a timer instance provides encoder error management.
5398 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5399 * @param TIMx Timer instance
5400 * @retval State of bit (1 or 0).
5401 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5402 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5403 {
5404 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5405 }
5406
5407 /**
5408 * @brief Clear the direction change interrupt flag (DIRF).
5409 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5410 * a timer instance provides encoder interrupt management.
5411 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5412 * @param TIMx Timer instance
5413 * @retval None
5414 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5415 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5416 {
5417 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5418 }
5419
5420 /**
5421 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5422 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5423 * a timer instance provides encoder interrupt management.
5424 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5425 * @param TIMx Timer instance
5426 * @retval State of bit (1 or 0).
5427 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5428 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5429 {
5430 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5431 }
5432
5433 /**
5434 * @brief Clear the index interrupt flag (IDXF).
5435 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5436 * a timer instance provides encoder interrupt management.
5437 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5438 * @param TIMx Timer instance
5439 * @retval None
5440 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5441 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5442 {
5443 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5444 }
5445
5446 /**
5447 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5448 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5449 * a timer instance provides encoder interrupt management.
5450 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5451 * @param TIMx Timer instance
5452 * @retval State of bit (1 or 0).
5453 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5454 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5455 {
5456 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5457 }
5458 /**
5459 * @}
5460 */
5461
5462 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5463 * @{
5464 */
5465 /**
5466 * @brief Enable update interrupt (UIE).
5467 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5468 * @param TIMx Timer instance
5469 * @retval None
5470 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5471 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5472 {
5473 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5474 }
5475
5476 /**
5477 * @brief Disable update interrupt (UIE).
5478 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5479 * @param TIMx Timer instance
5480 * @retval None
5481 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5482 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5483 {
5484 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5485 }
5486
5487 /**
5488 * @brief Indicates whether the update interrupt (UIE) is enabled.
5489 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5490 * @param TIMx Timer instance
5491 * @retval State of bit (1 or 0).
5492 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5493 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5494 {
5495 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5496 }
5497
5498 /**
5499 * @brief Enable capture/compare 1 interrupt (CC1IE).
5500 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5501 * @param TIMx Timer instance
5502 * @retval None
5503 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5504 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5505 {
5506 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5507 }
5508
5509 /**
5510 * @brief Disable capture/compare 1 interrupt (CC1IE).
5511 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5512 * @param TIMx Timer instance
5513 * @retval None
5514 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5515 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5516 {
5517 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5518 }
5519
5520 /**
5521 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5522 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5523 * @param TIMx Timer instance
5524 * @retval State of bit (1 or 0).
5525 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5526 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5527 {
5528 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5529 }
5530
5531 /**
5532 * @brief Enable capture/compare 2 interrupt (CC2IE).
5533 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5534 * @param TIMx Timer instance
5535 * @retval None
5536 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5537 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5538 {
5539 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5540 }
5541
5542 /**
5543 * @brief Disable capture/compare 2 interrupt (CC2IE).
5544 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5545 * @param TIMx Timer instance
5546 * @retval None
5547 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5548 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5549 {
5550 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5551 }
5552
5553 /**
5554 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5555 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5556 * @param TIMx Timer instance
5557 * @retval State of bit (1 or 0).
5558 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5559 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5560 {
5561 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5562 }
5563
5564 /**
5565 * @brief Enable capture/compare 3 interrupt (CC3IE).
5566 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5567 * @param TIMx Timer instance
5568 * @retval None
5569 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5570 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5571 {
5572 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5573 }
5574
5575 /**
5576 * @brief Disable capture/compare 3 interrupt (CC3IE).
5577 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5578 * @param TIMx Timer instance
5579 * @retval None
5580 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5581 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5582 {
5583 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5584 }
5585
5586 /**
5587 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5588 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5589 * @param TIMx Timer instance
5590 * @retval State of bit (1 or 0).
5591 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5592 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5593 {
5594 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5595 }
5596
5597 /**
5598 * @brief Enable capture/compare 4 interrupt (CC4IE).
5599 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5600 * @param TIMx Timer instance
5601 * @retval None
5602 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5603 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5604 {
5605 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5606 }
5607
5608 /**
5609 * @brief Disable capture/compare 4 interrupt (CC4IE).
5610 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5611 * @param TIMx Timer instance
5612 * @retval None
5613 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5614 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5615 {
5616 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5617 }
5618
5619 /**
5620 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5621 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5622 * @param TIMx Timer instance
5623 * @retval State of bit (1 or 0).
5624 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5625 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5626 {
5627 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5628 }
5629
5630 /**
5631 * @brief Enable commutation interrupt (COMIE).
5632 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5633 * @param TIMx Timer instance
5634 * @retval None
5635 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5636 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5637 {
5638 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5639 }
5640
5641 /**
5642 * @brief Disable commutation interrupt (COMIE).
5643 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5644 * @param TIMx Timer instance
5645 * @retval None
5646 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5647 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5648 {
5649 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5650 }
5651
5652 /**
5653 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5654 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5655 * @param TIMx Timer instance
5656 * @retval State of bit (1 or 0).
5657 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5658 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5659 {
5660 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5661 }
5662
5663 /**
5664 * @brief Enable trigger interrupt (TIE).
5665 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5666 * @param TIMx Timer instance
5667 * @retval None
5668 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5669 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5670 {
5671 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5672 }
5673
5674 /**
5675 * @brief Disable trigger interrupt (TIE).
5676 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5677 * @param TIMx Timer instance
5678 * @retval None
5679 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5680 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5681 {
5682 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5683 }
5684
5685 /**
5686 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5687 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5688 * @param TIMx Timer instance
5689 * @retval State of bit (1 or 0).
5690 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5691 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5692 {
5693 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5694 }
5695
5696 /**
5697 * @brief Enable break interrupt (BIE).
5698 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5699 * @param TIMx Timer instance
5700 * @retval None
5701 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5702 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5703 {
5704 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5705 }
5706
5707 /**
5708 * @brief Disable break interrupt (BIE).
5709 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5710 * @param TIMx Timer instance
5711 * @retval None
5712 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5713 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5714 {
5715 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5716 }
5717
5718 /**
5719 * @brief Indicates whether the break interrupt (BIE) is enabled.
5720 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5721 * @param TIMx Timer instance
5722 * @retval State of bit (1 or 0).
5723 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5724 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5725 {
5726 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5727 }
5728
5729 /**
5730 * @brief Enable transition error interrupt (TERRIE).
5731 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5732 * a timer instance provides encoder error management.
5733 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5734 * @param TIMx Timer instance
5735 * @retval None
5736 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5737 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5738 {
5739 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5740 }
5741
5742 /**
5743 * @brief Disable transition error interrupt (TERRIE).
5744 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5745 * a timer instance provides encoder error management.
5746 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5747 * @param TIMx Timer instance
5748 * @retval None
5749 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5750 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5751 {
5752 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5753 }
5754
5755 /**
5756 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5757 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5758 * a timer instance provides encoder error management.
5759 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5760 * @param TIMx Timer instance
5761 * @retval State of bit (1 or 0).
5762 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5763 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5764 {
5765 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5766 }
5767
5768 /**
5769 * @brief Enable index error interrupt (IERRIE).
5770 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5771 * a timer instance provides encoder error management.
5772 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5773 * @param TIMx Timer instance
5774 * @retval None
5775 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5776 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5777 {
5778 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5779 }
5780
5781 /**
5782 * @brief Disable index error interrupt (IERRIE).
5783 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5784 * a timer instance provides encoder error management.
5785 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
5786 * @param TIMx Timer instance
5787 * @retval None
5788 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)5789 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
5790 {
5791 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5792 }
5793
5794 /**
5795 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
5796 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5797 * a timer instance provides encoder error management.
5798 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
5799 * @param TIMx Timer instance
5800 * @retval State of bit (1 or 0).
5801 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)5802 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
5803 {
5804 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
5805 }
5806
5807 /**
5808 * @brief Enable direction change interrupt (DIRIE).
5809 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5810 * a timer instance provides encoder interrupt management.
5811 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
5812 * @param TIMx Timer instance
5813 * @retval None
5814 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)5815 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
5816 {
5817 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5818 }
5819
5820 /**
5821 * @brief Disable direction change interrupt (DIRIE).
5822 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5823 * a timer instance provides encoder interrupt management.
5824 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
5825 * @param TIMx Timer instance
5826 * @retval None
5827 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)5828 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
5829 {
5830 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5831 }
5832
5833 /**
5834 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
5835 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5836 * a timer instance provides encoder interrupt management.
5837 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
5838 * @param TIMx Timer instance
5839 * @retval State of bit (1 or 0).
5840 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)5841 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
5842 {
5843 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
5844 }
5845
5846 /**
5847 * @brief Enable index interrupt (IDXIE).
5848 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5849 * a timer instance provides encoder interrupt management.
5850 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
5851 * @param TIMx Timer instance
5852 * @retval None
5853 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)5854 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
5855 {
5856 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5857 }
5858
5859 /**
5860 * @brief Disable index interrupt (IDXIE).
5861 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5862 * a timer instance provides encoder interrupt management.
5863 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
5864 * @param TIMx Timer instance
5865 * @retval None
5866 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)5867 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
5868 {
5869 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5870 }
5871
5872 /**
5873 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
5874 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5875 * a timer instance provides encoder interrupt management.
5876 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
5877 * @param TIMx Timer instance
5878 * @retval State of bit (1 or 0).
5879 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)5880 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
5881 {
5882 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
5883 }
5884
5885 /**
5886 * @}
5887 */
5888
5889 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
5890 * @{
5891 */
5892 /**
5893 * @brief Enable update DMA request (UDE).
5894 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
5895 * @param TIMx Timer instance
5896 * @retval None
5897 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)5898 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5899 {
5900 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
5901 }
5902
5903 /**
5904 * @brief Disable update DMA request (UDE).
5905 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
5906 * @param TIMx Timer instance
5907 * @retval None
5908 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)5909 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5910 {
5911 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
5912 }
5913
5914 /**
5915 * @brief Indicates whether the update DMA request (UDE) is enabled.
5916 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
5917 * @param TIMx Timer instance
5918 * @retval State of bit (1 or 0).
5919 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)5920 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
5921 {
5922 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
5923 }
5924
5925 /**
5926 * @brief Enable capture/compare 1 DMA request (CC1DE).
5927 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
5928 * @param TIMx Timer instance
5929 * @retval None
5930 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)5931 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
5932 {
5933 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5934 }
5935
5936 /**
5937 * @brief Disable capture/compare 1 DMA request (CC1DE).
5938 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
5939 * @param TIMx Timer instance
5940 * @retval None
5941 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)5942 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
5943 {
5944 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5945 }
5946
5947 /**
5948 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
5949 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
5950 * @param TIMx Timer instance
5951 * @retval State of bit (1 or 0).
5952 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)5953 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
5954 {
5955 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
5956 }
5957
5958 /**
5959 * @brief Enable capture/compare 2 DMA request (CC2DE).
5960 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
5961 * @param TIMx Timer instance
5962 * @retval None
5963 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)5964 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
5965 {
5966 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5967 }
5968
5969 /**
5970 * @brief Disable capture/compare 2 DMA request (CC2DE).
5971 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
5972 * @param TIMx Timer instance
5973 * @retval None
5974 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)5975 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
5976 {
5977 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5978 }
5979
5980 /**
5981 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
5982 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
5983 * @param TIMx Timer instance
5984 * @retval State of bit (1 or 0).
5985 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)5986 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
5987 {
5988 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
5989 }
5990
5991 /**
5992 * @brief Enable capture/compare 3 DMA request (CC3DE).
5993 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
5994 * @param TIMx Timer instance
5995 * @retval None
5996 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)5997 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
5998 {
5999 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6000 }
6001
6002 /**
6003 * @brief Disable capture/compare 3 DMA request (CC3DE).
6004 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6005 * @param TIMx Timer instance
6006 * @retval None
6007 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6008 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6009 {
6010 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6011 }
6012
6013 /**
6014 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6015 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6016 * @param TIMx Timer instance
6017 * @retval State of bit (1 or 0).
6018 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)6019 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
6020 {
6021 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6022 }
6023
6024 /**
6025 * @brief Enable capture/compare 4 DMA request (CC4DE).
6026 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6027 * @param TIMx Timer instance
6028 * @retval None
6029 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6030 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6031 {
6032 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6033 }
6034
6035 /**
6036 * @brief Disable capture/compare 4 DMA request (CC4DE).
6037 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6038 * @param TIMx Timer instance
6039 * @retval None
6040 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6041 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6042 {
6043 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6044 }
6045
6046 /**
6047 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6048 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6049 * @param TIMx Timer instance
6050 * @retval State of bit (1 or 0).
6051 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)6052 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
6053 {
6054 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6055 }
6056
6057 /**
6058 * @brief Enable commutation DMA request (COMDE).
6059 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6060 * @param TIMx Timer instance
6061 * @retval None
6062 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6063 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6064 {
6065 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6066 }
6067
6068 /**
6069 * @brief Disable commutation DMA request (COMDE).
6070 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6071 * @param TIMx Timer instance
6072 * @retval None
6073 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6074 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6075 {
6076 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6077 }
6078
6079 /**
6080 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6081 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6082 * @param TIMx Timer instance
6083 * @retval State of bit (1 or 0).
6084 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)6085 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
6086 {
6087 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6088 }
6089
6090 /**
6091 * @brief Enable trigger interrupt (TDE).
6092 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6093 * @param TIMx Timer instance
6094 * @retval None
6095 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6096 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6097 {
6098 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6099 }
6100
6101 /**
6102 * @brief Disable trigger interrupt (TDE).
6103 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6104 * @param TIMx Timer instance
6105 * @retval None
6106 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6107 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6108 {
6109 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6110 }
6111
6112 /**
6113 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6114 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6115 * @param TIMx Timer instance
6116 * @retval State of bit (1 or 0).
6117 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)6118 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
6119 {
6120 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6121 }
6122
6123 /**
6124 * @}
6125 */
6126
6127 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6128 * @{
6129 */
6130 /**
6131 * @brief Generate an update event.
6132 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6133 * @param TIMx Timer instance
6134 * @retval None
6135 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6136 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6137 {
6138 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6139 }
6140
6141 /**
6142 * @brief Generate Capture/Compare 1 event.
6143 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6144 * @param TIMx Timer instance
6145 * @retval None
6146 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6147 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6148 {
6149 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6150 }
6151
6152 /**
6153 * @brief Generate Capture/Compare 2 event.
6154 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6155 * @param TIMx Timer instance
6156 * @retval None
6157 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6158 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6159 {
6160 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6161 }
6162
6163 /**
6164 * @brief Generate Capture/Compare 3 event.
6165 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6166 * @param TIMx Timer instance
6167 * @retval None
6168 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6169 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6170 {
6171 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6172 }
6173
6174 /**
6175 * @brief Generate Capture/Compare 4 event.
6176 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6177 * @param TIMx Timer instance
6178 * @retval None
6179 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6180 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6181 {
6182 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6183 }
6184
6185 /**
6186 * @brief Generate commutation event.
6187 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6188 * @param TIMx Timer instance
6189 * @retval None
6190 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6191 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6192 {
6193 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6194 }
6195
6196 /**
6197 * @brief Generate trigger event.
6198 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6199 * @param TIMx Timer instance
6200 * @retval None
6201 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6202 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6203 {
6204 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6205 }
6206
6207 /**
6208 * @brief Generate break event.
6209 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6210 * @param TIMx Timer instance
6211 * @retval None
6212 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6213 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6214 {
6215 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6216 }
6217
6218 /**
6219 * @brief Generate break 2 event.
6220 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6221 * @param TIMx Timer instance
6222 * @retval None
6223 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6224 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6225 {
6226 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6227 }
6228
6229 /**
6230 * @}
6231 */
6232
6233 #if defined(USE_FULL_LL_DRIVER)
6234 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6235 * @{
6236 */
6237
6238 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
6239 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6240 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6241 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6242 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6243 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6244 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6245 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6246 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6247 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6248 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6249 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6250 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6251 /**
6252 * @}
6253 */
6254 #endif /* USE_FULL_LL_DRIVER */
6255
6256 /**
6257 * @}
6258 */
6259
6260 /**
6261 * @}
6262 */
6263
6264 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
6265
6266 /**
6267 * @}
6268 */
6269
6270 #ifdef __cplusplus
6271 }
6272 #endif
6273
6274 #endif /* __STM32H5xx_LL_TIM_H */
6275
