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/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c72 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
169 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
175 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
181 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
189 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
281 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
287 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
293 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
301 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
401 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrke18f/project_template/
Dclock_config.c73 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
176 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
182 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
188 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
196 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
287 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
293 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
299 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
307 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
416 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.c88 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
196 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
204 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
211 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
220 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
327 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
335 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
342 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
351 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
443 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l3a6/project_template/
Dclock_config.c74 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
151 ….div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock outp…
158 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
166 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
250 ….div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock outp…
257 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
265 … .div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
354 ….div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by…
361 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
369 … .div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c74 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
149 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
157 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
166 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
249 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
257 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
266 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
357 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
365 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
374 ….div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l2a4s/project_template/
Dclock_config.c89 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
212 ….div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided …
219 ….div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by…
225 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
233 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
323 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
330 ….div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock outp…
336 ….div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock outp…
344 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/project_template/
Dclock_config.c72 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
145 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
152 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
159 … .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
168 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/project_template/
Dclock_config.c72 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
145 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
152 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
159 … .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
168 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/project_template/
Dclock_config.c72 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
145 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
152 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
159 … .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
168 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-k32w042/
Dclock_config.c66 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
137 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
143 ….div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock outp…
150 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
158 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/project_template/
Dclock_config.c73 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
164 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
172 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
179 … .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
188 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/project_template/
Dclock_config.c73 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
164 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
172 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
179 … .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
188 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/project_template/
Dclock_config.c71 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
134 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
142 … .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
151 ….div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmcimx7ulp/project_template/
Dclock_config.c35 .div1 = kSCG_AsyncClkDisable,
48 .div1 = kSCG_AsyncClkDisable,
61 .div1 = kSCG_AsyncClkDisable,
76 .div1 = kSCG_AsyncClkDivBy1,
93 .div1 = kSCG_AsyncClkDivBy1,
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/project_template/
Dclock_config.c35 .div1 = kSCG_AsyncClkDisable,
48 .div1 = kSCG_AsyncClkDisable,
61 .div1 = kSCG_AsyncClkDisable,
76 .div1 = kSCG_AsyncClkDivBy1,
93 .div1 = kSCG_AsyncClkDivBy1,
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/project_template/
Dclock_config.c35 .div1 = kSCG_AsyncClkDisable,
48 .div1 = kSCG_AsyncClkDisable,
61 .div1 = kSCG_AsyncClkDisable,
76 .div1 = kSCG_AsyncClkDivBy1,
93 .div1 = kSCG_AsyncClkDivBy1,
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c25 .div1 = kSCG_AsyncClkDisable,
38 .div1 = kSCG_AsyncClkDisable,
51 .div1 = kSCG_AsyncClkDisable,
66 .div1 = kSCG_AsyncClkDisable,
83 .div1 = kSCG_AsyncClkDivBy1,
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.h462 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
491 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
574 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
617 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
Dfsl_clock.c439 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
587 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
730 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.h468 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
497 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
580 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
623 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.h468 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
497 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
580 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
623 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.h461 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
492 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
577 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
621 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.h461 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
492 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
577 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
621 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h629 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
659 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
744 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
787 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
851 scg_async_clk_div_t div1; /*!< APLLDIV1 value. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h629 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
659 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
744 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
787 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
851 scg_async_clk_div_t div1; /*!< APLLDIV1 value. */ member

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