1 /*
2 * Copyright 2019 ,2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v7.0
34 processor: K32L2A41xxxxA
35 package_id: K32L2A41VLL1A
36 mcu_data: ksdk2_0
37 processor_version: 9.0.0
38 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
39 /* clang-format on */
40
41 #include "fsl_smc.h"
42 #include "clock_config.h"
43
44 /*******************************************************************************
45 * Definitions
46 ******************************************************************************/
47 #define SCG_CLKOUTCNFG_SIRC 2U /*!< SCG CLKOUT clock select: Slow IRC */
48 #define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
49 #define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
50 #define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
51
52 /*******************************************************************************
53 * Variables
54 ******************************************************************************/
55 /* System clock frequency. */
56 extern uint32_t SystemCoreClock;
57
58 /*******************************************************************************
59 * Code
60 ******************************************************************************/
61 /*FUNCTION**********************************************************************
62 *
63 * Function Name : CLOCK_CONFIG_SetScgOutSel
64 * Description : Set the SCG clock out select (CLKOUTSEL).
65 * Param setting : The selected clock source.
66 *
67 *END**************************************************************************/
CLOCK_CONFIG_SetScgOutSel(uint8_t setting)68 static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
69 {
70 SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
71 }
72
73 /*FUNCTION**********************************************************************
74 *
75 * Function Name : CLOCK_CONFIG_FircSafeConfig
76 * Description : This function is used to safely configure FIRC clock.
77 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
78 * Before setting FIRC, change to use SIRC as system clock,
79 * then configure FIRC. After FIRC is set, change back to use FIRC
80 * in case SIRC need to be configured.
81 * Param fircConfig : FIRC configuration.
82 *
83 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)84 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
85 {
86 scg_sys_clk_config_t curConfig;
87 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
88 .div1 = kSCG_AsyncClkDisable,
89 .div3 = kSCG_AsyncClkDivBy2,
90 .range = kSCG_SircRangeHigh};
91 scg_sys_clk_config_t sysClkSafeConfigSource = {
92 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
93 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
94 .reserved1 = 0,
95 .reserved2 = 0,
96 .reserved3 = 0,
97 #endif
98 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
99 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
100 .reserved4 = 0,
101 #endif
102 .src = kSCG_SysClkSrcSirc, /* System clock source */
103 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
104 .reserved5 = 0,
105 #endif
106 };
107 /* Init Sirc. */
108 CLOCK_InitSirc(&scgSircConfig);
109 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
110 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
111 /* Wait for clock source switch finished. */
112 do
113 {
114 CLOCK_GetCurSysClkConfig(&curConfig);
115 } while (curConfig.src != sysClkSafeConfigSource.src);
116
117 /* Init Firc. */
118 CLOCK_InitFirc(fircConfig);
119 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
120 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
121 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
122 /* Wait for clock source switch finished. */
123 do
124 {
125 CLOCK_GetCurSysClkConfig(&curConfig);
126 } while (curConfig.src != sysClkSafeConfigSource.src);
127 }
128
129 /*******************************************************************************
130 ************************ BOARD_InitBootClocks function ************************
131 ******************************************************************************/
BOARD_InitBootClocks(void)132 void BOARD_InitBootClocks(void)
133 {
134 BOARD_BootClockRUN();
135 }
136
137 /*******************************************************************************
138 ********************** Configuration BOARD_BootClockRUN ***********************
139 ******************************************************************************/
140 /* clang-format off */
141 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
142 !!Configuration
143 name: BOARD_BootClockRUN
144 called_from_default_init: true
145 outputs:
146 - {id: Core_clock.outFreq, value: 48 MHz}
147 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
148 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
149 - {id: LPO_clock.outFreq, value: 1 kHz}
150 - {id: OSC32KCLK.outFreq, value: 32.768 kHz}
151 - {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
152 - {id: SIRC_CLK.outFreq, value: 8 MHz}
153 - {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
154 - {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
155 - {id: SOSC_CLK.outFreq, value: 32.768 kHz}
156 - {id: Slow_clock.outFreq, value: 24 MHz}
157 - {id: System_clock.outFreq, value: 48 MHz}
158 settings:
159 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
160 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
161 - {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
162 - {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
163 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
164 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
165 - {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
166 sources:
167 - {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
168 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
169 /* clang-format on */
170
171 /*******************************************************************************
172 * Variables for BOARD_BootClockRUN configuration
173 ******************************************************************************/
174 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
175 {
176 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
177 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
178 .reserved1 = 0,
179 .reserved2 = 0,
180 .reserved3 = 0,
181 #endif
182 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
183 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
184 .reserved4 = 0,
185 #endif
186 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
187 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
188 .reserved5 = 0,
189 #endif
190 };
191 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
192 {
193 .freq = 32768U, /* System Oscillator frequency: 32768Hz */
194 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
195 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
196 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
197 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
198 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
199 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
200 };
201 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
202 {
203 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
204 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
205 .div3 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 3: divided by 2 */
206 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
207 };
208 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
209 {
210 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
211 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
212 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
213 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
214 .trimConfig = NULL, /* Fast IRC Trim disabled */
215 };
216 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
217 {
218 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
219 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
220 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
221 .div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
222 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
223 .prediv = 0, /* Divided by 1 */
224 .mult = 0, /* Multiply Factor is 16 */
225 };
226 /*******************************************************************************
227 * Code for BOARD_BootClockRUN configuration
228 ******************************************************************************/
BOARD_BootClockRUN(void)229 void BOARD_BootClockRUN(void)
230 {
231 scg_sys_clk_config_t curConfig;
232
233 /* Init SOSC according to board configuration. */
234 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
235 /* Set the XTAL0 frequency based on board settings. */
236 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
237 /* Init FIRC. */
238 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
239 /* Init SIRC. */
240 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
241 /* Set SCG to FIRC mode. */
242 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
243 /* Wait for clock source switch finished. */
244 do
245 {
246 CLOCK_GetCurSysClkConfig(&curConfig);
247 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
248 /* Set SystemCoreClock variable. */
249 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
250 }
251
252 /*******************************************************************************
253 ********************* Configuration BOARD_BootClockHSRUN **********************
254 ******************************************************************************/
255 /* clang-format off */
256 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
257 !!Configuration
258 name: BOARD_BootClockHSRUN
259 outputs:
260 - {id: CLKOUT.outFreq, value: 8 MHz}
261 - {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
262 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
263 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
264 - {id: LPO_clock.outFreq, value: 1 kHz}
265 - {id: OSC32KCLK.outFreq, value: 32.768 kHz}
266 - {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
267 - {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
268 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
269 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
270 - {id: SIRC_CLK.outFreq, value: 8 MHz}
271 - {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
272 - {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
273 - {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
274 - {id: SOSC_CLK.outFreq, value: 32.768 kHz}
275 - {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
276 - {id: System_clock.outFreq, value: 96 MHz}
277 settings:
278 - {id: SCGMode, value: SPLL}
279 - {id: powerMode, value: HSRUN}
280 - {id: CLKOUTConfig, value: 'yes'}
281 - {id: SCG.DIVSLOW.scale, value: '4'}
282 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
283 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
284 - {id: SCG.PREDIV.scale, value: '4'}
285 - {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
286 - {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
287 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
288 - {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
289 - {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
290 - {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
291 - {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
292 - {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
293 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
294 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
295 - {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
296 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
297 sources:
298 - {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
299 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
300 /* clang-format on */
301
302 /*******************************************************************************
303 * Variables for BOARD_BootClockHSRUN configuration
304 ******************************************************************************/
305 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
306 {
307 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
308 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
309 .reserved1 = 0,
310 .reserved2 = 0,
311 .reserved3 = 0,
312 #endif
313 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
314 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
315 .reserved4 = 0,
316 #endif
317 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
318 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
319 .reserved5 = 0,
320 #endif
321 };
322 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
323 {
324 .freq = 32768U, /* System Oscillator frequency: 32768Hz */
325 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
326 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
327 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
328 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
329 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
330 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
331 };
332 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
333 {
334 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
335 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
336 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
337 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
338 };
339 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
340 {
341 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
342 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
343 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
344 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
345 .trimConfig = NULL, /* Fast IRC Trim disabled */
346 };
347 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
348 {
349 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
350 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
351 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
352 .div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
353 .src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
354 .prediv = 3, /* Divided by 4 */
355 .mult = 0, /* Multiply Factor is 16 */
356 };
357 /*******************************************************************************
358 * Code for BOARD_BootClockHSRUN configuration
359 ******************************************************************************/
BOARD_BootClockHSRUN(void)360 void BOARD_BootClockHSRUN(void)
361 {
362 scg_sys_clk_config_t curConfig;
363
364 /* Init SOSC according to board configuration. */
365 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
366 /* Set the XTAL0 frequency based on board settings. */
367 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
368 /* Init FIRC. */
369 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
370 /* Init SIRC. */
371 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
372 /* Init SysPll. */
373 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
374 /* Set HSRUN power mode. */
375 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
376 SMC_SetPowerModeHsrun(SMC);
377 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
378 {
379 }
380
381 /* Set SCG to SPLL mode. */
382 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
383 /* Wait for clock source switch finished. */
384 do
385 {
386 CLOCK_GetCurSysClkConfig(&curConfig);
387 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
388 /* Set SystemCoreClock variable. */
389 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
390 /* Set SCG CLKOUT selection. */
391 CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
392 }
393
394 /*******************************************************************************
395 ********************* Configuration BOARD_BootClockVLPR ***********************
396 ******************************************************************************/
397 /* clang-format off */
398 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
399 !!Configuration
400 name: BOARD_BootClockVLPR
401 outputs:
402 - {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
403 - {id: LPO_clock.outFreq, value: 1 kHz}
404 - {id: SIRC_CLK.outFreq, value: 8 MHz}
405 - {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
406 - {id: System_clock.outFreq, value: 8 MHz}
407 settings:
408 - {id: SCGMode, value: SIRC}
409 - {id: powerMode, value: VLPR}
410 - {id: SCG.DIVSLOW.scale, value: '8'}
411 - {id: SCG.SCSSEL.sel, value: SCG.SIRC}
412 - {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
413 sources:
414 - {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
415 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
416 /* clang-format on */
417
418 /*******************************************************************************
419 * Variables for BOARD_BootClockVLPR configuration
420 ******************************************************************************/
421 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
422 {
423 .divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
424 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
425 .reserved1 = 0,
426 .reserved2 = 0,
427 .reserved3 = 0,
428 #endif
429 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
430 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
431 .reserved4 = 0,
432 #endif
433 .src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
434 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
435 .reserved5 = 0,
436 #endif
437 };
438 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
439 {
440 .freq = 0U, /* System Oscillator frequency: 0Hz */
441 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
442 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
443 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
444 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
445 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
446 .workMode = kSCG_SysOscModeExt, /* Use external clock */
447 };
448 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
449 {
450 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
451 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
452 .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
453 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
454 };
455 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
456 {
457 .enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
458 .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
459 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
460 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
461 .trimConfig = NULL, /* Fast IRC Trim disabled */
462 };
463 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
464 {
465 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
466 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
467 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
468 .div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
469 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
470 .prediv = 0, /* Divided by 1 */
471 .mult = 0, /* Multiply Factor is 16 */
472 };
473 /*******************************************************************************
474 * Code for BOARD_BootClockVLPR configuration
475 ******************************************************************************/
BOARD_BootClockVLPR(void)476 void BOARD_BootClockVLPR(void)
477 {
478 /* Init FIRC. */
479 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
480 /* Init SIRC. */
481 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
482 /* Allow SMC all power modes. */
483 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
484 /* Set VLPR power mode. */
485 SMC_SetPowerModeVlpr(SMC);
486 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
487 {
488 }
489 /* Set SystemCoreClock variable. */
490 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
491 }
492
493
