1 /*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v6.0
34 processor: K32L2A41xxxxA
35 package_id: K32L2A41VLL1A
36 mcu_data: ksdk2_0
37 processor_version: 0.0.0
38 board: FRDM-K32L2A4S
39 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40 /* clang-format on */
41
42 #include "fsl_smc.h"
43 #include "clock_config.h"
44
45 /*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48 #define SCG_CLKOUTCNFG_SIRC 2U /*!< SCG CLKOUT clock select: Slow IRC */
49 #define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
50 #define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
51 #define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
52
53 /*******************************************************************************
54 * Variables
55 ******************************************************************************/
56 /* System clock frequency. */
57 extern uint32_t SystemCoreClock;
58
59 /*******************************************************************************
60 * Code
61 ******************************************************************************/
62 /*FUNCTION**********************************************************************
63 *
64 * Function Name : CLOCK_CONFIG_SetScgOutSel
65 * Description : Set the SCG clock out select (CLKOUTSEL).
66 * Param setting : The selected clock source.
67 *
68 *END**************************************************************************/
CLOCK_CONFIG_SetScgOutSel(uint8_t setting)69 static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
70 {
71 SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
72 }
73
74 /*FUNCTION**********************************************************************
75 *
76 * Function Name : CLOCK_CONFIG_FircSafeConfig
77 * Description : This function is used to safely configure FIRC clock.
78 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
79 * Before setting FIRC, change to use SIRC as system clock,
80 * then configure FIRC. After FIRC is set, change back to use FIRC
81 * in case SIRC need to be configured.
82 * Param fircConfig : FIRC configuration.
83 *
84 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)85 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
86 {
87 scg_sys_clk_config_t curConfig;
88 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
89 .div1 = kSCG_AsyncClkDisable,
90 .div3 = kSCG_AsyncClkDivBy2,
91 .range = kSCG_SircRangeHigh};
92 scg_sys_clk_config_t sysClkSafeConfigSource = {
93 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
94 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
95 .reserved1 = 0,
96 .reserved2 = 0,
97 .reserved3 = 0,
98 #endif
99 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
100 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
101 .reserved4 = 0,
102 #endif
103 .src = kSCG_SysClkSrcSirc, /* System clock source */
104 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
105 .reserved5 = 0,
106 #endif
107 };
108 /* Init Sirc. */
109 CLOCK_InitSirc(&scgSircConfig);
110 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
111 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
112 /* Wait for clock source switch finished. */
113 do
114 {
115 CLOCK_GetCurSysClkConfig(&curConfig);
116 } while (curConfig.src != sysClkSafeConfigSource.src);
117
118 /* Init Firc. */
119 CLOCK_InitFirc(fircConfig);
120 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
121 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
122 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
123 /* Wait for clock source switch finished. */
124 do
125 {
126 CLOCK_GetCurSysClkConfig(&curConfig);
127 } while (curConfig.src != sysClkSafeConfigSource.src);
128 }
129
130 /*******************************************************************************
131 ************************ BOARD_InitBootClocks function ************************
132 ******************************************************************************/
BOARD_InitBootClocks(void)133 void BOARD_InitBootClocks(void)
134 {
135 BOARD_BootClockHSRUN();
136 }
137
138 /*******************************************************************************
139 ********************* Configuration BOARD_BootClockHSRUN **********************
140 ******************************************************************************/
141 /* clang-format off */
142 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
143 !!Configuration
144 name: BOARD_BootClockHSRUN
145 called_from_default_init: true
146 outputs:
147 - {id: CLKOUT.outFreq, value: 8 MHz}
148 - {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
149 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
150 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
151 - {id: LPO_clock.outFreq, value: 1 kHz}
152 - {id: OSC32KCLK.outFreq, value: 32.768 kHz}
153 - {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
154 - {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
155 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
156 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
157 - {id: SIRC_CLK.outFreq, value: 8 MHz}
158 - {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
159 - {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
160 - {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
161 - {id: SOSC_CLK.outFreq, value: 32.768 kHz}
162 - {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
163 - {id: System_clock.outFreq, value: 96 MHz}
164 settings:
165 - {id: SCGMode, value: SPLL}
166 - {id: powerMode, value: HSRUN}
167 - {id: CLKOUTConfig, value: 'yes'}
168 - {id: SCG.DIVSLOW.scale, value: '4'}
169 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
170 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
171 - {id: SCG.PREDIV.scale, value: '4'}
172 - {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
173 - {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
174 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
175 - {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
176 - {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
177 - {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
178 - {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
179 - {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
180 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
181 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
182 - {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
183 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
184 sources:
185 - {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
186 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
187 /* clang-format on */
188
189 /*******************************************************************************
190 * Variables for BOARD_BootClockHSRUN configuration
191 ******************************************************************************/
192 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN = {
193 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
194 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
195 .reserved1 = 0,
196 .reserved2 = 0,
197 .reserved3 = 0,
198 #endif
199 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
200 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
201 .reserved4 = 0,
202 #endif
203 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
204 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
205 .reserved5 = 0,
206 #endif
207 };
208 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN = {
209 .freq = 32768U, /* System Oscillator frequency: 32768Hz */
210 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk, /* Enable System OSC clock, Enable OSCERCLK */
211 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
212 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
213 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
214 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
215 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
216 };
217 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = {
218 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
219 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
220 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
221 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
222 };
223 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN = {
224 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
225 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
226 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
227 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
228 .trimConfig = NULL, /* Fast IRC Trim disabled */
229 };
230 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN = {
231 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
232 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
233 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
234 .div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
235 .src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
236 .prediv = 3, /* Divided by 4 */
237 .mult = 0, /* Multiply Factor is 16 */
238 };
239 /*******************************************************************************
240 * Code for BOARD_BootClockHSRUN configuration
241 ******************************************************************************/
BOARD_BootClockHSRUN(void)242 void BOARD_BootClockHSRUN(void)
243 {
244 scg_sys_clk_config_t curConfig;
245
246 /* Init SOSC according to board configuration. */
247 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
248 /* Set the XTAL0 frequency based on board settings. */
249 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
250 /* Init FIRC. */
251 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
252 /* Init SIRC. */
253 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
254 /* Init SysPll. */
255 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
256 /* Set HSRUN power mode. */
257 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
258 SMC_SetPowerModeHsrun(SMC);
259 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
260 {
261 }
262
263 /* Set SCG to SPLL mode. */
264 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
265 /* Wait for clock source switch finished. */
266 do
267 {
268 CLOCK_GetCurSysClkConfig(&curConfig);
269 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
270 /* Set SystemCoreClock variable. */
271 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
272 /* Set SCG CLKOUT selection. */
273 CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
274 }
275
276 /*******************************************************************************
277 ********************* Configuration BOARD_BootClockVLPR ***********************
278 ******************************************************************************/
279 /* clang-format off */
280 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
281 !!Configuration
282 name: BOARD_BootClockVLPR
283 outputs:
284 - {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
285 - {id: LPO_clock.outFreq, value: 1 kHz}
286 - {id: SIRC_CLK.outFreq, value: 8 MHz}
287 - {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
288 - {id: System_clock.outFreq, value: 8 MHz}
289 settings:
290 - {id: SCGMode, value: SIRC}
291 - {id: powerMode, value: VLPR}
292 - {id: SCG.DIVSLOW.scale, value: '8'}
293 - {id: SCG.SCSSEL.sel, value: SCG.SIRC}
294 - {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
295 sources:
296 - {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
297 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
298 /* clang-format on */
299
300 /*******************************************************************************
301 * Variables for BOARD_BootClockVLPR configuration
302 ******************************************************************************/
303 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
304 .divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
305 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
306 .reserved1 = 0,
307 .reserved2 = 0,
308 .reserved3 = 0,
309 #endif
310 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
311 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
312 .reserved4 = 0,
313 #endif
314 .src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
315 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
316 .reserved5 = 0,
317 #endif
318 };
319 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
320 .freq = 0U, /* System Oscillator frequency: 0Hz */
321 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
322 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
323 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
324 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
325 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
326 .workMode = kSCG_SysOscModeExt, /* Use external clock */
327 };
328 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
329 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
330 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
331 .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
332 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
333 };
334 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
335 .enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower, /* Enable FIRC clock, Enable FIRC in low power mode */
336 .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
337 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
338 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
339 .trimConfig = NULL, /* Fast IRC Trim disabled */
340 };
341 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR = {
342 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
343 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
344 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
345 .div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
346 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
347 .prediv = 0, /* Divided by 1 */
348 .mult = 0, /* Multiply Factor is 16 */
349 };
350 /*******************************************************************************
351 * Code for BOARD_BootClockVLPR configuration
352 ******************************************************************************/
BOARD_BootClockVLPR(void)353 void BOARD_BootClockVLPR(void)
354 {
355 /* Init FIRC. */
356 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
357 /* Init SIRC. */
358 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
359 /* Allow SMC all power modes. */
360 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
361 /* Set VLPR power mode. */
362 SMC_SetPowerModeVlpr(SMC);
363 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
364 {
365 }
366 /* Set SystemCoreClock variable. */
367 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
368 }
369
