1 /*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v7.0
34 processor: K32L2A31xxxxA
35 mcu_data: ksdk2_0
36 processor_version: 0.10.4
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38 /* clang-format on */
39
40 #include "clock_config.h"
41
42 /*******************************************************************************
43 * Definitions
44 ******************************************************************************/
45 #define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
46 #define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
47 #define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
48
49 /*******************************************************************************
50 * Variables
51 ******************************************************************************/
52 /* System clock frequency. */
53 extern uint32_t SystemCoreClock;
54
55 /*******************************************************************************
56 * Code
57 ******************************************************************************/
58 /*FUNCTION**********************************************************************
59 *
60 * Function Name : CLOCK_CONFIG_FircSafeConfig
61 * Description : This function is used to safely configure FIRC clock.
62 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
63 * Before setting FIRC, change to use SIRC as system clock,
64 * then configure FIRC. After FIRC is set, change back to use FIRC
65 * in case SIRC need to be configured.
66 * Param fircConfig : FIRC configuration.
67 *
68 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)69 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
70 {
71 scg_sys_clk_config_t curConfig;
72 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
73 .div1 = kSCG_AsyncClkDisable,
74 .div3 = kSCG_AsyncClkDivBy2,
75 .range = kSCG_SircRangeHigh};
76 scg_sys_clk_config_t sysClkSafeConfigSource = {
77 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
78 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
79 .reserved1 = 0,
80 .reserved2 = 0,
81 .reserved3 = 0,
82 #endif
83 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
84 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
85 .reserved4 = 0,
86 #endif
87 .src = kSCG_SysClkSrcSirc, /* System clock source */
88 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
89 .reserved5 = 0,
90 #endif
91 };
92 /* Init Sirc. */
93 CLOCK_InitSirc(&scgSircConfig);
94 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
95 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
96 /* Wait for clock source switch finished. */
97 do
98 {
99 CLOCK_GetCurSysClkConfig(&curConfig);
100 } while (curConfig.src != sysClkSafeConfigSource.src);
101
102 /* Init Firc. */
103 CLOCK_InitFirc(fircConfig);
104 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
105 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
106 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
107 /* Wait for clock source switch finished. */
108 do
109 {
110 CLOCK_GetCurSysClkConfig(&curConfig);
111 } while (curConfig.src != sysClkSafeConfigSource.src);
112 }
113
114 /*******************************************************************************
115 ************************ BOARD_InitBootClocks function ************************
116 ******************************************************************************/
BOARD_InitBootClocks(void)117 void BOARD_InitBootClocks(void)
118 {
119 BOARD_BootClockRUN();
120 }
121
122 /*******************************************************************************
123 ********************** Configuration BOARD_BootClockRUN ***********************
124 ******************************************************************************/
125 /* clang-format off */
126 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
127 !!Configuration
128 name: BOARD_BootClockRUN
129 called_from_default_init: true
130 outputs:
131 - {id: Core_clock.outFreq, value: 48 MHz}
132 - {id: LPO_clock.outFreq, value: 1 kHz}
133 - {id: SIRC_CLK.outFreq, value: 8 MHz}
134 - {id: Slow_clock.outFreq, value: 24 MHz}
135 - {id: System_clock.outFreq, value: 48 MHz}
136 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
137 /* clang-format on */
138
139 /*******************************************************************************
140 * Variables for BOARD_BootClockRUN configuration
141 ******************************************************************************/
142 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
143 {
144 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
145 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
146 .reserved1 = 0,
147 .reserved2 = 0,
148 .reserved3 = 0,
149 #endif
150 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
151 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
152 .reserved4 = 0,
153 #endif
154 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
155 #if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
156 .reserved5 = 0,
157 #endif
158 };
159 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
160 {
161 .freq = 0U, /* System Oscillator frequency: 0Hz */
162 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
163 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
164 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
165 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
166 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
167 .workMode = kSCG_SysOscModeExt, /* Use external clock */
168 };
169 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
170 {
171 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
172 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
173 .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
174 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
175 };
176 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
177 {
178 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
179 .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
180 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
181 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
182 .trimConfig = NULL, /* Fast IRC Trim disabled */
183 };
184 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
185 {
186 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
187 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
188 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
189 .div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
190 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
191 .prediv = 0, /* Divided by 1 */
192 .mult = 0, /* Multiply Factor is 16 */
193 };
194 /*******************************************************************************
195 * Code for BOARD_BootClockRUN configuration
196 ******************************************************************************/
BOARD_BootClockRUN(void)197 void BOARD_BootClockRUN(void)
198 {
199 scg_sys_clk_config_t curConfig;
200
201 /* Init FIRC. */
202 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
203 /* Init SIRC. */
204 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
205 /* Set SCG to FIRC mode. */
206 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
207 /* Wait for clock source switch finished. */
208 do
209 {
210 CLOCK_GetCurSysClkConfig(&curConfig);
211 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
212 /* Set SystemCoreClock variable. */
213 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
214 }
215
216
