Searched refs:uint32_t (Results 1 – 25 of 431) sorted by relevance
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23 volatile uint32_t SOFT_RESET;24 volatile uint32_t LFWF_R0;25 volatile uint32_t LOVR_R0;26 volatile uint32_t LPIP_R0;27 volatile uint32_t L64_R0;28 volatile uint32_t L64_R1;29 volatile uint32_t L64_R2;30 volatile uint32_t L64_R3;31 volatile uint32_t L64_R4;32 volatile uint32_t L64_R5;[all …]
14 uint32_t ID:29; /*!< bit: 0..28 Identifier */15 uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */16 uint32_t XTD:1; /*!< bit: 30 Extended Identifier */17 uint32_t ESI:1; /*!< bit: 31 Error State Indicator */19 uint32_t reg; /*!< Type used for register access */27 uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */28 uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */29 uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */30 uint32_t FDF:1; /*!< bit: 21 FD Format */31 uint32_t :2; /*!< bit: 22..23 Reserved */[all …]
14 uint32_t SWRST:1; /*!< bit: 0 Software Reset */15 uint32_t ENABLE:1; /*!< bit: 1 Enable */16 uint32_t :3; /*!< bit: 2.. 4 Reserved */17 uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */18 uint32_t :1; /*!< bit: 7 Reserved */19 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */20 uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */21 uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */22 uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */23 …uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) …[all …]
14 uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 */16 uint32_t reg; /*!< Type used for register access */24 uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 */25 uint32_t :16; /*!< bit: 16..31 Reserved */27 uint32_t reg; /*!< Type used for register access */35 uint32_t :1; /*!< bit: 0 Reserved */36 uint32_t LBL:1; /*!< bit: 1 Loop Back Local */37 uint32_t RXEN:1; /*!< bit: 2 Receive Enable */38 uint32_t TXEN:1; /*!< bit: 3 Transmit Enable */39 uint32_t MPE:1; /*!< bit: 4 Management Port Enable */[all …]
14 uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */15 uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */16 uint32_t :8; /*!< bit: 24..31 Reserved */18 uint32_t reg; /*!< Type used for register access */59 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */60 __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */61 __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */62 __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */63 __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */64 __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */[all …]
28 uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */29 uint32_t :3; /*!< bit: 13..15 Reserved */30 uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */31 uint32_t :11; /*!< bit: 21..31 Reserved */33 uint32_t reg; /*!< Type used for register access */41 uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */42 uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */43 uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */44 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */45 uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */[all …]
14 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */15 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */16 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */17 uint32_t :5; /*!< bit: 3.. 7 Reserved */18 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */19 uint32_t :1; /*!< bit: 9 Reserved */20 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */21 uint32_t :21; /*!< bit: 11..31 Reserved */23 uint32_t reg; /*!< Type used for register access */31 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */[all …]
13 uint32_t reg; /*!< Type used for register access */21 uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */22 uint32_t WRAP:1; /*!< bit: 1 Region Wrap */23 uint32_t EOM:1; /*!< bit: 2 End of Monitoring */24 uint32_t :1; /*!< bit: 3 Reserved */25 uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */26 uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */27 uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */28 uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */29 … uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */[all …]
42 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */44 uint32_t reg; /*!< Type used for register access */52 uint32_t CHKINIT:32; /*!< bit: 0..31 CRC Checksum Initial Value */55 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */57 uint32_t reg; /*!< Type used for register access */65 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */67 uint32_t reg; /*!< Type used for register access */75 uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */76 uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */77 uint32_t :4; /*!< bit: 2.. 5 Reserved */[all …]
14 uint32_t SWRST:1; /*!< bit: 0 Software Reset */15 uint32_t ENABLE:1; /*!< bit: 1 Enable */16 uint32_t :22; /*!< bit: 2..23 Reserved */17 uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */18 uint32_t :7; /*!< bit: 25..31 Reserved */20 uint32_t reg; /*!< Type used for register access */28 uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */29 uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */30 uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */31 uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */[all …]
67 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */68 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */69 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */70 uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */71 uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */72 uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */73 uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */74 uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */75 uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */76 uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */[all …]
14 uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */15 uint32_t :1; /*!< bit: 7 Reserved */16 uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */17 uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */18 uint32_t :2; /*!< bit: 12..13 Reserved */19 uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */20 uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */21 uint32_t :16; /*!< bit: 16..31 Reserved */23 uint32_t reg; /*!< Type used for register access */90 uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */[all …]
68 uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */69 uint32_t ADDR:30; /*!< bit: 2..31 Address */71 uint32_t reg; /*!< Type used for register access */79 uint32_t :2; /*!< bit: 0.. 1 Reserved */80 uint32_t LENGTH:30; /*!< bit: 2..31 Length */82 uint32_t reg; /*!< Type used for register access */90 uint32_t DATA:32; /*!< bit: 0..31 Data */92 uint32_t reg; /*!< Type used for register access */100 uint32_t DATA:32; /*!< bit: 0..31 Data */102 uint32_t reg; /*!< Type used for register access */[all …]
131 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */132 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */133 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */134 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */135 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */136 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */137 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */138 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */139 uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */140 uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */[all …]
14 uint32_t :1; /*!< bit: 0 Reserved */15 uint32_t DCGCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ /* MDS */16 uint32_t :2; /*!< bit: 2.. 3 Reserved */17 uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */18 uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */19 uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */20 uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */21 uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */22 uint32_t :18; /*!< bit: 14..31 Reserved */24 uint32_t reg; /*!< Type used for register access */[all …]
35 uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */36 uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */37 uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */38 uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */39 uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */40 uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */41 uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */42 uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */43 uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */44 uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */[all …]
14 uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */15 uint32_t :3; /*!< bit: 1.. 3 Reserved */16 uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */17 uint32_t :2; /*!< bit: 6.. 7 Reserved */18 uint32_t SCALE:1; /*!< bit: 8 Scale data */19 uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */20 uint32_t HALFS:1; /*!< bit: 10 Half Sampling */21 uint32_t FRSTS:1; /*!< bit: 11 First sample */22 uint32_t :4; /*!< bit: 12..15 Reserved */23 uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */[all …]
31 __IO uint32_t NETWORK_CONTROL; /* 0x0000 */32 __IO uint32_t NETWORK_CONFIG; /* 0x0004 */33 __I uint32_t NETWORK_STATUS; /* 0x0008 */34 __IO uint32_t USER_IO; /* 0x000C */35 __IO uint32_t DMA_CONFIG; /* 0x0010 */36 __IO uint32_t TRANSMIT_STATUS; /* 0x0014 */37 __IO uint32_t RECEIVE_Q_PTR; /* 0x0018 */38 __IO uint32_t TRANSMIT_Q_PTR; /* 0x001C */39 __IO uint32_t RECEIVE_STATUS; /* 0x0020 */40 __IO uint32_t INT_STATUS; /* 0x0024 */[all …]
229 __IO uint32_t SOFT_RESET_DDR_PHY;234 __I uint32_t reserved_01 :6;236 __I uint32_t reserved_02 :7;237 __I uint32_t BLOCKID_DDR_PHY :16;242 __IO uint32_t DDRPHY_MODE;245 __IO uint32_t DDRMODE :3;246 __IO uint32_t ECC :1;247 __IO uint32_t CRC :1;248 __IO uint32_t Bus_width :3;249 __IO uint32_t DMI_DBI :1;[all …]
45 __IO uint32_t CFG_MANUAL_ADDRESS_MAP;48 __IO uint32_t cfg_manual_address_map :1;49 __I uint32_t reserved :31;54 __IO uint32_t CFG_CHIPADDR_MAP;57 __IO uint32_t cfg_chipaddr_map :24;58 __I uint32_t reserved :8;63 __IO uint32_t CFG_CIDADDR_MAP;66 __IO uint32_t cfg_cidaddr_map :18;67 __I uint32_t reserved :14;72 __IO uint32_t CFG_MB_AUTOPCH_COL_BIT_POS_LOW;[all …]
258 …__IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control …261 …__IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode …262 uint32_t : 1;263 …__IO uint32_t TEST : 1; /*!< [2..2] Test bit …264 …__IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode …269 …__IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Regist…279 …__IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate …284 …__IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock do…287 …__IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Cloc…292 …__IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register …[all …]
204 #define MCHP_GPIO_CTRL_PUD_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_PUD_POS)\206 #define MCHP_GPIO_CTRL_PUD_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_PUD_MASK0)\218 #define MCHP_GPIO_CTRL_PWRG_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_PWRG_POS)\220 #define MCHP_GPIO_CTRL_PWRG_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_PWRG_MASK0)\234 #define MCHP_GPIO_CTRL_IDET_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_IDET_POS)\236 #define MCHP_GPIO_CTRL_IDET_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_IDET_MASK0)\246 #define MCHP_GPIO_CTRL_BUFT_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_BUFT_POS)\248 #define MCHP_GPIO_CTRL_BUFT_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_BUFT_MASK0)\258 #define MCHP_GPIO_CTRL_DIR_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_DIR_POS)\260 #define MCHP_GPIO_CTRL_DIR_SET(x) (((uint32_t)(x) & MCHP_GPIO_CTRL_DIR_MASK0)\[all …]
538 __IO uint32_t N_ID:3;539 __IO uint32_t ID:29;547 __IO uint32_t DATAHIGH;548 __IO uint32_t DATALOW;557 __IO uint32_t L; /* 32 bit flag */561 __IO uint32_t NA0:16;562 __IO uint32_t DLC:4; 563 __IO uint32_t IDE:1; 564 __IO uint32_t RTR:1; 565 __IO uint32_t NA1:10;[all …]
17 …__IOM uint32_t DEV_CTRL; /*!< (@ 0x00000000) Target device control register …18 …__IOM uint32_t DEV_ADDR; /*!< (@ 0x00000004) Target device address register …19 …__IM uint32_t HW_CAP; /*!< (@ 0x00000008) I3C Host controller hardware cap…20 …__IOM uint32_t CMD; /*!< (@ 0x0000000C) Command register …21 …__IOM uint32_t RESP; /*!< (@ 0x00000010) Response register …24 …__OM uint32_t TX_DATA; /*!< (@ 0x00000014) Transmit data register …25 …__IM uint32_t RX_DATA; /*!< (@ 0x00000014) Receive data register …27 …__IOM uint32_t IBI_QUE_STS; /*!< (@ 0x00000018) IBI Queue status register …28 …__IOM uint32_t QUE_THLD_CTRL; /*!< (@ 0x0000001C) Queue threshold control register…29 …__IOM uint32_t DB_THLD_CTRL; /*!< (@ 0x00000020) Data buffer threshold control re…[all …]
