1 /******************************************************************************* 2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * PolarFire and PolarFire SoC PCIe subsystem Core Registers data structures. 7 * 8 */ 9 #ifndef PF_PCIESS_REGS_H_ 10 #define PF_PCIESS_REGS_H_ 11 12 #include <stdint.h> 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 /*------------------------------------------------------------------------------ 19 PCS LANE Registers. 20 */ 21 typedef struct 22 { 23 volatile uint32_t SOFT_RESET; 24 volatile uint32_t LFWF_R0; 25 volatile uint32_t LOVR_R0; 26 volatile uint32_t LPIP_R0; 27 volatile uint32_t L64_R0; 28 volatile uint32_t L64_R1; 29 volatile uint32_t L64_R2; 30 volatile uint32_t L64_R3; 31 volatile uint32_t L64_R4; 32 volatile uint32_t L64_R5; 33 volatile uint32_t L64_R6; 34 volatile uint32_t L64_R7; 35 volatile uint32_t L64_R8; 36 volatile uint32_t L64_R9; 37 volatile uint32_t L64_R10; 38 volatile uint32_t RESERVED0; 39 volatile uint32_t L8_R0; 40 volatile uint32_t RESERVED1[3]; 41 volatile uint32_t LNTV_R0; 42 volatile uint32_t RESERVED2; 43 volatile uint32_t LCLK_R0; 44 volatile uint32_t LCLK_R1; 45 volatile uint32_t RESERVED3[2]; 46 volatile uint32_t LRST_R0; 47 volatile uint32_t LRST_OPT; 48 volatile uint32_t RESERVED4[2]; 49 volatile uint32_t OOB_R0; 50 volatile uint32_t OOB_R1; 51 volatile uint32_t OOB_R2; 52 volatile uint32_t OOB_R3; 53 volatile uint32_t PMA_CTRL_R0; 54 volatile uint32_t PMA_CTRL_R1; 55 volatile uint32_t PMA_CTRL_R2; 56 volatile uint32_t MSTR_CTRL; 57 58 } PCS_LANE_TypeDef; 59 60 /*------------------------------------------------------------------------------ 61 PCS Common Registers. 62 */ 63 typedef struct 64 { 65 volatile uint32_t SOFT_RESET; 66 volatile uint32_t GSSCLK_CTRL; 67 volatile uint32_t QRST_R0; 68 volatile uint32_t QDBG_R0; 69 70 } PCS_CMN_TypeDef; 71 72 /*------------------------------------------------------------------------------ 73 PMA Lane Registers. 74 */ 75 typedef struct 76 { 77 volatile uint32_t SOFT_RESET; 78 volatile uint32_t DES_CDR_CTRL_1; 79 volatile uint32_t DES_CDR_CTRL_2; 80 volatile uint32_t DES_CDR_CTRL_3; 81 volatile uint32_t DES_DFEEM_CTRL_1; 82 volatile uint32_t DES_DFEEM_CTRL_2; 83 volatile uint32_t DES_DFEEM_CTRL_3; 84 volatile uint32_t RESERVED0; 85 volatile uint32_t DES_DFE_CTRL_1; 86 volatile uint32_t DES_DFE_CTRL_2; 87 volatile uint32_t DES_EM_CTRL_1; 88 volatile uint32_t DES_EM_CTRL_2; 89 volatile uint32_t DES_IN_TERM; 90 volatile uint32_t DES_PKDET; 91 volatile uint32_t DES_RTL_EM; 92 volatile uint32_t DES_RTL_LOCK_CTR; 93 volatile uint32_t DES_RXPLL_DIV; 94 volatile uint32_t DES_TEST_BUS; 95 volatile uint32_t DES_CLK_CTRL; 96 volatile uint32_t DES_RSTPD; 97 volatile uint32_t DES_RTL_ERR_CHK; 98 volatile uint32_t DES_PCIE1_2_RXPLL_DIV; 99 volatile uint32_t DES_SATA1_2_RXPLL_DIV; 100 volatile uint32_t DES_SATA3_RXPLL_DIV; 101 volatile uint32_t RESERVED1[4]; 102 volatile uint32_t SER_CTRL; 103 volatile uint32_t SER_CLK_CTRL; 104 volatile uint32_t SER_RSTPD; 105 volatile uint32_t SER_DRV_BYP; 106 volatile uint32_t SER_RXDET_CTRL; 107 volatile uint32_t SER_RXDET_OUT; 108 volatile uint32_t SER_STATIC_LSB; 109 volatile uint32_t SER_STATIC_MSB; 110 volatile uint32_t SER_TERM_CTRL; 111 volatile uint32_t SER_TEST_BUS; 112 volatile uint32_t SER_DRV_DATA_CTRL; 113 volatile uint32_t SER_DRV_CTRL; 114 volatile uint32_t SER_DRV_CTRL_SEL; 115 volatile uint32_t SER_DRV_CTRL_M0; 116 volatile uint32_t SER_DRV_CTRL_M1; 117 volatile uint32_t SER_DRV_CTRL_M2; 118 volatile uint32_t SER_DRV_CTRL_M3; 119 volatile uint32_t SER_DRV_CTRL_M4; 120 volatile uint32_t SER_DRV_CTRL_M5; 121 volatile uint32_t RESERVED2; 122 volatile uint32_t SERDES_RTL_CTRL; 123 volatile uint32_t RESERVED3[3]; 124 volatile uint32_t DES_DFE_CAL_CTRL_0; 125 volatile uint32_t DES_DFE_CAL_CTRL_1; 126 volatile uint32_t DES_DFE_CAL_CTRL_2; 127 volatile uint32_t DES_DFE_CAL_CMD; 128 volatile uint32_t DES_DFE_CAL_BYPASS; 129 volatile uint32_t DES_DFE_CAL_EYE_DATA; 130 volatile uint32_t DES_DFE_CDRH0_MON; 131 volatile uint32_t DES_DFE_COEFF_MON_0; 132 volatile uint32_t DES_DFE_COEFF_MON_1; 133 volatile uint32_t DES_DFE_CAL_OS_MON; 134 volatile uint32_t DES_DFE_CAL_ST_0; 135 volatile uint32_t DES_DFE_CAL_ST_1; 136 volatile uint32_t DES_DFE_CAL_FLAG; 137 138 } PMA_LANE_TypeDef; 139 140 /*------------------------------------------------------------------------------ 141 TXPLL_SSC (PMA Common) Registers. 142 */ 143 typedef struct 144 { 145 volatile uint32_t SOFT_RESET; 146 volatile uint32_t TXPLL_CLKBUF; 147 volatile uint32_t TXPLL_CTRL; 148 volatile uint32_t TXPLL_CLK_SEL; 149 volatile uint32_t TXPLL_DIV_1; 150 volatile uint32_t TXPLL_DIV_2; 151 volatile uint32_t TXPLL_JA_1; 152 volatile uint32_t TXPLL_JA_2; 153 volatile uint32_t TXPLL_JA_3; 154 volatile uint32_t TXPLL_JA_4; 155 volatile uint32_t TXPLL_JA_5; 156 volatile uint32_t TXPLL_JA_6; 157 volatile uint32_t TXPLL_JA_7; 158 volatile uint32_t TXPLL_JA_8; 159 volatile uint32_t TXPLL_JA_9; 160 volatile uint32_t TXPLL_JA_10; 161 volatile uint32_t TXPLL_JA_RST; 162 volatile uint32_t SERDES_SSMOD; 163 volatile uint32_t RESERVED[2]; 164 volatile uint32_t SERDES_RTERM; 165 volatile uint32_t SERDES_RTT; 166 167 } TXPLL_SSC_TypeDef; 168 169 /*------------------------------------------------------------------------------ 170 TXPLL (QAUD - extpll) Registers. 171 */ 172 typedef struct 173 { 174 volatile uint32_t SOFT_RESET; 175 volatile uint32_t EXTPLL_CLKBUF; 176 volatile uint32_t EXTPLL_CTRL; 177 volatile uint32_t EXTPLL_CLK_SEL; 178 volatile uint32_t EXTPLL_DIV_1; 179 volatile uint32_t EXTPLL_DIV_2; 180 volatile uint32_t EXTPLL_JA_1; 181 volatile uint32_t EXTPLL_JA_2; 182 volatile uint32_t EXTPLL_JA_3; 183 volatile uint32_t EXTPLL_JA_4; 184 volatile uint32_t EXTPLL_JA_5; 185 volatile uint32_t EXTPLL_JA_6; 186 volatile uint32_t EXTPLL_JA_7; 187 volatile uint32_t EXTPLL_JA_8; 188 volatile uint32_t EXTPLL_JA_9; 189 volatile uint32_t EXTPLL_JA_10; 190 volatile uint32_t EXTPLL_JA_RST; 191 192 } TXPLL_TypeDef; 193 194 /*------------------------------------------------------------------------------ 195 PCIESS main Registers. 196 */ 197 typedef struct 198 { 199 volatile uint32_t SOFT_RESET; 200 volatile uint32_t OVRLY; 201 volatile uint32_t MAJOR; 202 volatile uint32_t INT_PIPE_CLK_CTRL; 203 volatile uint32_t EXT_PIPE_CLK_CTRL; 204 volatile uint32_t CLK_CTRL; 205 volatile uint32_t QMUX_R0; 206 volatile uint32_t RESERVED0[57]; 207 volatile uint32_t DLL_CTRL0; 208 volatile uint32_t DLL_CTRL1; 209 volatile uint32_t DLL_STAT0; 210 volatile uint32_t DLL_STAT1; 211 volatile uint32_t DLL_STAT2; 212 volatile uint32_t TEST_DLL; 213 volatile uint32_t RESERVED1[29]; 214 volatile uint32_t SPARE; 215 216 } PCIESS_MAIN_TypeDef; 217 218 /*------------------------------------------------------------------------------ 219 PCIE Control Registers. 220 */ 221 typedef struct 222 { 223 volatile uint32_t SOFT_RESET; 224 volatile uint32_t DEV_CONTROL; 225 volatile uint32_t CLOCK_CONTROL; 226 volatile uint32_t RESERVED0; 227 volatile uint32_t SOFT_RESET_DEBUG_INFO; 228 volatile uint32_t SOFT_RESET_CTLR; 229 volatile uint32_t RESERVED1[2]; 230 volatile uint32_t SEC_ERROR_EVENT_CNT; 231 volatile uint32_t DED_ERROR_EVENT_CNT; 232 volatile uint32_t SEC_ERROR_INT; 233 volatile uint32_t SEC_ERROR_INT_MASK; 234 volatile uint32_t DED_ERROR_INT; 235 volatile uint32_t DED_ERROR_INT_MASK; 236 volatile uint32_t ECC_CONTROL; 237 volatile uint32_t ECC_ERR_LOC; 238 volatile uint32_t RAM_MARGIN_1; 239 volatile uint32_t RAM_MARGIN_2; 240 volatile uint32_t RAM_POWER_CONTROL; 241 volatile uint32_t RESERVED2; 242 volatile uint32_t DEBUG_SEL; 243 volatile uint32_t RESERVED3[2]; 244 volatile uint32_t LTSSM_STATE; 245 volatile uint32_t PHY_COMMON_INTERFACE; 246 volatile uint32_t PL_TX_LANEIF_0; 247 volatile uint32_t PL_RX_LANEIF_0; 248 volatile uint32_t PL_WAKECLKREQ; 249 volatile uint32_t RESERVED4[4]; 250 volatile uint32_t PCICONF_PCI_IDS_OVERRIDE; 251 volatile uint32_t PCICONF_PCI_IDS_31_0; 252 volatile uint32_t PCICONF_PCI_IDS_63_32; 253 volatile uint32_t PCICONF_PCI_IDS_95_64; 254 volatile uint32_t RESERVED5[4]; 255 volatile uint32_t PCIE_PEX_DEV_LINK_SPC2; 256 volatile uint32_t PCIE_PEX_SPC; 257 volatile uint32_t RESERVED6[22]; 258 volatile uint32_t PCIE_AXI_MASTER_ATR_CFG0; 259 volatile uint32_t PCIE_AXI_MASTER_ATR_CFG1; 260 volatile uint32_t PCIE_AXI_MASTER_ATR_CFG2; 261 volatile uint32_t RESERVED7[5]; 262 volatile uint32_t AXI_SLAVE_PCIE_ATR_CFG0; 263 volatile uint32_t AXI_SLAVE_PCIE_ATR_CFG1; 264 volatile uint32_t AXI_SLAVE_PCIE_ATR_CFG2; 265 volatile uint32_t RESERVED8[5]; 266 volatile uint32_t PCIE_BAR_01; 267 volatile uint32_t PCIE_BAR_23; 268 volatile uint32_t PCIE_BAR_45; 269 volatile uint32_t PCIE_EVENT_INT; 270 volatile uint32_t RESERVED9[12]; 271 volatile uint32_t PCIE_BAR_WIN; 272 volatile uint32_t RESERVED10[703]; 273 volatile uint32_t TEST_BUS_IN_31_0; 274 volatile uint32_t TEST_BUS_IN_63_32; 275 276 } PCIE_CTRL_TypeDef; 277 278 /*------------------------------------------------------------------------------ 279 PCIE Bridge Control Registers. 280 */ 281 typedef struct 282 { 283 volatile uint32_t BRIDGE_VER; 284 volatile uint32_t BRIDGE_BUS; 285 volatile uint32_t BRIDGE_IMPL_IF; 286 volatile uint32_t RESERVED; 287 volatile uint32_t PCIE_IF_CONF; 288 volatile uint32_t PCIE_BASIC_CONF; 289 volatile uint32_t PCIE_BASIC_STATUS; 290 volatile uint32_t RESERVED0[2]; 291 volatile uint32_t AXI_SLVL_CONF; 292 volatile uint32_t RESERVED1[2]; 293 volatile uint32_t AXI_MST0_CONF; 294 volatile uint32_t AXI_SLV0_CONF; 295 volatile uint32_t RESERVED2[18]; 296 volatile uint32_t GEN_SETTINGS; 297 volatile uint32_t PCIE_CFGCTRL; 298 volatile uint32_t PCIE_PIPE_DW0; 299 volatile uint32_t PCIE_PIPE_DW1; 300 volatile uint32_t PCIE_VC_CRED_DW0; 301 volatile uint32_t PCIE_VC_CRED_DW1; 302 volatile uint32_t PCIE_PCI_IDS_DW0; 303 volatile uint32_t PCIE_PCI_IDS_DW1; 304 volatile uint32_t PCIE_PCI_IDS_DW2; 305 volatile uint32_t PCIE_PCI_LPM; 306 volatile uint32_t PCIE_PCI_IRQ_DW0; 307 volatile uint32_t PCIE_PCI_IRQ_DW1; 308 volatile uint32_t PCIE_PCI_IRQ_DW2; 309 volatile uint32_t PCIE_PCI_IOV_DW0; 310 volatile uint32_t PCIE_PCI_IOV_DW1; 311 volatile uint32_t RESERVED3; 312 volatile uint32_t PCIE_PEX_DEV; 313 volatile uint32_t PCIE_PEX_DEV2; 314 volatile uint32_t PCIE_PEX_LINK; 315 volatile uint32_t PCIE_PEX_SLOT; 316 volatile uint32_t PCIE_PEX_ROOT_VC; 317 volatile uint32_t PCIE_PEX_SPC; 318 volatile uint32_t PCIE_PEX_SPC2; 319 volatile uint32_t PCIE_PEX_NFTS; 320 volatile uint32_t PCIE_PEX_L1SS; 321 volatile uint32_t PCIE_BAR_01_DW0; 322 volatile uint32_t PCIE_BAR_01_DW1; 323 volatile uint32_t PCIE_BAR_23_DW0; 324 volatile uint32_t PCIE_BAR_23_DW1; 325 volatile uint32_t PCIE_BAR_45_DW0; 326 volatile uint32_t PCIE_BAR_45_DW1; 327 volatile uint32_t PCIE_BAR_WIN; 328 volatile uint32_t PCIE_EQ_PRESET_DW0; 329 volatile uint32_t PCIE_EQ_PRESET_DW1; 330 volatile uint32_t PCIE_EQ_PRESET_DW2; 331 volatile uint32_t PCIE_EQ_PRESET_DW3; 332 volatile uint32_t PCIE_EQ_PRESET_DW4; 333 volatile uint32_t PCIE_EQ_PRESET_DW5; 334 volatile uint32_t PCIE_EQ_PRESET_DW6; 335 volatile uint32_t PCIE_EQ_PRESET_DW7; 336 volatile uint32_t PCIE_SRIOV_DW0; 337 volatile uint32_t PCIE_SRIOV_DW1; 338 volatile uint32_t PCIE_SRIOV_DW2; 339 volatile uint32_t PCIE_SRIOV_DW3; 340 volatile uint32_t PCIE_SRIOV_DW4; 341 volatile uint32_t PCIE_SRIOV_DW5; 342 volatile uint32_t PCIE_SRIOV_DW6; 343 volatile uint32_t PCIE_SRIOV_DW7; 344 volatile uint32_t PCIE_CFGNUM; 345 volatile uint32_t RESERVED4[12]; 346 volatile uint32_t PM_CONF_DW0; 347 volatile uint32_t PM_CONF_DW1; 348 volatile uint32_t PM_CONF_DW2; 349 volatile uint32_t IMASK_LOCAL; 350 volatile uint32_t ISTATUS_LOCAL; 351 volatile uint32_t IMASK_HOST; 352 volatile uint32_t ISTATUS_HOST; 353 volatile uint32_t IMSI_ADDR; 354 volatile uint32_t ISTATUS_MSI; 355 volatile uint32_t ICMD_PM; 356 volatile uint32_t ISTATUS_PM; 357 volatile uint32_t ATS_PRI_REPORT; 358 volatile uint32_t LTR_VALUES; 359 volatile uint32_t RESERVED5[2]; 360 volatile uint32_t ISTATUS_DMA0; 361 volatile uint32_t ISTATUS_DMA1; 362 volatile uint32_t RESERVED6[8]; 363 volatile uint32_t ISTATUS_P_ADT_WIN0; 364 volatile uint32_t ISTATUS_P_ADT_WIN1; 365 volatile uint32_t ISTATUS_A_ADT_SLV0; 366 volatile uint32_t ISTATUS_A_ADT_SLV1; 367 volatile uint32_t ISTATUS_A_ADT_SLV2; 368 volatile uint32_t ISTATUS_A_ADT_SLV3; 369 volatile uint32_t RESERVED7[4]; 370 volatile uint32_t ROUTING_RULES_R_DW0; 371 volatile uint32_t ROUTING_RULES_R_DW1; 372 volatile uint32_t ROUTING_RULES_R_DW2; 373 volatile uint32_t ROUTING_RULES_R_DW3; 374 volatile uint32_t ROUTING_RULES_R_DW4; 375 volatile uint32_t ROUTING_RULES_R_DW5; 376 volatile uint32_t ROUTING_RULES_R_DW6; 377 volatile uint32_t ROUTING_RULES_R_DW7; 378 volatile uint32_t ROUTING_RULES_R_DW8; 379 volatile uint32_t ROUTING_RULES_R_DW9; 380 volatile uint32_t ROUTING_RULES_R_DW10; 381 volatile uint32_t ROUTING_RULES_R_DW11; 382 volatile uint32_t ROUTING_RULES_R_DW12; 383 volatile uint32_t ROUTING_RULES_R_DW13; 384 volatile uint32_t ROUTING_RULES_R_DW14; 385 volatile uint32_t ROUTING_RULES_R_DW15; 386 volatile uint32_t ROUTING_RULES_W_DW0; 387 volatile uint32_t ROUTING_RULES_W_DW1; 388 volatile uint32_t ROUTING_RULES_W_DW2; 389 volatile uint32_t ROUTING_RULES_W_DW3; 390 volatile uint32_t ROUTING_RULES_W_DW4; 391 volatile uint32_t ROUTING_RULES_W_DW5; 392 volatile uint32_t ROUTING_RULES_W_DW6; 393 volatile uint32_t ROUTING_RULES_W_DW7; 394 volatile uint32_t ROUTING_RULES_W_DW8; 395 volatile uint32_t ROUTING_RULES_W_DW9; 396 volatile uint32_t ROUTING_RULES_W_DW10; 397 volatile uint32_t ROUTING_RULES_W_DW11; 398 volatile uint32_t ROUTING_RULES_W_DW12; 399 volatile uint32_t ROUTING_RULES_W_DW13; 400 volatile uint32_t ROUTING_RULES_W_DW14; 401 volatile uint32_t ROUTING_RULES_W_DW15; 402 volatile uint32_t ARBITRATION_RULES_DW0; 403 volatile uint32_t ARBITRATION_RULES_DW1; 404 volatile uint32_t ARBITRATION_RULES_DW2; 405 volatile uint32_t ARBITRATION_RULES_DW3; 406 volatile uint32_t ARBITRATION_RULES_DW4; 407 volatile uint32_t ARBITRATION_RULES_DW5; 408 volatile uint32_t ARBITRATION_RULES_DW6; 409 volatile uint32_t ARBITRATION_RULES_DW7; 410 volatile uint32_t ARBITRATION_RULES_DW8; 411 volatile uint32_t ARBITRATION_RULES_DW9; 412 volatile uint32_t ARBITRATION_RULES_DW10; 413 volatile uint32_t ARBITRATION_RULES_DW11; 414 volatile uint32_t ARBITRATION_RULES_DW12; 415 volatile uint32_t ARBITRATION_RULES_DW13; 416 volatile uint32_t ARBITRATION_RULES_DW14; 417 volatile uint32_t ARBITRATION_RULES_DW15; 418 volatile uint32_t PRIORITY_RULES_DW0; 419 volatile uint32_t PRIORITY_RULES_DW1; 420 volatile uint32_t PRIORITY_RULES_DW2; 421 volatile uint32_t PRIORITY_RULES_DW3; 422 volatile uint32_t PRIORITY_RULES_DW4; 423 volatile uint32_t PRIORITY_RULES_DW5; 424 volatile uint32_t PRIORITY_RULES_DW6; 425 volatile uint32_t PRIORITY_RULES_DW7; 426 volatile uint32_t PRIORITY_RULES_DW8; 427 volatile uint32_t PRIORITY_RULES_DW9; 428 volatile uint32_t PRIORITY_RULES_DW10; 429 volatile uint32_t PRIORITY_RULES_DW11; 430 volatile uint32_t PRIORITY_RULES_DW12; 431 volatile uint32_t PRIORITY_RULES_DW13; 432 volatile uint32_t PRIORITY_RULES_DW14; 433 volatile uint32_t PRIORITY_RULES_DW15; 434 volatile uint32_t RESERVED8[48]; 435 volatile uint32_t P2A_TC_QOS_CONV; 436 volatile uint32_t P2A_ATTR_CACHE_CONV; 437 volatile uint32_t P2A_NC_BASE_ADDR_DW0; 438 volatile uint32_t P2A_NC_BASE_ADDR_DW1; 439 volatile uint32_t RESERVED9[12]; 440 volatile uint32_t DMA0_SRC_PARAM; 441 volatile uint32_t DMA0_DESTPARAM; 442 volatile uint32_t DMA0_SRCADDR_LDW; 443 volatile uint32_t DMA0_SRCADDR_UDW; 444 volatile uint32_t DMA0_DESTADDR_LDW; 445 volatile uint32_t DMA0_DESTADDR_UDW; 446 volatile uint32_t DMA0_LENGTH; 447 volatile uint32_t DMA0_CONTROL; 448 volatile uint32_t DMA0_STATUS; 449 volatile uint32_t DMA0_PRC_LENGTH; 450 volatile uint32_t DMA0_SHARE_ACCESS; 451 volatile uint32_t RESERVED10[5]; 452 volatile uint32_t DMA1_SRC_PARAM; 453 volatile uint32_t DMA1_DESTPARAM; 454 volatile uint32_t DMA1_SRCADDR_LDW; 455 volatile uint32_t DMA1_SRCADDR_UDW; 456 volatile uint32_t DMA1_DESTADDR_LDW; 457 volatile uint32_t DMA1_DESTADDR_UDW; 458 volatile uint32_t DMA1_LENGTH; 459 volatile uint32_t DMA1_CONTROL; 460 volatile uint32_t DMA1_STATUS; 461 volatile uint32_t DMA1_PRC_LENGTH; 462 volatile uint32_t DMA1_SHARE_ACCESS; 463 volatile uint32_t RESERVED11[101]; 464 volatile uint32_t ATR0_PCIE_WIN0_SRCADDR_PARAM; 465 volatile uint32_t ATR0_PCIE_WIN0_SRC_ADDR; 466 volatile uint32_t ATR0_PCIE_WIN0_TRSL_ADDR_LSB; 467 volatile uint32_t ATR0_PCIE_WIN0_TRSL_ADDR_UDW; 468 volatile uint32_t ATR0_PCIE_WIN0_TRSL_PARAM; 469 volatile uint32_t RESERVED12; 470 volatile uint32_t ATR0_PCIE_WIN0_TRSL_MASK_DW0; 471 volatile uint32_t ATR0_PCIE_WIN0_TRSL_MASK_DW1; 472 volatile uint32_t ATR1_PCIE_WIN0_SRCADDR_PARAM; 473 volatile uint32_t ATR1_PCIE_WIN0_SRC_ADDR; 474 volatile uint32_t ATR1_PCIE_WIN0_TRSL_ADDR_LSB; 475 volatile uint32_t ATR1_PCIE_WIN0_TRSL_ADDR_UDW; 476 volatile uint32_t ATR1_PCIE_WIN0_TRSL_PARAM; 477 volatile uint32_t RESERVED13; 478 volatile uint32_t ATR1_PCIE_WIN0_TRSL_MASK_DW0; 479 volatile uint32_t ATR1_PCIE_WIN0_TRSL_MASK_DW1; 480 volatile uint32_t ATR2_PCIE_WIN0_SRCADDR_PARAM; 481 volatile uint32_t ATR2_PCIE_WIN0_SRC_ADDR; 482 volatile uint32_t ATR2_PCIE_WIN0_TRSL_ADDR_LSB; 483 volatile uint32_t ATR2_PCIE_WIN0_TRSL_ADDR_UDW; 484 volatile uint32_t ATR2_PCIE_WIN0_TRSL_PARAM; 485 volatile uint32_t RESERVED14; 486 volatile uint32_t ATR2_PCIE_WIN0_TRSL_MASK_DW0; 487 volatile uint32_t ATR2_PCIE_WIN0_TRSL_MASK_DW1; 488 volatile uint32_t ATR3_PCIE_WIN0_SRCADDR_PARAM; 489 volatile uint32_t ATR3_PCIE_WIN0_SRC_ADDR; 490 volatile uint32_t ATR3_PCIE_WIN0_TRSL_ADDR_LSB; 491 volatile uint32_t ATR3_PCIE_WIN0_TRSL_ADDR_UDW; 492 volatile uint32_t ATR3_PCIE_WIN0_TRSL_PARAM; 493 volatile uint32_t RESERVED15; 494 volatile uint32_t ATR3_PCIE_WIN0_TRSL_MASK_DW0; 495 volatile uint32_t ATR3_PCIE_WIN0_TRSL_MASK_DW1; 496 volatile uint32_t ATR4_PCIE_WIN0_SRCADDR_PARAM; 497 volatile uint32_t ATR4_PCIE_WIN0_SRC_ADDR; 498 volatile uint32_t ATR4_PCIE_WIN0_TRSL_ADDR_LSB; 499 volatile uint32_t ATR4_PCIE_WIN0_TRSL_ADDR_UDW; 500 volatile uint32_t ATR4_PCIE_WIN0_TRSL_PARAM; 501 volatile uint32_t RESERVED16; 502 volatile uint32_t ATR4_PCIE_WIN0_TRSL_MASK_DW0; 503 volatile uint32_t ATR4_PCIE_WIN0_TRSL_MASK_DW1; 504 volatile uint32_t ATR5_PCIE_WIN0_SRCADDR_PARAM; 505 volatile uint32_t ATR5_PCIE_WIN0_SRC_ADDR; 506 volatile uint32_t ATR5_PCIE_WIN0_TRSL_ADDR_LSB; 507 volatile uint32_t ATR5_PCIE_WIN0_TRSL_ADDR_UDW; 508 volatile uint32_t ATR5_PCIE_WIN0_TRSL_PARAM; 509 volatile uint32_t RESERVED17; 510 volatile uint32_t ATR5_PCIE_WIN0_TRSL_MASK_DW0; 511 volatile uint32_t ATR5_PCIE_WIN0_TRSL_MASK_DW1; 512 volatile uint32_t ATR6_PCIE_WIN0_SRCADDR_PARAM; 513 volatile uint32_t ATR6_PCIE_WIN0_SRC_ADDR; 514 volatile uint32_t ATR6_PCIE_WIN0_TRSL_ADDR_LSB; 515 volatile uint32_t ATR6_PCIE_WIN0_TRSL_ADDR_UDW; 516 volatile uint32_t ATR6_PCIE_WIN0_TRSL_PARAM; 517 volatile uint32_t RESERVED18; 518 volatile uint32_t ATR6_PCIE_WIN0_TRSL_MASK_DW0; 519 volatile uint32_t ATR6_PCIE_WIN0_TRSL_MASK_DW1; 520 volatile uint32_t ATR7_PCIE_WIN0_SRCADDR_PARAM; 521 volatile uint32_t ATR7_PCIE_WIN0_SRC_ADDR; 522 volatile uint32_t ATR7_PCIE_WIN0_TRSL_ADDR_LSB; 523 volatile uint32_t ATR7_PCIE_WIN0_TRSL_ADDR_UDW; 524 volatile uint32_t ATR7_PCIE_WIN0_TRSL_PARAM; 525 volatile uint32_t RESERVED19; 526 volatile uint32_t ATR7_PCIE_WIN0_TRSL_MASK_DW0; 527 volatile uint32_t ATR7_PCIE_WIN0_TRSL_MASK_DW1; 528 529 volatile uint32_t ATR0_PCIE_WIN1_SRCADDR_PARAM; 530 volatile uint32_t ATR0_PCIE_WIN1_SRC_ADDR; 531 volatile uint32_t ATR0_PCIE_WIN1_TRSL_ADDR_LSB; 532 volatile uint32_t ATR0_PCIE_WIN1_TRSL_ADDR_UDW; 533 volatile uint32_t ATR0_PCIE_WIN1_TRSL_PARAM; 534 volatile uint32_t RESERVED20; 535 volatile uint32_t ATR0_PCIE_WIN1_TRSL_MASK_DW0; 536 volatile uint32_t ATR0_PCIE_WIN1_TRSL_MASK_DW1; 537 volatile uint32_t ATR1_PCIE_WIN1_SRCADDR_PARAM; 538 volatile uint32_t ATR1_PCIE_WIN1_SRC_ADDR; 539 volatile uint32_t ATR1_PCIE_WIN1_TRSL_ADDR_LSB; 540 volatile uint32_t ATR1_PCIE_WIN1_TRSL_ADDR_UDW; 541 volatile uint32_t ATR1_PCIE_WIN1_TRSL_PARAM; 542 volatile uint32_t RESERVED21; 543 volatile uint32_t ATR1_PCIE_WIN1_TRSL_MASK_DW0; 544 volatile uint32_t ATR1_PCIE_WIN1_TRSL_MASK_DW1; 545 volatile uint32_t ATR2_PCIE_WIN1_SRCADDR_PARAM; 546 volatile uint32_t ATR2_PCIE_WIN1_SRC_ADDR; 547 volatile uint32_t ATR2_PCIE_WIN1_TRSL_ADDR_LSB; 548 volatile uint32_t ATR2_PCIE_WIN1_TRSL_ADDR_UDW; 549 volatile uint32_t ATR2_PCIE_WIN1_TRSL_PARAM; 550 volatile uint32_t RESERVED22; 551 volatile uint32_t ATR2_PCIE_WIN1_TRSL_MASK_DW0; 552 volatile uint32_t ATR2_PCIE_WIN1_TRSL_MASK_DW1; 553 volatile uint32_t ATR3_PCIE_WIN1_SRCADDR_PARAM; 554 volatile uint32_t ATR3_PCIE_WIN1_SRC_ADDR; 555 volatile uint32_t ATR3_PCIE_WIN1_TRSL_ADDR_LSB; 556 volatile uint32_t ATR3_PCIE_WIN1_TRSL_ADDR_UDW; 557 volatile uint32_t ATR3_PCIE_WIN1_TRSL_PARAM; 558 volatile uint32_t RESERVED23; 559 volatile uint32_t ATR3_PCIE_WIN1_TRSL_MASK_DW0; 560 volatile uint32_t ATR3_PCIE_WIN1_TRSL_MASK_DW1; 561 volatile uint32_t ATR4_PCIE_WIN1_SRCADDR_PARAM; 562 volatile uint32_t ATR4_PCIE_WIN1_SRC_ADDR; 563 volatile uint32_t ATR4_PCIE_WIN1_TRSL_ADDR_LSB; 564 volatile uint32_t ATR4_PCIE_WIN1_TRSL_ADDR_UDW; 565 volatile uint32_t ATR4_PCIE_WIN1_TRSL_PARAM; 566 volatile uint32_t RESERVED24; 567 volatile uint32_t ATR4_PCIE_WIN1_TRSL_MASK_DW0; 568 volatile uint32_t ATR4_PCIE_WIN1_TRSL_MASK_DW1; 569 volatile uint32_t ATR5_PCIE_WIN1_SRCADDR_PARAM; 570 volatile uint32_t ATR5_PCIE_WIN1_SRC_ADDR; 571 volatile uint32_t ATR5_PCIE_WIN1_TRSL_ADDR_LSB; 572 volatile uint32_t ATR5_PCIE_WIN1_TRSL_ADDR_UDW; 573 volatile uint32_t ATR5_PCIE_WIN1_TRSL_PARAM; 574 volatile uint32_t RESERVED25; 575 volatile uint32_t ATR5_PCIE_WIN1_TRSL_MASK_DW0; 576 volatile uint32_t ATR5_PCIE_WIN1_TRSL_MASK_DW1; 577 volatile uint32_t ATR6_PCIE_WIN1_SRCADDR_PARAM; 578 volatile uint32_t ATR6_PCIE_WIN1_SRC_ADDR; 579 volatile uint32_t ATR6_PCIE_WIN1_TRSL_ADDR_LSB; 580 volatile uint32_t ATR6_PCIE_WIN1_TRSL_ADDR_UDW; 581 volatile uint32_t ATR6_PCIE_WIN1_TRSL_PARAM; 582 volatile uint32_t RESERVED26; 583 volatile uint32_t ATR6_PCIE_WIN1_TRSL_MASK_DW0; 584 volatile uint32_t ATR6_PCIE_WIN1_TRSL_MASK_DW1; 585 volatile uint32_t ATR7_PCIE_WIN1_SRCADDR_PARAM; 586 volatile uint32_t ATR7_PCIE_WIN1_SRC_ADDR; 587 volatile uint32_t ATR7_PCIE_WIN1_TRSL_ADDR_LSB; 588 volatile uint32_t ATR7_PCIE_WIN1_TRSL_ADDR_UDW; 589 volatile uint32_t ATR7_PCIE_WIN1_TRSL_PARAM; 590 volatile uint32_t RESERVED27; 591 volatile uint32_t ATR7_PCIE_WIN1_TRSL_MASK_DW0; 592 volatile uint32_t ATR7_PCIE_WIN1_TRSL_MASK_DW1; 593 594 volatile uint32_t ATR0_AXI4_SLV0_SRCADDR_PARAM; 595 volatile uint32_t ATR0_AXI4_SLV0_SRC_ADDR; 596 volatile uint32_t ATR0_AXI4_SLV0_TRSL_ADDR_LSB; 597 volatile uint32_t ATR0_AXI4_SLV0_TRSL_ADDR_UDW; 598 volatile uint32_t ATR0_AXI4_SLV0_TRSL_PARAM; 599 volatile uint32_t RESERVED28; 600 volatile uint32_t ATR0_AXI4_SLV0_TRSL_MASK_DW0; 601 volatile uint32_t ATR0_AXI4_SLV0_TRSL_MASK_DW1; 602 volatile uint32_t ATR1_AXI4_SLV0_SRCADDR_PARAM; 603 volatile uint32_t ATR1_AXI4_SLV0_SRC_ADDR; 604 volatile uint32_t ATR1_AXI4_SLV0_TRSL_ADDR_LSB; 605 volatile uint32_t ATR1_AXI4_SLV0_TRSL_ADDR_UDW; 606 volatile uint32_t ATR1_AXI4_SLV0_TRSL_PARAM; 607 volatile uint32_t RESERVED29; 608 volatile uint32_t ATR1_AXI4_SLV0_TRSL_MASK_DW0; 609 volatile uint32_t ATR1_AXI4_SLV0_TRSL_MASK_DW1; 610 volatile uint32_t ATR2_AXI4_SLV0_SRCADDR_PARAM; 611 volatile uint32_t ATR2_AXI4_SLV0_SRC_ADDR; 612 volatile uint32_t ATR2_AXI4_SLV0_TRSL_ADDR_LSB; 613 volatile uint32_t ATR2_AXI4_SLV0_TRSL_ADDR_UDW; 614 volatile uint32_t ATR2_AXI4_SLV0_TRSL_PARAM; 615 volatile uint32_t RESERVED30; 616 volatile uint32_t ATR2_AXI4_SLV0_TRSL_MASK_DW0; 617 volatile uint32_t ATR2_AXI4_SLV0_TRSL_MASK_DW1; 618 volatile uint32_t ATR3_AXI4_SLV0_SRCADDR_PARAM; 619 volatile uint32_t ATR3_AXI4_SLV0_SRC_ADDR; 620 volatile uint32_t ATR3_AXI4_SLV0_TRSL_ADDR_LSB; 621 volatile uint32_t ATR3_AXI4_SLV0_TRSL_ADDR_UDW; 622 volatile uint32_t ATR3_AXI4_SLV0_TRSL_PARAM; 623 volatile uint32_t RESERVED31; 624 volatile uint32_t ATR3_AXI4_SLV0_TRSL_MASK_DW0; 625 volatile uint32_t ATR3_AXI4_SLV0_TRSL_MASK_DW1; 626 volatile uint32_t ATR4_AXI4_SLV0_SRCADDR_PARAM; 627 volatile uint32_t ATR4_AXI4_SLV0_SRC_ADDR; 628 volatile uint32_t ATR4_AXI4_SLV0_TRSL_ADDR_LSB; 629 volatile uint32_t ATR4_AXI4_SLV0_TRSL_ADDR_UDW; 630 volatile uint32_t ATR4_AXI4_SLV0_TRSL_PARAM; 631 volatile uint32_t RESERVED32; 632 volatile uint32_t ATR4_AXI4_SLV0_TRSL_MASK_DW0; 633 volatile uint32_t ATR4_AXI4_SLV0_TRSL_MASK_DW1; 634 volatile uint32_t ATR5_AXI4_SLV0_SRCADDR_PARAM; 635 volatile uint32_t ATR5_AXI4_SLV0_SRC_ADDR; 636 volatile uint32_t ATR5_AXI4_SLV0_TRSL_ADDR_LSB; 637 volatile uint32_t ATR5_AXI4_SLV0_TRSL_ADDR_UDW; 638 volatile uint32_t ATR5_AXI4_SLV0_TRSL_PARAM; 639 volatile uint32_t RESERVED33; 640 volatile uint32_t ATR5_AXI4_SLV0_TRSL_MASK_DW0; 641 volatile uint32_t ATR5_AXI4_SLV0_TRSL_MASK_DW1; 642 volatile uint32_t ATR6_AXI4_SLV0_SRCADDR_PARAM; 643 volatile uint32_t ATR6_AXI4_SLV0_SRC_ADDR; 644 volatile uint32_t ATR6_AXI4_SLV0_TRSL_ADDR_LSB; 645 volatile uint32_t ATR6_AXI4_SLV0_TRSL_ADDR_UDW; 646 volatile uint32_t ATR6_AXI4_SLV0_TRSL_PARAM; 647 volatile uint32_t RESERVED34; 648 volatile uint32_t ATR6_AXI4_SLV0_TRSL_MASK_DW0; 649 volatile uint32_t ATR6_AXI4_SLV0_TRSL_MASK_DW1; 650 volatile uint32_t ATR7_AXI4_SLV0_SRCADDR_PARAM; 651 volatile uint32_t ATR7_AXI4_SLV0_SRC_ADDR; 652 volatile uint32_t ATR7_AXI4_SLV0_TRSL_ADDR_LSB; 653 volatile uint32_t ATR7_AXI4_SLV0_TRSL_ADDR_UDW; 654 volatile uint32_t ATR7_AXI4_SLV0_TRSL_PARAM; 655 volatile uint32_t RESERVED35; 656 volatile uint32_t ATR7_AXI4_SLV0_TRSL_MASK_DW0; 657 volatile uint32_t ATR7_AXI4_SLV0_TRSL_MASK_DW1; 658 659 } PCIE_BRIDGE_TypeDef; 660 661 /*------------------------------------------------------------------------------ 662 PCIE Configuration Type 0 Space Registers. 663 */ 664 typedef struct 665 { 666 /*======================= Information registers ======================*/ 667 /** 668 Information register: vendor_id & device_id 669 bits [15:0] vendor_id 670 bits [31:16] device_id 671 */ 672 /* 0x000 */ 673 volatile uint32_t VID_DEVID; 674 675 /** 676 PCI Express Control & Status Register: cfg_prmscr 677 */ 678 /* 0x004 */ 679 volatile uint32_t CFG_PRMSCR; 680 681 /** 682 Information register: class_code 683 */ 684 /* 0x008 */ 685 volatile uint32_t CLASS_CODE; 686 687 /** 688 BIST, Header, master latency timer, cache : BIST_HEADER 689 */ 690 /* 0x00C */ 691 volatile uint32_t BIST_HEADER; 692 693 /** 694 Bridge Configuration Register: bar0 695 */ 696 /* 0x010 */ 697 volatile uint32_t BAR0; 698 699 /** 700 Bridge Configuration Register: bar1 701 */ 702 /* 0x014 */ 703 volatile uint32_t BAR1; 704 705 /** 706 Bridge Configuration Register: bar2 707 */ 708 /* 0x018 */ 709 volatile uint32_t BAR2; 710 711 /** 712 Bridge Configuration Register: bar3 713 */ 714 /* 0x01C */ 715 volatile uint32_t BAR3; 716 717 /** 718 Bridge Configuration Register: bar4 719 */ 720 /* 0x020 */ 721 volatile uint32_t BAR4; 722 723 /** 724 Bridge Configuration Register: bar5 725 */ 726 /* 0x024 */ 727 volatile uint32_t BAR5; 728 729 730 volatile uint32_t RESERVED1; 731 732 /** 733 Information register: subsystem_id 734 */ 735 /* 0x02C */ 736 volatile uint32_t SUBSYSTEM_ID; 737 738 /** 739 Expansion ROM Base Address Register: expansion_rom 740 */ 741 /* 0x030 */ 742 volatile uint32_t EXPAN_ROM; 743 744 /** 745 Capability pointer register: capab_pointer 746 */ 747 /* 0x034 */ 748 volatile uint32_t CAPAB_POINTER; 749 750 /** 751 Expansion ROM Base Address register: expansion_rom_base 752 */ 753 /* 0x038 */ 754 volatile uint32_t EXPAN_ROM_BASE; 755 756 /** 757 Interrupt Line and Pin register: int_line_pin 758 */ 759 /* 0x03C */ 760 volatile uint32_t INT_LINE_PIN; 761 762 /* 0x40 to 0x7C */ 763 volatile uint32_t RESERVED2[16]; 764 765 /* PCIe Capability structure register */ 766 767 /** 768 PCIe Capability list register: CAPAB_LIST 769 */ 770 /* 0x080 */ 771 volatile uint32_t CAPAB_LIST; 772 773 /** 774 Device Capabilities register: device_capab 775 */ 776 /* 0x084 */ 777 volatile uint32_t DEVICE_CAPAB; 778 779 /** 780 Device Control and status register: device_ctrl_stat 781 */ 782 /* 0x088 */ 783 volatile uint32_t DEVICE_CTRL_STAT; 784 785 /** 786 Link Capabilities register: link_capab 787 */ 788 /* 0x08C */ 789 volatile uint32_t LINK_CAPAB; 790 791 /** 792 Link Control and status register: link_ctrl_stat 793 */ 794 /* 0x090 */ 795 volatile uint32_t LINK_CTRL_STAT; 796 797 /** 798 Slot capabilities register: slot_capab 799 */ 800 /* 0x094 */ 801 volatile uint32_t SLOT_CAPAB; 802 803 /** 804 Slot Control and status register: slot_ctrl_stat 805 */ 806 /* 0x098 */ 807 volatile uint32_t SLOT_CTRL_STAT; 808 809 /** 810 Root control register: root_ctrl 811 */ 812 /* 0x09C */ 813 volatile uint32_t ROOT_CTRL; 814 815 /** 816 Root status register: root_stat 817 */ 818 /* 0x0A0 */ 819 volatile uint32_t ROOT_STAT; 820 821 /** 822 Device 2 Capabilities register: device2_capab 823 */ 824 /* 0x0A4 */ 825 volatile uint32_t DEVICE2_CAPAB; 826 827 /** 828 Device 2 Control and status register: device2_ctrl_stat 829 */ 830 /* 0x0A8 */ 831 volatile uint32_t DEVICE2_CTRL_STAT; 832 833 /** 834 Link Capabilities 2 register: link2_capab 835 */ 836 /* 0x0AC */ 837 volatile uint32_t LINK2_CAPAB; 838 839 /** 840 Link Control and status 2register: link2_ctrl_stat 841 */ 842 /* 0x0B0 */ 843 volatile uint32_t LINK2_CTRL_STAT; 844 845 /** 846 Slot 2 capabilities register: slot2_capab 847 */ 848 /* 0x0B4 */ 849 volatile uint32_t SLOT2_CAPAB; 850 851 /** 852 Slot 2 Control and status register: slot2_ctrl_stat 853 */ 854 /* 0x0B8 */ 855 volatile uint32_t SLOT2_CTRL_STAT; 856 857 /* 0xBC to 0xCC */ 858 volatile uint32_t RESERVED3[5]; 859 860 /* MSI-X Capability (optional)*/ 861 862 /** 863 MSI-X capability and control register: msi_x_capab_ctrl 864 */ 865 /* 0x0D0 */ 866 volatile uint32_t MSI_X_CAPAB_CTRL; 867 868 /** 869 MSI-X table register: msi_x_table 870 */ 871 /* 0x0D4 */ 872 volatile uint32_t MSI_X_TABLE; 873 874 /** 875 MSI-X PBA register: msi_x_pba 876 */ 877 /* 0x0D8 */ 878 volatile uint32_t MSI_X_PBA; 879 880 /* 0xDC */ 881 volatile uint32_t RESERVED4; 882 883 /** 884 MSI capability id and message control register: msi_capab_ctrl 885 */ 886 /* 0x0E0 */ 887 volatile uint32_t MSI_CAPAB_CTRL; 888 889 /** 890 MSI message lower address register: msi_lower address 891 */ 892 /* 0x0E4 */ 893 volatile uint32_t MSI_LOWER_ADDRESS; 894 895 /** 896 MSI message upper address register: msi_upper address 897 */ 898 /* 0x0E8 */ 899 volatile uint32_t MSI_UPPER_ADDRESS; 900 901 /* 0xEC */ 902 volatile uint32_t RESERVED5; 903 904 /** 905 MSI message data register: msi_data 906 */ 907 /* 0x0F0 */ 908 volatile uint32_t MSI_DATA; 909 /* 0xF4 */ 910 volatile uint32_t RESERVED6; 911 912 /* Power Management Capability Structure */ 913 /** 914 Power Management Capability register: power_mngm_capab 915 */ 916 /* 0x0F8 */ 917 volatile uint32_t POWER_MNGM_CAPAB; 918 919 /** 920 Power Management control and status register: power_ctrl_stat 921 */ 922 /* 0x0FC */ 923 volatile uint32_t POWER_CTRL_STAT; 924 925 } PCIE_END_CONF_TypeDef; 926 927 /*------------------------------------------------------------------------------ 928 PCIE Configuration Type 1 Space Registers. 929 */ 930 typedef struct 931 { 932 /*======================= Information registers ======================*/ 933 /** 934 Information register: vendor_id & device_id 935 bits [15:0] vendor_id 936 bits [31:16] device_id 937 */ 938 /* 0x000 */ 939 volatile uint32_t VID_DEVID; 940 941 /** 942 PCI Express Control & Status Register: cfg_prmscr 943 */ 944 /* 0x004 */ 945 volatile uint32_t CFG_PRMSCR; 946 947 /** 948 Information register: class_code 949 */ 950 /* 0x008 */ 951 volatile uint32_t CLASS_CODE; 952 953 /** 954 BIST, Header, master latency timer, cache : BIST_HEADER 955 */ 956 /* 0x00C */ 957 volatile uint32_t BIST_HEADER; 958 959 /** 960 Bridge Configuration Register: bar0 961 */ 962 /* 0x010 */ 963 volatile uint32_t BAR0; 964 965 /** 966 Bridge Configuration Register: bar1 967 */ 968 /* 0x014 */ 969 volatile uint32_t BAR1; 970 971 /** 972 Secondary Latency timer, Subordinate bus number, 973 Secondary bus Number, primary bus number Register: prim_sec_bus_num 974 */ 975 /* 0x018 */ 976 volatile uint32_t PRIM_SEC_BUS_NUM; 977 978 /** 979 Secondary status, I/O limit, I/O base Register: io_limit_base 980 */ 981 /* 0x01C */ 982 volatile uint32_t IO_LIMIT_BASE; 983 984 /** 985 memory limit, memory base Register: mem_limit_base 986 */ 987 /* 0x020 */ 988 volatile uint32_t MEM_LIMIT_BASE; 989 990 /** 991 prefetchable memory limit, memory base Register: pref_mem_limit_base 992 */ 993 /* 0x024 */ 994 volatile uint32_t PREF_MEM_LIMIT_BASE; 995 996 /** 997 prefetchable base upper Register: pref_base_upper 998 */ 999 /* 0x028 */ 1000 volatile uint32_t PREF_BASE_UPPER; 1001 1002 /** 1003 prefetchable limit upper Register: pref_limit_upper 1004 */ 1005 /* 0x02C */ 1006 volatile uint32_t PREF_LIMIT_UPPER; 1007 1008 /** 1009 i/o base, limit upper Register: io_limit_base_upper 1010 */ 1011 /* 0x030 */ 1012 volatile uint32_t IO_LIMIT_BASE_UPPER; 1013 1014 /** 1015 Capability pointer register: capab_pointer 1016 */ 1017 /* 0x034 */ 1018 volatile uint32_t CAPAB_POINTER; 1019 1020 /** 1021 Expansion ROM Base Address register: expansion_rom_base 1022 */ 1023 /* 0x038 */ 1024 volatile uint32_t EXPAN_ROM_BASE; 1025 1026 /** 1027 Interrupt Line and Pin register: int_line_pin 1028 */ 1029 /* 0x03C */ 1030 volatile uint32_t INT_LINE_PIN; 1031 1032 /* 0x40 to 0x7C */ 1033 volatile uint32_t RESERVED2[16]; 1034 1035 /* PCIe Capability structure register */ 1036 1037 /** 1038 PCIe Capability list register: CAPAB_LIST 1039 */ 1040 /* 0x080 */ 1041 volatile uint32_t CAPAB_LIST; 1042 1043 /** 1044 Device Capabilities register: device_capab 1045 */ 1046 /* 0x084 */ 1047 volatile uint32_t DEVICE_CAPAB; 1048 1049 /** 1050 Device Control and status register: device_ctrl_stat 1051 */ 1052 /* 0x088 */ 1053 volatile uint32_t DEVICE_CTRL_STAT; 1054 1055 /** 1056 Link Capabilities register: link_capab 1057 */ 1058 /* 0x08C */ 1059 volatile uint32_t LINK_CAPAB; 1060 1061 /** 1062 Link Control and status register: link_ctrl_stat 1063 */ 1064 /* 0x090 */ 1065 volatile uint32_t LINK_CTRL_STAT; 1066 1067 /** 1068 Slot capabilities register: slot_capab 1069 */ 1070 /* 0x094 */ 1071 volatile uint32_t SLOT_CAPAB; 1072 1073 /** 1074 Slot Control and status register: slot_ctrl_stat 1075 */ 1076 /* 0x098 */ 1077 volatile uint32_t SLOT_CTRL_STAT; 1078 1079 /** 1080 Root control register: root_ctrl 1081 */ 1082 /* 0x09C */ 1083 volatile uint32_t ROOT_CTRL; 1084 1085 /** 1086 Root status register: root_stat 1087 */ 1088 /* 0x0A0 */ 1089 volatile uint32_t ROOT_STAT; 1090 1091 /** 1092 Device 2 Capabilities register: device2_capab 1093 */ 1094 /* 0x0A4 */ 1095 volatile uint32_t DEVICE2_CAPAB; 1096 1097 /** 1098 Device 2 Control and status register: device2_ctrl_stat 1099 */ 1100 /* 0x0A8 */ 1101 volatile uint32_t DEVICE2_CTRL_STAT; 1102 1103 /** 1104 Link Capabilities 2 register: link2_capab 1105 */ 1106 /* 0x0AC */ 1107 volatile uint32_t LINK2_CAPAB; 1108 1109 /** 1110 Link Control and status 2register: link2_ctrl_stat 1111 */ 1112 /* 0x0B0 */ 1113 volatile uint32_t LINK2_CTRL_STAT; 1114 1115 /** 1116 Slot 2 capabilities register: slot2_capab 1117 */ 1118 /* 0x0B4 */ 1119 volatile uint32_t SLOT2_CAPAB; 1120 1121 /** 1122 Slot 2 Control and status register: slot2_ctrl_stat 1123 */ 1124 /* 0x0B8 */ 1125 volatile uint32_t SLOT2_CTRL_STAT; 1126 1127 /* 0xBC to 0xCC */ 1128 volatile uint32_t RESERVED3[5]; 1129 1130 /* MSI-X Capability (optional)*/ 1131 1132 /** 1133 MSI-X capability and control register: msi_x_capab_ctrl 1134 */ 1135 /* 0x0D0 */ 1136 volatile uint32_t MSI_X_CAPAB_CTRL; 1137 1138 /** 1139 MSI-X table register: msi_x_table 1140 */ 1141 /* 0x0D4 */ 1142 volatile uint32_t MSI_X_TABLE; 1143 1144 /** 1145 MSI-X PBA register: msi_x_pba 1146 */ 1147 /* 0x0D8 */ 1148 volatile uint32_t MSI_X_PBA; 1149 1150 /* 0xDC */ 1151 volatile uint32_t RESERVED4; 1152 1153 /** 1154 MSI capability id and message control register: msi_capab_ctrl 1155 */ 1156 /* 0x0E0 */ 1157 volatile uint32_t MSI_CAPAB_CTRL; 1158 1159 /** 1160 MSI message lower address register: msi_lower address 1161 */ 1162 /* 0x0E4 */ 1163 volatile uint32_t MSI_LOWER_ADDRESS; 1164 1165 /** 1166 MSI message upper address register: msi_upper address 1167 */ 1168 /* 0x0E8 */ 1169 volatile uint32_t MSI_UPPER_ADDRESS; 1170 1171 /* 0xEC */ 1172 volatile uint32_t RESERVED5; 1173 1174 /** 1175 MSI message data register: msi_data 1176 */ 1177 /* 0x0F0 */ 1178 volatile uint32_t MSI_DATA; 1179 /* 0xF4 */ 1180 volatile uint32_t RESERVED6; 1181 1182 /* Power Management Capability Structure */ 1183 /** 1184 Power Management Capability register: power_mngm_capab 1185 */ 1186 /* 0x0F8 */ 1187 volatile uint32_t POWER_MNGM_CAPAB; 1188 1189 /** 1190 Power Management control and status register: power_ctrl_stat 1191 */ 1192 /* 0x0FC */ 1193 volatile uint32_t POWER_CTRL_STAT; 1194 1195 } PCIE_ROOT_CONF_TypeDef; 1196 1197 /*------------------------------------------------------------------------------ 1198 PCIESS sub system registers 1199 1200 typedef struct 1201 { 1202 PCS_LANE_TypeDef pcs_lane[4]; 1203 PCS_CMN_TypeDef pcs_cmn; 1204 PMA_LANE_TypeDef pma_lane[4]; 1205 TXPLL_SSC_TypeDef txpll_ssc; 1206 TXPLL_TypeDef txpll[2]; 1207 PCIESS_MAIN_TypeDef pciess_main; 1208 PCIE_BRIDGE_TypeDef pcie_bridge[2]; 1209 PCIE_END_CONF_TypeDef pcie_end_config_space; 1210 PCIE_ROOT_CONF_TypeDef pcie_root_config_space; 1211 PCIE_CTRL_TypeDef pcie_ctrl[2]; 1212 1213 } PCIESS_TypeDef; 1214 */ 1215 1216 /*----------------------------------------------------------------------------*/ 1217 #define PCS_LANE PCS_LANE_TypeDef 1218 #define PCS_CMN PCS_CMN_TypeDef 1219 #define PMA_LANE PMA_LANE_TypeDef 1220 #define TXPLL_SSC TXPLL_SSC_TypeDef 1221 #define TXPLL TXPLL_TypeDef 1222 #define PCIESS_MAIN PCIESS_MAIN_TypeDef 1223 #define PCIE_BRIDGE PCIE_BRIDGE_TypeDef 1224 #define PCIE_END_CONF PCIE_END_CONF_TypeDef 1225 #define PCIE_ROOT_CONF PCIE_ROOT_CONF_TypeDef 1226 #define PCIE_CTRL PCIE_CTRL_TypeDef 1227 1228 /*----------------------------------------------------------------------------*/ 1229 /*------------------------------------------------------------------------------ 1230 PCIE Configuration Type 0 Space Registers offset definitions. 1231 */ 1232 #define DEVICE_VID_DEVID 0x000u 1233 #define DEVICE_CFG_PRMSCR 0x004u 1234 #define DEVICE_CLASS_CODE 0x008u 1235 #define DEVICE_BIST_HEADER 0x00Cu 1236 #define DEVICE_BAR0 0x010u 1237 #define DEVICE_BAR1 0x014u 1238 #define DEVICE_BAR2 0x018u 1239 #define DEVICE_BAR3 0x01Cu 1240 #define DEVICE_BAR4 0x020u 1241 #define DEVICE_BAR5 0x024u 1242 #define DEVICE_SUBSYSTEM_ID 0x02Cu 1243 #define DEVICE_EXPAN_ROM 0x030u 1244 #define DEVICE_CAPAB_POINTER 0x034u 1245 #define DEVICE_EXPAN_ROM_BASE 0x038u 1246 #define DEVICE_INT_LINE_PIN 0x03Cu 1247 #define DEVICE_CAPAB_LIST 0x080u 1248 #define DEVICE_DEVICE_CAPAB 0x084u 1249 #define DEVICE_DEVICE_CTRL_STAT 0x088u 1250 #define DEVICE_LINK_CAPAB 0x08Cu 1251 #define DEVICE_LINK_CTRL_STAT 0x090u 1252 #define DEVICE_SLOT_CAPAB 0x094u 1253 #define DEVICE_SLOT_CTRL_STAT 0x098u 1254 #define DEVICE_ROOT_CTRL 0x09Cu 1255 #define DEVICE_ROOT_STAT 0x0A0u 1256 #define DEVICE_DEVICE2_CAPAB 0x0A4u 1257 #define DEVICE_DEVICE2_CTRL_STAT 0x0A8u 1258 #define DEVICE_LINK2_CAPAB 0x0ACu 1259 #define DEVICE_LINK2_CTRL_STAT 0x0B0u 1260 #define DEVICE_SLOT2_CAPAB 0x0B4u 1261 #define DEVICE_SLOT2_CTRL_STAT 0x0B8u 1262 #define DEVICE_MSI_X_CAPAB_CTRL 0x0D0u 1263 #define DEVICE_MSI_X_TABLE 0x0D4u 1264 #define DEVICE_MSI_X_PBA 0x0D8u 1265 #define DEVICE_MSI_CAPAB_CTRL 0x0E0u 1266 #define DEVICE_MSI_LOWER_ADDRESS 0x0E4u 1267 #define DEVICE_MSI_UPPER_ADDRESS 0x0E8u 1268 #define DEVICE_MSI_DATA 0x0F0u 1269 #define DEVICE_POWER_MNGM_CAPAB 0x0F8u 1270 #define DEVICE_POWER_CTRL_STAT 0x0FCu 1271 1272 /*------------------------------------------------------------------------------ 1273 The table below shows the base address and available address space for each of 1274 the leaf instances in the pciess system. 1275 1276 Instance Name Base Address Range 1277 1278 pcs_lane_0 0x004 1000 4 KBytes 1279 pcs_lane_1 0x004 2000 4 KBytes 1280 pcs_lane_2 0x004 4000 4 KBytes 1281 pcs_lane_3 0x004 8000 4 KBytes 1282 pcs_cmn 0x005 0000 4 KBytes 1283 pma_lane_0 0x104 1000 4 KBytes 1284 pma_lane_1 0x104 2000 4 KBytes 1285 pma_lane_2 0x104 4000 4 KBytes 1286 pma_lane_3 0x104 8000 4 KBytes 1287 txpll_ssc(pma_cmn) 0x105 0000 4 KBytes 1288 tx(quad)_pll_0 0x204 4000 4 KBytes 1289 tx(quad)_pll_1 0x204 8000 4 KBytes 1290 pciess_main 0x205 0000 4 KBytes 1291 1292 pcie_top_0__g5_xpressrich3_bridge 0x300 4000 8 KBytes 1293 pcie_top_0__pcie_ctrl 0x300 6000 4 KBytes 1294 pcie_top_1__g5_xpressrich3_bridge 0x300 8000 8 KBytes 1295 pcie_top_1__pcie_ctrl 0x300 A000 4 KBytes 1296 ------------------------------------------------------------------------------*/ 1297 1298 #define PCIESS_PCS_LANE0_PHY_ADDR_OFFSET 0x00041000u 1299 #define PCIESS_PCS_LANE1_PHY_ADDR_OFFSET 0x00042000u 1300 #define PCIESS_PCS_LANE2_PHY_ADDR_OFFSET 0x00044000u 1301 #define PCIESS_PCS_LANE3_PHY_ADDR_OFFSET 0x00048000u 1302 1303 #define PCIESS_PCS_CMN_PHY_ADDR_OFFSET 0x00050000u 1304 1305 #define PCIESS_PMA_LANE0_PHY_ADDR_OFFSET 0x01041000u 1306 #define PCIESS_PMA_LANE1_PHY_ADDR_OFFSET 0x01042000u 1307 #define PCIESS_PMA_LANE2_PHY_ADDR_OFFSET 0x01044000u 1308 #define PCIESS_PMA_LANE3_PHY_ADDR_OFFSET 0x01048000u 1309 1310 #define PCIESS_TXPLL_SSC_PHY_ADDR_OFFSET 0x01050000u 1311 1312 #define PCIESS_TXPLL0_PHY_ADDR_OFFSET 0x02044000u 1313 #define PCIESS_TXPLL1_PHY_ADDR_OFFSET 0x02048000u 1314 1315 #define PCIESS_MAIN_PHY_ADDR_OFFSET 0x02050000u 1316 1317 #define PCIE0_BRIDGE_PHY_ADDR_OFFSET 0x03004000u 1318 #define PCIE0_CRTL_PHY_ADDR_OFFSET 0x03006000u 1319 1320 #define PCIE1_BRIDGE_PHY_ADDR_OFFSET 0x03008000u 1321 #define PCIE1_CRTL_PHY_ADDR_OFFSET 0x0300A000u 1322 1323 #ifdef __cplusplus 1324 } 1325 #endif 1326 1327 #endif /* PF_PCIESS_REGS_H_ */ 1328
