Home
last modified time | relevance | path

Searched refs:SRSS_NUM_CLKPATH (Results 1 – 20 of 20) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_hwmgr_impl_part.h182 #define CY_CHANNEL_COUNT_CLOCK (12 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + P…
186 #define CY_CHANNEL_COUNT_CLOCK (13 + 6 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + P…
190 #define CY_CHANNEL_COUNT_CLOCK (10 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400…
195 #define CY_CHANNEL_COUNT_CLOCK (14 + 2 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + …
199 #define CY_CHANNEL_COUNT_CLOCK (6 + 6 + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP…
629 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
672 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 7, // FLL
674 …PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 8, // PLL…
675 …PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 8 + SRSS_NUM_PLL, // PLL…
677 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 8, // PLL
[all …]
Dcyhal_clock.c100 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PATHMUX[SRSS_NUM_CLKPATH] =
103 #if (SRSS_NUM_CLKPATH > 1)
106 #if (SRSS_NUM_CLKPATH > 2)
109 #if (SRSS_NUM_CLKPATH > 3)
112 #if (SRSS_NUM_CLKPATH > 4)
115 #if (SRSS_NUM_CLKPATH > 5)
118 #if (SRSS_NUM_CLKPATH > 6)
121 #if (SRSS_NUM_CLKPATH > 7)
124 #if (SRSS_NUM_CLKPATH > 8)
127 #if (SRSS_NUM_CLKPATH > 9)
[all …]
Dcyhal_utils_impl.c490 return SRSS_NUM_CLKPATH; in _cyhal_utils_get_clock_count()
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_clock_impl.h217 #if (SRSS_NUM_CLKPATH > 0)
219 extern const cyhal_clock_t CYHAL_CLOCK_PATHMUX[SRSS_NUM_CLKPATH];
221 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PATHMUX[SRSS_NUM_CLKPATH];
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcyw20829B0_config.h2183 #define SRSS_NUM_CLKPATH 4u macro
Dcyw20829_config.h2183 #define SRSS_NUM_CLKPATH 4u macro
Dcy_device.h941 #define CY_SRSS_NUM_CLKPATH SRSS_NUM_CLKPATH
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h2968 #define SRSS_NUM_CLKPATH 5u macro
Dpsoc6_03_config.h3019 #define SRSS_NUM_CLKPATH 5u macro
Dpsoc6_04_config.h3047 #define SRSS_NUM_CLKPATH 5u macro
Dpsoc6_02_config.h3835 #define SRSS_NUM_CLKPATH 6u macro
Dfx3g2_config.h3722 #define SRSS_NUM_CLKPATH 5u macro
Dtviibe1m_config.h3713 #define SRSS_NUM_CLKPATH 4u macro
Dtviibe2m_config.h3883 #define SRSS_NUM_CLKPATH 4u macro
Dtviibe4m_config.h3888 #define SRSS_NUM_CLKPATH 4u macro
Dcy_device.h309 #define CY_SRSS_NUM_CLKPATH (SRSS_NUM_CLKPATH)
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h4529 #define SRSS_NUM_CLKPATH 7u macro
Dtviic2d6m_config.h5106 #define SRSS_NUM_CLKPATH 11u macro
Dxmc7200_config.h5189 #define SRSS_NUM_CLKPATH 7u macro
Dcy_device.h125 #define CY_SRSS_NUM_CLKPATH SRSS_NUM_CLKPATH