1 /***************************************************************************//** 2 * \file psoc6_04_config.h 3 * 4 * \brief 5 * PSoC6_04 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _PSOC6_04_CONFIG_H_ 28 #define _PSOC6_04_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ 34 PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ 35 PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ 36 PCLK_SCB4_CLOCK = 0x0003u, /* scb[4].clock */ 37 PCLK_SCB5_CLOCK = 0x0004u, /* scb[5].clock */ 38 PCLK_SCB6_CLOCK = 0x0005u, /* scb[6].clock */ 39 PCLK_SMARTIO9_CLOCK = 0x0006u, /* smartio[9].clock */ 40 PCLK_TCPWM0_CLOCKS0 = 0x0007u, /* tcpwm[0].clocks[0] */ 41 PCLK_TCPWM0_CLOCKS1 = 0x0008u, /* tcpwm[0].clocks[1] */ 42 PCLK_TCPWM0_CLOCKS2 = 0x0009u, /* tcpwm[0].clocks[2] */ 43 PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ 44 PCLK_TCPWM0_CLOCKS256 = 0x000Bu, /* tcpwm[0].clocks[256] */ 45 PCLK_TCPWM0_CLOCKS257 = 0x000Cu, /* tcpwm[0].clocks[257] */ 46 PCLK_TCPWM0_CLOCKS258 = 0x000Du, /* tcpwm[0].clocks[258] */ 47 PCLK_TCPWM0_CLOCKS259 = 0x000Eu, /* tcpwm[0].clocks[259] */ 48 PCLK_TCPWM0_CLOCKS260 = 0x000Fu, /* tcpwm[0].clocks[260] */ 49 PCLK_TCPWM0_CLOCKS261 = 0x0010u, /* tcpwm[0].clocks[261] */ 50 PCLK_TCPWM0_CLOCKS262 = 0x0011u, /* tcpwm[0].clocks[262] */ 51 PCLK_TCPWM0_CLOCKS263 = 0x0012u, /* tcpwm[0].clocks[263] */ 52 PCLK_CSD_CLOCK = 0x0013u, /* csd.clock */ 53 PCLK_LCD_CLOCK = 0x0014u, /* lcd.clock */ 54 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0015u, /* cpuss.clock_trace_in */ 55 PCLK_PASS_CLOCK_PUMP_PERI = 0x0016u, /* pass.clock_pump_peri */ 56 PCLK_PASS_CLOCK_SAR0 = 0x0017u, /* pass.clock_sar[0] */ 57 PCLK_CANFD0_CLOCK_CAN0 = 0x0018u, /* canfd[0].clock_can[0] */ 58 PCLK_USB_CLOCK_DEV_BRS = 0x0019u, /* usb.clock_dev_brs */ 59 PCLK_PASS_CLOCK_CTDAC = 0x001Au, /* pass.clock_ctdac */ 60 PCLK_PASS_CLOCK_SAR1 = 0x001Bu /* pass.clock_sar[1] */ 61 } en_clk_dst_t; 62 63 /* Trigger Group */ 64 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 65 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 66 */ 67 /* Trigger Group Inputs */ 68 /* Trigger Input Group 0 - PDMA0 Request Assignments */ 69 typedef enum 70 { 71 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 72 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 73 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 74 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 75 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 76 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 77 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 78 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 79 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ 80 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ 81 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ 82 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ 83 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ 84 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ 85 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ 86 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ 87 TRIG_IN_MUX_0_TCPWM0_TR_OUT00 = 0x00000011u, /* tcpwm[0].tr_out0[0] */ 88 TRIG_IN_MUX_0_TCPWM0_TR_OUT10 = 0x00000012u, /* tcpwm[0].tr_out1[0] */ 89 TRIG_IN_MUX_0_TCPWM0_TR_OUT01 = 0x00000014u, /* tcpwm[0].tr_out0[1] */ 90 TRIG_IN_MUX_0_TCPWM0_TR_OUT11 = 0x00000015u, /* tcpwm[0].tr_out1[1] */ 91 TRIG_IN_MUX_0_TCPWM0_TR_OUT02 = 0x00000017u, /* tcpwm[0].tr_out0[2] */ 92 TRIG_IN_MUX_0_TCPWM0_TR_OUT12 = 0x00000018u, /* tcpwm[0].tr_out1[2] */ 93 TRIG_IN_MUX_0_TCPWM0_TR_OUT03 = 0x0000001Au, /* tcpwm[0].tr_out0[3] */ 94 TRIG_IN_MUX_0_TCPWM0_TR_OUT13 = 0x0000001Bu, /* tcpwm[0].tr_out1[3] */ 95 TRIG_IN_MUX_0_TCPWM0_TR_OUT0256 = 0x0000001Du, /* tcpwm[0].tr_out0[256] */ 96 TRIG_IN_MUX_0_TCPWM0_TR_OUT1256 = 0x0000001Eu, /* tcpwm[0].tr_out1[256] */ 97 TRIG_IN_MUX_0_TCPWM0_TR_OUT0257 = 0x00000020u, /* tcpwm[0].tr_out0[257] */ 98 TRIG_IN_MUX_0_TCPWM0_TR_OUT1257 = 0x00000021u, /* tcpwm[0].tr_out1[257] */ 99 TRIG_IN_MUX_0_TCPWM0_TR_OUT0258 = 0x00000023u, /* tcpwm[0].tr_out0[258] */ 100 TRIG_IN_MUX_0_TCPWM0_TR_OUT1258 = 0x00000024u, /* tcpwm[0].tr_out1[258] */ 101 TRIG_IN_MUX_0_TCPWM0_TR_OUT0259 = 0x00000026u, /* tcpwm[0].tr_out0[259] */ 102 TRIG_IN_MUX_0_TCPWM0_TR_OUT1259 = 0x00000027u, /* tcpwm[0].tr_out1[259] */ 103 TRIG_IN_MUX_0_TCPWM0_TR_OUT0260 = 0x00000029u, /* tcpwm[0].tr_out0[260] */ 104 TRIG_IN_MUX_0_TCPWM0_TR_OUT1260 = 0x0000002Au, /* tcpwm[0].tr_out1[260] */ 105 TRIG_IN_MUX_0_TCPWM0_TR_OUT0261 = 0x0000002Cu, /* tcpwm[0].tr_out0[261] */ 106 TRIG_IN_MUX_0_TCPWM0_TR_OUT1261 = 0x0000002Du, /* tcpwm[0].tr_out1[261] */ 107 TRIG_IN_MUX_0_TCPWM0_TR_OUT0262 = 0x0000002Fu, /* tcpwm[0].tr_out0[262] */ 108 TRIG_IN_MUX_0_TCPWM0_TR_OUT1262 = 0x00000030u, /* tcpwm[0].tr_out1[262] */ 109 TRIG_IN_MUX_0_TCPWM0_TR_OUT0263 = 0x00000032u, /* tcpwm[0].tr_out0[263] */ 110 TRIG_IN_MUX_0_TCPWM0_TR_OUT1263 = 0x00000033u, /* tcpwm[0].tr_out1[263] */ 111 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ 112 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ 113 TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ 114 TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ 115 TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ 116 TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ 117 TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ 118 TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ 119 TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ 120 TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ 121 TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ 122 TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ 123 TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ 124 TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ 125 TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ 126 TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ 127 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ 128 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ 129 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ 130 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ 131 } en_trig_input_pdma0_tr_t; 132 133 /* Trigger Input Group 1 - PDMA1 Request Assignments */ 134 typedef enum 135 { 136 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 137 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 138 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 139 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 140 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 141 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 142 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 143 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 144 TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ 145 TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ 146 TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ 147 TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ 148 TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ 149 TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ 150 TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ 151 TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ 152 TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ 153 TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ 154 TRIG_IN_MUX_1_CSD_ADC_DONE = 0x00000145u, /* csd.tr_adc_done */ 155 TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ 156 TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ 157 TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ 158 TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ 159 TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ 160 TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ 161 TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ 162 TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ 163 TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ 164 TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ 165 TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ 166 TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u, /* lpcomp.dsi_comp1 */ 167 TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000156u /* canfd[0].tr_tmp_rtp_out[0] */ 168 } en_trig_input_pdma1_tr_t; 169 170 /* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ 171 typedef enum 172 { 173 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ 174 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ 175 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ 176 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ 177 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ 178 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ 179 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ 180 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ 181 TRIG_IN_MUX_2_TCPWM0_TR_OUT00 = 0x00000209u, /* tcpwm[0].tr_out0[0] */ 182 TRIG_IN_MUX_2_TCPWM0_TR_OUT10 = 0x0000020Au, /* tcpwm[0].tr_out1[0] */ 183 TRIG_IN_MUX_2_TCPWM0_TR_OUT01 = 0x0000020Cu, /* tcpwm[0].tr_out0[1] */ 184 TRIG_IN_MUX_2_TCPWM0_TR_OUT11 = 0x0000020Du, /* tcpwm[0].tr_out1[1] */ 185 TRIG_IN_MUX_2_TCPWM0_TR_OUT02 = 0x0000020Fu, /* tcpwm[0].tr_out0[2] */ 186 TRIG_IN_MUX_2_TCPWM0_TR_OUT12 = 0x00000210u, /* tcpwm[0].tr_out1[2] */ 187 TRIG_IN_MUX_2_TCPWM0_TR_OUT03 = 0x00000212u, /* tcpwm[0].tr_out0[3] */ 188 TRIG_IN_MUX_2_TCPWM0_TR_OUT13 = 0x00000213u, /* tcpwm[0].tr_out1[3] */ 189 TRIG_IN_MUX_2_TCPWM0_TR_OUT0256 = 0x00000221u, /* tcpwm[0].tr_out0[256] */ 190 TRIG_IN_MUX_2_TCPWM0_TR_OUT1256 = 0x00000222u, /* tcpwm[0].tr_out1[256] */ 191 TRIG_IN_MUX_2_TCPWM0_TR_OUT0257 = 0x00000224u, /* tcpwm[0].tr_out0[257] */ 192 TRIG_IN_MUX_2_TCPWM0_TR_OUT1257 = 0x00000225u, /* tcpwm[0].tr_out1[257] */ 193 TRIG_IN_MUX_2_TCPWM0_TR_OUT0258 = 0x00000227u, /* tcpwm[0].tr_out0[258] */ 194 TRIG_IN_MUX_2_TCPWM0_TR_OUT1258 = 0x00000228u, /* tcpwm[0].tr_out1[258] */ 195 TRIG_IN_MUX_2_TCPWM0_TR_OUT0259 = 0x0000022Au, /* tcpwm[0].tr_out0[259] */ 196 TRIG_IN_MUX_2_TCPWM0_TR_OUT1259 = 0x0000022Bu, /* tcpwm[0].tr_out1[259] */ 197 TRIG_IN_MUX_2_TCPWM0_TR_OUT0260 = 0x0000022Du, /* tcpwm[0].tr_out0[260] */ 198 TRIG_IN_MUX_2_TCPWM0_TR_OUT1260 = 0x0000022Eu, /* tcpwm[0].tr_out1[260] */ 199 TRIG_IN_MUX_2_TCPWM0_TR_OUT0261 = 0x00000230u, /* tcpwm[0].tr_out0[261] */ 200 TRIG_IN_MUX_2_TCPWM0_TR_OUT1261 = 0x00000231u, /* tcpwm[0].tr_out1[261] */ 201 TRIG_IN_MUX_2_TCPWM0_TR_OUT0262 = 0x00000233u, /* tcpwm[0].tr_out0[262] */ 202 TRIG_IN_MUX_2_TCPWM0_TR_OUT1262 = 0x00000234u, /* tcpwm[0].tr_out1[262] */ 203 TRIG_IN_MUX_2_TCPWM0_TR_OUT0263 = 0x00000236u, /* tcpwm[0].tr_out0[263] */ 204 TRIG_IN_MUX_2_TCPWM0_TR_OUT1263 = 0x00000237u, /* tcpwm[0].tr_out1[263] */ 205 TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ 206 TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ 207 TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ 208 TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ 209 TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ 210 TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ 211 TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ 212 TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ 213 TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ 214 TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ 215 TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ 216 TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ 217 TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ 218 TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ 219 TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ 220 TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ 221 TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ 222 TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ 223 TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ 224 TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ 225 TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ 226 TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ 227 TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ 228 TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ 229 TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ 230 TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ 231 TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ 232 TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ 233 TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ 234 TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ 235 TRIG_IN_MUX_2_PASS_SAR0_DONE = 0x00000273u, /* pass.tr_sar_out[0] */ 236 TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ 237 TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ 238 TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ 239 TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ 240 TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ 241 TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ 242 TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ 243 TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ 244 TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ 245 TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ 246 TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ 247 TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ 248 TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ 249 TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ 250 TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ 251 TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ 252 TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ 253 TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ 254 TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u, /* lpcomp.dsi_comp1 */ 255 TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000287u, /* canfd[0].tr_tmp_rtp_out[0] */ 256 TRIG_IN_MUX_2_PASS_CTDAC_EMPTY = 0x00000288u, /* pass.tr_ctdac_empty */ 257 TRIG_IN_MUX_2_PASS_CTB_CMP0 = 0x00000289u, /* pass.dsi_ctb_cmp0 */ 258 TRIG_IN_MUX_2_PASS_SAR1_DONE = 0x0000028Au /* pass.tr_sar_out[1] */ 259 } en_trig_input_tcpwm0_0_t; 260 261 /* Trigger Input Group 3 - TCPWM0 trigger multiplexer - 2nd */ 262 typedef enum 263 { 264 TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ 265 TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ 266 TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ 267 TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ 268 TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ 269 TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ 270 TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ 271 TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ 272 TRIG_IN_MUX_3_TCPWM0_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[0] */ 273 TRIG_IN_MUX_3_TCPWM0_TR_OUT10 = 0x0000030Au, /* tcpwm[0].tr_out1[0] */ 274 TRIG_IN_MUX_3_TCPWM0_TR_OUT01 = 0x0000030Cu, /* tcpwm[0].tr_out0[1] */ 275 TRIG_IN_MUX_3_TCPWM0_TR_OUT11 = 0x0000030Du, /* tcpwm[0].tr_out1[1] */ 276 TRIG_IN_MUX_3_TCPWM0_TR_OUT02 = 0x0000030Fu, /* tcpwm[0].tr_out0[2] */ 277 TRIG_IN_MUX_3_TCPWM0_TR_OUT12 = 0x00000310u, /* tcpwm[0].tr_out1[2] */ 278 TRIG_IN_MUX_3_TCPWM0_TR_OUT03 = 0x00000312u, /* tcpwm[0].tr_out0[3] */ 279 TRIG_IN_MUX_3_TCPWM0_TR_OUT13 = 0x00000313u, /* tcpwm[0].tr_out1[3] */ 280 TRIG_IN_MUX_3_TCPWM0_TR_OUT0256 = 0x00000321u, /* tcpwm[0].tr_out0[256] */ 281 TRIG_IN_MUX_3_TCPWM0_TR_OUT1256 = 0x00000322u, /* tcpwm[0].tr_out1[256] */ 282 TRIG_IN_MUX_3_TCPWM0_TR_OUT0257 = 0x00000324u, /* tcpwm[0].tr_out0[257] */ 283 TRIG_IN_MUX_3_TCPWM0_TR_OUT1257 = 0x00000325u, /* tcpwm[0].tr_out1[257] */ 284 TRIG_IN_MUX_3_TCPWM0_TR_OUT0258 = 0x00000327u, /* tcpwm[0].tr_out0[258] */ 285 TRIG_IN_MUX_3_TCPWM0_TR_OUT1258 = 0x00000328u, /* tcpwm[0].tr_out1[258] */ 286 TRIG_IN_MUX_3_TCPWM0_TR_OUT0259 = 0x0000032Au, /* tcpwm[0].tr_out0[259] */ 287 TRIG_IN_MUX_3_TCPWM0_TR_OUT1259 = 0x0000032Bu, /* tcpwm[0].tr_out1[259] */ 288 TRIG_IN_MUX_3_TCPWM0_TR_OUT0260 = 0x0000032Du, /* tcpwm[0].tr_out0[260] */ 289 TRIG_IN_MUX_3_TCPWM0_TR_OUT1260 = 0x0000032Eu, /* tcpwm[0].tr_out1[260] */ 290 TRIG_IN_MUX_3_TCPWM0_TR_OUT0261 = 0x00000330u, /* tcpwm[0].tr_out0[261] */ 291 TRIG_IN_MUX_3_TCPWM0_TR_OUT1261 = 0x00000331u, /* tcpwm[0].tr_out1[261] */ 292 TRIG_IN_MUX_3_TCPWM0_TR_OUT0262 = 0x00000333u, /* tcpwm[0].tr_out0[262] */ 293 TRIG_IN_MUX_3_TCPWM0_TR_OUT1262 = 0x00000334u, /* tcpwm[0].tr_out1[262] */ 294 TRIG_IN_MUX_3_TCPWM0_TR_OUT0263 = 0x00000336u, /* tcpwm[0].tr_out0[263] */ 295 TRIG_IN_MUX_3_TCPWM0_TR_OUT1263 = 0x00000337u, /* tcpwm[0].tr_out1[263] */ 296 TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ 297 TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ 298 TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ 299 TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ 300 TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ 301 TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ 302 TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ 303 TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ 304 TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ 305 TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ 306 TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ 307 TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ 308 TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ 309 TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ 310 TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ 311 TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ 312 TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ 313 TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ 314 TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ 315 TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ 316 TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ 317 TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ 318 TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ 319 TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ 320 TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ 321 TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ 322 TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ 323 TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ 324 TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ 325 TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ 326 TRIG_IN_MUX_3_PASS_SAR0_DONE = 0x00000373u, /* pass.tr_sar_out[0] */ 327 TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ 328 TRIG_IN_MUX_3_HSIOM_TR_OUT14 = 0x00000375u, /* peri.tr_io_input[14] */ 329 TRIG_IN_MUX_3_HSIOM_TR_OUT15 = 0x00000376u, /* peri.tr_io_input[15] */ 330 TRIG_IN_MUX_3_HSIOM_TR_OUT16 = 0x00000377u, /* peri.tr_io_input[16] */ 331 TRIG_IN_MUX_3_HSIOM_TR_OUT17 = 0x00000378u, /* peri.tr_io_input[17] */ 332 TRIG_IN_MUX_3_HSIOM_TR_OUT18 = 0x00000379u, /* peri.tr_io_input[18] */ 333 TRIG_IN_MUX_3_HSIOM_TR_OUT19 = 0x0000037Au, /* peri.tr_io_input[19] */ 334 TRIG_IN_MUX_3_HSIOM_TR_OUT20 = 0x0000037Bu, /* peri.tr_io_input[20] */ 335 TRIG_IN_MUX_3_HSIOM_TR_OUT21 = 0x0000037Cu, /* peri.tr_io_input[21] */ 336 TRIG_IN_MUX_3_HSIOM_TR_OUT22 = 0x0000037Du, /* peri.tr_io_input[22] */ 337 TRIG_IN_MUX_3_HSIOM_TR_OUT23 = 0x0000037Eu, /* peri.tr_io_input[23] */ 338 TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ 339 TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ 340 TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ 341 TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u, /* lpcomp.dsi_comp1 */ 342 TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x00000387u, /* canfd[0].tr_tmp_rtp_out[0] */ 343 TRIG_IN_MUX_3_PASS_CTDAC_EMPTY = 0x00000388u, /* pass.tr_ctdac_empty */ 344 TRIG_IN_MUX_3_PASS_CTB_CMP0 = 0x00000389u, /* pass.dsi_ctb_cmp1 */ 345 TRIG_IN_MUX_3_PASS_SAR1_DONE = 0x0000038Au /* pass.tr_sar_out[1] */ 346 } en_trig_input_tcpwm0_1_t; 347 348 /* Trigger Input Group 4 - HSIOM trigger multiplexer */ 349 typedef enum 350 { 351 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 352 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 353 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 354 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 355 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 356 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 357 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 358 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 359 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 360 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 361 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 362 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 363 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 364 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 365 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 366 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 367 TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ 368 TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ 369 TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ 370 TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ 371 TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ 372 TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ 373 TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ 374 TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ 375 TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ 376 TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ 377 TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ 378 TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ 379 TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ 380 TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ 381 TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ 382 TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ 383 TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ 384 TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ 385 TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ 386 TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ 387 TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ 388 TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ 389 TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ 390 TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ 391 TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ 392 TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ 393 TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ 394 TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ 395 TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ 396 TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ 397 TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ 398 TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ 399 TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ 400 TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ 401 TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ 402 TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ 403 TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ 404 TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ 405 TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ 406 TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ 407 TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ 408 TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ 409 TRIG_IN_MUX_4_TCPWM0_TR_OUT00 = 0x0000043Bu, /* tcpwm[0].tr_out0[0] */ 410 TRIG_IN_MUX_4_TCPWM0_TR_OUT10 = 0x0000043Cu, /* tcpwm[0].tr_out1[0] */ 411 TRIG_IN_MUX_4_TCPWM0_TR_OUT01 = 0x0000043Eu, /* tcpwm[0].tr_out0[1] */ 412 TRIG_IN_MUX_4_TCPWM0_TR_OUT11 = 0x0000043Fu, /* tcpwm[0].tr_out1[1] */ 413 TRIG_IN_MUX_4_TCPWM0_TR_OUT02 = 0x00000441u, /* tcpwm[0].tr_out0[2] */ 414 TRIG_IN_MUX_4_TCPWM0_TR_OUT12 = 0x00000442u, /* tcpwm[0].tr_out1[2] */ 415 TRIG_IN_MUX_4_TCPWM0_TR_OUT03 = 0x00000444u, /* tcpwm[0].tr_out0[3] */ 416 TRIG_IN_MUX_4_TCPWM0_TR_OUT13 = 0x00000445u, /* tcpwm[0].tr_out1[3] */ 417 TRIG_IN_MUX_4_TCPWM0_TR_OUT0256 = 0x00000453u, /* tcpwm[0].tr_out0[256] */ 418 TRIG_IN_MUX_4_TCPWM0_TR_OUT1256 = 0x00000454u, /* tcpwm[0].tr_out1[256] */ 419 TRIG_IN_MUX_4_TCPWM0_TR_OUT0257 = 0x00000456u, /* tcpwm[0].tr_out0[257] */ 420 TRIG_IN_MUX_4_TCPWM0_TR_OUT1257 = 0x00000457u, /* tcpwm[0].tr_out1[257] */ 421 TRIG_IN_MUX_4_TCPWM0_TR_OUT0258 = 0x00000459u, /* tcpwm[0].tr_out0[258] */ 422 TRIG_IN_MUX_4_TCPWM0_TR_OUT1258 = 0x0000045Au, /* tcpwm[0].tr_out1[258] */ 423 TRIG_IN_MUX_4_TCPWM0_TR_OUT0259 = 0x0000045Cu, /* tcpwm[0].tr_out0[259] */ 424 TRIG_IN_MUX_4_TCPWM0_TR_OUT1259 = 0x0000045Du, /* tcpwm[0].tr_out1[259] */ 425 TRIG_IN_MUX_4_TCPWM0_TR_OUT0260 = 0x0000045Fu, /* tcpwm[0].tr_out0[260] */ 426 TRIG_IN_MUX_4_TCPWM0_TR_OUT1260 = 0x00000460u, /* tcpwm[0].tr_out1[260] */ 427 TRIG_IN_MUX_4_TCPWM0_TR_OUT0261 = 0x00000462u, /* tcpwm[0].tr_out0[261] */ 428 TRIG_IN_MUX_4_TCPWM0_TR_OUT1261 = 0x00000463u, /* tcpwm[0].tr_out1[261] */ 429 TRIG_IN_MUX_4_TCPWM0_TR_OUT0262 = 0x00000465u, /* tcpwm[0].tr_out0[262] */ 430 TRIG_IN_MUX_4_TCPWM0_TR_OUT1262 = 0x00000466u, /* tcpwm[0].tr_out1[262] */ 431 TRIG_IN_MUX_4_TCPWM0_TR_OUT0263 = 0x00000468u, /* tcpwm[0].tr_out0[263] */ 432 TRIG_IN_MUX_4_TCPWM0_TR_OUT1263 = 0x00000469u, /* tcpwm[0].tr_out1[263] */ 433 TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ 434 TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ 435 TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ 436 TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ 437 TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ 438 TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ 439 TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ 440 TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ 441 TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ 442 TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ 443 TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ 444 TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ 445 TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ 446 TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ 447 TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ 448 TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ 449 TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ 450 TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ 451 TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ 452 TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ 453 TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ 454 TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ 455 TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ 456 TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ 457 TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ 458 TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ 459 TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ 460 TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ 461 TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ 462 TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ 463 TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ 464 TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ 465 TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ 466 TRIG_IN_MUX_4_PASS_SAR0_DONE = 0x000004D8u, /* pass.tr_sar_out[0] */ 467 TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ 468 TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ 469 TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ 470 TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ 471 TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ 472 TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu, /* lpcomp.dsi_comp1 */ 473 TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x000004DFu, /* canfd[0].tr_tmp_rtp_out[0] */ 474 TRIG_IN_MUX_4_PDMA1_TR_OUT29 = 0x000004E0u, /* cpuss.dw1_tr_out[29] */ 475 TRIG_IN_MUX_4_PDMA1_TR_OUT30 = 0x000004E1u, /* cpuss.dw1_tr_out[30] */ 476 TRIG_IN_MUX_4_PDMA1_TR_OUT31 = 0x000004E2u, /* cpuss.dw1_tr_out[31] */ 477 TRIG_IN_MUX_4_PASS_SAR1_DONE = 0x000004E3u, /* pass.tr_sar_out[1] */ 478 TRIG_IN_MUX_4_PDMA0_TR_OUT29 = 0x000004E4u /* cpuss.dw0_tr_out[29] */ 479 } en_trig_input_hsiom_t; 480 481 /* Trigger Input Group 5 - CPUSS Debug trigger multiplexer */ 482 typedef enum 483 { 484 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ 485 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ 486 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ 487 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ 488 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ 489 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ 490 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ 491 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ 492 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ 493 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ 494 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ 495 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ 496 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ 497 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ 498 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ 499 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ 500 TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ 501 TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ 502 TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ 503 TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ 504 TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ 505 TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ 506 TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ 507 TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ 508 TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ 509 TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ 510 TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ 511 TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ 512 TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ 513 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ 514 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ 515 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ 516 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ 517 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ 518 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ 519 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ 520 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ 521 TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ 522 TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ 523 TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ 524 TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ 525 TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ 526 TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ 527 TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ 528 TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ 529 TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ 530 TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ 531 TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ 532 TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ 533 TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ 534 TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ 535 TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ 536 TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ 537 TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ 538 TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ 539 TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ 540 TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ 541 TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ 542 TRIG_IN_MUX_5_TCPWM0_TR_OUT00 = 0x0000053Bu, /* tcpwm[0].tr_out0[0] */ 543 TRIG_IN_MUX_5_TCPWM0_TR_OUT10 = 0x0000053Cu, /* tcpwm[0].tr_out1[0] */ 544 TRIG_IN_MUX_5_TCPWM0_TR_OUT01 = 0x0000053Eu, /* tcpwm[0].tr_out0[1] */ 545 TRIG_IN_MUX_5_TCPWM0_TR_OUT11 = 0x0000053Fu, /* tcpwm[0].tr_out1[1] */ 546 TRIG_IN_MUX_5_TCPWM0_TR_OUT02 = 0x00000541u, /* tcpwm[0].tr_out0[2] */ 547 TRIG_IN_MUX_5_TCPWM0_TR_OUT12 = 0x00000542u, /* tcpwm[0].tr_out1[2] */ 548 TRIG_IN_MUX_5_TCPWM0_TR_OUT03 = 0x00000544u, /* tcpwm[0].tr_out0[3] */ 549 TRIG_IN_MUX_5_TCPWM0_TR_OUT13 = 0x00000545u, /* tcpwm[0].tr_out1[3] */ 550 TRIG_IN_MUX_5_TCPWM0_TR_OUT0256 = 0x00000553u, /* tcpwm[0].tr_out0[256] */ 551 TRIG_IN_MUX_5_TCPWM0_TR_OUT1256 = 0x00000554u, /* tcpwm[0].tr_out1[256] */ 552 TRIG_IN_MUX_5_TCPWM0_TR_OUT0257 = 0x00000556u, /* tcpwm[0].tr_out0[257] */ 553 TRIG_IN_MUX_5_TCPWM0_TR_OUT1257 = 0x00000557u, /* tcpwm[0].tr_out1[257] */ 554 TRIG_IN_MUX_5_TCPWM0_TR_OUT0258 = 0x00000559u, /* tcpwm[0].tr_out0[258] */ 555 TRIG_IN_MUX_5_TCPWM0_TR_OUT1258 = 0x0000055Au, /* tcpwm[0].tr_out1[258] */ 556 TRIG_IN_MUX_5_TCPWM0_TR_OUT0259 = 0x0000055Cu, /* tcpwm[0].tr_out0[259] */ 557 TRIG_IN_MUX_5_TCPWM0_TR_OUT1259 = 0x0000055Du, /* tcpwm[0].tr_out1[259] */ 558 TRIG_IN_MUX_5_TCPWM0_TR_OUT0260 = 0x0000055Fu, /* tcpwm[0].tr_out0[260] */ 559 TRIG_IN_MUX_5_TCPWM0_TR_OUT1260 = 0x00000560u, /* tcpwm[0].tr_out1[260] */ 560 TRIG_IN_MUX_5_TCPWM0_TR_OUT0261 = 0x00000562u, /* tcpwm[0].tr_out0[261] */ 561 TRIG_IN_MUX_5_TCPWM0_TR_OUT1261 = 0x00000563u, /* tcpwm[0].tr_out1[261] */ 562 TRIG_IN_MUX_5_TCPWM0_TR_OUT0262 = 0x00000565u, /* tcpwm[0].tr_out0[262] */ 563 TRIG_IN_MUX_5_TCPWM0_TR_OUT1262 = 0x00000566u, /* tcpwm[0].tr_out1[262] */ 564 TRIG_IN_MUX_5_TCPWM0_TR_OUT0263 = 0x00000568u, /* tcpwm[0].tr_out0[263] */ 565 TRIG_IN_MUX_5_TCPWM0_TR_OUT1263 = 0x00000569u, /* tcpwm[0].tr_out1[263] */ 566 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ 567 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ 568 TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ 569 TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ 570 TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ 571 TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ 572 TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ 573 TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ 574 TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ 575 TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ 576 TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ 577 TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ 578 TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ 579 TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ 580 TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ 581 TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ 582 TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ 583 TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ 584 TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ 585 TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ 586 TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ 587 TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ 588 TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ 589 TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ 590 TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ 591 TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ 592 TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ 593 TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ 594 TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ 595 TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ 596 TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ 597 TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ 598 TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ 599 TRIG_IN_MUX_5_PASS_SAR0_DONE = 0x000005D8u, /* pass.tr_sar_out[0] */ 600 TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ 601 TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ 602 TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ 603 TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ 604 TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ 605 TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ 606 TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ 607 TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ 608 TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ 609 TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ 610 TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ 611 TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ 612 TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ 613 TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ 614 TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ 615 TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ 616 TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ 617 TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ 618 TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ 619 TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ 620 TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ 621 TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ 622 TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ 623 TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ 624 TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ 625 TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ 626 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ 627 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ 628 TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ 629 TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu, /* lpcomp.dsi_comp1 */ 630 TRIG_IN_MUX_5_CANFD_TT_TR_OUT0 = 0x000005FBu, /* canfd[0].tr_tmp_rtp_out[0] */ 631 TRIG_IN_MUX_5_PDMA1_TR_OUT29 = 0x000005FCu, /* cpuss.dw1_tr_out[29] */ 632 TRIG_IN_MUX_5_PDMA1_TR_OUT30 = 0x000005FDu, /* cpuss.dw1_tr_out[30] */ 633 TRIG_IN_MUX_5_PDMA1_TR_OUT31 = 0x000005FEu, /* cpuss.dw1_tr_out[31] */ 634 TRIG_IN_MUX_5_PASS_SAR1_DONE = 0x000005FFu /* pass.tr_sar_out[1] */ 635 } en_trig_input_cpuss_cti_t; 636 637 /* Trigger Input Group 6 - MDMA trigger multiplexer */ 638 typedef enum 639 { 640 TRIG_IN_MUX_6_TCPWM0_TR_OUT0256 = 0x00000601u, /* tcpwm[0].tr_out0[256] */ 641 TRIG_IN_MUX_6_TCPWM0_TR_OUT1256 = 0x00000602u, /* tcpwm[0].tr_out1[256] */ 642 TRIG_IN_MUX_6_TCPWM0_TR_OUT0257 = 0x00000604u, /* tcpwm[0].tr_out0[257] */ 643 TRIG_IN_MUX_6_TCPWM0_TR_OUT1257 = 0x00000605u, /* tcpwm[0].tr_out1[257] */ 644 TRIG_IN_MUX_6_TCPWM0_TR_OUT0258 = 0x00000607u, /* tcpwm[0].tr_out0[258] */ 645 TRIG_IN_MUX_6_TCPWM0_TR_OUT1258 = 0x00000608u, /* tcpwm[0].tr_out1[258] */ 646 TRIG_IN_MUX_6_TCPWM0_TR_OUT0259 = 0x0000060Au, /* tcpwm[0].tr_out0[259] */ 647 TRIG_IN_MUX_6_TCPWM0_TR_OUT1259 = 0x0000060Bu, /* tcpwm[0].tr_out1[259] */ 648 TRIG_IN_MUX_6_TCPWM0_TR_OUT0260 = 0x0000060Du, /* tcpwm[0].tr_out0[260] */ 649 TRIG_IN_MUX_6_TCPWM0_TR_OUT1260 = 0x0000060Eu, /* tcpwm[0].tr_out1[260] */ 650 TRIG_IN_MUX_6_TCPWM0_TR_OUT0261 = 0x00000610u, /* tcpwm[0].tr_out0[261] */ 651 TRIG_IN_MUX_6_TCPWM0_TR_OUT1261 = 0x00000611u, /* tcpwm[0].tr_out1[261] */ 652 TRIG_IN_MUX_6_TCPWM0_TR_OUT0262 = 0x00000613u, /* tcpwm[0].tr_out0[262] */ 653 TRIG_IN_MUX_6_TCPWM0_TR_OUT1262 = 0x00000614u, /* tcpwm[0].tr_out1[262] */ 654 TRIG_IN_MUX_6_TCPWM0_TR_OUT0263 = 0x00000616u, /* tcpwm[0].tr_out0[263] */ 655 TRIG_IN_MUX_6_TCPWM0_TR_OUT1263 = 0x00000617u, /* tcpwm[0].tr_out1[263] */ 656 TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ 657 TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ 658 } en_trig_input_mdma_t; 659 660 /* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ 661 typedef enum 662 { 663 TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ 664 TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ 665 } en_trig_input_peri_freeze_t; 666 667 /* Trigger Input Group 8 - Capsense trigger multiplexer */ 668 typedef enum 669 { 670 TRIG_IN_MUX_8_TCPWM0_TR_OUT00 = 0x00000801u, /* tcpwm[0].tr_out0[0] */ 671 TRIG_IN_MUX_8_TCPWM0_TR_OUT10 = 0x00000802u, /* tcpwm[0].tr_out1[0] */ 672 TRIG_IN_MUX_8_TCPWM0_TR_OUT01 = 0x00000804u, /* tcpwm[0].tr_out0[1] */ 673 TRIG_IN_MUX_8_TCPWM0_TR_OUT11 = 0x00000805u, /* tcpwm[0].tr_out1[1] */ 674 TRIG_IN_MUX_8_TCPWM0_TR_OUT02 = 0x00000807u, /* tcpwm[0].tr_out0[2] */ 675 TRIG_IN_MUX_8_TCPWM0_TR_OUT12 = 0x00000808u, /* tcpwm[0].tr_out1[2] */ 676 TRIG_IN_MUX_8_TCPWM0_TR_OUT03 = 0x0000080Au, /* tcpwm[0].tr_out0[3] */ 677 TRIG_IN_MUX_8_TCPWM0_TR_OUT13 = 0x0000080Bu, /* tcpwm[0].tr_out1[3] */ 678 TRIG_IN_MUX_8_TCPWM0_TR_OUT0256 = 0x00000819u, /* tcpwm[0].tr_out0[256] */ 679 TRIG_IN_MUX_8_TCPWM0_TR_OUT1256 = 0x0000081Au, /* tcpwm[0].tr_out1[256] */ 680 TRIG_IN_MUX_8_TCPWM0_TR_OUT0257 = 0x0000081Cu, /* tcpwm[0].tr_out0[257] */ 681 TRIG_IN_MUX_8_TCPWM0_TR_OUT1257 = 0x0000081Du, /* tcpwm[0].tr_out1[257] */ 682 TRIG_IN_MUX_8_TCPWM0_TR_OUT0258 = 0x0000081Fu, /* tcpwm[0].tr_out0[258] */ 683 TRIG_IN_MUX_8_TCPWM0_TR_OUT1258 = 0x00000820u, /* tcpwm[0].tr_out1[258] */ 684 TRIG_IN_MUX_8_TCPWM0_TR_OUT0259 = 0x00000822u, /* tcpwm[0].tr_out0[259] */ 685 TRIG_IN_MUX_8_TCPWM0_TR_OUT1259 = 0x00000823u, /* tcpwm[0].tr_out1[259] */ 686 TRIG_IN_MUX_8_TCPWM0_TR_OUT0260 = 0x00000825u, /* tcpwm[0].tr_out0[260] */ 687 TRIG_IN_MUX_8_TCPWM0_TR_OUT1260 = 0x00000826u, /* tcpwm[0].tr_out1[260] */ 688 TRIG_IN_MUX_8_TCPWM0_TR_OUT0261 = 0x00000828u, /* tcpwm[0].tr_out0[261] */ 689 TRIG_IN_MUX_8_TCPWM0_TR_OUT1261 = 0x00000829u, /* tcpwm[0].tr_out1[261] */ 690 TRIG_IN_MUX_8_TCPWM0_TR_OUT0262 = 0x0000082Bu, /* tcpwm[0].tr_out0[262] */ 691 TRIG_IN_MUX_8_TCPWM0_TR_OUT1262 = 0x0000082Cu, /* tcpwm[0].tr_out1[262] */ 692 TRIG_IN_MUX_8_TCPWM0_TR_OUT0263 = 0x0000082Eu, /* tcpwm[0].tr_out0[263] */ 693 TRIG_IN_MUX_8_TCPWM0_TR_OUT1263 = 0x0000082Fu, /* tcpwm[0].tr_out1[263] */ 694 TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x0000086Du, /* peri.tr_io_input[0] */ 695 TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x0000086Eu, /* peri.tr_io_input[1] */ 696 TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x0000086Fu, /* peri.tr_io_input[2] */ 697 TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000870u, /* peri.tr_io_input[3] */ 698 TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000871u, /* peri.tr_io_input[4] */ 699 TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000872u, /* peri.tr_io_input[5] */ 700 TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000873u, /* peri.tr_io_input[6] */ 701 TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000874u, /* peri.tr_io_input[7] */ 702 TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000875u, /* peri.tr_io_input[8] */ 703 TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000876u, /* peri.tr_io_input[9] */ 704 TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000877u, /* peri.tr_io_input[10] */ 705 TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000878u, /* peri.tr_io_input[11] */ 706 TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000879u, /* peri.tr_io_input[12] */ 707 TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000087Au, /* peri.tr_io_input[13] */ 708 TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000087Bu, /* peri.tr_io_input[14] */ 709 TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x0000087Cu, /* peri.tr_io_input[15] */ 710 TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x0000087Du, /* peri.tr_io_input[16] */ 711 TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x0000087Eu, /* peri.tr_io_input[17] */ 712 TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x0000087Fu, /* peri.tr_io_input[18] */ 713 TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000880u, /* peri.tr_io_input[19] */ 714 TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000881u, /* peri.tr_io_input[20] */ 715 TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000882u, /* peri.tr_io_input[21] */ 716 TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000883u, /* peri.tr_io_input[22] */ 717 TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000884u, /* peri.tr_io_input[23] */ 718 TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x00000889u, /* lpcomp.dsi_comp0 */ 719 TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000088Au /* lpcomp.dsi_comp1 */ 720 } en_trig_input_csd_t; 721 722 /* Trigger Input Group 9 - ADC trigger multiplexer */ 723 typedef enum 724 { 725 TRIG_IN_MUX_9_TCPWM0_TR_OUT00 = 0x00000901u, /* tcpwm[0].tr_out0[0] */ 726 TRIG_IN_MUX_9_TCPWM0_TR_OUT10 = 0x00000902u, /* tcpwm[0].tr_out1[0] */ 727 TRIG_IN_MUX_9_TCPWM0_TR_OUT01 = 0x00000904u, /* tcpwm[0].tr_out0[1] */ 728 TRIG_IN_MUX_9_TCPWM0_TR_OUT11 = 0x00000905u, /* tcpwm[0].tr_out1[1] */ 729 TRIG_IN_MUX_9_TCPWM0_TR_OUT02 = 0x00000907u, /* tcpwm[0].tr_out0[2] */ 730 TRIG_IN_MUX_9_TCPWM0_TR_OUT12 = 0x00000908u, /* tcpwm[0].tr_out1[2] */ 731 TRIG_IN_MUX_9_TCPWM0_TR_OUT03 = 0x0000090Au, /* tcpwm[0].tr_out0[3] */ 732 TRIG_IN_MUX_9_TCPWM0_TR_OUT13 = 0x0000090Bu, /* tcpwm[0].tr_out1[3] */ 733 TRIG_IN_MUX_9_TCPWM0_TR_OUT0256 = 0x00000919u, /* tcpwm[0].tr_out0[256] */ 734 TRIG_IN_MUX_9_TCPWM0_TR_OUT1256 = 0x0000091Au, /* tcpwm[0].tr_out1[256] */ 735 TRIG_IN_MUX_9_TCPWM0_TR_OUT0257 = 0x0000091Cu, /* tcpwm[0].tr_out0[257] */ 736 TRIG_IN_MUX_9_TCPWM0_TR_OUT1257 = 0x0000091Du, /* tcpwm[0].tr_out1[257] */ 737 TRIG_IN_MUX_9_TCPWM0_TR_OUT0258 = 0x0000091Fu, /* tcpwm[0].tr_out0[258] */ 738 TRIG_IN_MUX_9_TCPWM0_TR_OUT1258 = 0x00000920u, /* tcpwm[0].tr_out1[258] */ 739 TRIG_IN_MUX_9_TCPWM0_TR_OUT0259 = 0x00000922u, /* tcpwm[0].tr_out0[259] */ 740 TRIG_IN_MUX_9_TCPWM0_TR_OUT1259 = 0x00000923u, /* tcpwm[0].tr_out1[259] */ 741 TRIG_IN_MUX_9_TCPWM0_TR_OUT0260 = 0x00000925u, /* tcpwm[0].tr_out0[260] */ 742 TRIG_IN_MUX_9_TCPWM0_TR_OUT1260 = 0x00000926u, /* tcpwm[0].tr_out1[260] */ 743 TRIG_IN_MUX_9_TCPWM0_TR_OUT0261 = 0x00000928u, /* tcpwm[0].tr_out0[261] */ 744 TRIG_IN_MUX_9_TCPWM0_TR_OUT1261 = 0x00000929u, /* tcpwm[0].tr_out1[261] */ 745 TRIG_IN_MUX_9_TCPWM0_TR_OUT0262 = 0x0000092Bu, /* tcpwm[0].tr_out0[262] */ 746 TRIG_IN_MUX_9_TCPWM0_TR_OUT1262 = 0x0000092Cu, /* tcpwm[0].tr_out1[262] */ 747 TRIG_IN_MUX_9_TCPWM0_TR_OUT0263 = 0x0000092Eu, /* tcpwm[0].tr_out0[263] */ 748 TRIG_IN_MUX_9_TCPWM0_TR_OUT1263 = 0x0000092Fu, /* tcpwm[0].tr_out1[263] */ 749 TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ 750 TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ 751 TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ 752 TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ 753 TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ 754 TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ 755 TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ 756 TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ 757 TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ 758 TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ 759 TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ 760 TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ 761 TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ 762 TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ 763 TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ 764 TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ 765 TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ 766 TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ 767 TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ 768 TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ 769 TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ 770 TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ 771 TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ 772 TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ 773 TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ 774 TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ 775 } en_trig_input_sar_adc_start_t; 776 777 /* Trigger Input Group 10 - CAN TT Synchronization triggers */ 778 typedef enum 779 { 780 TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ 781 } en_trig_input_cantt_t; 782 783 /* Trigger Input Group 11 - CTDAC trigger multiplexer */ 784 typedef enum 785 { 786 TRIG_IN_MUX_11_TCPWM0_TR_OUT00 = 0x00000B01u, /* tcpwm[0].tr_out0[0] */ 787 TRIG_IN_MUX_11_TCPWM0_TR_OUT10 = 0x00000B02u, /* tcpwm[0].tr_out1[0] */ 788 TRIG_IN_MUX_11_TCPWM0_TR_OUT01 = 0x00000B03u, /* tcpwm[0].tr_out0[1] */ 789 TRIG_IN_MUX_11_TCPWM0_TR_OUT11 = 0x00000B04u, /* tcpwm[0].tr_out1[1] */ 790 TRIG_IN_MUX_11_TCPWM0_TR_OUT02 = 0x00000B05u, /* tcpwm[0].tr_out0[2] */ 791 TRIG_IN_MUX_11_TCPWM0_TR_OUT12 = 0x00000B06u, /* tcpwm[0].tr_out1[2] */ 792 TRIG_IN_MUX_11_TCPWM0_TR_OUT03 = 0x00000B07u, /* tcpwm[0].tr_out0[3] */ 793 TRIG_IN_MUX_11_TCPWM0_TR_OUT13 = 0x00000B08u, /* tcpwm[0].tr_out1[3] */ 794 TRIG_IN_MUX_11_TCPWM0_TR_OUT0256 = 0x00000B09u, /* tcpwm[0].tr_out0[256] */ 795 TRIG_IN_MUX_11_TCPWM0_TR_OUT1256 = 0x00000B0Au, /* tcpwm[0].tr_out1[256] */ 796 TRIG_IN_MUX_11_TCPWM0_TR_OUT0257 = 0x00000B0Bu, /* tcpwm[0].tr_out0[257] */ 797 TRIG_IN_MUX_11_TCPWM0_TR_OUT1257 = 0x00000B0Cu, /* tcpwm[0].tr_out1[257] */ 798 TRIG_IN_MUX_11_TCPWM0_TR_OUT0258 = 0x00000B0Du, /* tcpwm[0].tr_out0[258] */ 799 TRIG_IN_MUX_11_TCPWM0_TR_OUT1258 = 0x00000B0Eu, /* tcpwm[0].tr_out1[258] */ 800 TRIG_IN_MUX_11_TCPWM0_TR_OUT0259 = 0x00000B0Fu, /* tcpwm[0].tr_out0[259] */ 801 TRIG_IN_MUX_11_TCPWM0_TR_OUT1259 = 0x00000B10u, /* tcpwm[0].tr_out1[259] */ 802 TRIG_IN_MUX_11_TCPWM0_TR_OUT0260 = 0x00000B11u, /* tcpwm[0].tr_out0[260] */ 803 TRIG_IN_MUX_11_TCPWM0_TR_OUT1260 = 0x00000B12u, /* tcpwm[0].tr_out1[260] */ 804 TRIG_IN_MUX_11_TCPWM0_TR_OUT0261 = 0x00000B13u, /* tcpwm[0].tr_out0[261] */ 805 TRIG_IN_MUX_11_TCPWM0_TR_OUT1261 = 0x00000B14u, /* tcpwm[0].tr_out1[261] */ 806 TRIG_IN_MUX_11_TCPWM0_TR_OUT0262 = 0x00000B15u, /* tcpwm[0].tr_out0[262] */ 807 TRIG_IN_MUX_11_TCPWM0_TR_OUT1262 = 0x00000B16u, /* tcpwm[0].tr_out1[262] */ 808 TRIG_IN_MUX_11_TCPWM0_TR_OUT0263 = 0x00000B17u, /* tcpwm[0].tr_out0[263] */ 809 TRIG_IN_MUX_11_TCPWM0_TR_OUT1263 = 0x00000B18u, /* tcpwm[0].tr_out1[263] */ 810 TRIG_IN_MUX_11_HSIOM_TR_OUT0 = 0x00000B19u, /* peri.tr_io_input[0] */ 811 TRIG_IN_MUX_11_HSIOM_TR_OUT1 = 0x00000B1Au, /* peri.tr_io_input[1] */ 812 TRIG_IN_MUX_11_HSIOM_TR_OUT2 = 0x00000B1Bu, /* peri.tr_io_input[2] */ 813 TRIG_IN_MUX_11_HSIOM_TR_OUT3 = 0x00000B1Cu, /* peri.tr_io_input[3] */ 814 TRIG_IN_MUX_11_HSIOM_TR_OUT4 = 0x00000B1Du, /* peri.tr_io_input[4] */ 815 TRIG_IN_MUX_11_HSIOM_TR_OUT5 = 0x00000B1Eu, /* peri.tr_io_input[5] */ 816 TRIG_IN_MUX_11_HSIOM_TR_OUT6 = 0x00000B1Fu, /* peri.tr_io_input[6] */ 817 TRIG_IN_MUX_11_HSIOM_TR_OUT7 = 0x00000B20u, /* peri.tr_io_input[7] */ 818 TRIG_IN_MUX_11_HSIOM_TR_OUT8 = 0x00000B21u, /* peri.tr_io_input[8] */ 819 TRIG_IN_MUX_11_HSIOM_TR_OUT9 = 0x00000B22u, /* peri.tr_io_input[9] */ 820 TRIG_IN_MUX_11_HSIOM_TR_OUT10 = 0x00000B23u, /* peri.tr_io_input[10] */ 821 TRIG_IN_MUX_11_HSIOM_TR_OUT11 = 0x00000B24u, /* peri.tr_io_input[11] */ 822 TRIG_IN_MUX_11_HSIOM_TR_OUT12 = 0x00000B25u, /* peri.tr_io_input[12] */ 823 TRIG_IN_MUX_11_HSIOM_TR_OUT13 = 0x00000B26u, /* peri.tr_io_input[13] */ 824 TRIG_IN_MUX_11_HSIOM_TR_OUT14 = 0x00000B27u, /* peri.tr_io_input[14] */ 825 TRIG_IN_MUX_11_HSIOM_TR_OUT15 = 0x00000B28u, /* peri.tr_io_input[15] */ 826 TRIG_IN_MUX_11_HSIOM_TR_OUT16 = 0x00000B29u, /* peri.tr_io_input[16] */ 827 TRIG_IN_MUX_11_HSIOM_TR_OUT17 = 0x00000B2Au, /* peri.tr_io_input[17] */ 828 TRIG_IN_MUX_11_HSIOM_TR_OUT18 = 0x00000B2Bu, /* peri.tr_io_input[18] */ 829 TRIG_IN_MUX_11_HSIOM_TR_OUT19 = 0x00000B2Cu, /* peri.tr_io_input[19] */ 830 TRIG_IN_MUX_11_HSIOM_TR_OUT20 = 0x00000B2Du, /* peri.tr_io_input[20] */ 831 TRIG_IN_MUX_11_HSIOM_TR_OUT21 = 0x00000B2Eu, /* peri.tr_io_input[21] */ 832 TRIG_IN_MUX_11_HSIOM_TR_OUT22 = 0x00000B2Fu, /* peri.tr_io_input[22] */ 833 TRIG_IN_MUX_11_HSIOM_TR_OUT23 = 0x00000B30u, /* peri.tr_io_input[23] */ 834 TRIG_IN_MUX_11_LPCOMP_DSI_COMP0 = 0x00000B31u, /* lpcomp.dsi_comp0 */ 835 TRIG_IN_MUX_11_LPCOMP_DSI_COMP1 = 0x00000B32u /* lpcomp.dsi_comp1 */ 836 } en_trig_input_ctadc_strobe_t; 837 838 /* Trigger Group Outputs */ 839 /* Trigger Output Group 0 - PDMA0 Request Assignments */ 840 typedef enum 841 { 842 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 843 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 844 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 845 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 846 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 847 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 848 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 849 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ 850 } en_trig_output_pdma0_tr_t; 851 852 /* Trigger Output Group 1 - PDMA1 Request Assignments */ 853 typedef enum 854 { 855 TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ 856 TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ 857 TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ 858 TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ 859 TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ 860 TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ 861 TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ 862 TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ 863 } en_trig_output_pdma1_tr_t; 864 865 /* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ 866 typedef enum 867 { 868 TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_all_cnt_in[0] */ 869 TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_all_cnt_in[1] */ 870 TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_all_cnt_in[2] */ 871 TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_all_cnt_in[3] */ 872 TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_all_cnt_in[4] */ 873 TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_all_cnt_in[5] */ 874 TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_all_cnt_in[6] */ 875 TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_all_cnt_in[7] */ 876 TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_all_cnt_in[8] */ 877 TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_all_cnt_in[9] */ 878 TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_all_cnt_in[10] */ 879 TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[11] */ 880 TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_all_cnt_in[12] */ 881 TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_all_cnt_in[13] */ 882 } en_trig_output_tcpwm0_0_t; 883 884 /* Trigger Output Group 3 - TCPWM0 trigger multiplexer - 2nd */ 885 typedef enum 886 { 887 TRIG_OUT_MUX_3_TCPWM0_TR_IN14 = 0x40000300u, /* tcpwm[0].tr_all_cnt_in[14] */ 888 TRIG_OUT_MUX_3_TCPWM0_TR_IN15 = 0x40000301u, /* tcpwm[0].tr_all_cnt_in[15] */ 889 TRIG_OUT_MUX_3_TCPWM0_TR_IN16 = 0x40000302u, /* tcpwm[0].tr_all_cnt_in[16] */ 890 TRIG_OUT_MUX_3_TCPWM0_TR_IN17 = 0x40000303u, /* tcpwm[0].tr_all_cnt_in[17] */ 891 TRIG_OUT_MUX_3_TCPWM0_TR_IN18 = 0x40000304u, /* tcpwm[0].tr_all_cnt_in[18] */ 892 TRIG_OUT_MUX_3_TCPWM0_TR_IN19 = 0x40000305u, /* tcpwm[0].tr_all_cnt_in[19] */ 893 TRIG_OUT_MUX_3_TCPWM0_TR_IN20 = 0x40000306u, /* tcpwm[0].tr_all_cnt_in[20] */ 894 TRIG_OUT_MUX_3_TCPWM0_TR_IN21 = 0x40000307u, /* tcpwm[0].tr_all_cnt_in[21] */ 895 TRIG_OUT_MUX_3_TCPWM0_TR_IN22 = 0x40000308u, /* tcpwm[0].tr_all_cnt_in[22] */ 896 TRIG_OUT_MUX_3_TCPWM0_TR_IN23 = 0x40000309u, /* tcpwm[0].tr_all_cnt_in[23] */ 897 TRIG_OUT_MUX_3_TCPWM0_TR_IN24 = 0x4000030Au, /* tcpwm[0].tr_all_cnt_in[24] */ 898 TRIG_OUT_MUX_3_TCPWM0_TR_IN25 = 0x4000030Bu, /* tcpwm[0].tr_all_cnt_in[25] */ 899 TRIG_OUT_MUX_3_TCPWM0_TR_IN26 = 0x4000030Cu, /* tcpwm[0].tr_all_cnt_in[26] */ 900 TRIG_OUT_MUX_3_TCPWM0_TR_IN27 = 0x4000030Du /* tcpwm[0].tr_all_cnt_in[27] */ 901 } en_trig_output_tcpwm0_1_t; 902 903 /* Trigger Output Group 4 - HSIOM trigger multiplexer */ 904 typedef enum 905 { 906 TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ 907 TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ 908 } en_trig_output_hsiom_t; 909 910 /* Trigger Output Group 5 - CPUSS Debug trigger multiplexer */ 911 typedef enum 912 { 913 TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ 914 TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ 915 } en_trig_output_cpuss_cti_t; 916 917 /* Trigger Output Group 6 - MDMA trigger multiplexer */ 918 typedef enum 919 { 920 TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ 921 TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u /* cpuss.dmac_tr_in[1] */ 922 } en_trig_output_mdma_t; 923 924 /* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ 925 typedef enum 926 { 927 TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u, /* peri.tr_dbg_freeze */ 928 TRIG_OUT_MUX_7_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000701u /* tcpwm[0].tr_debug_freeze */ 929 } en_trig_output_peri_freeze_t; 930 931 /* Trigger Output Group 8 - Capsense trigger multiplexer */ 932 typedef enum 933 { 934 TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ 935 } en_trig_output_csd_t; 936 937 /* Trigger Output Group 9 - ADC trigger multiplexer */ 938 typedef enum 939 { 940 TRIG_OUT_MUX_9_PASS_TR_SAR_IN0 = 0x40000900u, /* pass.tr_sar_in[0] */ 941 TRIG_OUT_MUX_9_PASS_TR_SAR_IN1 = 0x40000901u /* pass.tr_sar_in[1] */ 942 } en_trig_output_sar_adc_start_t; 943 944 /* Trigger Output Group 10 - CAN TT Synchronization triggers */ 945 typedef enum 946 { 947 TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ 948 } en_trig_output_cantt_t; 949 950 /* Trigger Output Group 11 - CTDAC trigger multiplexer */ 951 typedef enum 952 { 953 TRIG_OUT_MUX_11_PASS_CTDAC_STROBE = 0x40000B00u /* pass.dsi_ctdac_strobe */ 954 } en_trig_output_ctadc_strobe_t; 955 956 /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ 957 typedef enum 958 { 959 TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ 960 TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ 961 TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ 962 TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ 963 TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ 964 TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ 965 TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN22 = 0x40001006u, /* From cpuss.zero to cpuss.dw0_tr_in[22] */ 966 TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN23 = 0x40001007u, /* From cpuss.zero to cpuss.dw0_tr_in[23] */ 967 TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ 968 TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ 969 TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ 970 TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ 971 } en_trig_output_1to1_scb_pdma0_tr_t; 972 973 /* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ 974 typedef enum 975 { 976 TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ 977 TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ 978 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN10 = 0x40001102u, /* From cpuss.zero to cpuss.dw1_tr_in[10] */ 979 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN11 = 0x40001103u, /* From cpuss.zero to cpuss.dw1_tr_in[11] */ 980 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN12 = 0x40001104u, /* From cpuss.zero to cpuss.dw1_tr_in[12] */ 981 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN13 = 0x40001105u, /* From cpuss.zero to cpuss.dw1_tr_in[13] */ 982 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN14 = 0x40001106u, /* From cpuss.zero to cpuss.dw1_tr_in[14] */ 983 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN15 = 0x40001107u, /* From cpuss.zero to cpuss.dw1_tr_in[15] */ 984 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN16 = 0x40001108u, /* From cpuss.zero to cpuss.dw1_tr_in[16] */ 985 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN17 = 0x40001109u, /* From cpuss.zero to cpuss.dw1_tr_in[17] */ 986 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN18 = 0x4000110Au, /* From cpuss.zero to cpuss.dw1_tr_in[18] */ 987 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN19 = 0x4000110Bu, /* From cpuss.zero to cpuss.dw1_tr_in[19] */ 988 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN20 = 0x4000110Cu, /* From cpuss.zero to cpuss.dw1_tr_in[20] */ 989 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN21 = 0x4000110Du /* From cpuss.zero to cpuss.dw1_tr_in[21] */ 990 } en_trig_output_1to1_scb_pdma1_tr_t; 991 992 /* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ 993 typedef enum 994 { 995 TRIG_OUT_1TO1_2_PASS_SAR0_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out[0] to cpuss.dw0_tr_in[28] */ 996 } en_trig_output_1to1_sar0_to_pdma1_t; 997 998 /* Trigger Output Group 3 - (OneToOne) */ 999 typedef enum 1000 { 1001 TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ 1002 TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u, /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ 1003 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN24 = 0x40001302u, /* From cpuss.zero to cpuss.dw1_tr_in[24] */ 1004 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN25 = 0x40001303u, /* From cpuss.zero to cpuss.dw1_tr_in[25] */ 1005 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN26 = 0x40001304u, /* From cpuss.zero to cpuss.dw1_tr_in[26] */ 1006 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN27 = 0x40001305u, /* From cpuss.zero to cpuss.dw1_tr_in[27] */ 1007 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN28 = 0x40001306u /* From cpuss.zero to cpuss.dw1_tr_in[28] */ 1008 } en_trig_output_1to1_smif_to_pdma1_t; 1009 1010 /* Trigger Output Group 4 - CAN DW triggers (OneToOne) */ 1011 typedef enum 1012 { 1013 TRIG_OUT_1TO1_4_CAN_DBG_TO_PDMA1_TR_IN29 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[29] */ 1014 TRIG_OUT_1TO1_4_CAN_FIFO0_TO_PDMA1_TR_IN30 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw1_tr_in[30] */ 1015 TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ 1016 } en_trig_output_1to1_can_dw_tr_t; 1017 1018 /* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ 1019 typedef enum 1020 { 1021 TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ 1022 TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ 1023 TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ 1024 TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ 1025 TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ 1026 TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ 1027 TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ 1028 TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ 1029 } en_trig_output_1to1_usb_pdma0_tr_t; 1030 1031 /* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ 1032 typedef enum 1033 { 1034 TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ 1035 TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ 1036 TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ 1037 TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ 1038 TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ 1039 TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ 1040 TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ 1041 TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ 1042 } en_trig_output_1to1_usb_pdma0_ack_tr_t; 1043 1044 /* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ 1045 typedef enum 1046 { 1047 TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ 1048 } en_trig_output_1to1_can0_dw_ack_t; 1049 1050 /* Trigger Output Group 8 - PASS SAR1 to PDMA0 direct connect (OneToOne) */ 1051 typedef enum 1052 { 1053 TRIG_OUT_1TO1_8_PASS_SAR1_DONE_TO_PDMA0_TR_IN29 = 0x40001800u /* From pass.tr_sar_out[1] to cpuss.dw0_tr_in[29] */ 1054 } en_trig_output_1to1_sar1_to_pdma1_t; 1055 1056 /* Level or edge detection setting for a trigger mux */ 1057 typedef enum 1058 { 1059 /* The trigger is a simple level output */ 1060 TRIGGER_TYPE_LEVEL = 0u, 1061 /* The trigger is synchronized to the consumer blocks clock 1062 and a two cycle pulse is generated on this clock */ 1063 TRIGGER_TYPE_EDGE = 1u 1064 } en_trig_type_t; 1065 1066 /* Trigger Type Defines */ 1067 /* CANFD Trigger Types */ 1068 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1069 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1070 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1071 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1072 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1073 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1074 /* CPUSS Trigger Types */ 1075 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1076 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1077 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1078 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1079 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1080 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1081 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1082 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1083 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1084 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1085 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1086 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1087 /* CSD Trigger Types */ 1088 #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE 1089 /* LPCOMP Trigger Types */ 1090 #define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL 1091 #define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL 1092 /* PASS Trigger Types */ 1093 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL 1094 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE 1095 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL 1096 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE 1097 #define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE 1098 #define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL 1099 #define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE 1100 #define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE 1101 /* PERI Trigger Types */ 1102 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1103 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1104 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1105 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1106 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1107 /* SCB Trigger Types */ 1108 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1109 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1110 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1111 /* SMIF Trigger Types */ 1112 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 1113 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 1114 /* TCPWM Trigger Types */ 1115 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1116 /* USB Trigger Types */ 1117 #define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE 1118 #define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE 1119 1120 /* Fault connections */ 1121 typedef enum 1122 { 1123 CPUSS_MPU_VIO_0 = 0x0000u, 1124 CPUSS_MPU_VIO_1 = 0x0001u, 1125 CPUSS_MPU_VIO_2 = 0x0002u, 1126 CPUSS_MPU_VIO_3 = 0x0003u, 1127 CPUSS_MPU_VIO_4 = 0x0004u, 1128 CPUSS_MPU_VIO_15 = 0x000Fu, 1129 CPUSS_MPU_VIO_16 = 0x0010u, 1130 CPUSS_MPU_VIO_17 = 0x0011u, 1131 CPUSS_MPU_VIO_18 = 0x0012u, 1132 PERI_MS_VIO_0 = 0x001Cu, 1133 PERI_MS_VIO_1 = 0x001Du, 1134 PERI_MS_VIO_2 = 0x001Eu, 1135 PERI_MS_VIO_3 = 0x001Fu, 1136 PERI_GROUP_VIO_0 = 0x0020u, 1137 PERI_GROUP_VIO_1 = 0x0021u, 1138 PERI_GROUP_VIO_2 = 0x0022u, 1139 PERI_GROUP_VIO_3 = 0x0023u, 1140 PERI_GROUP_VIO_4 = 0x0024u, 1141 PERI_GROUP_VIO_5 = 0x0025u, 1142 PERI_GROUP_VIO_6 = 0x0026u, 1143 PERI_GROUP_VIO_9 = 0x0029u, 1144 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u 1145 } en_sysfault_source_t; 1146 1147 /* Bus masters */ 1148 typedef enum 1149 { 1150 CPUSS_MS_ID_CM0 = 0, 1151 CPUSS_MS_ID_CRYPTO = 1, 1152 CPUSS_MS_ID_DW0 = 2, 1153 CPUSS_MS_ID_DW1 = 3, 1154 CPUSS_MS_ID_DMAC = 4, 1155 CPUSS_MS_ID_SLOW0 = 5, 1156 CPUSS_MS_ID_SLOW1 = 6, 1157 CPUSS_MS_ID_CM4 = 14, 1158 CPUSS_MS_ID_TC = 15 1159 } en_prot_master_t; 1160 1161 /* Pointer to device configuration structure */ 1162 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_04) 1163 1164 /* Include IP definitions */ 1165 #include "ip/cyip_sflash_psoc6_04.h" 1166 #include "ip/cyip_peri_v2.h" 1167 #include "ip/cyip_peri_ms_v2.h" 1168 #include "ip/cyip_crypto_v2.h" 1169 #include "ip/cyip_cpuss_v2.h" 1170 #include "ip/cyip_fault_v2.h" 1171 #include "ip/cyip_ipc_v2.h" 1172 #include "ip/cyip_prot_v2.h" 1173 #include "ip/cyip_flashc_v2.h" 1174 #include "ip/cyip_srss.h" 1175 #include "ip/cyip_backup.h" 1176 #include "ip/cyip_dw_v2.h" 1177 #include "ip/cyip_dmac_v2.h" 1178 #include "ip/cyip_efuse.h" 1179 #include "ip/cyip_efuse_data_psoc6_04.h" 1180 #include "ip/cyip_hsiom_v2.h" 1181 #include "ip/cyip_gpio_v2.h" 1182 #include "ip/cyip_smartio_v2.h" 1183 #include "ip/cyip_lpcomp.h" 1184 #include "ip/cyip_csd.h" 1185 #include "ip/cyip_tcpwm_v2.h" 1186 #include "ip/cyip_lcd_v2.h" 1187 #include "ip/cyip_usbfs.h" 1188 #include "ip/cyip_smif.h" 1189 #include "ip/cyip_canfd.h" 1190 #include "ip/cyip_scb.h" 1191 #include "ip/cyip_ctbm_v2.h" 1192 #include "ip/cyip_ctdac_v2.h" 1193 #include "ip/cyip_sar_v2.h" 1194 #include "ip/cyip_pass_v2.h" 1195 1196 /* IP type definitions */ 1197 typedef SFLASH_V1_Type SFLASH_Type; 1198 typedef PERI_GR_V2_Type PERI_GR_Type; 1199 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 1200 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 1201 typedef PERI_V2_Type PERI_Type; 1202 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 1203 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 1204 typedef PERI_MS_V2_Type PERI_MS_Type; 1205 typedef CRYPTO_V2_Type CRYPTO_Type; 1206 typedef CPUSS_V2_Type CPUSS_Type; 1207 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 1208 typedef FAULT_V2_Type FAULT_Type; 1209 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 1210 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 1211 typedef IPC_V2_Type IPC_Type; 1212 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 1213 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 1214 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 1215 typedef PROT_MPU_V2_Type PROT_MPU_Type; 1216 typedef PROT_V2_Type PROT_Type; 1217 typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; 1218 typedef FLASHC_V2_Type FLASHC_Type; 1219 typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; 1220 typedef SRSS_V1_Type SRSS_Type; 1221 typedef BACKUP_V1_Type BACKUP_Type; 1222 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 1223 typedef DW_V2_Type DW_Type; 1224 typedef DMAC_CH_V2_Type DMAC_CH_Type; 1225 typedef DMAC_V2_Type DMAC_Type; 1226 typedef EFUSE_V1_Type EFUSE_Type; 1227 typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; 1228 typedef HSIOM_V2_Type HSIOM_Type; 1229 typedef GPIO_PRT_V2_Type GPIO_PRT_Type; 1230 typedef GPIO_V2_Type GPIO_Type; 1231 typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; 1232 typedef SMARTIO_V2_Type SMARTIO_Type; 1233 typedef LPCOMP_V1_Type LPCOMP_Type; 1234 typedef CSD_V1_Type CSD_Type; 1235 typedef TCPWM_GRP_CNT_V2_Type TCPWM_GRP_CNT_Type; 1236 typedef TCPWM_GRP_V2_Type TCPWM_GRP_Type; 1237 typedef TCPWM_V2_Type TCPWM_Type; 1238 typedef LCD_V2_Type LCD_Type; 1239 typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; 1240 typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; 1241 typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; 1242 typedef USBFS_V1_Type USBFS_Type; 1243 typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; 1244 typedef SMIF_V1_Type SMIF_Type; 1245 typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; 1246 typedef CANFD_CH_V1_Type CANFD_CH_Type; 1247 typedef CANFD_V1_Type CANFD_Type; 1248 typedef CySCB_V1_Type CySCB_Type; 1249 typedef CTBM_V2_Type CTBM_Type; 1250 typedef CTDAC_V2_Type CTDAC_Type; 1251 typedef SAR_V2_Type SAR_Type; 1252 typedef PASS_TIMER_V2_Type PASS_TIMER_Type; 1253 typedef PASS_LPOSC_V2_Type PASS_LPOSC_Type; 1254 typedef PASS_FIFO_V2_Type PASS_FIFO_Type; 1255 typedef PASS_AREFV2_V2_Type PASS_AREFV2_Type; 1256 typedef PASS_V2_Type PASS_Type; 1257 1258 /* Parameter Defines */ 1259 /* Number of TTCAN instances */ 1260 #define CANFD_CAN_NR 1u 1261 /* ECC logic present or not */ 1262 #define CANFD_ECC_PRESENT 0u 1263 /* address included in ECC logic or not */ 1264 #define CANFD_ECC_ADDR_PRESENT 0u 1265 /* Time Stamp counter present or not (required for instance 0, otherwise not 1266 allowed) */ 1267 #define CANFD_TS_PRESENT 1u 1268 /* Message RAM size in KB */ 1269 #define CANFD_MRAM_SIZE 4u 1270 /* Message RAM address width */ 1271 #define CANFD_MRAM_ADDR_WIDTH 10u 1272 /* UDB present or not ('0': no, '1': yes) */ 1273 #define CPUSS_UDB_PRESENT 0u 1274 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 1275 chips which doesn't use mxdft. */ 1276 #define CPUSS_MBIST_MMIO_PRESENT 1u 1277 /* System RAM 0 size in kilobytes */ 1278 #define CPUSS_SRAM0_SIZE 128u 1279 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System 1280 SRAM0 is implemented with 8 32KB macros. */ 1281 #define CPUSS_RAMC0_MACRO_NR 4u 1282 /* System RAM 1 present or not (0=No, 1=Yes) */ 1283 #define CPUSS_RAMC1_PRESENT 0u 1284 /* System RAM 1 size in kilobytes */ 1285 #define CPUSS_SRAM1_SIZE 1u 1286 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 1287 RAM 1 is implemented with 8 32KB macros. */ 1288 #define CPUSS_RAMC1_MACRO_NR 1u 1289 /* System RAM 2 present or not (0=No, 1=Yes) */ 1290 #define CPUSS_RAMC2_PRESENT 0u 1291 /* System RAM 2 size in kilobytes */ 1292 #define CPUSS_SRAM2_SIZE 1u 1293 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 1294 RAM 2 is implemented with 8 32KB macros. */ 1295 #define CPUSS_RAMC2_MACRO_NR 1u 1296 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 1297 #define CPUSS_RAMC_ECC_PRESENT 0u 1298 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 1299 #define CPUSS_RAMC_ECC_ADDR_PRESENT 0u 1300 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 1301 #define CPUSS_ECC_PRESENT 0u 1302 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1303 #define CPUSS_DW_ECC_PRESENT 0u 1304 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 1305 #define CPUSS_DW_ECC_ADDR_PRESENT 0u 1306 /* System ROM size in KB */ 1307 #define CPUSS_ROM_SIZE 64u 1308 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 1309 is implemented with 4 128KB macros. */ 1310 #define CPUSS_ROMC_MACRO_NR 1u 1311 /* Flash memory present or not ('0': no, '1': yes) */ 1312 #define CPUSS_FLASHC_PRESENT 1u 1313 /* Flash memory type ('0' : SONOS, '1': ECT) */ 1314 #define CPUSS_FLASHC_ECT 0u 1315 /* Flash main region size in KB */ 1316 #define CPUSS_FLASH_SIZE 256u 1317 /* Flash work region size in KB (EEPROM emulation, data) */ 1318 #define CPUSS_WFLASH_SIZE 0u 1319 /* Flash supervisory region size in KB */ 1320 #define CPUSS_SFLASH_SIZE 32u 1321 /* Flash data output word size (in Bytes) */ 1322 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u 1323 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 1324 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 1325 Flash, and no Work Flash present. */ 1326 #define CPUSS_FLASHC_SONOS_RWW 1u 1327 /* SONOS Flash, number of main sectors. */ 1328 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u 1329 /* SONOS Flash, number of rows per main sector. */ 1330 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 256u 1331 /* SONOS Flash, number of words per row of main sector. */ 1332 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u 1333 /* SONOS Flash, number of special sectors. */ 1334 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 1u 1335 /* SONOS Flash, number of rows per special sector. */ 1336 #define CPUSS_FLASHC_SONOS_SPL_ROWS 64u 1337 /* Flash memory ECC present or not ('0': no, '1': yes) */ 1338 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u 1339 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 1340 #define CPUSS_FLASHC_RAM_ECC_PRESENT 0u 1341 /* Number of external slaves directly connected to slow AHB-Lite infrastructure. 1342 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1343 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1344 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK 1345 parameters (for the slaves present) should be derived from the Memory Map. */ 1346 #define CPUSS_SLOW_SL_PRESENT 1u 1347 /* Number of external slaves directly connected to fast AHB-Lite infrastructure. 1348 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1349 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1350 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 1351 parameters (for the slaves present) should be derived from the Memory Map. */ 1352 #define CPUSS_FAST_SL_PRESENT 1u 1353 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum 1354 number of masters supported is 2. Width of this parameter is 2-bits. 1-bit 1355 mask for each master indicating present or not. Example: 2'b01 - master 0 is 1356 present. */ 1357 #define CPUSS_SLOW_MS_PRESENT 0u 1358 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 1359 CM0+ PCU, which always uses system interrupt functionality. */ 1360 #define CPUSS_SYSTEM_IRQ_PRESENT 0u 1361 /* Number of total interrupt request inputs to CPUSS */ 1362 #define CPUSS_SYSTEM_INT_NR 175u 1363 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */ 1364 #define CPUSS_SYSTEM_DPSLP_INT_NR 45u 1365 /* CM4 CPU present or not ('0': no, '1': yes) */ 1366 #define CPUSS_CM4_PRESENT 1u 1367 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 1368 levels of priority 8 = 256 levels of priority */ 1369 #define CPUSS_CM4_LVL_WIDTH 3u 1370 /* CM4 Floating point unit present or not (0=No, 1=Yes) */ 1371 #define CPUSS_CM4_FPU_PRESENT 1u 1372 /* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 1373 breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 1374 watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ 1375 #define CPUSS_DEBUG_LVL 3u 1376 /* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + 1377 ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace 1378 level is not supported in CPUSS. */ 1379 #define CPUSS_TRACE_LVL 2u 1380 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */ 1381 #define CPUSS_ETB_PRESENT 0u 1382 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1383 #define CPUSS_MTB_SRAM_SIZE 4u 1384 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1385 #define CPUSS_ETB_SRAM_SIZE 8u 1386 /* PTM interface present (0=No, 1=Yes) */ 1387 #define CPUSS_PTM_PRESENT 0u 1388 /* Width of the PTM interface in bits ([2,32]) */ 1389 #define CPUSS_PTM_WIDTH 1u 1390 /* Width of the TPIU interface in bits ([1,4]) */ 1391 #define CPUSS_TPIU_WIDTH 4u 1392 /* CoreSight Part Identification Number */ 1393 #define CPUSS_JEPID 52u 1394 /* CoreSight Part Identification Number */ 1395 #define CPUSS_JEPCONTINUATION 0u 1396 /* CoreSight Part Identification Number */ 1397 #define CPUSS_FAMILYID 270u 1398 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 1399 #define CPUSS_ROM_TRIM_WIDTH 5u 1400 /* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ 1401 #define CPUSS_ROM_TRIM_DEFAULT 18u 1402 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 1403 #define CPUSS_RAM_TRIM_WIDTH 15u 1404 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 1405 #define CPUSS_RAM_TRIM_DEFAULT 0x00006012u 1406 /* Cryptography IP present or not (0=No, 1=Yes) */ 1407 #define CPUSS_CRYPTO_PRESENT 1u 1408 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1409 #define CPUSS_SW_TR_PRESENT 0u 1410 /* DataWire 0 present or not (0=No, 1=Yes) */ 1411 #define CPUSS_DW0_PRESENT 1u 1412 /* Number of DataWire 0 channels (8, 16 or 32) */ 1413 #define CPUSS_DW0_CH_NR 30u 1414 /* DataWire 1 present or not (0=No, 1=Yes) */ 1415 #define CPUSS_DW1_PRESENT 1u 1416 /* Number of DataWire 1 channels (8, 16 or 32) */ 1417 #define CPUSS_DW1_CH_NR 32u 1418 /* DMA controller present or not ('0': no, '1': yes) */ 1419 #define CPUSS_DMAC_PRESENT 1u 1420 /* Number of DMA controller channels ([1, 8]) */ 1421 #define CPUSS_DMAC_CH_NR 2u 1422 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1423 #define CPUSS_CH_SW_TR_PRESENT 0u 1424 /* Copy value from Globals */ 1425 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 1426 /* ETAS Calibration support pin out present (automotive only) */ 1427 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u 1428 /* TRACE_LVL>0 */ 1429 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 1430 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 1431 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u 1432 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 1433 #define CPUSS_CPUSS_DW_DW_NR 2u 1434 /* Number of channels in each DataWire controller */ 1435 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 30u 1436 /* Width of a channel number in bits */ 1437 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u 1438 /* Number of channels in each DataWire controller */ 1439 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u 1440 /* Width of a channel number in bits */ 1441 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u 1442 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 1443 #define CPUSS_CRYPTO_ECC_PRESENT 0u 1444 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 1445 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u 1446 /* AES cipher support ('0': no, '1': yes) */ 1447 #define CPUSS_CRYPTO_AES 1u 1448 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 1449 #define CPUSS_CRYPTO_DES 1u 1450 /* Chacha support ('0': no, '1': yes) */ 1451 #define CPUSS_CRYPTO_CHACHA 1u 1452 /* Pseudo random number generation support ('0': no, '1': yes) */ 1453 #define CPUSS_CRYPTO_PR 1u 1454 /* SHA1 hash support ('0': no, '1': yes) */ 1455 #define CPUSS_CRYPTO_SHA1 1u 1456 /* SHA2 hash support ('0': no, '1': yes) */ 1457 #define CPUSS_CRYPTO_SHA2 1u 1458 /* SHA3 hash support ('0': no, '1': yes) */ 1459 #define CPUSS_CRYPTO_SHA3 1u 1460 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 1461 #define CPUSS_CRYPTO_CRC 1u 1462 /* True random number generation support ('0': no, '1': yes) */ 1463 #define CPUSS_CRYPTO_TR 1u 1464 /* Vector unit support ('0': no, '1': yes) */ 1465 #define CPUSS_CRYPTO_VU 1u 1466 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 1467 #define CPUSS_CRYPTO_GCM 1u 1468 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 1469 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 1470 kB and 16 kB memory buffer) */ 1471 #define CPUSS_CRYPTO_BUFF_SIZE 1024u 1472 /* Number of DMA controller channels ([1, 8]) */ 1473 #define CPUSS_DMAC_CH_NR 2u 1474 /* Number of DataWire controllers present (max 2) */ 1475 #define CPUSS_DW_NR 2u 1476 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1477 #define CPUSS_DW_ECC_PRESENT 0u 1478 /* Number of fault structures. Legal range [1, 4] */ 1479 #define CPUSS_FAULT_FAULT_NR 2u 1480 /* Number of Flash BIST_DATA registers */ 1481 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u 1482 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 1483 #define CPUSS_FLASHC_PA_SIZE 128u 1484 /* SONOS Flash is used or not ('0': no, '1': yes) */ 1485 #define CPUSS_FLASHC_FLASHC_IS_SONOS 1u 1486 /* eCT Flash is used or not ('0': no, '1': yes) */ 1487 #define CPUSS_FLASHC_FLASHC_IS_ECT 0u 1488 /* CM4 CPU present or not ('0': no, '1': yes) */ 1489 #define CPUSS_FLASHC_CM4_PRESENT 1u 1490 /* Number of IPC structures. Legal range [1, 16] */ 1491 #define CPUSS_IPC_IPC_NR 16u 1492 /* Number of IPC interrupt structures. Legal range [1, 16] */ 1493 #define CPUSS_IPC_IPC_IRQ_NR 16u 1494 /* Master 0 protect contexts minus one */ 1495 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 1496 /* Master 1 protect contexts minus one */ 1497 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 1498 /* Master 2 protect contexts minus one */ 1499 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 1500 /* Master 3 protect contexts minus one */ 1501 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 1502 /* Master 4 protect contexts minus one */ 1503 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 1504 /* Master 5 protect contexts minus one */ 1505 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u 1506 /* Master 6 protect contexts minus one */ 1507 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 1508 /* Master 7 protect contexts minus one */ 1509 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 1510 /* Master 8 protect contexts minus one */ 1511 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 1512 /* Master 9 protect contexts minus one */ 1513 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 1514 /* Master 10 protect contexts minus one */ 1515 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 1516 /* Master 11 protect contexts minus one */ 1517 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 1518 /* Master 12 protect contexts minus one */ 1519 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 1520 /* Master 13 protect contexts minus one */ 1521 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u 1522 /* Master 14 protect contexts minus one */ 1523 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 1524 /* Master 15 protect contexts minus one */ 1525 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 1526 /* Number of SMPU protection structures */ 1527 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 1528 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 1529 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 1530 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 1531 #define EFUSE_EFUSE_NR 4u 1532 /* Number of GPIO ports in range 0..31 */ 1533 #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u 1534 /* Number of GPIO ports in range 32..63 */ 1535 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 1536 /* Number of GPIO ports in range 64..95 */ 1537 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 1538 /* Number of GPIO ports in range 96..127 */ 1539 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 1540 /* Number of ports in device */ 1541 #define IOSS_GPIO_GPIO_PORT_NR 15u 1542 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1543 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 1544 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1545 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 1546 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1547 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u 1548 /* Indicates that pin #0 exists for this port with slew control feature */ 1549 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 1550 /* Indicates that pin #1 exists for this port with slew control feature */ 1551 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 1552 /* Indicates that pin #2 exists for this port with slew control feature */ 1553 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 1554 /* Indicates that pin #3 exists for this port with slew control feature */ 1555 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 1556 /* Indicates that pin #4 exists for this port with slew control feature */ 1557 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u 1558 /* Indicates that pin #5 exists for this port with slew control feature */ 1559 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u 1560 /* Indicates that pin #6 exists for this port with slew control feature */ 1561 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 1562 /* Indicates that pin #7 exists for this port with slew control feature */ 1563 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 1564 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1565 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 1566 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1567 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 1568 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1569 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u 1570 /* Indicates that pin #0 exists for this port with slew control feature */ 1571 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 1u 1572 /* Indicates that pin #1 exists for this port with slew control feature */ 1573 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 1u 1574 /* Indicates that pin #2 exists for this port with slew control feature */ 1575 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 1u 1576 /* Indicates that pin #3 exists for this port with slew control feature */ 1577 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 1578 /* Indicates that pin #4 exists for this port with slew control feature */ 1579 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 1580 /* Indicates that pin #5 exists for this port with slew control feature */ 1581 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 1582 /* Indicates that pin #6 exists for this port with slew control feature */ 1583 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 1584 /* Indicates that pin #7 exists for this port with slew control feature */ 1585 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 1586 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1587 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 1588 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1589 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 1590 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1591 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u 1592 /* Indicates that pin #0 exists for this port with slew control feature */ 1593 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u 1594 /* Indicates that pin #1 exists for this port with slew control feature */ 1595 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u 1596 /* Indicates that pin #2 exists for this port with slew control feature */ 1597 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u 1598 /* Indicates that pin #3 exists for this port with slew control feature */ 1599 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u 1600 /* Indicates that pin #4 exists for this port with slew control feature */ 1601 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u 1602 /* Indicates that pin #5 exists for this port with slew control feature */ 1603 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u 1604 /* Indicates that pin #6 exists for this port with slew control feature */ 1605 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u 1606 /* Indicates that pin #7 exists for this port with slew control feature */ 1607 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u 1608 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1609 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 1610 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1611 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 1612 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1613 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u 1614 /* Indicates that pin #0 exists for this port with slew control feature */ 1615 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u 1616 /* Indicates that pin #1 exists for this port with slew control feature */ 1617 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u 1618 /* Indicates that pin #2 exists for this port with slew control feature */ 1619 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 1620 /* Indicates that pin #3 exists for this port with slew control feature */ 1621 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 1622 /* Indicates that pin #4 exists for this port with slew control feature */ 1623 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 1624 /* Indicates that pin #5 exists for this port with slew control feature */ 1625 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 1626 /* Indicates that pin #6 exists for this port with slew control feature */ 1627 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 1628 /* Indicates that pin #7 exists for this port with slew control feature */ 1629 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 1630 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1631 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 0u 1632 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1633 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 1634 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1635 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u 1636 /* Indicates that pin #0 exists for this port with slew control feature */ 1637 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 1638 /* Indicates that pin #1 exists for this port with slew control feature */ 1639 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 1640 /* Indicates that pin #2 exists for this port with slew control feature */ 1641 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 1642 /* Indicates that pin #3 exists for this port with slew control feature */ 1643 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 1644 /* Indicates that pin #4 exists for this port with slew control feature */ 1645 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 1646 /* Indicates that pin #5 exists for this port with slew control feature */ 1647 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 1648 /* Indicates that pin #6 exists for this port with slew control feature */ 1649 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 1650 /* Indicates that pin #7 exists for this port with slew control feature */ 1651 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 1652 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1653 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 1654 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1655 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 1656 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1657 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u 1658 /* Indicates that pin #0 exists for this port with slew control feature */ 1659 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u 1660 /* Indicates that pin #1 exists for this port with slew control feature */ 1661 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u 1662 /* Indicates that pin #2 exists for this port with slew control feature */ 1663 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 1u 1664 /* Indicates that pin #3 exists for this port with slew control feature */ 1665 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 1666 /* Indicates that pin #4 exists for this port with slew control feature */ 1667 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 1668 /* Indicates that pin #5 exists for this port with slew control feature */ 1669 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 1670 /* Indicates that pin #6 exists for this port with slew control feature */ 1671 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u 1672 /* Indicates that pin #7 exists for this port with slew control feature */ 1673 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u 1674 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1675 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 1676 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1677 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 1678 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1679 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u 1680 /* Indicates that pin #0 exists for this port with slew control feature */ 1681 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u 1682 /* Indicates that pin #1 exists for this port with slew control feature */ 1683 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u 1684 /* Indicates that pin #2 exists for this port with slew control feature */ 1685 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u 1686 /* Indicates that pin #3 exists for this port with slew control feature */ 1687 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u 1688 /* Indicates that pin #4 exists for this port with slew control feature */ 1689 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u 1690 /* Indicates that pin #5 exists for this port with slew control feature */ 1691 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u 1692 /* Indicates that pin #6 exists for this port with slew control feature */ 1693 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u 1694 /* Indicates that pin #7 exists for this port with slew control feature */ 1695 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u 1696 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1697 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 1698 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1699 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 1700 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1701 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u 1702 /* Indicates that pin #0 exists for this port with slew control feature */ 1703 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u 1704 /* Indicates that pin #1 exists for this port with slew control feature */ 1705 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u 1706 /* Indicates that pin #2 exists for this port with slew control feature */ 1707 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u 1708 /* Indicates that pin #3 exists for this port with slew control feature */ 1709 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u 1710 /* Indicates that pin #4 exists for this port with slew control feature */ 1711 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u 1712 /* Indicates that pin #5 exists for this port with slew control feature */ 1713 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u 1714 /* Indicates that pin #6 exists for this port with slew control feature */ 1715 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u 1716 /* Indicates that pin #7 exists for this port with slew control feature */ 1717 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u 1718 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1719 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 1720 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1721 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 1722 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1723 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 0u 1724 /* Indicates that pin #0 exists for this port with slew control feature */ 1725 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u 1726 /* Indicates that pin #1 exists for this port with slew control feature */ 1727 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u 1728 /* Indicates that pin #2 exists for this port with slew control feature */ 1729 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 1730 /* Indicates that pin #3 exists for this port with slew control feature */ 1731 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 1732 /* Indicates that pin #4 exists for this port with slew control feature */ 1733 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 1734 /* Indicates that pin #5 exists for this port with slew control feature */ 1735 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 1736 /* Indicates that pin #6 exists for this port with slew control feature */ 1737 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 1738 /* Indicates that pin #7 exists for this port with slew control feature */ 1739 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 1740 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1741 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 1742 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1743 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 1744 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1745 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 0u 1746 /* Indicates that pin #0 exists for this port with slew control feature */ 1747 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u 1748 /* Indicates that pin #1 exists for this port with slew control feature */ 1749 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u 1750 /* Indicates that pin #2 exists for this port with slew control feature */ 1751 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u 1752 /* Indicates that pin #3 exists for this port with slew control feature */ 1753 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u 1754 /* Indicates that pin #4 exists for this port with slew control feature */ 1755 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 1u 1756 /* Indicates that pin #5 exists for this port with slew control feature */ 1757 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 1u 1758 /* Indicates that pin #6 exists for this port with slew control feature */ 1759 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 1760 /* Indicates that pin #7 exists for this port with slew control feature */ 1761 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 1762 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1763 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 1764 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1765 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 1766 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1767 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 0u 1768 /* Indicates that pin #0 exists for this port with slew control feature */ 1769 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u 1770 /* Indicates that pin #1 exists for this port with slew control feature */ 1771 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u 1772 /* Indicates that pin #2 exists for this port with slew control feature */ 1773 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u 1774 /* Indicates that pin #3 exists for this port with slew control feature */ 1775 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u 1776 /* Indicates that pin #4 exists for this port with slew control feature */ 1777 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u 1778 /* Indicates that pin #5 exists for this port with slew control feature */ 1779 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u 1780 /* Indicates that pin #6 exists for this port with slew control feature */ 1781 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u 1782 /* Indicates that pin #7 exists for this port with slew control feature */ 1783 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u 1784 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1785 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 1786 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1787 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 1788 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1789 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 0u 1790 /* Indicates that pin #0 exists for this port with slew control feature */ 1791 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u 1792 /* Indicates that pin #1 exists for this port with slew control feature */ 1793 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u 1794 /* Indicates that pin #2 exists for this port with slew control feature */ 1795 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u 1796 /* Indicates that pin #3 exists for this port with slew control feature */ 1797 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u 1798 /* Indicates that pin #4 exists for this port with slew control feature */ 1799 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u 1800 /* Indicates that pin #5 exists for this port with slew control feature */ 1801 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u 1802 /* Indicates that pin #6 exists for this port with slew control feature */ 1803 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u 1804 /* Indicates that pin #7 exists for this port with slew control feature */ 1805 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u 1806 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1807 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 1808 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1809 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 1810 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1811 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u 1812 /* Indicates that pin #0 exists for this port with slew control feature */ 1813 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u 1814 /* Indicates that pin #1 exists for this port with slew control feature */ 1815 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u 1816 /* Indicates that pin #2 exists for this port with slew control feature */ 1817 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 1818 /* Indicates that pin #3 exists for this port with slew control feature */ 1819 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 1820 /* Indicates that pin #4 exists for this port with slew control feature */ 1821 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 1822 /* Indicates that pin #5 exists for this port with slew control feature */ 1823 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 1824 /* Indicates that pin #6 exists for this port with slew control feature */ 1825 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u 1826 /* Indicates that pin #7 exists for this port with slew control feature */ 1827 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u 1828 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1829 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 0u 1830 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1831 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 1832 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1833 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u 1834 /* Indicates that pin #0 exists for this port with slew control feature */ 1835 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 1836 /* Indicates that pin #1 exists for this port with slew control feature */ 1837 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 1838 /* Indicates that pin #2 exists for this port with slew control feature */ 1839 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 1840 /* Indicates that pin #3 exists for this port with slew control feature */ 1841 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 1842 /* Indicates that pin #4 exists for this port with slew control feature */ 1843 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 1844 /* Indicates that pin #5 exists for this port with slew control feature */ 1845 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 1846 /* Indicates that pin #6 exists for this port with slew control feature */ 1847 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 1848 /* Indicates that pin #7 exists for this port with slew control feature */ 1849 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 1850 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1851 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u 1852 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1853 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 1854 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1855 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u 1856 /* Indicates that pin #0 exists for this port with slew control feature */ 1857 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u 1858 /* Indicates that pin #1 exists for this port with slew control feature */ 1859 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u 1860 /* Indicates that pin #2 exists for this port with slew control feature */ 1861 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 1862 /* Indicates that pin #3 exists for this port with slew control feature */ 1863 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 1864 /* Indicates that pin #4 exists for this port with slew control feature */ 1865 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 1866 /* Indicates that pin #5 exists for this port with slew control feature */ 1867 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 1868 /* Indicates that pin #6 exists for this port with slew control feature */ 1869 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 1870 /* Indicates that pin #7 exists for this port with slew control feature */ 1871 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 1872 /* Number of AMUX splitter cells */ 1873 #define IOSS_HSIOM_AMUX_SPLIT_NR 6u 1874 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 1875 #define IOSS_HSIOM_HSIOM_PORT_NR 15u 1876 /* Number of PWR/GND MONITOR CELLs in the device */ 1877 #define IOSS_HSIOM_MONITOR_NR 0u 1878 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 1879 #define IOSS_HSIOM_MONITOR_NR_0_31 0u 1880 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 1881 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 1882 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 1883 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 1884 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 1885 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 1886 /* Indicates the presence of alternate JTAG interface */ 1887 #define IOSS_HSIOM_ALTJTAG_PRESENT 0u 1888 /* Mask of SMARTIO instances presence */ 1889 #define IOSS_SMARTIO_SMARTIO_MASK 512u 1890 /* Number of ports supoprting up to 4 COMs */ 1891 #define LCD_NUMPORTS 8u 1892 /* Number of ports supporting up to 8 COMs */ 1893 #define LCD_NUMPORTS8 8u 1894 /* Number of ports supporting up to 16 COMs */ 1895 #define LCD_NUMPORTS16 0u 1896 /* Max number of LCD commons supported */ 1897 #define LCD_CHIP_TOP_COM_NR 8u 1898 /* Max number of LCD pins (total) supported */ 1899 #define LCD_CHIP_TOP_PIN_NR 64u 1900 /* LCD Pin Mask */ 1901 #define LCD_CHIP_TOP_PIN_NR0_PIN_MASK 1u 1902 /* LCD Pin Mask */ 1903 #define LCD_CHIP_TOP_PIN_NR1_PIN_MASK 1u 1904 /* LCD Pin Mask */ 1905 #define LCD_CHIP_TOP_PIN_NR2_PIN_MASK 1u 1906 /* LCD Pin Mask */ 1907 #define LCD_CHIP_TOP_PIN_NR3_PIN_MASK 1u 1908 /* LCD Pin Mask */ 1909 #define LCD_CHIP_TOP_PIN_NR4_PIN_MASK 1u 1910 /* LCD Pin Mask */ 1911 #define LCD_CHIP_TOP_PIN_NR5_PIN_MASK 1u 1912 /* LCD Pin Mask */ 1913 #define LCD_CHIP_TOP_PIN_NR6_PIN_MASK 1u 1914 /* LCD Pin Mask */ 1915 #define LCD_CHIP_TOP_PIN_NR7_PIN_MASK 1u 1916 /* LCD Pin Mask */ 1917 #define LCD_CHIP_TOP_PIN_NR8_PIN_MASK 1u 1918 /* LCD Pin Mask */ 1919 #define LCD_CHIP_TOP_PIN_NR9_PIN_MASK 1u 1920 /* LCD Pin Mask */ 1921 #define LCD_CHIP_TOP_PIN_NR10_PIN_MASK 1u 1922 /* LCD Pin Mask */ 1923 #define LCD_CHIP_TOP_PIN_NR11_PIN_MASK 1u 1924 /* LCD Pin Mask */ 1925 #define LCD_CHIP_TOP_PIN_NR12_PIN_MASK 1u 1926 /* LCD Pin Mask */ 1927 #define LCD_CHIP_TOP_PIN_NR13_PIN_MASK 1u 1928 /* LCD Pin Mask */ 1929 #define LCD_CHIP_TOP_PIN_NR14_PIN_MASK 1u 1930 /* LCD Pin Mask */ 1931 #define LCD_CHIP_TOP_PIN_NR15_PIN_MASK 1u 1932 /* LCD Pin Mask */ 1933 #define LCD_CHIP_TOP_PIN_NR16_PIN_MASK 1u 1934 /* LCD Pin Mask */ 1935 #define LCD_CHIP_TOP_PIN_NR17_PIN_MASK 1u 1936 /* LCD Pin Mask */ 1937 #define LCD_CHIP_TOP_PIN_NR18_PIN_MASK 1u 1938 /* LCD Pin Mask */ 1939 #define LCD_CHIP_TOP_PIN_NR19_PIN_MASK 1u 1940 /* LCD Pin Mask */ 1941 #define LCD_CHIP_TOP_PIN_NR20_PIN_MASK 0u 1942 /* LCD Pin Mask */ 1943 #define LCD_CHIP_TOP_PIN_NR21_PIN_MASK 0u 1944 /* LCD Pin Mask */ 1945 #define LCD_CHIP_TOP_PIN_NR22_PIN_MASK 1u 1946 /* LCD Pin Mask */ 1947 #define LCD_CHIP_TOP_PIN_NR23_PIN_MASK 1u 1948 /* LCD Pin Mask */ 1949 #define LCD_CHIP_TOP_PIN_NR24_PIN_MASK 1u 1950 /* LCD Pin Mask */ 1951 #define LCD_CHIP_TOP_PIN_NR25_PIN_MASK 1u 1952 /* LCD Pin Mask */ 1953 #define LCD_CHIP_TOP_PIN_NR26_PIN_MASK 1u 1954 /* LCD Pin Mask */ 1955 #define LCD_CHIP_TOP_PIN_NR27_PIN_MASK 1u 1956 /* LCD Pin Mask */ 1957 #define LCD_CHIP_TOP_PIN_NR28_PIN_MASK 1u 1958 /* LCD Pin Mask */ 1959 #define LCD_CHIP_TOP_PIN_NR29_PIN_MASK 1u 1960 /* LCD Pin Mask */ 1961 #define LCD_CHIP_TOP_PIN_NR30_PIN_MASK 1u 1962 /* LCD Pin Mask */ 1963 #define LCD_CHIP_TOP_PIN_NR31_PIN_MASK 1u 1964 /* LCD Pin Mask */ 1965 #define LCD_CHIP_TOP_PIN_NR32_PIN_MASK 1u 1966 /* LCD Pin Mask */ 1967 #define LCD_CHIP_TOP_PIN_NR33_PIN_MASK 1u 1968 /* LCD Pin Mask */ 1969 #define LCD_CHIP_TOP_PIN_NR34_PIN_MASK 0u 1970 /* LCD Pin Mask */ 1971 #define LCD_CHIP_TOP_PIN_NR35_PIN_MASK 1u 1972 /* LCD Pin Mask */ 1973 #define LCD_CHIP_TOP_PIN_NR36_PIN_MASK 1u 1974 /* LCD Pin Mask */ 1975 #define LCD_CHIP_TOP_PIN_NR37_PIN_MASK 1u 1976 /* LCD Pin Mask */ 1977 #define LCD_CHIP_TOP_PIN_NR38_PIN_MASK 0u 1978 /* LCD Pin Mask */ 1979 #define LCD_CHIP_TOP_PIN_NR39_PIN_MASK 0u 1980 /* LCD Pin Mask */ 1981 #define LCD_CHIP_TOP_PIN_NR40_PIN_MASK 1u 1982 /* LCD Pin Mask */ 1983 #define LCD_CHIP_TOP_PIN_NR41_PIN_MASK 1u 1984 /* LCD Pin Mask */ 1985 #define LCD_CHIP_TOP_PIN_NR42_PIN_MASK 1u 1986 /* LCD Pin Mask */ 1987 #define LCD_CHIP_TOP_PIN_NR43_PIN_MASK 1u 1988 /* LCD Pin Mask */ 1989 #define LCD_CHIP_TOP_PIN_NR44_PIN_MASK 1u 1990 /* LCD Pin Mask */ 1991 #define LCD_CHIP_TOP_PIN_NR45_PIN_MASK 1u 1992 /* LCD Pin Mask */ 1993 #define LCD_CHIP_TOP_PIN_NR46_PIN_MASK 1u 1994 /* LCD Pin Mask */ 1995 #define LCD_CHIP_TOP_PIN_NR47_PIN_MASK 1u 1996 /* LCD Pin Mask */ 1997 #define LCD_CHIP_TOP_PIN_NR48_PIN_MASK 1u 1998 /* LCD Pin Mask */ 1999 #define LCD_CHIP_TOP_PIN_NR49_PIN_MASK 1u 2000 /* LCD Pin Mask */ 2001 #define LCD_CHIP_TOP_PIN_NR50_PIN_MASK 1u 2002 /* LCD Pin Mask */ 2003 #define LCD_CHIP_TOP_PIN_NR51_PIN_MASK 1u 2004 /* LCD Pin Mask */ 2005 #define LCD_CHIP_TOP_PIN_NR52_PIN_MASK 0u 2006 /* LCD Pin Mask */ 2007 #define LCD_CHIP_TOP_PIN_NR53_PIN_MASK 1u 2008 /* LCD Pin Mask */ 2009 #define LCD_CHIP_TOP_PIN_NR54_PIN_MASK 1u 2010 /* LCD Pin Mask */ 2011 #define LCD_CHIP_TOP_PIN_NR55_PIN_MASK 1u 2012 /* LCD Pin Mask */ 2013 #define LCD_CHIP_TOP_PIN_NR56_PIN_MASK 1u 2014 /* LCD Pin Mask */ 2015 #define LCD_CHIP_TOP_PIN_NR57_PIN_MASK 1u 2016 /* LCD Pin Mask */ 2017 #define LCD_CHIP_TOP_PIN_NR58_PIN_MASK 1u 2018 /* LCD Pin Mask */ 2019 #define LCD_CHIP_TOP_PIN_NR59_PIN_MASK 1u 2020 /* LCD Pin Mask */ 2021 #define LCD_CHIP_TOP_PIN_NR60_PIN_MASK 0u 2022 /* LCD Pin Mask */ 2023 #define LCD_CHIP_TOP_PIN_NR61_PIN_MASK 0u 2024 /* LCD Pin Mask */ 2025 #define LCD_CHIP_TOP_PIN_NR62_PIN_MASK 0u 2026 /* LCD Pin Mask */ 2027 #define LCD_CHIP_TOP_PIN_NR63_PIN_MASK 0u 2028 /* Number of CTBs in the Subsystem */ 2029 #define PASS_NR_CTBS 1u 2030 /* Number of CTDACs in the Subsystem */ 2031 #define PASS_NR_CTDACS 1u 2032 /* Number of SARs in the Subsystem */ 2033 #define PASS_NR_SARS 2u 2034 /* Number of IREF outputs from AREF */ 2035 #define PASS_NR_IREFS 4u 2036 /* CTB0 Exists */ 2037 #define PASS_CTB0_EXISTS 1u 2038 /* CTB1 Exists */ 2039 #define PASS_CTB1_EXISTS 0u 2040 /* CTB2 Exists */ 2041 #define PASS_CTB2_EXISTS 0u 2042 /* CTB3 Exists */ 2043 #define PASS_CTB3_EXISTS 0u 2044 /* CTDAC0 Exists */ 2045 #define PASS_CTDAC0_EXISTS 1u 2046 /* CTDAC1 Exists */ 2047 #define PASS_CTDAC1_EXISTS 0u 2048 /* CTDAC2 Exists */ 2049 #define PASS_CTDAC2_EXISTS 0u 2050 /* CTDAC3 Exists */ 2051 #define PASS_CTDAC3_EXISTS 0u 2052 /* SAR0 Exists */ 2053 #define PASS_SAR0_EXISTS 1u 2054 /* SAR1 Exists */ 2055 #define PASS_SAR1_EXISTS 1u 2056 /* SAR2 Exists */ 2057 #define PASS_SAR2_EXISTS 0u 2058 /* SAR3 Exists */ 2059 #define PASS_SAR3_EXISTS 0u 2060 /* NR_SARS*UDB_PRESENT */ 2061 #define PASS_SAR_UDB_IF 0u 2062 /* NR_CTBS*UDB_PRESENT */ 2063 #define PASS_CTB_UDB_IF 0u 2064 /* NR_CTDACS*UDB_PRESENT */ 2065 #define PASS_CTDAC_UDB_IF 0u 2066 #define PASS_CTBM_CTDAC_PRESENT 1u 2067 #define PASS_CTBM_UDB_PRESENT 0u 2068 /* Number of SAR channels */ 2069 #define PASS_SAR_SAR_CHANNELS 16u 2070 /* Averaging logic present in SAR */ 2071 #define PASS_SAR_SAR_AVERAGE 1u 2072 /* Range detect logic present in SAR */ 2073 #define PASS_SAR_SAR_RANGEDET 1u 2074 /* Support for UAB sampling */ 2075 #define PASS_SAR_SAR_UAB 0u 2076 #define PASS_SAR_CTB0_EXISTS 1u 2077 #define PASS_SAR_UDB_PRESENT 0u 2078 /* The number of protection contexts ([2, 16]). */ 2079 #define PERI_PC_NR 8u 2080 /* Master interface presence mask (4 bits) */ 2081 #define PERI_MS_PRESENT 15u 2082 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 2083 #define PERI_ECC_PRESENT 0u 2084 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 2085 #define PERI_ECC_ADDR_PRESENT 0u 2086 /* Clock control functionality present ('0': no, '1': yes) */ 2087 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2088 /* Slave present (0:No, 1:Yes) */ 2089 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2090 /* Slave present (0:No, 1:Yes) */ 2091 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2092 /* Slave present (0:No, 1:Yes) */ 2093 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2094 /* Slave present (0:No, 1:Yes) */ 2095 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2096 /* Slave present (0:No, 1:Yes) */ 2097 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2098 /* Slave present (0:No, 1:Yes) */ 2099 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2100 /* Slave present (0:No, 1:Yes) */ 2101 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2102 /* Slave present (0:No, 1:Yes) */ 2103 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2104 /* Slave present (0:No, 1:Yes) */ 2105 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2106 /* Slave present (0:No, 1:Yes) */ 2107 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2108 /* Slave present (0:No, 1:Yes) */ 2109 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2110 /* Slave present (0:No, 1:Yes) */ 2111 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2112 /* Slave present (0:No, 1:Yes) */ 2113 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2114 /* Slave present (0:No, 1:Yes) */ 2115 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2116 /* Slave present (0:No, 1:Yes) */ 2117 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2118 /* Slave present (0:No, 1:Yes) */ 2119 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2120 /* Clock control functionality present ('0': no, '1': yes) */ 2121 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2122 /* Slave present (0:No, 1:Yes) */ 2123 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2124 /* Slave present (0:No, 1:Yes) */ 2125 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2126 /* Slave present (0:No, 1:Yes) */ 2127 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2128 /* Slave present (0:No, 1:Yes) */ 2129 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2130 /* Slave present (0:No, 1:Yes) */ 2131 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2132 /* Slave present (0:No, 1:Yes) */ 2133 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2134 /* Slave present (0:No, 1:Yes) */ 2135 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2136 /* Slave present (0:No, 1:Yes) */ 2137 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2138 /* Slave present (0:No, 1:Yes) */ 2139 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2140 /* Slave present (0:No, 1:Yes) */ 2141 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2142 /* Slave present (0:No, 1:Yes) */ 2143 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2144 /* Slave present (0:No, 1:Yes) */ 2145 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2146 /* Slave present (0:No, 1:Yes) */ 2147 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2148 /* Slave present (0:No, 1:Yes) */ 2149 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2150 /* Slave present (0:No, 1:Yes) */ 2151 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2152 /* Slave present (0:No, 1:Yes) */ 2153 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2154 /* Clock control functionality present ('0': no, '1': yes) */ 2155 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2156 /* Slave present (0:No, 1:Yes) */ 2157 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2158 /* Slave present (0:No, 1:Yes) */ 2159 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2160 /* Slave present (0:No, 1:Yes) */ 2161 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2162 /* Slave present (0:No, 1:Yes) */ 2163 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2164 /* Slave present (0:No, 1:Yes) */ 2165 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2166 /* Slave present (0:No, 1:Yes) */ 2167 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2168 /* Slave present (0:No, 1:Yes) */ 2169 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2170 /* Slave present (0:No, 1:Yes) */ 2171 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2172 /* Slave present (0:No, 1:Yes) */ 2173 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2174 /* Slave present (0:No, 1:Yes) */ 2175 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2176 /* Slave present (0:No, 1:Yes) */ 2177 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2178 /* Slave present (0:No, 1:Yes) */ 2179 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2180 /* Slave present (0:No, 1:Yes) */ 2181 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u 2182 /* Slave present (0:No, 1:Yes) */ 2183 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2184 /* Slave present (0:No, 1:Yes) */ 2185 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2186 /* Slave present (0:No, 1:Yes) */ 2187 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2188 /* Clock control functionality present ('0': no, '1': yes) */ 2189 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2190 /* Slave present (0:No, 1:Yes) */ 2191 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2192 /* Slave present (0:No, 1:Yes) */ 2193 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2194 /* Slave present (0:No, 1:Yes) */ 2195 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2196 /* Slave present (0:No, 1:Yes) */ 2197 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2198 /* Slave present (0:No, 1:Yes) */ 2199 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2200 /* Slave present (0:No, 1:Yes) */ 2201 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2202 /* Slave present (0:No, 1:Yes) */ 2203 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2204 /* Slave present (0:No, 1:Yes) */ 2205 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2206 /* Slave present (0:No, 1:Yes) */ 2207 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2208 /* Slave present (0:No, 1:Yes) */ 2209 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2210 /* Slave present (0:No, 1:Yes) */ 2211 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2212 /* Slave present (0:No, 1:Yes) */ 2213 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u 2214 /* Slave present (0:No, 1:Yes) */ 2215 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2216 /* Slave present (0:No, 1:Yes) */ 2217 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2218 /* Slave present (0:No, 1:Yes) */ 2219 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2220 /* Slave present (0:No, 1:Yes) */ 2221 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u 2222 /* Clock control functionality present ('0': no, '1': yes) */ 2223 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2224 /* Slave present (0:No, 1:Yes) */ 2225 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2226 /* Slave present (0:No, 1:Yes) */ 2227 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2228 /* Slave present (0:No, 1:Yes) */ 2229 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2230 /* Slave present (0:No, 1:Yes) */ 2231 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2232 /* Slave present (0:No, 1:Yes) */ 2233 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2234 /* Slave present (0:No, 1:Yes) */ 2235 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2236 /* Slave present (0:No, 1:Yes) */ 2237 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2238 /* Slave present (0:No, 1:Yes) */ 2239 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2240 /* Slave present (0:No, 1:Yes) */ 2241 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2242 /* Slave present (0:No, 1:Yes) */ 2243 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2244 /* Slave present (0:No, 1:Yes) */ 2245 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2246 /* Slave present (0:No, 1:Yes) */ 2247 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2248 /* Slave present (0:No, 1:Yes) */ 2249 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2250 /* Slave present (0:No, 1:Yes) */ 2251 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2252 /* Slave present (0:No, 1:Yes) */ 2253 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2254 /* Slave present (0:No, 1:Yes) */ 2255 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2256 /* Clock control functionality present ('0': no, '1': yes) */ 2257 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2258 /* Slave present (0:No, 1:Yes) */ 2259 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2260 /* Slave present (0:No, 1:Yes) */ 2261 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2262 /* Slave present (0:No, 1:Yes) */ 2263 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2264 /* Slave present (0:No, 1:Yes) */ 2265 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2266 /* Slave present (0:No, 1:Yes) */ 2267 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2268 /* Slave present (0:No, 1:Yes) */ 2269 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2270 /* Slave present (0:No, 1:Yes) */ 2271 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2272 /* Slave present (0:No, 1:Yes) */ 2273 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2274 /* Slave present (0:No, 1:Yes) */ 2275 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2276 /* Slave present (0:No, 1:Yes) */ 2277 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2278 /* Slave present (0:No, 1:Yes) */ 2279 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2280 /* Slave present (0:No, 1:Yes) */ 2281 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2282 /* Slave present (0:No, 1:Yes) */ 2283 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2284 /* Slave present (0:No, 1:Yes) */ 2285 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2286 /* Slave present (0:No, 1:Yes) */ 2287 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2288 /* Slave present (0:No, 1:Yes) */ 2289 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2290 /* Clock control functionality present ('0': no, '1': yes) */ 2291 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2292 /* Slave present (0:No, 1:Yes) */ 2293 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2294 /* Slave present (0:No, 1:Yes) */ 2295 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2296 /* Slave present (0:No, 1:Yes) */ 2297 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2298 /* Slave present (0:No, 1:Yes) */ 2299 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2300 /* Slave present (0:No, 1:Yes) */ 2301 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2302 /* Slave present (0:No, 1:Yes) */ 2303 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2304 /* Slave present (0:No, 1:Yes) */ 2305 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2306 /* Slave present (0:No, 1:Yes) */ 2307 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2308 /* Slave present (0:No, 1:Yes) */ 2309 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2310 /* Slave present (0:No, 1:Yes) */ 2311 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2312 /* Slave present (0:No, 1:Yes) */ 2313 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2314 /* Slave present (0:No, 1:Yes) */ 2315 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2316 /* Slave present (0:No, 1:Yes) */ 2317 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2318 /* Slave present (0:No, 1:Yes) */ 2319 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2320 /* Slave present (0:No, 1:Yes) */ 2321 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2322 /* Slave present (0:No, 1:Yes) */ 2323 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2324 /* Clock control functionality present ('0': no, '1': yes) */ 2325 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2326 /* Slave present (0:No, 1:Yes) */ 2327 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2328 /* Slave present (0:No, 1:Yes) */ 2329 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2330 /* Slave present (0:No, 1:Yes) */ 2331 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2332 /* Slave present (0:No, 1:Yes) */ 2333 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2334 /* Slave present (0:No, 1:Yes) */ 2335 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2336 /* Slave present (0:No, 1:Yes) */ 2337 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2338 /* Slave present (0:No, 1:Yes) */ 2339 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2340 /* Slave present (0:No, 1:Yes) */ 2341 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2342 /* Slave present (0:No, 1:Yes) */ 2343 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2344 /* Slave present (0:No, 1:Yes) */ 2345 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2346 /* Slave present (0:No, 1:Yes) */ 2347 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2348 /* Slave present (0:No, 1:Yes) */ 2349 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2350 /* Slave present (0:No, 1:Yes) */ 2351 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2352 /* Slave present (0:No, 1:Yes) */ 2353 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2354 /* Slave present (0:No, 1:Yes) */ 2355 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2356 /* Slave present (0:No, 1:Yes) */ 2357 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2358 /* Clock control functionality present ('0': no, '1': yes) */ 2359 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2360 /* Slave present (0:No, 1:Yes) */ 2361 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2362 /* Slave present (0:No, 1:Yes) */ 2363 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2364 /* Slave present (0:No, 1:Yes) */ 2365 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2366 /* Slave present (0:No, 1:Yes) */ 2367 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2368 /* Slave present (0:No, 1:Yes) */ 2369 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2370 /* Slave present (0:No, 1:Yes) */ 2371 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2372 /* Slave present (0:No, 1:Yes) */ 2373 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2374 /* Slave present (0:No, 1:Yes) */ 2375 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2376 /* Slave present (0:No, 1:Yes) */ 2377 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2378 /* Slave present (0:No, 1:Yes) */ 2379 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2380 /* Slave present (0:No, 1:Yes) */ 2381 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2382 /* Slave present (0:No, 1:Yes) */ 2383 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2384 /* Slave present (0:No, 1:Yes) */ 2385 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2386 /* Slave present (0:No, 1:Yes) */ 2387 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2388 /* Slave present (0:No, 1:Yes) */ 2389 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2390 /* Slave present (0:No, 1:Yes) */ 2391 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2392 /* Clock control functionality present ('0': no, '1': yes) */ 2393 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2394 /* Slave present (0:No, 1:Yes) */ 2395 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2396 /* Slave present (0:No, 1:Yes) */ 2397 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2398 /* Slave present (0:No, 1:Yes) */ 2399 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2400 /* Slave present (0:No, 1:Yes) */ 2401 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2402 /* Slave present (0:No, 1:Yes) */ 2403 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2404 /* Slave present (0:No, 1:Yes) */ 2405 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2406 /* Slave present (0:No, 1:Yes) */ 2407 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2408 /* Slave present (0:No, 1:Yes) */ 2409 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2410 /* Slave present (0:No, 1:Yes) */ 2411 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2412 /* Slave present (0:No, 1:Yes) */ 2413 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2414 /* Slave present (0:No, 1:Yes) */ 2415 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2416 /* Slave present (0:No, 1:Yes) */ 2417 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2418 /* Slave present (0:No, 1:Yes) */ 2419 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2420 /* Slave present (0:No, 1:Yes) */ 2421 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2422 /* Slave present (0:No, 1:Yes) */ 2423 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2424 /* Slave present (0:No, 1:Yes) */ 2425 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2426 /* Clock control functionality present ('0': no, '1': yes) */ 2427 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2428 /* Slave present (0:No, 1:Yes) */ 2429 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2430 /* Slave present (0:No, 1:Yes) */ 2431 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2432 /* Slave present (0:No, 1:Yes) */ 2433 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2434 /* Slave present (0:No, 1:Yes) */ 2435 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2436 /* Slave present (0:No, 1:Yes) */ 2437 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2438 /* Slave present (0:No, 1:Yes) */ 2439 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2440 /* Slave present (0:No, 1:Yes) */ 2441 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2442 /* Slave present (0:No, 1:Yes) */ 2443 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2444 /* Slave present (0:No, 1:Yes) */ 2445 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2446 /* Slave present (0:No, 1:Yes) */ 2447 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2448 /* Slave present (0:No, 1:Yes) */ 2449 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2450 /* Slave present (0:No, 1:Yes) */ 2451 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2452 /* Slave present (0:No, 1:Yes) */ 2453 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2454 /* Slave present (0:No, 1:Yes) */ 2455 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2456 /* Slave present (0:No, 1:Yes) */ 2457 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2458 /* Slave present (0:No, 1:Yes) */ 2459 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2460 /* Clock control functionality present ('0': no, '1': yes) */ 2461 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2462 /* Slave present (0:No, 1:Yes) */ 2463 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2464 /* Slave present (0:No, 1:Yes) */ 2465 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2466 /* Slave present (0:No, 1:Yes) */ 2467 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2468 /* Slave present (0:No, 1:Yes) */ 2469 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2470 /* Slave present (0:No, 1:Yes) */ 2471 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2472 /* Slave present (0:No, 1:Yes) */ 2473 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2474 /* Slave present (0:No, 1:Yes) */ 2475 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2476 /* Slave present (0:No, 1:Yes) */ 2477 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2478 /* Slave present (0:No, 1:Yes) */ 2479 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2480 /* Slave present (0:No, 1:Yes) */ 2481 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2482 /* Slave present (0:No, 1:Yes) */ 2483 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2484 /* Slave present (0:No, 1:Yes) */ 2485 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2486 /* Slave present (0:No, 1:Yes) */ 2487 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2488 /* Slave present (0:No, 1:Yes) */ 2489 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2490 /* Slave present (0:No, 1:Yes) */ 2491 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2492 /* Slave present (0:No, 1:Yes) */ 2493 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2494 /* Clock control functionality present ('0': no, '1': yes) */ 2495 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2496 /* Slave present (0:No, 1:Yes) */ 2497 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2498 /* Slave present (0:No, 1:Yes) */ 2499 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2500 /* Slave present (0:No, 1:Yes) */ 2501 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2502 /* Slave present (0:No, 1:Yes) */ 2503 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2504 /* Slave present (0:No, 1:Yes) */ 2505 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2506 /* Slave present (0:No, 1:Yes) */ 2507 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2508 /* Slave present (0:No, 1:Yes) */ 2509 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2510 /* Slave present (0:No, 1:Yes) */ 2511 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2512 /* Slave present (0:No, 1:Yes) */ 2513 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2514 /* Slave present (0:No, 1:Yes) */ 2515 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2516 /* Slave present (0:No, 1:Yes) */ 2517 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2518 /* Slave present (0:No, 1:Yes) */ 2519 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2520 /* Slave present (0:No, 1:Yes) */ 2521 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2522 /* Slave present (0:No, 1:Yes) */ 2523 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2524 /* Slave present (0:No, 1:Yes) */ 2525 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2526 /* Slave present (0:No, 1:Yes) */ 2527 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2528 /* Clock control functionality present ('0': no, '1': yes) */ 2529 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2530 /* Slave present (0:No, 1:Yes) */ 2531 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2532 /* Slave present (0:No, 1:Yes) */ 2533 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2534 /* Slave present (0:No, 1:Yes) */ 2535 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2536 /* Slave present (0:No, 1:Yes) */ 2537 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2538 /* Slave present (0:No, 1:Yes) */ 2539 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2540 /* Slave present (0:No, 1:Yes) */ 2541 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2542 /* Slave present (0:No, 1:Yes) */ 2543 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2544 /* Slave present (0:No, 1:Yes) */ 2545 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2546 /* Slave present (0:No, 1:Yes) */ 2547 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2548 /* Slave present (0:No, 1:Yes) */ 2549 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2550 /* Slave present (0:No, 1:Yes) */ 2551 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2552 /* Slave present (0:No, 1:Yes) */ 2553 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2554 /* Slave present (0:No, 1:Yes) */ 2555 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2556 /* Slave present (0:No, 1:Yes) */ 2557 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2558 /* Slave present (0:No, 1:Yes) */ 2559 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2560 /* Slave present (0:No, 1:Yes) */ 2561 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2562 /* Clock control functionality present ('0': no, '1': yes) */ 2563 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2564 /* Slave present (0:No, 1:Yes) */ 2565 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2566 /* Slave present (0:No, 1:Yes) */ 2567 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2568 /* Slave present (0:No, 1:Yes) */ 2569 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2570 /* Slave present (0:No, 1:Yes) */ 2571 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2572 /* Slave present (0:No, 1:Yes) */ 2573 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2574 /* Slave present (0:No, 1:Yes) */ 2575 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2576 /* Slave present (0:No, 1:Yes) */ 2577 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2578 /* Slave present (0:No, 1:Yes) */ 2579 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2580 /* Slave present (0:No, 1:Yes) */ 2581 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2582 /* Slave present (0:No, 1:Yes) */ 2583 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2584 /* Slave present (0:No, 1:Yes) */ 2585 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2586 /* Slave present (0:No, 1:Yes) */ 2587 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2588 /* Slave present (0:No, 1:Yes) */ 2589 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2590 /* Slave present (0:No, 1:Yes) */ 2591 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2592 /* Slave present (0:No, 1:Yes) */ 2593 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2594 /* Slave present (0:No, 1:Yes) */ 2595 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2596 /* Clock control functionality present ('0': no, '1': yes) */ 2597 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2598 /* Slave present (0:No, 1:Yes) */ 2599 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2600 /* Slave present (0:No, 1:Yes) */ 2601 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2602 /* Slave present (0:No, 1:Yes) */ 2603 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2604 /* Slave present (0:No, 1:Yes) */ 2605 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2606 /* Slave present (0:No, 1:Yes) */ 2607 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2608 /* Slave present (0:No, 1:Yes) */ 2609 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2610 /* Slave present (0:No, 1:Yes) */ 2611 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2612 /* Slave present (0:No, 1:Yes) */ 2613 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2614 /* Slave present (0:No, 1:Yes) */ 2615 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2616 /* Slave present (0:No, 1:Yes) */ 2617 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2618 /* Slave present (0:No, 1:Yes) */ 2619 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2620 /* Slave present (0:No, 1:Yes) */ 2621 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2622 /* Slave present (0:No, 1:Yes) */ 2623 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2624 /* Slave present (0:No, 1:Yes) */ 2625 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2626 /* Slave present (0:No, 1:Yes) */ 2627 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2628 /* Slave present (0:No, 1:Yes) */ 2629 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2630 /* Number of programmable clocks (outputs) */ 2631 #define PERI_CLOCK_NR 28u 2632 /* Number of 8.0 dividers */ 2633 #define PERI_DIV_8_NR 4u 2634 /* Number of 16.0 dividers */ 2635 #define PERI_DIV_16_NR 8u 2636 /* Number of 16.5 (fractional) dividers */ 2637 #define PERI_DIV_16_5_NR 2u 2638 /* Number of 24.5 (fractional) dividers */ 2639 #define PERI_DIV_24_5_NR 1u 2640 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 2641 #define PERI_DIV_ADDR_WIDTH 3u 2642 /* Timeout functionality present ('0': no, '1': yes) */ 2643 #define PERI_TIMEOUT_PRESENT 1u 2644 /* Trigger module present (0=No, 1=Yes) */ 2645 #define PERI_TR 1u 2646 /* Number of trigger groups */ 2647 #define PERI_TR_GROUP_NR 12u 2648 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2649 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2650 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2651 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2652 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2653 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2654 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2655 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2656 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2657 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2658 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2659 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2660 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2661 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2662 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2663 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2664 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2665 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2666 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2667 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2668 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2669 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2670 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2671 #define PERI_TR_GROUP_NR11_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2672 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2673 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2674 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2675 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2676 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2677 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2678 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2679 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2680 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2681 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2682 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2683 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2684 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2685 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2686 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2687 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2688 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2689 #define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2690 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2691 #define PERI_MASTER_WIDTH 8u 2692 /* DeepSleep support ('0':no, '1': yes) */ 2693 #define SCB0_DEEPSLEEP 0u 2694 /* Externally clocked support? ('0': no, '1': yes) */ 2695 #define SCB0_EC 0u 2696 /* I2C master support? ('0': no, '1': yes) */ 2697 #define SCB0_I2C_M 1u 2698 /* I2C slave support? ('0': no, '1': yes) */ 2699 #define SCB0_I2C_S 1u 2700 /* I2C support? (I2C_M | I2C_S) */ 2701 #define SCB0_I2C 1u 2702 /* I2C glitch filters present? ('0': no, '1': yes) */ 2703 #define SCB0_I2C_GLITCH 1u 2704 /* I2C externally clocked support? ('0': no, '1': yes) */ 2705 #define SCB0_I2C_EC 0u 2706 /* I2C master and slave support? (I2C_M & I2C_S) */ 2707 #define SCB0_I2C_M_S 1u 2708 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2709 #define SCB0_I2C_S_EC 0u 2710 /* SPI master support? ('0': no, '1': yes) */ 2711 #define SCB0_SPI_M 1u 2712 /* SPI slave support? ('0': no, '1': yes) */ 2713 #define SCB0_SPI_S 1u 2714 /* SPI support? (SPI_M | SPI_S) */ 2715 #define SCB0_SPI 1u 2716 /* SPI externally clocked support? ('0': no, '1': yes) */ 2717 #define SCB0_SPI_EC 0u 2718 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2719 #define SCB0_SPI_S_EC 0u 2720 /* UART support? ('0': no, '1': yes) */ 2721 #define SCB0_UART 1u 2722 /* SPI or UART (SPI | UART) */ 2723 #define SCB0_SPI_UART 1u 2724 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2725 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2726 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2727 #define SCB0_EZ_DATA_NR 256u 2728 /* Command/response mode support? ('0': no, '1': yes) */ 2729 #define SCB0_CMD_RESP 0u 2730 /* EZ mode support? ('0': no, '1': yes) */ 2731 #define SCB0_EZ 0u 2732 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2733 #define SCB0_EZ_CMD_RESP 0u 2734 /* I2C slave with EZ mode (I2C_S & EZ) */ 2735 #define SCB0_I2C_S_EZ 0u 2736 /* SPI slave with EZ mode (SPI_S & EZ) */ 2737 #define SCB0_SPI_S_EZ 0u 2738 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2739 #define SCB0_I2C_FAST_PLUS 1u 2740 /* Number of used spi_select signals (max 4) */ 2741 #define SCB0_CHIP_TOP_SPI_SEL_NR 3u 2742 /* DeepSleep support ('0':no, '1': yes) */ 2743 #define SCB1_DEEPSLEEP 0u 2744 /* Externally clocked support? ('0': no, '1': yes) */ 2745 #define SCB1_EC 0u 2746 /* I2C master support? ('0': no, '1': yes) */ 2747 #define SCB1_I2C_M 1u 2748 /* I2C slave support? ('0': no, '1': yes) */ 2749 #define SCB1_I2C_S 1u 2750 /* I2C support? (I2C_M | I2C_S) */ 2751 #define SCB1_I2C 1u 2752 /* I2C glitch filters present? ('0': no, '1': yes) */ 2753 #define SCB1_I2C_GLITCH 1u 2754 /* I2C externally clocked support? ('0': no, '1': yes) */ 2755 #define SCB1_I2C_EC 0u 2756 /* I2C master and slave support? (I2C_M & I2C_S) */ 2757 #define SCB1_I2C_M_S 1u 2758 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2759 #define SCB1_I2C_S_EC 0u 2760 /* SPI master support? ('0': no, '1': yes) */ 2761 #define SCB1_SPI_M 1u 2762 /* SPI slave support? ('0': no, '1': yes) */ 2763 #define SCB1_SPI_S 1u 2764 /* SPI support? (SPI_M | SPI_S) */ 2765 #define SCB1_SPI 1u 2766 /* SPI externally clocked support? ('0': no, '1': yes) */ 2767 #define SCB1_SPI_EC 0u 2768 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2769 #define SCB1_SPI_S_EC 0u 2770 /* UART support? ('0': no, '1': yes) */ 2771 #define SCB1_UART 1u 2772 /* SPI or UART (SPI | UART) */ 2773 #define SCB1_SPI_UART 1u 2774 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2775 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2776 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2777 #define SCB1_EZ_DATA_NR 256u 2778 /* Command/response mode support? ('0': no, '1': yes) */ 2779 #define SCB1_CMD_RESP 0u 2780 /* EZ mode support? ('0': no, '1': yes) */ 2781 #define SCB1_EZ 0u 2782 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2783 #define SCB1_EZ_CMD_RESP 0u 2784 /* I2C slave with EZ mode (I2C_S & EZ) */ 2785 #define SCB1_I2C_S_EZ 0u 2786 /* SPI slave with EZ mode (SPI_S & EZ) */ 2787 #define SCB1_SPI_S_EZ 0u 2788 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2789 #define SCB1_I2C_FAST_PLUS 1u 2790 /* Number of used spi_select signals (max 4) */ 2791 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 2792 /* DeepSleep support ('0':no, '1': yes) */ 2793 #define SCB2_DEEPSLEEP 0u 2794 /* Externally clocked support? ('0': no, '1': yes) */ 2795 #define SCB2_EC 0u 2796 /* I2C master support? ('0': no, '1': yes) */ 2797 #define SCB2_I2C_M 1u 2798 /* I2C slave support? ('0': no, '1': yes) */ 2799 #define SCB2_I2C_S 1u 2800 /* I2C support? (I2C_M | I2C_S) */ 2801 #define SCB2_I2C 1u 2802 /* I2C glitch filters present? ('0': no, '1': yes) */ 2803 #define SCB2_I2C_GLITCH 1u 2804 /* I2C externally clocked support? ('0': no, '1': yes) */ 2805 #define SCB2_I2C_EC 0u 2806 /* I2C master and slave support? (I2C_M & I2C_S) */ 2807 #define SCB2_I2C_M_S 1u 2808 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2809 #define SCB2_I2C_S_EC 0u 2810 /* SPI master support? ('0': no, '1': yes) */ 2811 #define SCB2_SPI_M 1u 2812 /* SPI slave support? ('0': no, '1': yes) */ 2813 #define SCB2_SPI_S 1u 2814 /* SPI support? (SPI_M | SPI_S) */ 2815 #define SCB2_SPI 1u 2816 /* SPI externally clocked support? ('0': no, '1': yes) */ 2817 #define SCB2_SPI_EC 0u 2818 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2819 #define SCB2_SPI_S_EC 0u 2820 /* UART support? ('0': no, '1': yes) */ 2821 #define SCB2_UART 1u 2822 /* SPI or UART (SPI | UART) */ 2823 #define SCB2_SPI_UART 1u 2824 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2825 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2826 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2827 #define SCB2_EZ_DATA_NR 256u 2828 /* Command/response mode support? ('0': no, '1': yes) */ 2829 #define SCB2_CMD_RESP 0u 2830 /* EZ mode support? ('0': no, '1': yes) */ 2831 #define SCB2_EZ 0u 2832 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2833 #define SCB2_EZ_CMD_RESP 0u 2834 /* I2C slave with EZ mode (I2C_S & EZ) */ 2835 #define SCB2_I2C_S_EZ 0u 2836 /* SPI slave with EZ mode (SPI_S & EZ) */ 2837 #define SCB2_SPI_S_EZ 0u 2838 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2839 #define SCB2_I2C_FAST_PLUS 1u 2840 /* Number of used spi_select signals (max 4) */ 2841 #define SCB2_CHIP_TOP_SPI_SEL_NR 3u 2842 /* DeepSleep support ('0':no, '1': yes) */ 2843 #define SCB4_DEEPSLEEP 0u 2844 /* Externally clocked support? ('0': no, '1': yes) */ 2845 #define SCB4_EC 0u 2846 /* I2C master support? ('0': no, '1': yes) */ 2847 #define SCB4_I2C_M 1u 2848 /* I2C slave support? ('0': no, '1': yes) */ 2849 #define SCB4_I2C_S 1u 2850 /* I2C support? (I2C_M | I2C_S) */ 2851 #define SCB4_I2C 1u 2852 /* I2C glitch filters present? ('0': no, '1': yes) */ 2853 #define SCB4_I2C_GLITCH 1u 2854 /* I2C externally clocked support? ('0': no, '1': yes) */ 2855 #define SCB4_I2C_EC 0u 2856 /* I2C master and slave support? (I2C_M & I2C_S) */ 2857 #define SCB4_I2C_M_S 1u 2858 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2859 #define SCB4_I2C_S_EC 0u 2860 /* SPI master support? ('0': no, '1': yes) */ 2861 #define SCB4_SPI_M 1u 2862 /* SPI slave support? ('0': no, '1': yes) */ 2863 #define SCB4_SPI_S 1u 2864 /* SPI support? (SPI_M | SPI_S) */ 2865 #define SCB4_SPI 1u 2866 /* SPI externally clocked support? ('0': no, '1': yes) */ 2867 #define SCB4_SPI_EC 0u 2868 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2869 #define SCB4_SPI_S_EC 0u 2870 /* UART support? ('0': no, '1': yes) */ 2871 #define SCB4_UART 1u 2872 /* SPI or UART (SPI | UART) */ 2873 #define SCB4_SPI_UART 1u 2874 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2875 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2876 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2877 #define SCB4_EZ_DATA_NR 256u 2878 /* Command/response mode support? ('0': no, '1': yes) */ 2879 #define SCB4_CMD_RESP 0u 2880 /* EZ mode support? ('0': no, '1': yes) */ 2881 #define SCB4_EZ 0u 2882 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2883 #define SCB4_EZ_CMD_RESP 0u 2884 /* I2C slave with EZ mode (I2C_S & EZ) */ 2885 #define SCB4_I2C_S_EZ 0u 2886 /* SPI slave with EZ mode (SPI_S & EZ) */ 2887 #define SCB4_SPI_S_EZ 0u 2888 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2889 #define SCB4_I2C_FAST_PLUS 1u 2890 /* Number of used spi_select signals (max 4) */ 2891 #define SCB4_CHIP_TOP_SPI_SEL_NR 3u 2892 /* DeepSleep support ('0':no, '1': yes) */ 2893 #define SCB5_DEEPSLEEP 0u 2894 /* Externally clocked support? ('0': no, '1': yes) */ 2895 #define SCB5_EC 0u 2896 /* I2C master support? ('0': no, '1': yes) */ 2897 #define SCB5_I2C_M 1u 2898 /* I2C slave support? ('0': no, '1': yes) */ 2899 #define SCB5_I2C_S 1u 2900 /* I2C support? (I2C_M | I2C_S) */ 2901 #define SCB5_I2C 1u 2902 /* I2C glitch filters present? ('0': no, '1': yes) */ 2903 #define SCB5_I2C_GLITCH 1u 2904 /* I2C externally clocked support? ('0': no, '1': yes) */ 2905 #define SCB5_I2C_EC 0u 2906 /* I2C master and slave support? (I2C_M & I2C_S) */ 2907 #define SCB5_I2C_M_S 1u 2908 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2909 #define SCB5_I2C_S_EC 0u 2910 /* SPI master support? ('0': no, '1': yes) */ 2911 #define SCB5_SPI_M 1u 2912 /* SPI slave support? ('0': no, '1': yes) */ 2913 #define SCB5_SPI_S 1u 2914 /* SPI support? (SPI_M | SPI_S) */ 2915 #define SCB5_SPI 1u 2916 /* SPI externally clocked support? ('0': no, '1': yes) */ 2917 #define SCB5_SPI_EC 0u 2918 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2919 #define SCB5_SPI_S_EC 0u 2920 /* UART support? ('0': no, '1': yes) */ 2921 #define SCB5_UART 1u 2922 /* SPI or UART (SPI | UART) */ 2923 #define SCB5_SPI_UART 1u 2924 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2925 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2926 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2927 #define SCB5_EZ_DATA_NR 256u 2928 /* Command/response mode support? ('0': no, '1': yes) */ 2929 #define SCB5_CMD_RESP 0u 2930 /* EZ mode support? ('0': no, '1': yes) */ 2931 #define SCB5_EZ 0u 2932 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2933 #define SCB5_EZ_CMD_RESP 0u 2934 /* I2C slave with EZ mode (I2C_S & EZ) */ 2935 #define SCB5_I2C_S_EZ 0u 2936 /* SPI slave with EZ mode (SPI_S & EZ) */ 2937 #define SCB5_SPI_S_EZ 0u 2938 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2939 #define SCB5_I2C_FAST_PLUS 1u 2940 /* Number of used spi_select signals (max 4) */ 2941 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 2942 /* DeepSleep support ('0':no, '1': yes) */ 2943 #define SCB6_DEEPSLEEP 1u 2944 /* Externally clocked support? ('0': no, '1': yes) */ 2945 #define SCB6_EC 1u 2946 /* I2C master support? ('0': no, '1': yes) */ 2947 #define SCB6_I2C_M 1u 2948 /* I2C slave support? ('0': no, '1': yes) */ 2949 #define SCB6_I2C_S 1u 2950 /* I2C support? (I2C_M | I2C_S) */ 2951 #define SCB6_I2C 1u 2952 /* I2C glitch filters present? ('0': no, '1': yes) */ 2953 #define SCB6_I2C_GLITCH 1u 2954 /* I2C externally clocked support? ('0': no, '1': yes) */ 2955 #define SCB6_I2C_EC 1u 2956 /* I2C master and slave support? (I2C_M & I2C_S) */ 2957 #define SCB6_I2C_M_S 1u 2958 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2959 #define SCB6_I2C_S_EC 1u 2960 /* SPI master support? ('0': no, '1': yes) */ 2961 #define SCB6_SPI_M 1u 2962 /* SPI slave support? ('0': no, '1': yes) */ 2963 #define SCB6_SPI_S 1u 2964 /* SPI support? (SPI_M | SPI_S) */ 2965 #define SCB6_SPI 1u 2966 /* SPI externally clocked support? ('0': no, '1': yes) */ 2967 #define SCB6_SPI_EC 1u 2968 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2969 #define SCB6_SPI_S_EC 1u 2970 /* UART support? ('0': no, '1': yes) */ 2971 #define SCB6_UART 0u 2972 /* SPI or UART (SPI | UART) */ 2973 #define SCB6_SPI_UART 1u 2974 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2975 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2976 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2977 #define SCB6_EZ_DATA_NR 256u 2978 /* Command/response mode support? ('0': no, '1': yes) */ 2979 #define SCB6_CMD_RESP 1u 2980 /* EZ mode support? ('0': no, '1': yes) */ 2981 #define SCB6_EZ 1u 2982 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2983 #define SCB6_EZ_CMD_RESP 1u 2984 /* I2C slave with EZ mode (I2C_S & EZ) */ 2985 #define SCB6_I2C_S_EZ 1u 2986 /* SPI slave with EZ mode (SPI_S & EZ) */ 2987 #define SCB6_SPI_S_EZ 1u 2988 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2989 #define SCB6_I2C_FAST_PLUS 1u 2990 /* Number of used spi_select signals (max 4) */ 2991 #define SCB6_CHIP_TOP_SPI_SEL_NR 1u 2992 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2993 #define SFLASH_FLASHC_IS_SONOS 1u 2994 /* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ 2995 #define SFLASH_CPUSS_WOUNDING_PRESENT 0u 2996 /* Base address of the SMIF XIP memory region. This address must be a multiple of 2997 the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This 2998 address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP 2999 memory region should NOT overlap with other memory regions. */ 3000 #define SMIF_SMIF_XIP_ADDR 0x18000000u 3001 /* Capacity of the SMIF XIP memory region. The more significant bits of this 3002 parameter must be '1' and the lesser significant bits of this paramter must 3003 be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are 3004 {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 3005 0xffe0:0000, ..., 0xe000:0000}. */ 3006 #define SMIF_SMIF_XIP_MASK 0xF8000000u 3007 /* Cryptography (AES) support ('0' = no support, '1' = support) */ 3008 #define SMIF_CRYPTO 1u 3009 /* Number of external devices supported ([1,4]) */ 3010 #define SMIF_DEVICE_NR 3u 3011 /* External device write support. This is a 4-bit field. Each external device has 3012 a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ 3013 #define SMIF_DEVICE_WR_EN 15u 3014 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3015 #define SMIF_MASTER_WIDTH 8u 3016 /* Chip top connect all 8 data pins (0= connect 4 or 6 data pins based on 3017 DATA6_PRESENT, 1= connect 8 data pins) */ 3018 #define SMIF_CHIP_TOP_DATA8_PRESENT 0u 3019 /* Number of used spi_select signals (max 4) */ 3020 #define SMIF_CHIP_TOP_SPI_SEL_NR 3u 3021 /* Number of regulator modules instantiated within SRSS, start with estimate, 3022 update after CMR feedback */ 3023 #define SRSS_NUM_ACTREG_PWRMOD 2u 3024 /* Number of shorting switches between vccd and vccact (target dynamic voltage 3025 drop < 10mV) */ 3026 #define SRSS_NUM_ACTIVE_SWITCH 3u 3027 /* ULP linear regulator system is present */ 3028 #define SRSS_ULPLINREG_PRESENT 1u 3029 /* HT linear regulator system is present */ 3030 #define SRSS_HTLINREG_PRESENT 0u 3031 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 3032 or SIMOBUCK_PRESENT. */ 3033 #define SRSS_BUCKCTL_PRESENT 1u 3034 /* Low-current SISO buck core regulator is present. Only compatible with ULP 3035 linear regulator system (ULPLINREG_PRESENT==1). */ 3036 #define SRSS_S40S_SISOBUCKLC_PRESENT 1u 3037 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 3038 system (ULPLINREG_PRESENT==1). */ 3039 #define SRSS_SIMOBUCK_PRESENT 0u 3040 /* Precision ILO (PILO) is present */ 3041 #define SRSS_PILO_PRESENT 0u 3042 /* External Crystal Oscillator is present (high frequency) */ 3043 #define SRSS_ECO_PRESENT 1u 3044 /* System Buck-Boost is present */ 3045 #define SRSS_SYSBB_PRESENT 0u 3046 /* Number of clock paths. Must be > 0 */ 3047 #define SRSS_NUM_CLKPATH 5u 3048 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 3049 #define SRSS_NUM_PLL 1u 3050 /* Number of HFCLK roots present. Must be > 0 */ 3051 #define SRSS_NUM_HFROOT 4u 3052 /* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ 3053 #define SRSS_NUM_HIBDATA 1u 3054 /* Backup domain is present (includes RTC and WCO) */ 3055 #define SRSS_BACKUP_PRESENT 1u 3056 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 3057 mask indicates presence of a CSV. */ 3058 #define SRSS_MASK_HFCSV 0u 3059 /* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ 3060 #define SRSS_WCOCSV_PRESENT 0u 3061 /* Number of software watchdog timers. */ 3062 #define SRSS_NUM_MCWDT 2u 3063 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 3064 #define SRSS_NUM_DSI 0u 3065 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 3066 #define SRSS_ALTHF_PRESENT 0u 3067 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 3068 #define SRSS_ALTLF_PRESENT 0u 3069 /* Use the hardened clkactfllmux block */ 3070 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 3071 /* Number of clock paths, including direct paths in hardened clkactfllmux block 3072 (Must be >= NUM_CLKPATH) */ 3073 #define SRSS_HARD_CLKPATH 6u 3074 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= 3075 NUM_PLL+1) */ 3076 #define SRSS_HARD_CLKPATHMUX 6u 3077 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ 3078 #define SRSS_HARD_HFROOT 6u 3079 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ 3080 #define SRSS_HARD_ECOMUX_PRESENT 1u 3081 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ 3082 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 3083 /* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for 3084 PSoC6ABLE2, PSoC6A2M. */ 3085 #define SRSS_SRSS_VER1P3 1u 3086 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 3087 #define SRSS_BACKUP_BMEM_PRESENT 0u 3088 /* Number of Backup registers to include (each is 32b). Only used when 3089 BACKUP_PRESENT==1. */ 3090 #define SRSS_BACKUP_NUM_BREG 16u 3091 /* Number of input triggers per counter only routed to one counter (0..8) */ 3092 #define TCPWM_TR_ONE_CNT_NR 1u 3093 /* Number of input triggers routed to all counters (0..254), TR_ONE_CNT_NR+TR_ALL 3094 CNT_NR <= 254 */ 3095 #define TCPWM_TR_ALL_CNT_NR 28u 3096 /* Number of TCPWM counter groups (1..4) */ 3097 #define TCPWM_GRP_NR 2u 3098 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3099 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 32u 3100 /* Second Capture / Compare Unit is present (0, 1) */ 3101 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 0u 3102 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3103 GRP_CC1_PRESENT = 1 */ 3104 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 3105 /* Stepper Motor Control features are present (0, 1). */ 3106 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 3107 /* Number of counters per TCPWM group (1..256) */ 3108 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 4u 3109 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3110 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 3111 /* Second Capture / Compare Unit is present (0, 1) */ 3112 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 3113 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3114 GRP_CC1_PRESENT = 1 */ 3115 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 3116 /* Stepper Motor Control features are present (0, 1). */ 3117 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 0u 3118 /* Number of counters per TCPWM group (1..256) */ 3119 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 8u 3120 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3121 #define TCPWM_MASTER_WIDTH 8u 3122 3123 /* MMIO Targets Defines */ 3124 /* MMIO1.CRYPTO */ 3125 #define CY_MMIO_CRYPTO_GROUP_NR 1u 3126 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 3127 /* MMIO2.CPUSS */ 3128 #define CY_MMIO_CPUSS_GROUP_NR 2u 3129 #define CY_MMIO_CPUSS_SLAVE_NR 0u 3130 /* MMIO2.FAULT */ 3131 #define CY_MMIO_FAULT_GROUP_NR 2u 3132 #define CY_MMIO_FAULT_SLAVE_NR 1u 3133 /* MMIO2.IPC */ 3134 #define CY_MMIO_IPC_GROUP_NR 2u 3135 #define CY_MMIO_IPC_SLAVE_NR 2u 3136 /* MMIO2.PROT */ 3137 #define CY_MMIO_PROT_GROUP_NR 2u 3138 #define CY_MMIO_PROT_SLAVE_NR 3u 3139 /* MMIO2.FLASHC */ 3140 #define CY_MMIO_FLASHC_GROUP_NR 2u 3141 #define CY_MMIO_FLASHC_SLAVE_NR 4u 3142 /* MMIO2.SRSS */ 3143 #define CY_MMIO_SRSS_GROUP_NR 2u 3144 #define CY_MMIO_SRSS_SLAVE_NR 6u 3145 /* MMIO2.BACKUP */ 3146 #define CY_MMIO_BACKUP_GROUP_NR 2u 3147 #define CY_MMIO_BACKUP_SLAVE_NR 7u 3148 /* MMIO2.DW */ 3149 #define CY_MMIO_DW_GROUP_NR 2u 3150 #define CY_MMIO_DW_SLAVE_NR 8u 3151 /* MMIO2.DMAC */ 3152 #define CY_MMIO_DMAC_GROUP_NR 2u 3153 #define CY_MMIO_DMAC_SLAVE_NR 10u 3154 /* MMIO2.EFUSE */ 3155 #define CY_MMIO_EFUSE_GROUP_NR 2u 3156 #define CY_MMIO_EFUSE_SLAVE_NR 12u 3157 /* MMIO3.HSIOM */ 3158 #define CY_MMIO_HSIOM_GROUP_NR 3u 3159 #define CY_MMIO_HSIOM_SLAVE_NR 0u 3160 /* MMIO3.GPIO */ 3161 #define CY_MMIO_GPIO_GROUP_NR 3u 3162 #define CY_MMIO_GPIO_SLAVE_NR 1u 3163 /* MMIO3.SMARTIO */ 3164 #define CY_MMIO_SMARTIO_GROUP_NR 3u 3165 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 3166 /* MMIO3.LPCOMP */ 3167 #define CY_MMIO_LPCOMP_GROUP_NR 3u 3168 #define CY_MMIO_LPCOMP_SLAVE_NR 5u 3169 /* MMIO3.CSD0 */ 3170 #define CY_MMIO_CSD0_GROUP_NR 3u 3171 #define CY_MMIO_CSD0_SLAVE_NR 6u 3172 /* MMIO3.TCPWM0 */ 3173 #define CY_MMIO_TCPWM0_GROUP_NR 3u 3174 #define CY_MMIO_TCPWM0_SLAVE_NR 8u 3175 /* MMIO3.LCD0 */ 3176 #define CY_MMIO_LCD0_GROUP_NR 3u 3177 #define CY_MMIO_LCD0_SLAVE_NR 11u 3178 /* MMIO3.USBFS0 */ 3179 #define CY_MMIO_USBFS0_GROUP_NR 3u 3180 #define CY_MMIO_USBFS0_SLAVE_NR 15u 3181 /* MMIO4.SMIF0 */ 3182 #define CY_MMIO_SMIF0_GROUP_NR 4u 3183 #define CY_MMIO_SMIF0_SLAVE_NR 2u 3184 /* MMIO5.CANFD0 */ 3185 #define CY_MMIO_CANFD0_GROUP_NR 5u 3186 #define CY_MMIO_CANFD0_SLAVE_NR 2u 3187 /* MMIO6.SCB0 */ 3188 #define CY_MMIO_SCB0_GROUP_NR 6u 3189 #define CY_MMIO_SCB0_SLAVE_NR 0u 3190 /* MMIO6.SCB1 */ 3191 #define CY_MMIO_SCB1_GROUP_NR 6u 3192 #define CY_MMIO_SCB1_SLAVE_NR 1u 3193 /* MMIO6.SCB2 */ 3194 #define CY_MMIO_SCB2_GROUP_NR 6u 3195 #define CY_MMIO_SCB2_SLAVE_NR 2u 3196 /* MMIO6.SCB4 */ 3197 #define CY_MMIO_SCB4_GROUP_NR 6u 3198 #define CY_MMIO_SCB4_SLAVE_NR 4u 3199 /* MMIO6.SCB5 */ 3200 #define CY_MMIO_SCB5_GROUP_NR 6u 3201 #define CY_MMIO_SCB5_SLAVE_NR 5u 3202 /* MMIO6.SCB6 */ 3203 #define CY_MMIO_SCB6_GROUP_NR 6u 3204 #define CY_MMIO_SCB6_SLAVE_NR 6u 3205 /* MMIO9.PASS */ 3206 #define CY_MMIO_PASS_GROUP_NR 9u 3207 #define CY_MMIO_PASS_SLAVE_NR 0u 3208 3209 /* Backward compatibility definitions */ 3210 #define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR 3211 #define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR 3212 3213 /* Protection regions */ 3214 typedef enum 3215 { 3216 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00002000 */ 3217 PROT_PERI_GR0_GROUP = 1, /* Address 0x40004010, size 0x00000004 */ 3218 PROT_PERI_GR1_GROUP = 2, /* Address 0x40004030, size 0x00000004 */ 3219 PROT_PERI_GR2_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 3220 PROT_PERI_GR3_GROUP = 4, /* Address 0x40004060, size 0x00000020 */ 3221 PROT_PERI_GR4_GROUP = 5, /* Address 0x40004080, size 0x00000020 */ 3222 PROT_PERI_GR5_GROUP = 6, /* Address 0x400040a0, size 0x00000020 */ 3223 PROT_PERI_GR6_GROUP = 7, /* Address 0x400040c0, size 0x00000020 */ 3224 PROT_PERI_GR9_GROUP = 8, /* Address 0x40004120, size 0x00000020 */ 3225 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 3226 PROT_CRYPTO_MAIN = 10, /* Address 0x40100000, size 0x00000400 */ 3227 PROT_CRYPTO_CRYPTO = 11, /* Address 0x40101000, size 0x00000800 */ 3228 PROT_CRYPTO_BOOT = 12, /* Address 0x40102000, size 0x00000100 */ 3229 PROT_CRYPTO_KEY0 = 13, /* Address 0x40102100, size 0x00000004 */ 3230 PROT_CRYPTO_KEY1 = 14, /* Address 0x40102120, size 0x00000004 */ 3231 PROT_CRYPTO_BUF = 15, /* Address 0x40108000, size 0x00001000 */ 3232 PROT_CPUSS_CM4 = 16, /* Address 0x40200000, size 0x00000400 */ 3233 PROT_CPUSS_CM0 = 17, /* Address 0x40201000, size 0x00001000 */ 3234 PROT_CPUSS_BOOT = 18, /* Address 0x40202000, size 0x00000200 */ 3235 PROT_CPUSS_CM0_INT = 19, /* Address 0x40208000, size 0x00000400 */ 3236 PROT_CPUSS_CM4_INT = 20, /* Address 0x4020a000, size 0x00000400 */ 3237 PROT_FAULT_STRUCT0_MAIN = 21, /* Address 0x40210000, size 0x00000100 */ 3238 PROT_FAULT_STRUCT1_MAIN = 22, /* Address 0x40210100, size 0x00000100 */ 3239 PROT_IPC_STRUCT0_IPC = 23, /* Address 0x40220000, size 0x00000020 */ 3240 PROT_IPC_STRUCT1_IPC = 24, /* Address 0x40220020, size 0x00000020 */ 3241 PROT_IPC_STRUCT2_IPC = 25, /* Address 0x40220040, size 0x00000020 */ 3242 PROT_IPC_STRUCT3_IPC = 26, /* Address 0x40220060, size 0x00000020 */ 3243 PROT_IPC_STRUCT4_IPC = 27, /* Address 0x40220080, size 0x00000020 */ 3244 PROT_IPC_STRUCT5_IPC = 28, /* Address 0x402200a0, size 0x00000020 */ 3245 PROT_IPC_STRUCT6_IPC = 29, /* Address 0x402200c0, size 0x00000020 */ 3246 PROT_IPC_STRUCT7_IPC = 30, /* Address 0x402200e0, size 0x00000020 */ 3247 PROT_IPC_STRUCT8_IPC = 31, /* Address 0x40220100, size 0x00000020 */ 3248 PROT_IPC_STRUCT9_IPC = 32, /* Address 0x40220120, size 0x00000020 */ 3249 PROT_IPC_STRUCT10_IPC = 33, /* Address 0x40220140, size 0x00000020 */ 3250 PROT_IPC_STRUCT11_IPC = 34, /* Address 0x40220160, size 0x00000020 */ 3251 PROT_IPC_STRUCT12_IPC = 35, /* Address 0x40220180, size 0x00000020 */ 3252 PROT_IPC_STRUCT13_IPC = 36, /* Address 0x402201a0, size 0x00000020 */ 3253 PROT_IPC_STRUCT14_IPC = 37, /* Address 0x402201c0, size 0x00000020 */ 3254 PROT_IPC_STRUCT15_IPC = 38, /* Address 0x402201e0, size 0x00000020 */ 3255 PROT_IPC_INTR_STRUCT0_INTR = 39, /* Address 0x40221000, size 0x00000010 */ 3256 PROT_IPC_INTR_STRUCT1_INTR = 40, /* Address 0x40221020, size 0x00000010 */ 3257 PROT_IPC_INTR_STRUCT2_INTR = 41, /* Address 0x40221040, size 0x00000010 */ 3258 PROT_IPC_INTR_STRUCT3_INTR = 42, /* Address 0x40221060, size 0x00000010 */ 3259 PROT_IPC_INTR_STRUCT4_INTR = 43, /* Address 0x40221080, size 0x00000010 */ 3260 PROT_IPC_INTR_STRUCT5_INTR = 44, /* Address 0x402210a0, size 0x00000010 */ 3261 PROT_IPC_INTR_STRUCT6_INTR = 45, /* Address 0x402210c0, size 0x00000010 */ 3262 PROT_IPC_INTR_STRUCT7_INTR = 46, /* Address 0x402210e0, size 0x00000010 */ 3263 PROT_IPC_INTR_STRUCT8_INTR = 47, /* Address 0x40221100, size 0x00000010 */ 3264 PROT_IPC_INTR_STRUCT9_INTR = 48, /* Address 0x40221120, size 0x00000010 */ 3265 PROT_IPC_INTR_STRUCT10_INTR = 49, /* Address 0x40221140, size 0x00000010 */ 3266 PROT_IPC_INTR_STRUCT11_INTR = 50, /* Address 0x40221160, size 0x00000010 */ 3267 PROT_IPC_INTR_STRUCT12_INTR = 51, /* Address 0x40221180, size 0x00000010 */ 3268 PROT_IPC_INTR_STRUCT13_INTR = 52, /* Address 0x402211a0, size 0x00000010 */ 3269 PROT_IPC_INTR_STRUCT14_INTR = 53, /* Address 0x402211c0, size 0x00000010 */ 3270 PROT_IPC_INTR_STRUCT15_INTR = 54, /* Address 0x402211e0, size 0x00000010 */ 3271 PROT_PROT_SMPU_MAIN = 55, /* Address 0x40230000, size 0x00000040 */ 3272 PROT_PROT_MPU0_MAIN = 56, /* Address 0x40234000, size 0x00000004 */ 3273 PROT_PROT_MPU14_MAIN = 57, /* Address 0x40237800, size 0x00000004 */ 3274 PROT_PROT_MPU15_MAIN = 58, /* Address 0x40237c00, size 0x00000400 */ 3275 PROT_FLASHC_MAIN = 59, /* Address 0x40240000, size 0x00000008 */ 3276 PROT_FLASHC_CMD = 60, /* Address 0x40240008, size 0x00000004 */ 3277 PROT_FLASHC_DFT = 61, /* Address 0x40240200, size 0x00000100 */ 3278 PROT_FLASHC_CM0 = 62, /* Address 0x40240400, size 0x00000080 */ 3279 PROT_FLASHC_CM4 = 63, /* Address 0x40240480, size 0x00000080 */ 3280 PROT_FLASHC_CRYPTO = 64, /* Address 0x40240500, size 0x00000004 */ 3281 PROT_FLASHC_DW0 = 65, /* Address 0x40240580, size 0x00000004 */ 3282 PROT_FLASHC_DW1 = 66, /* Address 0x40240600, size 0x00000004 */ 3283 PROT_FLASHC_DMAC = 67, /* Address 0x40240680, size 0x00000004 */ 3284 PROT_FLASHC_FM = 68, /* Address 0x4024f000, size 0x00001000 */ 3285 PROT_SRSS_MAIN1 = 69, /* Address 0x40260000, size 0x00000100 */ 3286 PROT_SRSS_MAIN2 = 70, /* Address 0x40260100, size 0x00000010 */ 3287 PROT_WDT = 71, /* Address 0x40260180, size 0x00000010 */ 3288 PROT_MAIN = 72, /* Address 0x40260200, size 0x00000080 */ 3289 PROT_SRSS_MAIN3 = 73, /* Address 0x40260300, size 0x00000100 */ 3290 PROT_SRSS_MAIN4 = 74, /* Address 0x40260400, size 0x00000400 */ 3291 PROT_SRSS_MAIN5 = 75, /* Address 0x40260800, size 0x00000008 */ 3292 PROT_SRSS_MAIN6 = 76, /* Address 0x40267000, size 0x00001000 */ 3293 PROT_SRSS_MAIN7 = 77, /* Address 0x4026ff00, size 0x00000080 */ 3294 PROT_BACKUP_BACKUP = 78, /* Address 0x40270000, size 0x00010000 */ 3295 PROT_DW0_DW = 79, /* Address 0x40280000, size 0x00000080 */ 3296 PROT_DW1_DW = 80, /* Address 0x40290000, size 0x00000080 */ 3297 PROT_DW0_DW_CRC = 81, /* Address 0x40280100, size 0x00000080 */ 3298 PROT_DW1_DW_CRC = 82, /* Address 0x40290100, size 0x00000080 */ 3299 PROT_DW0_CH_STRUCT0_CH = 83, /* Address 0x40288000, size 0x00000040 */ 3300 PROT_DW0_CH_STRUCT1_CH = 84, /* Address 0x40288040, size 0x00000040 */ 3301 PROT_DW0_CH_STRUCT2_CH = 85, /* Address 0x40288080, size 0x00000040 */ 3302 PROT_DW0_CH_STRUCT3_CH = 86, /* Address 0x402880c0, size 0x00000040 */ 3303 PROT_DW0_CH_STRUCT4_CH = 87, /* Address 0x40288100, size 0x00000040 */ 3304 PROT_DW0_CH_STRUCT5_CH = 88, /* Address 0x40288140, size 0x00000040 */ 3305 PROT_DW0_CH_STRUCT6_CH = 89, /* Address 0x40288180, size 0x00000040 */ 3306 PROT_DW0_CH_STRUCT7_CH = 90, /* Address 0x402881c0, size 0x00000040 */ 3307 PROT_DW0_CH_STRUCT8_CH = 91, /* Address 0x40288200, size 0x00000040 */ 3308 PROT_DW0_CH_STRUCT9_CH = 92, /* Address 0x40288240, size 0x00000040 */ 3309 PROT_DW0_CH_STRUCT10_CH = 93, /* Address 0x40288280, size 0x00000040 */ 3310 PROT_DW0_CH_STRUCT11_CH = 94, /* Address 0x402882c0, size 0x00000040 */ 3311 PROT_DW0_CH_STRUCT12_CH = 95, /* Address 0x40288300, size 0x00000040 */ 3312 PROT_DW0_CH_STRUCT13_CH = 96, /* Address 0x40288340, size 0x00000040 */ 3313 PROT_DW0_CH_STRUCT14_CH = 97, /* Address 0x40288380, size 0x00000040 */ 3314 PROT_DW0_CH_STRUCT15_CH = 98, /* Address 0x402883c0, size 0x00000040 */ 3315 PROT_DW0_CH_STRUCT16_CH = 99, /* Address 0x40288400, size 0x00000040 */ 3316 PROT_DW0_CH_STRUCT17_CH = 100, /* Address 0x40288440, size 0x00000040 */ 3317 PROT_DW0_CH_STRUCT18_CH = 101, /* Address 0x40288480, size 0x00000040 */ 3318 PROT_DW0_CH_STRUCT19_CH = 102, /* Address 0x402884c0, size 0x00000040 */ 3319 PROT_DW0_CH_STRUCT20_CH = 103, /* Address 0x40288500, size 0x00000040 */ 3320 PROT_DW0_CH_STRUCT21_CH = 104, /* Address 0x40288540, size 0x00000040 */ 3321 PROT_DW0_CH_STRUCT22_CH = 105, /* Address 0x40288580, size 0x00000040 */ 3322 PROT_DW0_CH_STRUCT23_CH = 106, /* Address 0x402885c0, size 0x00000040 */ 3323 PROT_DW0_CH_STRUCT24_CH = 107, /* Address 0x40288600, size 0x00000040 */ 3324 PROT_DW0_CH_STRUCT25_CH = 108, /* Address 0x40288640, size 0x00000040 */ 3325 PROT_DW0_CH_STRUCT26_CH = 109, /* Address 0x40288680, size 0x00000040 */ 3326 PROT_DW0_CH_STRUCT27_CH = 110, /* Address 0x402886c0, size 0x00000040 */ 3327 PROT_DW0_CH_STRUCT28_CH = 111, /* Address 0x40288700, size 0x00000040 */ 3328 PROT_DW0_CH_STRUCT29_CH = 112, /* Address 0x40288740, size 0x00000040 */ 3329 PROT_DW1_CH_STRUCT0_CH = 113, /* Address 0x40298000, size 0x00000040 */ 3330 PROT_DW1_CH_STRUCT1_CH = 114, /* Address 0x40298040, size 0x00000040 */ 3331 PROT_DW1_CH_STRUCT2_CH = 115, /* Address 0x40298080, size 0x00000040 */ 3332 PROT_DW1_CH_STRUCT3_CH = 116, /* Address 0x402980c0, size 0x00000040 */ 3333 PROT_DW1_CH_STRUCT4_CH = 117, /* Address 0x40298100, size 0x00000040 */ 3334 PROT_DW1_CH_STRUCT5_CH = 118, /* Address 0x40298140, size 0x00000040 */ 3335 PROT_DW1_CH_STRUCT6_CH = 119, /* Address 0x40298180, size 0x00000040 */ 3336 PROT_DW1_CH_STRUCT7_CH = 120, /* Address 0x402981c0, size 0x00000040 */ 3337 PROT_DW1_CH_STRUCT8_CH = 121, /* Address 0x40298200, size 0x00000040 */ 3338 PROT_DW1_CH_STRUCT9_CH = 122, /* Address 0x40298240, size 0x00000040 */ 3339 PROT_DW1_CH_STRUCT10_CH = 123, /* Address 0x40298280, size 0x00000040 */ 3340 PROT_DW1_CH_STRUCT11_CH = 124, /* Address 0x402982c0, size 0x00000040 */ 3341 PROT_DW1_CH_STRUCT12_CH = 125, /* Address 0x40298300, size 0x00000040 */ 3342 PROT_DW1_CH_STRUCT13_CH = 126, /* Address 0x40298340, size 0x00000040 */ 3343 PROT_DW1_CH_STRUCT14_CH = 127, /* Address 0x40298380, size 0x00000040 */ 3344 PROT_DW1_CH_STRUCT15_CH = 128, /* Address 0x402983c0, size 0x00000040 */ 3345 PROT_DW1_CH_STRUCT16_CH = 129, /* Address 0x40298400, size 0x00000040 */ 3346 PROT_DW1_CH_STRUCT17_CH = 130, /* Address 0x40298440, size 0x00000040 */ 3347 PROT_DW1_CH_STRUCT18_CH = 131, /* Address 0x40298480, size 0x00000040 */ 3348 PROT_DW1_CH_STRUCT19_CH = 132, /* Address 0x402984c0, size 0x00000040 */ 3349 PROT_DW1_CH_STRUCT20_CH = 133, /* Address 0x40298500, size 0x00000040 */ 3350 PROT_DW1_CH_STRUCT21_CH = 134, /* Address 0x40298540, size 0x00000040 */ 3351 PROT_DW1_CH_STRUCT22_CH = 135, /* Address 0x40298580, size 0x00000040 */ 3352 PROT_DW1_CH_STRUCT23_CH = 136, /* Address 0x402985c0, size 0x00000040 */ 3353 PROT_DW1_CH_STRUCT24_CH = 137, /* Address 0x40298600, size 0x00000040 */ 3354 PROT_DW1_CH_STRUCT25_CH = 138, /* Address 0x40298640, size 0x00000040 */ 3355 PROT_DW1_CH_STRUCT26_CH = 139, /* Address 0x40298680, size 0x00000040 */ 3356 PROT_DW1_CH_STRUCT27_CH = 140, /* Address 0x402986c0, size 0x00000040 */ 3357 PROT_DW1_CH_STRUCT28_CH = 141, /* Address 0x40298700, size 0x00000040 */ 3358 PROT_DW1_CH_STRUCT29_CH = 142, /* Address 0x40298740, size 0x00000040 */ 3359 PROT_DW1_CH_STRUCT30_CH = 143, /* Address 0x40298780, size 0x00000040 */ 3360 PROT_DW1_CH_STRUCT31_CH = 144, /* Address 0x402987c0, size 0x00000040 */ 3361 PROT_DMAC_TOP = 145, /* Address 0x402a0000, size 0x00000010 */ 3362 PROT_DMAC_CH0_CH = 146, /* Address 0x402a1000, size 0x00000100 */ 3363 PROT_DMAC_CH1_CH = 147, /* Address 0x402a1100, size 0x00000100 */ 3364 PROT_EFUSE_CTL = 148, /* Address 0x402c0000, size 0x00000080 */ 3365 PROT_EFUSE_DATA = 149, /* Address 0x402c0800, size 0x00000200 */ 3366 PROT_HSIOM_PRT0_PRT = 150, /* Address 0x40300000, size 0x00000008 */ 3367 PROT_HSIOM_PRT1_PRT = 151, /* Address 0x40300010, size 0x00000008 */ 3368 PROT_HSIOM_PRT2_PRT = 152, /* Address 0x40300020, size 0x00000008 */ 3369 PROT_HSIOM_PRT3_PRT = 153, /* Address 0x40300030, size 0x00000008 */ 3370 PROT_HSIOM_PRT4_PRT = 154, /* Address 0x40300040, size 0x00000008 */ 3371 PROT_HSIOM_PRT5_PRT = 155, /* Address 0x40300050, size 0x00000008 */ 3372 PROT_HSIOM_PRT6_PRT = 156, /* Address 0x40300060, size 0x00000008 */ 3373 PROT_HSIOM_PRT7_PRT = 157, /* Address 0x40300070, size 0x00000008 */ 3374 PROT_HSIOM_PRT8_PRT = 158, /* Address 0x40300080, size 0x00000008 */ 3375 PROT_HSIOM_PRT9_PRT = 159, /* Address 0x40300090, size 0x00000008 */ 3376 PROT_HSIOM_PRT10_PRT = 160, /* Address 0x403000a0, size 0x00000008 */ 3377 PROT_HSIOM_PRT11_PRT = 161, /* Address 0x403000b0, size 0x00000008 */ 3378 PROT_HSIOM_PRT12_PRT = 162, /* Address 0x403000c0, size 0x00000008 */ 3379 PROT_HSIOM_PRT13_PRT = 163, /* Address 0x403000d0, size 0x00000008 */ 3380 PROT_HSIOM_PRT14_PRT = 164, /* Address 0x403000e0, size 0x00000008 */ 3381 PROT_HSIOM_AMUX = 165, /* Address 0x40302000, size 0x00000020 */ 3382 PROT_HSIOM_MON = 166, /* Address 0x40302200, size 0x00000010 */ 3383 PROT_GPIO_PRT0_PRT = 167, /* Address 0x40310000, size 0x00000040 */ 3384 PROT_GPIO_PRT1_PRT = 168, /* Address 0x40310080, size 0x00000040 */ 3385 PROT_GPIO_PRT2_PRT = 169, /* Address 0x40310100, size 0x00000040 */ 3386 PROT_GPIO_PRT3_PRT = 170, /* Address 0x40310180, size 0x00000040 */ 3387 PROT_GPIO_PRT4_PRT = 171, /* Address 0x40310200, size 0x00000040 */ 3388 PROT_GPIO_PRT5_PRT = 172, /* Address 0x40310280, size 0x00000040 */ 3389 PROT_GPIO_PRT6_PRT = 173, /* Address 0x40310300, size 0x00000040 */ 3390 PROT_GPIO_PRT7_PRT = 174, /* Address 0x40310380, size 0x00000040 */ 3391 PROT_GPIO_PRT8_PRT = 175, /* Address 0x40310400, size 0x00000040 */ 3392 PROT_GPIO_PRT9_PRT = 176, /* Address 0x40310480, size 0x00000040 */ 3393 PROT_GPIO_PRT10_PRT = 177, /* Address 0x40310500, size 0x00000040 */ 3394 PROT_GPIO_PRT11_PRT = 178, /* Address 0x40310580, size 0x00000040 */ 3395 PROT_GPIO_PRT12_PRT = 179, /* Address 0x40310600, size 0x00000040 */ 3396 PROT_GPIO_PRT13_PRT = 180, /* Address 0x40310680, size 0x00000040 */ 3397 PROT_GPIO_PRT14_PRT = 181, /* Address 0x40310700, size 0x00000040 */ 3398 PROT_GPIO_PRT0_CFG = 182, /* Address 0x40310040, size 0x00000010 */ 3399 PROT_GPIO_PRT1_CFG = 183, /* Address 0x403100c0, size 0x00000010 */ 3400 PROT_GPIO_PRT2_CFG = 184, /* Address 0x40310140, size 0x00000010 */ 3401 PROT_GPIO_PRT3_CFG = 185, /* Address 0x403101c0, size 0x00000010 */ 3402 PROT_GPIO_PRT4_CFG = 186, /* Address 0x40310240, size 0x00000008 */ 3403 PROT_GPIO_PRT5_CFG = 187, /* Address 0x403102c0, size 0x00000010 */ 3404 PROT_GPIO_PRT6_CFG = 188, /* Address 0x40310340, size 0x00000010 */ 3405 PROT_GPIO_PRT7_CFG = 189, /* Address 0x403103c0, size 0x00000010 */ 3406 PROT_GPIO_PRT8_CFG = 190, /* Address 0x40310440, size 0x00000010 */ 3407 PROT_GPIO_PRT9_CFG = 191, /* Address 0x403104c0, size 0x00000010 */ 3408 PROT_GPIO_PRT10_CFG = 192, /* Address 0x40310540, size 0x00000010 */ 3409 PROT_GPIO_PRT11_CFG = 193, /* Address 0x403105c0, size 0x00000010 */ 3410 PROT_GPIO_PRT12_CFG = 194, /* Address 0x40310640, size 0x00000010 */ 3411 PROT_GPIO_PRT13_CFG = 195, /* Address 0x403106c0, size 0x00000008 */ 3412 PROT_GPIO_PRT14_CFG = 196, /* Address 0x40310740, size 0x00000008 */ 3413 PROT_GPIO_GPIO = 197, /* Address 0x40314000, size 0x00000040 */ 3414 PROT_GPIO_TEST = 198, /* Address 0x40315000, size 0x00000008 */ 3415 PROT_SMARTIO_PRT9_PRT = 199, /* Address 0x40320900, size 0x00000100 */ 3416 PROT_LPCOMP = 200, /* Address 0x40350000, size 0x00010000 */ 3417 PROT_CSD0 = 201, /* Address 0x40360000, size 0x00001000 */ 3418 PROT_TCPWM0_GRP0_CNT0_CNT = 202, /* Address 0x40380000, size 0x00000080 */ 3419 PROT_TCPWM0_GRP0_CNT1_CNT = 203, /* Address 0x40380080, size 0x00000080 */ 3420 PROT_TCPWM0_GRP0_CNT2_CNT = 204, /* Address 0x40380100, size 0x00000080 */ 3421 PROT_TCPWM0_GRP0_CNT3_CNT = 205, /* Address 0x40380180, size 0x00000080 */ 3422 PROT_TCPWM0_GRP1_CNT0_CNT = 206, /* Address 0x40388000, size 0x00000080 */ 3423 PROT_TCPWM0_GRP1_CNT1_CNT = 207, /* Address 0x40388080, size 0x00000080 */ 3424 PROT_TCPWM0_GRP1_CNT2_CNT = 208, /* Address 0x40388100, size 0x00000080 */ 3425 PROT_TCPWM0_GRP1_CNT3_CNT = 209, /* Address 0x40388180, size 0x00000080 */ 3426 PROT_TCPWM0_GRP1_CNT4_CNT = 210, /* Address 0x40388200, size 0x00000080 */ 3427 PROT_TCPWM0_GRP1_CNT5_CNT = 211, /* Address 0x40388280, size 0x00000080 */ 3428 PROT_TCPWM0_GRP1_CNT6_CNT = 212, /* Address 0x40388300, size 0x00000080 */ 3429 PROT_TCPWM0_GRP1_CNT7_CNT = 213, /* Address 0x40388380, size 0x00000080 */ 3430 PROT_LCD0 = 214, /* Address 0x403b0000, size 0x00010000 */ 3431 PROT_USBFS0 = 215, /* Address 0x403f0000, size 0x00010000 */ 3432 PROT_SMIF0 = 216, /* Address 0x40420000, size 0x00010000 */ 3433 PROT_CANFD0_CH0_CH = 217, /* Address 0x40520000, size 0x00000200 */ 3434 PROT_CANFD0_MAIN = 218, /* Address 0x40521000, size 0x00000040 */ 3435 PROT_CANFD0_BUF = 219, /* Address 0x40530000, size 0x00010000 */ 3436 PROT_SCB0 = 220, /* Address 0x40600000, size 0x00010000 */ 3437 PROT_SCB1 = 221, /* Address 0x40610000, size 0x00010000 */ 3438 PROT_SCB2 = 222, /* Address 0x40620000, size 0x00010000 */ 3439 PROT_SCB4 = 223, /* Address 0x40640000, size 0x00010000 */ 3440 PROT_SCB5 = 224, /* Address 0x40650000, size 0x00010000 */ 3441 PROT_SCB6 = 225, /* Address 0x40660000, size 0x00010000 */ 3442 PROT_PASS = 226 /* Address 0x40900000, size 0x00100000 */ 3443 } cy_en_prot_region_t; 3444 3445 #endif /* _PSOC6_04_CONFIG_H_ */ 3446 3447 3448 /* [] END OF FILE */ 3449
