1 /***************************************************************************//** 2 * \file xmc7100_config.h 3 * 4 * \brief 5 * XMC7100 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _XMC7100_CONFIG_H_ 28 #define _XMC7100_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0000u, /* cpuss.clock_trace_in */ 34 PCLK_SMARTIO12_CLOCK = 0x0001u, /* smartio[12].clock */ 35 PCLK_SMARTIO13_CLOCK = 0x0002u, /* smartio[13].clock */ 36 PCLK_SMARTIO14_CLOCK = 0x0003u, /* smartio[14].clock */ 37 PCLK_SMARTIO15_CLOCK = 0x0004u, /* smartio[15].clock */ 38 PCLK_SMARTIO17_CLOCK = 0x0005u, /* smartio[17].clock */ 39 PCLK_CANFD0_CLOCK_CAN0 = 0x0100u, /* canfd[0].clock_can[0] */ 40 PCLK_CANFD0_CLOCK_CAN1 = 0x0101u, /* canfd[0].clock_can[1] */ 41 PCLK_CANFD0_CLOCK_CAN2 = 0x0102u, /* canfd[0].clock_can[2] */ 42 PCLK_CANFD0_CLOCK_CAN3 = 0x0103u, /* canfd[0].clock_can[3] */ 43 PCLK_CANFD1_CLOCK_CAN0 = 0x0104u, /* canfd[1].clock_can[0] */ 44 PCLK_CANFD1_CLOCK_CAN1 = 0x0105u, /* canfd[1].clock_can[1] */ 45 PCLK_CANFD1_CLOCK_CAN2 = 0x0106u, /* canfd[1].clock_can[2] */ 46 PCLK_CANFD1_CLOCK_CAN3 = 0x0107u, /* canfd[1].clock_can[3] */ 47 PCLK_LIN0_CLOCK_CH_EN0 = 0x0108u, /* lin[0].clock_ch_en[0] */ 48 PCLK_LIN0_CLOCK_CH_EN1 = 0x0109u, /* lin[0].clock_ch_en[1] */ 49 PCLK_LIN0_CLOCK_CH_EN2 = 0x010Au, /* lin[0].clock_ch_en[2] */ 50 PCLK_LIN0_CLOCK_CH_EN3 = 0x010Bu, /* lin[0].clock_ch_en[3] */ 51 PCLK_LIN0_CLOCK_CH_EN4 = 0x010Cu, /* lin[0].clock_ch_en[4] */ 52 PCLK_LIN0_CLOCK_CH_EN5 = 0x010Du, /* lin[0].clock_ch_en[5] */ 53 PCLK_LIN0_CLOCK_CH_EN6 = 0x010Eu, /* lin[0].clock_ch_en[6] */ 54 PCLK_LIN0_CLOCK_CH_EN7 = 0x010Fu, /* lin[0].clock_ch_en[7] */ 55 PCLK_LIN0_CLOCK_CH_EN8 = 0x0110u, /* lin[0].clock_ch_en[8] */ 56 PCLK_LIN0_CLOCK_CH_EN9 = 0x0111u, /* lin[0].clock_ch_en[9] */ 57 PCLK_LIN0_CLOCK_CH_EN10 = 0x0112u, /* lin[0].clock_ch_en[10] */ 58 PCLK_LIN0_CLOCK_CH_EN11 = 0x0113u, /* lin[0].clock_ch_en[11] */ 59 PCLK_LIN0_CLOCK_CH_EN12 = 0x0114u, /* lin[0].clock_ch_en[12] */ 60 PCLK_LIN0_CLOCK_CH_EN13 = 0x0115u, /* lin[0].clock_ch_en[13] */ 61 PCLK_LIN0_CLOCK_CH_EN14 = 0x0116u, /* lin[0].clock_ch_en[14] */ 62 PCLK_LIN0_CLOCK_CH_EN15 = 0x0117u, /* lin[0].clock_ch_en[15] */ 63 PCLK_SCB0_CLOCK = 0x0118u, /* scb[0].clock */ 64 PCLK_SCB1_CLOCK = 0x0119u, /* scb[1].clock */ 65 PCLK_SCB2_CLOCK = 0x011Au, /* scb[2].clock */ 66 PCLK_SCB3_CLOCK = 0x011Bu, /* scb[3].clock */ 67 PCLK_SCB4_CLOCK = 0x011Cu, /* scb[4].clock */ 68 PCLK_SCB5_CLOCK = 0x011Du, /* scb[5].clock */ 69 PCLK_SCB6_CLOCK = 0x011Eu, /* scb[6].clock */ 70 PCLK_SCB7_CLOCK = 0x011Fu, /* scb[7].clock */ 71 PCLK_SCB8_CLOCK = 0x0120u, /* scb[8].clock */ 72 PCLK_SCB9_CLOCK = 0x0121u, /* scb[9].clock */ 73 PCLK_SCB10_CLOCK = 0x0122u, /* scb[10].clock */ 74 PCLK_PASS0_CLOCK_SAR0 = 0x0123u, /* pass[0].clock_sar[0] */ 75 PCLK_PASS0_CLOCK_SAR1 = 0x0124u, /* pass[0].clock_sar[1] */ 76 PCLK_PASS0_CLOCK_SAR2 = 0x0125u, /* pass[0].clock_sar[2] */ 77 PCLK_TCPWM0_CLOCKS0 = 0x0126u, /* tcpwm[0].clocks[0] */ 78 PCLK_TCPWM0_CLOCKS1 = 0x0127u, /* tcpwm[0].clocks[1] */ 79 PCLK_TCPWM0_CLOCKS2 = 0x0128u, /* tcpwm[0].clocks[2] */ 80 PCLK_TCPWM0_CLOCKS3 = 0x0129u, /* tcpwm[0].clocks[3] */ 81 PCLK_TCPWM0_CLOCKS4 = 0x012Au, /* tcpwm[0].clocks[4] */ 82 PCLK_TCPWM0_CLOCKS5 = 0x012Bu, /* tcpwm[0].clocks[5] */ 83 PCLK_TCPWM0_CLOCKS6 = 0x012Cu, /* tcpwm[0].clocks[6] */ 84 PCLK_TCPWM0_CLOCKS7 = 0x012Du, /* tcpwm[0].clocks[7] */ 85 PCLK_TCPWM0_CLOCKS8 = 0x012Eu, /* tcpwm[0].clocks[8] */ 86 PCLK_TCPWM0_CLOCKS9 = 0x012Fu, /* tcpwm[0].clocks[9] */ 87 PCLK_TCPWM0_CLOCKS10 = 0x0130u, /* tcpwm[0].clocks[10] */ 88 PCLK_TCPWM0_CLOCKS11 = 0x0131u, /* tcpwm[0].clocks[11] */ 89 PCLK_TCPWM0_CLOCKS12 = 0x0132u, /* tcpwm[0].clocks[12] */ 90 PCLK_TCPWM0_CLOCKS13 = 0x0133u, /* tcpwm[0].clocks[13] */ 91 PCLK_TCPWM0_CLOCKS14 = 0x0134u, /* tcpwm[0].clocks[14] */ 92 PCLK_TCPWM0_CLOCKS15 = 0x0135u, /* tcpwm[0].clocks[15] */ 93 PCLK_TCPWM0_CLOCKS16 = 0x0136u, /* tcpwm[0].clocks[16] */ 94 PCLK_TCPWM0_CLOCKS17 = 0x0137u, /* tcpwm[0].clocks[17] */ 95 PCLK_TCPWM0_CLOCKS18 = 0x0138u, /* tcpwm[0].clocks[18] */ 96 PCLK_TCPWM0_CLOCKS19 = 0x0139u, /* tcpwm[0].clocks[19] */ 97 PCLK_TCPWM0_CLOCKS20 = 0x013Au, /* tcpwm[0].clocks[20] */ 98 PCLK_TCPWM0_CLOCKS21 = 0x013Bu, /* tcpwm[0].clocks[21] */ 99 PCLK_TCPWM0_CLOCKS22 = 0x013Cu, /* tcpwm[0].clocks[22] */ 100 PCLK_TCPWM0_CLOCKS23 = 0x013Du, /* tcpwm[0].clocks[23] */ 101 PCLK_TCPWM0_CLOCKS24 = 0x013Eu, /* tcpwm[0].clocks[24] */ 102 PCLK_TCPWM0_CLOCKS25 = 0x013Fu, /* tcpwm[0].clocks[25] */ 103 PCLK_TCPWM0_CLOCKS26 = 0x0140u, /* tcpwm[0].clocks[26] */ 104 PCLK_TCPWM0_CLOCKS27 = 0x0141u, /* tcpwm[0].clocks[27] */ 105 PCLK_TCPWM0_CLOCKS28 = 0x0142u, /* tcpwm[0].clocks[28] */ 106 PCLK_TCPWM0_CLOCKS29 = 0x0143u, /* tcpwm[0].clocks[29] */ 107 PCLK_TCPWM0_CLOCKS30 = 0x0144u, /* tcpwm[0].clocks[30] */ 108 PCLK_TCPWM0_CLOCKS31 = 0x0145u, /* tcpwm[0].clocks[31] */ 109 PCLK_TCPWM0_CLOCKS32 = 0x0146u, /* tcpwm[0].clocks[32] */ 110 PCLK_TCPWM0_CLOCKS33 = 0x0147u, /* tcpwm[0].clocks[33] */ 111 PCLK_TCPWM0_CLOCKS34 = 0x0148u, /* tcpwm[0].clocks[34] */ 112 PCLK_TCPWM0_CLOCKS35 = 0x0149u, /* tcpwm[0].clocks[35] */ 113 PCLK_TCPWM0_CLOCKS36 = 0x014Au, /* tcpwm[0].clocks[36] */ 114 PCLK_TCPWM0_CLOCKS37 = 0x014Bu, /* tcpwm[0].clocks[37] */ 115 PCLK_TCPWM0_CLOCKS38 = 0x014Cu, /* tcpwm[0].clocks[38] */ 116 PCLK_TCPWM0_CLOCKS39 = 0x014Du, /* tcpwm[0].clocks[39] */ 117 PCLK_TCPWM0_CLOCKS40 = 0x014Eu, /* tcpwm[0].clocks[40] */ 118 PCLK_TCPWM0_CLOCKS41 = 0x014Fu, /* tcpwm[0].clocks[41] */ 119 PCLK_TCPWM0_CLOCKS42 = 0x0150u, /* tcpwm[0].clocks[42] */ 120 PCLK_TCPWM0_CLOCKS43 = 0x0151u, /* tcpwm[0].clocks[43] */ 121 PCLK_TCPWM0_CLOCKS44 = 0x0152u, /* tcpwm[0].clocks[44] */ 122 PCLK_TCPWM0_CLOCKS45 = 0x0153u, /* tcpwm[0].clocks[45] */ 123 PCLK_TCPWM0_CLOCKS46 = 0x0154u, /* tcpwm[0].clocks[46] */ 124 PCLK_TCPWM0_CLOCKS47 = 0x0155u, /* tcpwm[0].clocks[47] */ 125 PCLK_TCPWM0_CLOCKS48 = 0x0156u, /* tcpwm[0].clocks[48] */ 126 PCLK_TCPWM0_CLOCKS49 = 0x0157u, /* tcpwm[0].clocks[49] */ 127 PCLK_TCPWM0_CLOCKS50 = 0x0158u, /* tcpwm[0].clocks[50] */ 128 PCLK_TCPWM0_CLOCKS51 = 0x0159u, /* tcpwm[0].clocks[51] */ 129 PCLK_TCPWM0_CLOCKS52 = 0x015Au, /* tcpwm[0].clocks[52] */ 130 PCLK_TCPWM0_CLOCKS53 = 0x015Bu, /* tcpwm[0].clocks[53] */ 131 PCLK_TCPWM0_CLOCKS54 = 0x015Cu, /* tcpwm[0].clocks[54] */ 132 PCLK_TCPWM0_CLOCKS55 = 0x015Du, /* tcpwm[0].clocks[55] */ 133 PCLK_TCPWM0_CLOCKS56 = 0x015Eu, /* tcpwm[0].clocks[56] */ 134 PCLK_TCPWM0_CLOCKS57 = 0x015Fu, /* tcpwm[0].clocks[57] */ 135 PCLK_TCPWM0_CLOCKS58 = 0x0160u, /* tcpwm[0].clocks[58] */ 136 PCLK_TCPWM0_CLOCKS59 = 0x0161u, /* tcpwm[0].clocks[59] */ 137 PCLK_TCPWM0_CLOCKS60 = 0x0162u, /* tcpwm[0].clocks[60] */ 138 PCLK_TCPWM0_CLOCKS61 = 0x0163u, /* tcpwm[0].clocks[61] */ 139 PCLK_TCPWM0_CLOCKS62 = 0x0164u, /* tcpwm[0].clocks[62] */ 140 PCLK_TCPWM0_CLOCKS256 = 0x0165u, /* tcpwm[0].clocks[256] */ 141 PCLK_TCPWM0_CLOCKS257 = 0x0166u, /* tcpwm[0].clocks[257] */ 142 PCLK_TCPWM0_CLOCKS258 = 0x0167u, /* tcpwm[0].clocks[258] */ 143 PCLK_TCPWM0_CLOCKS259 = 0x0168u, /* tcpwm[0].clocks[259] */ 144 PCLK_TCPWM0_CLOCKS260 = 0x0169u, /* tcpwm[0].clocks[260] */ 145 PCLK_TCPWM0_CLOCKS261 = 0x016Au, /* tcpwm[0].clocks[261] */ 146 PCLK_TCPWM0_CLOCKS262 = 0x016Bu, /* tcpwm[0].clocks[262] */ 147 PCLK_TCPWM0_CLOCKS263 = 0x016Cu, /* tcpwm[0].clocks[263] */ 148 PCLK_TCPWM0_CLOCKS264 = 0x016Du, /* tcpwm[0].clocks[264] */ 149 PCLK_TCPWM0_CLOCKS265 = 0x016Eu, /* tcpwm[0].clocks[265] */ 150 PCLK_TCPWM0_CLOCKS266 = 0x016Fu, /* tcpwm[0].clocks[266] */ 151 PCLK_TCPWM0_CLOCKS267 = 0x0170u, /* tcpwm[0].clocks[267] */ 152 PCLK_TCPWM0_CLOCKS512 = 0x0171u, /* tcpwm[0].clocks[512] */ 153 PCLK_TCPWM0_CLOCKS513 = 0x0172u, /* tcpwm[0].clocks[513] */ 154 PCLK_TCPWM0_CLOCKS514 = 0x0173u, /* tcpwm[0].clocks[514] */ 155 PCLK_TCPWM0_CLOCKS515 = 0x0174u, /* tcpwm[0].clocks[515] */ 156 PCLK_TCPWM0_CLOCKS516 = 0x0175u, /* tcpwm[0].clocks[516] */ 157 PCLK_TCPWM0_CLOCKS517 = 0x0176u, /* tcpwm[0].clocks[517] */ 158 PCLK_TCPWM0_CLOCKS518 = 0x0177u, /* tcpwm[0].clocks[518] */ 159 PCLK_TCPWM0_CLOCKS519 = 0x0178u /* tcpwm[0].clocks[519] */ 160 } en_clk_dst_t; 161 162 /* Trigger Group */ 163 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 164 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 165 */ 166 /* Trigger Group Inputs */ 167 /* Trigger Input Group 0 - P-DMA0[0:7] Request Assignments */ 168 typedef enum 169 { 170 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 171 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 172 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 173 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 174 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 175 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 176 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 177 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 178 TRIG_IN_MUX_0_PDMA0_TR_OUT8 = 0x00000009u, /* cpuss.dw0_tr_out[8] */ 179 TRIG_IN_MUX_0_PDMA0_TR_OUT9 = 0x0000000Au, /* cpuss.dw0_tr_out[9] */ 180 TRIG_IN_MUX_0_PDMA0_TR_OUT10 = 0x0000000Bu, /* cpuss.dw0_tr_out[10] */ 181 TRIG_IN_MUX_0_PDMA0_TR_OUT11 = 0x0000000Cu, /* cpuss.dw0_tr_out[11] */ 182 TRIG_IN_MUX_0_PDMA0_TR_OUT12 = 0x0000000Du, /* cpuss.dw0_tr_out[12] */ 183 TRIG_IN_MUX_0_PDMA0_TR_OUT13 = 0x0000000Eu, /* cpuss.dw0_tr_out[13] */ 184 TRIG_IN_MUX_0_PDMA0_TR_OUT14 = 0x0000000Fu, /* cpuss.dw0_tr_out[14] */ 185 TRIG_IN_MUX_0_PDMA0_TR_OUT15 = 0x00000010u, /* cpuss.dw0_tr_out[15] */ 186 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000011u, /* cpuss.dw1_tr_out[0] */ 187 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x00000012u, /* cpuss.dw1_tr_out[1] */ 188 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x00000013u, /* cpuss.dw1_tr_out[2] */ 189 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x00000014u, /* cpuss.dw1_tr_out[3] */ 190 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x00000015u, /* cpuss.dw1_tr_out[4] */ 191 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x00000016u, /* cpuss.dw1_tr_out[5] */ 192 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x00000017u, /* cpuss.dw1_tr_out[6] */ 193 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000018u, /* cpuss.dw1_tr_out[7] */ 194 TRIG_IN_MUX_0_PDMA1_TR_OUT8 = 0x00000019u, /* cpuss.dw1_tr_out[8] */ 195 TRIG_IN_MUX_0_PDMA1_TR_OUT9 = 0x0000001Au, /* cpuss.dw1_tr_out[9] */ 196 TRIG_IN_MUX_0_PDMA1_TR_OUT10 = 0x0000001Bu, /* cpuss.dw1_tr_out[10] */ 197 TRIG_IN_MUX_0_PDMA1_TR_OUT11 = 0x0000001Cu, /* cpuss.dw1_tr_out[11] */ 198 TRIG_IN_MUX_0_PDMA1_TR_OUT12 = 0x0000001Du, /* cpuss.dw1_tr_out[12] */ 199 TRIG_IN_MUX_0_PDMA1_TR_OUT13 = 0x0000001Eu, /* cpuss.dw1_tr_out[13] */ 200 TRIG_IN_MUX_0_PDMA1_TR_OUT14 = 0x0000001Fu, /* cpuss.dw1_tr_out[14] */ 201 TRIG_IN_MUX_0_PDMA1_TR_OUT15 = 0x00000020u, /* cpuss.dw1_tr_out[15] */ 202 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000021u, /* cpuss.dmac_tr_out[0] */ 203 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000022u, /* cpuss.dmac_tr_out[1] */ 204 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x00000023u, /* cpuss.dmac_tr_out[2] */ 205 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x00000024u, /* cpuss.dmac_tr_out[3] */ 206 TRIG_IN_MUX_0_MDMA_TR_OUT4 = 0x00000025u, /* cpuss.dmac_tr_out[4] */ 207 TRIG_IN_MUX_0_MDMA_TR_OUT5 = 0x00000026u, /* cpuss.dmac_tr_out[5] */ 208 TRIG_IN_MUX_0_MDMA_TR_OUT6 = 0x00000027u, /* cpuss.dmac_tr_out[6] */ 209 TRIG_IN_MUX_0_MDMA_TR_OUT7 = 0x00000028u, /* cpuss.dmac_tr_out[7] */ 210 TRIG_IN_MUX_0_CAN0_TT_TR_OUT0 = 0x00000029u, /* canfd[0].tr_tmp_rtp_out[0] */ 211 TRIG_IN_MUX_0_CAN0_TT_TR_OUT1 = 0x0000002Au, /* canfd[0].tr_tmp_rtp_out[1] */ 212 TRIG_IN_MUX_0_CAN0_TT_TR_OUT2 = 0x0000002Bu, /* canfd[0].tr_tmp_rtp_out[2] */ 213 TRIG_IN_MUX_0_CAN0_TT_TR_OUT3 = 0x0000002Cu, /* canfd[0].tr_tmp_rtp_out[3] */ 214 TRIG_IN_MUX_0_CAN1_TT_TR_OUT0 = 0x0000002Du, /* canfd[1].tr_tmp_rtp_out[0] */ 215 TRIG_IN_MUX_0_CAN1_TT_TR_OUT1 = 0x0000002Eu, /* canfd[1].tr_tmp_rtp_out[1] */ 216 TRIG_IN_MUX_0_CAN1_TT_TR_OUT2 = 0x0000002Fu, /* canfd[1].tr_tmp_rtp_out[2] */ 217 TRIG_IN_MUX_0_CAN1_TT_TR_OUT3 = 0x00000030u, /* canfd[1].tr_tmp_rtp_out[3] */ 218 TRIG_IN_MUX_0_HSIOM_IO_INPUT0 = 0x00000031u, /* peri.tr_io_input[0] */ 219 TRIG_IN_MUX_0_HSIOM_IO_INPUT1 = 0x00000032u, /* peri.tr_io_input[1] */ 220 TRIG_IN_MUX_0_HSIOM_IO_INPUT2 = 0x00000033u, /* peri.tr_io_input[2] */ 221 TRIG_IN_MUX_0_HSIOM_IO_INPUT3 = 0x00000034u, /* peri.tr_io_input[3] */ 222 TRIG_IN_MUX_0_HSIOM_IO_INPUT4 = 0x00000035u, /* peri.tr_io_input[4] */ 223 TRIG_IN_MUX_0_HSIOM_IO_INPUT5 = 0x00000036u, /* peri.tr_io_input[5] */ 224 TRIG_IN_MUX_0_HSIOM_IO_INPUT6 = 0x00000037u, /* peri.tr_io_input[6] */ 225 TRIG_IN_MUX_0_HSIOM_IO_INPUT7 = 0x00000038u, /* peri.tr_io_input[7] */ 226 TRIG_IN_MUX_0_HSIOM_IO_INPUT8 = 0x00000039u, /* peri.tr_io_input[8] */ 227 TRIG_IN_MUX_0_HSIOM_IO_INPUT9 = 0x0000003Au, /* peri.tr_io_input[9] */ 228 TRIG_IN_MUX_0_HSIOM_IO_INPUT10 = 0x0000003Bu, /* peri.tr_io_input[10] */ 229 TRIG_IN_MUX_0_HSIOM_IO_INPUT11 = 0x0000003Cu, /* peri.tr_io_input[11] */ 230 TRIG_IN_MUX_0_HSIOM_IO_INPUT12 = 0x0000003Du, /* peri.tr_io_input[12] */ 231 TRIG_IN_MUX_0_HSIOM_IO_INPUT13 = 0x0000003Eu, /* peri.tr_io_input[13] */ 232 TRIG_IN_MUX_0_HSIOM_IO_INPUT14 = 0x0000003Fu, /* peri.tr_io_input[14] */ 233 TRIG_IN_MUX_0_HSIOM_IO_INPUT15 = 0x00000040u, /* peri.tr_io_input[15] */ 234 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000041u, /* cpuss.tr_fault[0] */ 235 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000042u, /* cpuss.tr_fault[1] */ 236 TRIG_IN_MUX_0_FAULT_TR_OUT2 = 0x00000043u, /* cpuss.tr_fault[2] */ 237 TRIG_IN_MUX_0_FAULT_TR_OUT3 = 0x00000044u /* cpuss.tr_fault[3] */ 238 } en_trig_input_pdma0_tr_0_t; 239 240 /* Trigger Input Group 1 - P-DMA0[8:15] Request Assignments */ 241 typedef enum 242 { 243 TRIG_IN_MUX_1_TCPWM_16_TR_OUT00 = 0x00000101u, /* tcpwm[0].tr_out0[0] */ 244 TRIG_IN_MUX_1_TCPWM_16_TR_OUT01 = 0x00000102u, /* tcpwm[0].tr_out0[1] */ 245 TRIG_IN_MUX_1_TCPWM_16_TR_OUT02 = 0x00000103u, /* tcpwm[0].tr_out0[2] */ 246 TRIG_IN_MUX_1_TCPWM_16_TR_OUT03 = 0x00000104u, /* tcpwm[0].tr_out0[3] */ 247 TRIG_IN_MUX_1_TCPWM_16_TR_OUT04 = 0x00000105u, /* tcpwm[0].tr_out0[4] */ 248 TRIG_IN_MUX_1_TCPWM_16_TR_OUT05 = 0x00000106u, /* tcpwm[0].tr_out0[5] */ 249 TRIG_IN_MUX_1_TCPWM_16_TR_OUT06 = 0x00000107u, /* tcpwm[0].tr_out0[6] */ 250 TRIG_IN_MUX_1_TCPWM_16_TR_OUT07 = 0x00000108u, /* tcpwm[0].tr_out0[7] */ 251 TRIG_IN_MUX_1_TCPWM_16_TR_OUT08 = 0x00000109u, /* tcpwm[0].tr_out0[8] */ 252 TRIG_IN_MUX_1_TCPWM_16_TR_OUT09 = 0x0000010Au, /* tcpwm[0].tr_out0[9] */ 253 TRIG_IN_MUX_1_TCPWM_16_TR_OUT010 = 0x0000010Bu, /* tcpwm[0].tr_out0[10] */ 254 TRIG_IN_MUX_1_TCPWM_16_TR_OUT011 = 0x0000010Cu, /* tcpwm[0].tr_out0[11] */ 255 TRIG_IN_MUX_1_TCPWM_16_TR_OUT012 = 0x0000010Du, /* tcpwm[0].tr_out0[12] */ 256 TRIG_IN_MUX_1_TCPWM_16_TR_OUT013 = 0x0000010Eu, /* tcpwm[0].tr_out0[13] */ 257 TRIG_IN_MUX_1_TCPWM_16_TR_OUT014 = 0x0000010Fu, /* tcpwm[0].tr_out0[14] */ 258 TRIG_IN_MUX_1_TCPWM_16_TR_OUT015 = 0x00000110u, /* tcpwm[0].tr_out0[15] */ 259 TRIG_IN_MUX_1_TCPWM_16_TR_OUT016 = 0x00000111u, /* tcpwm[0].tr_out0[16] */ 260 TRIG_IN_MUX_1_TCPWM_16_TR_OUT017 = 0x00000112u, /* tcpwm[0].tr_out0[17] */ 261 TRIG_IN_MUX_1_TCPWM_16_TR_OUT018 = 0x00000113u, /* tcpwm[0].tr_out0[18] */ 262 TRIG_IN_MUX_1_TCPWM_16_TR_OUT019 = 0x00000114u, /* tcpwm[0].tr_out0[19] */ 263 TRIG_IN_MUX_1_TCPWM_16_TR_OUT020 = 0x00000115u, /* tcpwm[0].tr_out0[20] */ 264 TRIG_IN_MUX_1_TCPWM_16_TR_OUT021 = 0x00000116u, /* tcpwm[0].tr_out0[21] */ 265 TRIG_IN_MUX_1_TCPWM_16_TR_OUT022 = 0x00000117u, /* tcpwm[0].tr_out0[22] */ 266 TRIG_IN_MUX_1_TCPWM_16_TR_OUT023 = 0x00000118u, /* tcpwm[0].tr_out0[23] */ 267 TRIG_IN_MUX_1_TCPWM_16_TR_OUT024 = 0x00000119u, /* tcpwm[0].tr_out0[24] */ 268 TRIG_IN_MUX_1_TCPWM_16_TR_OUT025 = 0x0000011Au, /* tcpwm[0].tr_out0[25] */ 269 TRIG_IN_MUX_1_TCPWM_16_TR_OUT026 = 0x0000011Bu, /* tcpwm[0].tr_out0[26] */ 270 TRIG_IN_MUX_1_TCPWM_16_TR_OUT027 = 0x0000011Cu, /* tcpwm[0].tr_out0[27] */ 271 TRIG_IN_MUX_1_TCPWM_16_TR_OUT028 = 0x0000011Du, /* tcpwm[0].tr_out0[28] */ 272 TRIG_IN_MUX_1_TCPWM_16_TR_OUT029 = 0x0000011Eu, /* tcpwm[0].tr_out0[29] */ 273 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT00 = 0x0000011Fu, /* tcpwm[0].tr_out0[256] */ 274 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT01 = 0x00000120u, /* tcpwm[0].tr_out0[257] */ 275 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT02 = 0x00000121u, /* tcpwm[0].tr_out0[258] */ 276 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT03 = 0x00000122u, /* tcpwm[0].tr_out0[259] */ 277 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT04 = 0x00000123u, /* tcpwm[0].tr_out0[260] */ 278 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT05 = 0x00000124u, /* tcpwm[0].tr_out0[261] */ 279 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT06 = 0x00000125u, /* tcpwm[0].tr_out0[262] */ 280 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT07 = 0x00000126u, /* tcpwm[0].tr_out0[263] */ 281 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT08 = 0x00000127u, /* tcpwm[0].tr_out0[264] */ 282 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT09 = 0x00000128u, /* tcpwm[0].tr_out0[265] */ 283 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT010 = 0x00000129u, /* tcpwm[0].tr_out0[266] */ 284 TRIG_IN_MUX_1_TCPWM_16M_TR_OUT011 = 0x0000012Au, /* tcpwm[0].tr_out0[267] */ 285 TRIG_IN_MUX_1_TCPWM_32_TR_OUT00 = 0x0000012Bu, /* tcpwm[0].tr_out0[512] */ 286 TRIG_IN_MUX_1_TCPWM_32_TR_OUT01 = 0x0000012Cu, /* tcpwm[0].tr_out0[513] */ 287 TRIG_IN_MUX_1_TCPWM_32_TR_OUT02 = 0x0000012Du, /* tcpwm[0].tr_out0[514] */ 288 TRIG_IN_MUX_1_TCPWM_32_TR_OUT03 = 0x0000012Eu, /* tcpwm[0].tr_out0[515] */ 289 TRIG_IN_MUX_1_TCPWM_32_TR_OUT04 = 0x0000012Fu, /* tcpwm[0].tr_out0[516] */ 290 TRIG_IN_MUX_1_TCPWM_32_TR_OUT05 = 0x00000130u, /* tcpwm[0].tr_out0[517] */ 291 TRIG_IN_MUX_1_TCPWM_32_TR_OUT06 = 0x00000131u, /* tcpwm[0].tr_out0[518] */ 292 TRIG_IN_MUX_1_TCPWM_32_TR_OUT07 = 0x00000132u, /* tcpwm[0].tr_out0[519] */ 293 TRIG_IN_MUX_1_PASS_GEN_TR_OUT0 = 0x00000133u, /* pass[0].tr_sar_gen_out[0] */ 294 TRIG_IN_MUX_1_PASS_GEN_TR_OUT1 = 0x00000134u, /* pass[0].tr_sar_gen_out[1] */ 295 TRIG_IN_MUX_1_PASS_GEN_TR_OUT2 = 0x00000135u, /* pass[0].tr_sar_gen_out[2] */ 296 TRIG_IN_MUX_1_PASS_GEN_TR_OUT3 = 0x00000136u, /* pass[0].tr_sar_gen_out[3] */ 297 TRIG_IN_MUX_1_PASS_GEN_TR_OUT4 = 0x00000137u, /* pass[0].tr_sar_gen_out[4] */ 298 TRIG_IN_MUX_1_PASS_GEN_TR_OUT5 = 0x00000138u, /* pass[0].tr_sar_gen_out[5] */ 299 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x00000139u, /* cpuss.cti_tr_out[0] */ 300 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x0000013Au, /* cpuss.cti_tr_out[1] */ 301 TRIG_IN_MUX_1_EVTGEN_TR_OUT0 = 0x0000013Bu, /* evtgen[0].tr_out[0] */ 302 TRIG_IN_MUX_1_EVTGEN_TR_OUT1 = 0x0000013Cu, /* evtgen[0].tr_out[1] */ 303 TRIG_IN_MUX_1_EVTGEN_TR_OUT2 = 0x0000013Du, /* evtgen[0].tr_out[2] */ 304 TRIG_IN_MUX_1_EVTGEN_TR_OUT3 = 0x0000013Eu /* evtgen[0].tr_out[3] */ 305 } en_trig_input_pdma0_tr_1_t; 306 307 /* Trigger Input Group 2 - P-DMA1[0:15] Request Assignments */ 308 typedef enum 309 { 310 TRIG_IN_MUX_2_PDMA1_TR_OUT0 = 0x00000201u, /* cpuss.dw1_tr_out[0] */ 311 TRIG_IN_MUX_2_PDMA1_TR_OUT1 = 0x00000202u, /* cpuss.dw1_tr_out[1] */ 312 TRIG_IN_MUX_2_PDMA1_TR_OUT2 = 0x00000203u, /* cpuss.dw1_tr_out[2] */ 313 TRIG_IN_MUX_2_PDMA1_TR_OUT3 = 0x00000204u, /* cpuss.dw1_tr_out[3] */ 314 TRIG_IN_MUX_2_PDMA1_TR_OUT4 = 0x00000205u, /* cpuss.dw1_tr_out[4] */ 315 TRIG_IN_MUX_2_PDMA1_TR_OUT5 = 0x00000206u, /* cpuss.dw1_tr_out[5] */ 316 TRIG_IN_MUX_2_PDMA1_TR_OUT6 = 0x00000207u, /* cpuss.dw1_tr_out[6] */ 317 TRIG_IN_MUX_2_PDMA1_TR_OUT7 = 0x00000208u, /* cpuss.dw1_tr_out[7] */ 318 TRIG_IN_MUX_2_PDMA1_TR_OUT8 = 0x00000209u, /* cpuss.dw1_tr_out[8] */ 319 TRIG_IN_MUX_2_PDMA1_TR_OUT9 = 0x0000020Au, /* cpuss.dw1_tr_out[9] */ 320 TRIG_IN_MUX_2_PDMA1_TR_OUT10 = 0x0000020Bu, /* cpuss.dw1_tr_out[10] */ 321 TRIG_IN_MUX_2_PDMA1_TR_OUT11 = 0x0000020Cu, /* cpuss.dw1_tr_out[11] */ 322 TRIG_IN_MUX_2_PDMA1_TR_OUT12 = 0x0000020Du, /* cpuss.dw1_tr_out[12] */ 323 TRIG_IN_MUX_2_PDMA1_TR_OUT13 = 0x0000020Eu, /* cpuss.dw1_tr_out[13] */ 324 TRIG_IN_MUX_2_PDMA1_TR_OUT14 = 0x0000020Fu, /* cpuss.dw1_tr_out[14] */ 325 TRIG_IN_MUX_2_PDMA1_TR_OUT15 = 0x00000210u, /* cpuss.dw1_tr_out[15] */ 326 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000211u, /* cpuss.dw0_tr_out[0] */ 327 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000212u, /* cpuss.dw0_tr_out[1] */ 328 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000213u, /* cpuss.dw0_tr_out[2] */ 329 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000214u, /* cpuss.dw0_tr_out[3] */ 330 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000215u, /* cpuss.dw0_tr_out[4] */ 331 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000216u, /* cpuss.dw0_tr_out[5] */ 332 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000217u, /* cpuss.dw0_tr_out[6] */ 333 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000218u, /* cpuss.dw0_tr_out[7] */ 334 TRIG_IN_MUX_2_PDMA0_TR_OUT8 = 0x00000219u, /* cpuss.dw0_tr_out[8] */ 335 TRIG_IN_MUX_2_PDMA0_TR_OUT9 = 0x0000021Au, /* cpuss.dw0_tr_out[9] */ 336 TRIG_IN_MUX_2_PDMA0_TR_OUT10 = 0x0000021Bu, /* cpuss.dw0_tr_out[10] */ 337 TRIG_IN_MUX_2_PDMA0_TR_OUT11 = 0x0000021Cu, /* cpuss.dw0_tr_out[11] */ 338 TRIG_IN_MUX_2_PDMA0_TR_OUT12 = 0x0000021Du, /* cpuss.dw0_tr_out[12] */ 339 TRIG_IN_MUX_2_PDMA0_TR_OUT13 = 0x0000021Eu, /* cpuss.dw0_tr_out[13] */ 340 TRIG_IN_MUX_2_PDMA0_TR_OUT14 = 0x0000021Fu, /* cpuss.dw0_tr_out[14] */ 341 TRIG_IN_MUX_2_PDMA0_TR_OUT15 = 0x00000220u, /* cpuss.dw0_tr_out[15] */ 342 TRIG_IN_MUX_2_TCPWM_16_TR_OUT030 = 0x00000221u, /* tcpwm[0].tr_out0[30] */ 343 TRIG_IN_MUX_2_TCPWM_16_TR_OUT031 = 0x00000222u, /* tcpwm[0].tr_out0[31] */ 344 TRIG_IN_MUX_2_TCPWM_16_TR_OUT032 = 0x00000223u, /* tcpwm[0].tr_out0[32] */ 345 TRIG_IN_MUX_2_TCPWM_16_TR_OUT033 = 0x00000224u, /* tcpwm[0].tr_out0[33] */ 346 TRIG_IN_MUX_2_TCPWM_16_TR_OUT034 = 0x00000225u, /* tcpwm[0].tr_out0[34] */ 347 TRIG_IN_MUX_2_TCPWM_16_TR_OUT035 = 0x00000226u, /* tcpwm[0].tr_out0[35] */ 348 TRIG_IN_MUX_2_TCPWM_16_TR_OUT036 = 0x00000227u, /* tcpwm[0].tr_out0[36] */ 349 TRIG_IN_MUX_2_TCPWM_16_TR_OUT037 = 0x00000228u, /* tcpwm[0].tr_out0[37] */ 350 TRIG_IN_MUX_2_TCPWM_16_TR_OUT038 = 0x00000229u, /* tcpwm[0].tr_out0[38] */ 351 TRIG_IN_MUX_2_TCPWM_16_TR_OUT039 = 0x0000022Au, /* tcpwm[0].tr_out0[39] */ 352 TRIG_IN_MUX_2_TCPWM_16_TR_OUT040 = 0x0000022Bu, /* tcpwm[0].tr_out0[40] */ 353 TRIG_IN_MUX_2_TCPWM_16_TR_OUT041 = 0x0000022Cu, /* tcpwm[0].tr_out0[41] */ 354 TRIG_IN_MUX_2_TCPWM_16_TR_OUT042 = 0x0000022Du, /* tcpwm[0].tr_out0[42] */ 355 TRIG_IN_MUX_2_TCPWM_16_TR_OUT043 = 0x0000022Eu, /* tcpwm[0].tr_out0[43] */ 356 TRIG_IN_MUX_2_TCPWM_16_TR_OUT044 = 0x0000022Fu, /* tcpwm[0].tr_out0[44] */ 357 TRIG_IN_MUX_2_TCPWM_16_TR_OUT045 = 0x00000230u, /* tcpwm[0].tr_out0[45] */ 358 TRIG_IN_MUX_2_TCPWM_16_TR_OUT046 = 0x00000231u, /* tcpwm[0].tr_out0[46] */ 359 TRIG_IN_MUX_2_TCPWM_16_TR_OUT047 = 0x00000232u, /* tcpwm[0].tr_out0[47] */ 360 TRIG_IN_MUX_2_TCPWM_16_TR_OUT048 = 0x00000233u, /* tcpwm[0].tr_out0[48] */ 361 TRIG_IN_MUX_2_TCPWM_16_TR_OUT049 = 0x00000234u, /* tcpwm[0].tr_out0[49] */ 362 TRIG_IN_MUX_2_TCPWM_16_TR_OUT050 = 0x00000235u, /* tcpwm[0].tr_out0[50] */ 363 TRIG_IN_MUX_2_TCPWM_16_TR_OUT051 = 0x00000236u, /* tcpwm[0].tr_out0[51] */ 364 TRIG_IN_MUX_2_TCPWM_16_TR_OUT052 = 0x00000237u, /* tcpwm[0].tr_out0[52] */ 365 TRIG_IN_MUX_2_TCPWM_16_TR_OUT053 = 0x00000238u, /* tcpwm[0].tr_out0[53] */ 366 TRIG_IN_MUX_2_TCPWM_16_TR_OUT054 = 0x00000239u, /* tcpwm[0].tr_out0[54] */ 367 TRIG_IN_MUX_2_TCPWM_16_TR_OUT055 = 0x0000023Au, /* tcpwm[0].tr_out0[55] */ 368 TRIG_IN_MUX_2_TCPWM_16_TR_OUT056 = 0x0000023Bu, /* tcpwm[0].tr_out0[56] */ 369 TRIG_IN_MUX_2_TCPWM_16_TR_OUT057 = 0x0000023Cu, /* tcpwm[0].tr_out0[57] */ 370 TRIG_IN_MUX_2_TCPWM_16_TR_OUT058 = 0x0000023Du, /* tcpwm[0].tr_out0[58] */ 371 TRIG_IN_MUX_2_TCPWM_16_TR_OUT059 = 0x0000023Eu, /* tcpwm[0].tr_out0[59] */ 372 TRIG_IN_MUX_2_TCPWM_16_TR_OUT060 = 0x0000023Fu, /* tcpwm[0].tr_out0[60] */ 373 TRIG_IN_MUX_2_TCPWM_16_TR_OUT061 = 0x00000240u, /* tcpwm[0].tr_out0[61] */ 374 TRIG_IN_MUX_2_TCPWM_16_TR_OUT062 = 0x00000241u, /* tcpwm[0].tr_out0[62] */ 375 TRIG_IN_MUX_2_HSIOM_IO_INPUT16 = 0x00000242u, /* peri.tr_io_input[16] */ 376 TRIG_IN_MUX_2_HSIOM_IO_INPUT17 = 0x00000243u, /* peri.tr_io_input[17] */ 377 TRIG_IN_MUX_2_HSIOM_IO_INPUT18 = 0x00000244u, /* peri.tr_io_input[18] */ 378 TRIG_IN_MUX_2_HSIOM_IO_INPUT19 = 0x00000245u, /* peri.tr_io_input[19] */ 379 TRIG_IN_MUX_2_HSIOM_IO_INPUT20 = 0x00000246u, /* peri.tr_io_input[20] */ 380 TRIG_IN_MUX_2_HSIOM_IO_INPUT21 = 0x00000247u, /* peri.tr_io_input[21] */ 381 TRIG_IN_MUX_2_HSIOM_IO_INPUT22 = 0x00000248u, /* peri.tr_io_input[22] */ 382 TRIG_IN_MUX_2_HSIOM_IO_INPUT23 = 0x00000249u, /* peri.tr_io_input[23] */ 383 TRIG_IN_MUX_2_HSIOM_IO_INPUT24 = 0x0000024Au, /* peri.tr_io_input[24] */ 384 TRIG_IN_MUX_2_HSIOM_IO_INPUT25 = 0x0000024Bu, /* peri.tr_io_input[25] */ 385 TRIG_IN_MUX_2_HSIOM_IO_INPUT26 = 0x0000024Cu, /* peri.tr_io_input[26] */ 386 TRIG_IN_MUX_2_HSIOM_IO_INPUT27 = 0x0000024Du, /* peri.tr_io_input[27] */ 387 TRIG_IN_MUX_2_HSIOM_IO_INPUT28 = 0x0000024Eu, /* peri.tr_io_input[28] */ 388 TRIG_IN_MUX_2_HSIOM_IO_INPUT29 = 0x0000024Fu, /* peri.tr_io_input[29] */ 389 TRIG_IN_MUX_2_HSIOM_IO_INPUT30 = 0x00000250u, /* peri.tr_io_input[30] */ 390 TRIG_IN_MUX_2_HSIOM_IO_INPUT31 = 0x00000251u /* peri.tr_io_input[31] */ 391 } en_trig_input_pdma1_tr_t; 392 393 /* Trigger Input Group 3 - M-DMA Request Assignments */ 394 typedef enum 395 { 396 TRIG_IN_MUX_3_TCPWM_16_TR_OUT10 = 0x00000301u, /* tcpwm[0].tr_out0[0] */ 397 TRIG_IN_MUX_3_TCPWM_16_TR_OUT11 = 0x00000302u, /* tcpwm[0].tr_out0[1] */ 398 TRIG_IN_MUX_3_TCPWM_16_TR_OUT12 = 0x00000303u, /* tcpwm[0].tr_out0[2] */ 399 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT10 = 0x00000304u, /* tcpwm[0].tr_out0[256] */ 400 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT11 = 0x00000305u, /* tcpwm[0].tr_out0[257] */ 401 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT12 = 0x00000306u /* tcpwm[0].tr_out0[258] */ 402 } en_trig_input_mdma_t; 403 404 /* Trigger Input Group 5 - */ 405 typedef enum 406 { 407 TRIG_IN_MUX_5_TCPWM_16_TR_OUT00 = 0x00000501u, /* tcpwm[0].tr_out0[0] */ 408 TRIG_IN_MUX_5_TCPWM_16_TR_OUT01 = 0x00000502u, /* tcpwm[0].tr_out0[1] */ 409 TRIG_IN_MUX_5_TCPWM_16_TR_OUT02 = 0x00000503u, /* tcpwm[0].tr_out0[2] */ 410 TRIG_IN_MUX_5_TCPWM_16_TR_OUT03 = 0x00000504u, /* tcpwm[0].tr_out0[3] */ 411 TRIG_IN_MUX_5_TCPWM_16_TR_OUT04 = 0x00000505u, /* tcpwm[0].tr_out0[4] */ 412 TRIG_IN_MUX_5_TCPWM_16_TR_OUT05 = 0x00000506u, /* tcpwm[0].tr_out0[5] */ 413 TRIG_IN_MUX_5_TCPWM_16_TR_OUT06 = 0x00000507u, /* tcpwm[0].tr_out0[6] */ 414 TRIG_IN_MUX_5_TCPWM_16_TR_OUT07 = 0x00000508u, /* tcpwm[0].tr_out0[7] */ 415 TRIG_IN_MUX_5_TCPWM_16_TR_OUT08 = 0x00000509u, /* tcpwm[0].tr_out0[8] */ 416 TRIG_IN_MUX_5_TCPWM_16_TR_OUT09 = 0x0000050Au, /* tcpwm[0].tr_out0[9] */ 417 TRIG_IN_MUX_5_TCPWM_16_TR_OUT010 = 0x0000050Bu, /* tcpwm[0].tr_out0[10] */ 418 TRIG_IN_MUX_5_TCPWM_16_TR_OUT011 = 0x0000050Cu, /* tcpwm[0].tr_out0[11] */ 419 TRIG_IN_MUX_5_TCPWM_16_TR_OUT012 = 0x0000050Du, /* tcpwm[0].tr_out0[12] */ 420 TRIG_IN_MUX_5_TCPWM_16_TR_OUT013 = 0x0000050Eu, /* tcpwm[0].tr_out0[13] */ 421 TRIG_IN_MUX_5_TCPWM_16_TR_OUT014 = 0x0000050Fu, /* tcpwm[0].tr_out0[14] */ 422 TRIG_IN_MUX_5_TCPWM_16_TR_OUT015 = 0x00000510u, /* tcpwm[0].tr_out0[15] */ 423 TRIG_IN_MUX_5_TCPWM_16_TR_OUT016 = 0x00000511u, /* tcpwm[0].tr_out0[16] */ 424 TRIG_IN_MUX_5_TCPWM_16_TR_OUT017 = 0x00000512u, /* tcpwm[0].tr_out0[17] */ 425 TRIG_IN_MUX_5_TCPWM_16_TR_OUT018 = 0x00000513u, /* tcpwm[0].tr_out0[18] */ 426 TRIG_IN_MUX_5_TCPWM_16_TR_OUT019 = 0x00000514u, /* tcpwm[0].tr_out0[19] */ 427 TRIG_IN_MUX_5_TCPWM_16_TR_OUT020 = 0x00000515u, /* tcpwm[0].tr_out0[20] */ 428 TRIG_IN_MUX_5_TCPWM_16_TR_OUT021 = 0x00000516u, /* tcpwm[0].tr_out0[21] */ 429 TRIG_IN_MUX_5_TCPWM_16_TR_OUT022 = 0x00000517u, /* tcpwm[0].tr_out0[22] */ 430 TRIG_IN_MUX_5_TCPWM_16_TR_OUT023 = 0x00000518u, /* tcpwm[0].tr_out0[23] */ 431 TRIG_IN_MUX_5_TCPWM_16_TR_OUT024 = 0x00000519u, /* tcpwm[0].tr_out0[24] */ 432 TRIG_IN_MUX_5_TCPWM_16_TR_OUT025 = 0x0000051Au, /* tcpwm[0].tr_out0[25] */ 433 TRIG_IN_MUX_5_TCPWM_16_TR_OUT026 = 0x0000051Bu, /* tcpwm[0].tr_out0[26] */ 434 TRIG_IN_MUX_5_TCPWM_16_TR_OUT027 = 0x0000051Cu, /* tcpwm[0].tr_out0[27] */ 435 TRIG_IN_MUX_5_TCPWM_16_TR_OUT028 = 0x0000051Du, /* tcpwm[0].tr_out0[28] */ 436 TRIG_IN_MUX_5_TCPWM_16_TR_OUT029 = 0x0000051Eu, /* tcpwm[0].tr_out0[29] */ 437 TRIG_IN_MUX_5_TCPWM_16_TR_OUT030 = 0x0000051Fu, /* tcpwm[0].tr_out0[30] */ 438 TRIG_IN_MUX_5_TCPWM_16_TR_OUT031 = 0x00000520u, /* tcpwm[0].tr_out0[31] */ 439 TRIG_IN_MUX_5_TCPWM_16_TR_OUT032 = 0x00000521u, /* tcpwm[0].tr_out0[32] */ 440 TRIG_IN_MUX_5_TCPWM_16_TR_OUT033 = 0x00000522u, /* tcpwm[0].tr_out0[33] */ 441 TRIG_IN_MUX_5_TCPWM_16_TR_OUT034 = 0x00000523u, /* tcpwm[0].tr_out0[34] */ 442 TRIG_IN_MUX_5_TCPWM_16_TR_OUT035 = 0x00000524u, /* tcpwm[0].tr_out0[35] */ 443 TRIG_IN_MUX_5_TCPWM_16_TR_OUT036 = 0x00000525u, /* tcpwm[0].tr_out0[36] */ 444 TRIG_IN_MUX_5_TCPWM_16_TR_OUT037 = 0x00000526u, /* tcpwm[0].tr_out0[37] */ 445 TRIG_IN_MUX_5_TCPWM_16_TR_OUT038 = 0x00000527u, /* tcpwm[0].tr_out0[38] */ 446 TRIG_IN_MUX_5_TCPWM_16_TR_OUT039 = 0x00000528u, /* tcpwm[0].tr_out0[39] */ 447 TRIG_IN_MUX_5_TCPWM_16_TR_OUT040 = 0x00000529u, /* tcpwm[0].tr_out0[40] */ 448 TRIG_IN_MUX_5_TCPWM_16_TR_OUT041 = 0x0000052Au, /* tcpwm[0].tr_out0[41] */ 449 TRIG_IN_MUX_5_TCPWM_16_TR_OUT042 = 0x0000052Bu, /* tcpwm[0].tr_out0[42] */ 450 TRIG_IN_MUX_5_TCPWM_16_TR_OUT043 = 0x0000052Cu, /* tcpwm[0].tr_out0[43] */ 451 TRIG_IN_MUX_5_TCPWM_16_TR_OUT044 = 0x0000052Du, /* tcpwm[0].tr_out0[44] */ 452 TRIG_IN_MUX_5_TCPWM_16_TR_OUT045 = 0x0000052Eu, /* tcpwm[0].tr_out0[45] */ 453 TRIG_IN_MUX_5_TCPWM_16_TR_OUT046 = 0x0000052Fu, /* tcpwm[0].tr_out0[46] */ 454 TRIG_IN_MUX_5_TCPWM_16_TR_OUT047 = 0x00000530u, /* tcpwm[0].tr_out0[47] */ 455 TRIG_IN_MUX_5_TCPWM_16_TR_OUT048 = 0x00000531u, /* tcpwm[0].tr_out0[48] */ 456 TRIG_IN_MUX_5_TCPWM_16_TR_OUT049 = 0x00000532u, /* tcpwm[0].tr_out0[49] */ 457 TRIG_IN_MUX_5_TCPWM_16_TR_OUT050 = 0x00000533u, /* tcpwm[0].tr_out0[50] */ 458 TRIG_IN_MUX_5_TCPWM_16_TR_OUT051 = 0x00000534u, /* tcpwm[0].tr_out0[51] */ 459 TRIG_IN_MUX_5_TCPWM_16_TR_OUT052 = 0x00000535u, /* tcpwm[0].tr_out0[52] */ 460 TRIG_IN_MUX_5_TCPWM_16_TR_OUT053 = 0x00000536u, /* tcpwm[0].tr_out0[53] */ 461 TRIG_IN_MUX_5_TCPWM_16_TR_OUT054 = 0x00000537u, /* tcpwm[0].tr_out0[54] */ 462 TRIG_IN_MUX_5_TCPWM_16_TR_OUT055 = 0x00000538u, /* tcpwm[0].tr_out0[55] */ 463 TRIG_IN_MUX_5_TCPWM_16_TR_OUT056 = 0x00000539u, /* tcpwm[0].tr_out0[56] */ 464 TRIG_IN_MUX_5_TCPWM_16_TR_OUT057 = 0x0000053Au, /* tcpwm[0].tr_out0[57] */ 465 TRIG_IN_MUX_5_TCPWM_16_TR_OUT058 = 0x0000053Bu, /* tcpwm[0].tr_out0[58] */ 466 TRIG_IN_MUX_5_TCPWM_16_TR_OUT059 = 0x0000053Cu, /* tcpwm[0].tr_out0[59] */ 467 TRIG_IN_MUX_5_TCPWM_16_TR_OUT060 = 0x0000053Du, /* tcpwm[0].tr_out0[60] */ 468 TRIG_IN_MUX_5_TCPWM_16_TR_OUT061 = 0x0000053Eu, /* tcpwm[0].tr_out0[61] */ 469 TRIG_IN_MUX_5_TCPWM_16_TR_OUT062 = 0x0000053Fu, /* tcpwm[0].tr_out0[62] */ 470 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT00 = 0x00000540u, /* tcpwm[0].tr_out0[256] */ 471 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT01 = 0x00000541u, /* tcpwm[0].tr_out0[257] */ 472 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT02 = 0x00000542u, /* tcpwm[0].tr_out0[258] */ 473 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT03 = 0x00000543u, /* tcpwm[0].tr_out0[259] */ 474 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT04 = 0x00000544u, /* tcpwm[0].tr_out0[260] */ 475 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT05 = 0x00000545u, /* tcpwm[0].tr_out0[261] */ 476 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT06 = 0x00000546u, /* tcpwm[0].tr_out0[262] */ 477 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT07 = 0x00000547u, /* tcpwm[0].tr_out0[263] */ 478 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT08 = 0x00000548u, /* tcpwm[0].tr_out0[264] */ 479 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT09 = 0x00000549u, /* tcpwm[0].tr_out0[265] */ 480 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT010 = 0x0000054Au, /* tcpwm[0].tr_out0[266] */ 481 TRIG_IN_MUX_5_TCPWM_16M_TR_OUT011 = 0x0000054Bu, /* tcpwm[0].tr_out0[267] */ 482 TRIG_IN_MUX_5_TCPWM_32_TR_OUT00 = 0x0000054Cu, /* tcpwm[0].tr_out0[512] */ 483 TRIG_IN_MUX_5_TCPWM_32_TR_OUT01 = 0x0000054Du, /* tcpwm[0].tr_out0[513] */ 484 TRIG_IN_MUX_5_TCPWM_32_TR_OUT02 = 0x0000054Eu, /* tcpwm[0].tr_out0[514] */ 485 TRIG_IN_MUX_5_TCPWM_32_TR_OUT03 = 0x0000054Fu, /* tcpwm[0].tr_out0[515] */ 486 TRIG_IN_MUX_5_TCPWM_32_TR_OUT04 = 0x00000550u, /* tcpwm[0].tr_out0[516] */ 487 TRIG_IN_MUX_5_TCPWM_32_TR_OUT05 = 0x00000551u, /* tcpwm[0].tr_out0[517] */ 488 TRIG_IN_MUX_5_TCPWM_32_TR_OUT06 = 0x00000552u, /* tcpwm[0].tr_out0[518] */ 489 TRIG_IN_MUX_5_TCPWM_32_TR_OUT07 = 0x00000553u, /* tcpwm[0].tr_out0[519] */ 490 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT0 = 0x00000554u, /* canfd[0].tr_dbg_dma_req[0] */ 491 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT1 = 0x00000555u, /* canfd[0].tr_dbg_dma_req[1] */ 492 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT2 = 0x00000556u, /* canfd[0].tr_dbg_dma_req[2] */ 493 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT3 = 0x00000557u, /* canfd[0].tr_dbg_dma_req[3] */ 494 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT0 = 0x00000558u, /* canfd[0].tr_fifo0[0] */ 495 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT1 = 0x00000559u, /* canfd[0].tr_fifo0[1] */ 496 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT2 = 0x0000055Au, /* canfd[0].tr_fifo0[2] */ 497 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT3 = 0x0000055Bu, /* canfd[0].tr_fifo0[3] */ 498 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT0 = 0x0000055Cu, /* canfd[0].tr_fifo1[0] */ 499 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT1 = 0x0000055Du, /* canfd[0].tr_fifo1[1] */ 500 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT2 = 0x0000055Eu, /* canfd[0].tr_fifo1[2] */ 501 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT3 = 0x0000055Fu, /* canfd[0].tr_fifo1[3] */ 502 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT0 = 0x00000560u, /* canfd[1].tr_dbg_dma_req[0] */ 503 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT1 = 0x00000561u, /* canfd[1].tr_dbg_dma_req[1] */ 504 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT2 = 0x00000562u, /* canfd[1].tr_dbg_dma_req[2] */ 505 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT3 = 0x00000563u, /* canfd[1].tr_dbg_dma_req[3] */ 506 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT0 = 0x00000564u, /* canfd[1].tr_fifo0[0] */ 507 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT1 = 0x00000565u, /* canfd[1].tr_fifo0[1] */ 508 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT2 = 0x00000566u, /* canfd[1].tr_fifo0[2] */ 509 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT3 = 0x00000567u, /* canfd[1].tr_fifo0[3] */ 510 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT0 = 0x00000568u, /* canfd[1].tr_fifo1[0] */ 511 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT1 = 0x00000569u, /* canfd[1].tr_fifo1[1] */ 512 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT2 = 0x0000056Au, /* canfd[1].tr_fifo1[2] */ 513 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT3 = 0x0000056Bu, /* canfd[1].tr_fifo1[3] */ 514 TRIG_IN_MUX_5_CAN0_TT_TR_OUT0 = 0x0000056Cu, /* canfd[0].tr_tmp_rtp_out[0] */ 515 TRIG_IN_MUX_5_CAN0_TT_TR_OUT1 = 0x0000056Du, /* canfd[0].tr_tmp_rtp_out[1] */ 516 TRIG_IN_MUX_5_CAN0_TT_TR_OUT2 = 0x0000056Eu, /* canfd[0].tr_tmp_rtp_out[2] */ 517 TRIG_IN_MUX_5_CAN0_TT_TR_OUT3 = 0x0000056Fu, /* canfd[0].tr_tmp_rtp_out[3] */ 518 TRIG_IN_MUX_5_CAN1_TT_TR_OUT0 = 0x00000570u, /* canfd[1].tr_tmp_rtp_out[0] */ 519 TRIG_IN_MUX_5_CAN1_TT_TR_OUT1 = 0x00000571u, /* canfd[1].tr_tmp_rtp_out[1] */ 520 TRIG_IN_MUX_5_CAN1_TT_TR_OUT2 = 0x00000572u, /* canfd[1].tr_tmp_rtp_out[2] */ 521 TRIG_IN_MUX_5_CAN1_TT_TR_OUT3 = 0x00000573u, /* canfd[1].tr_tmp_rtp_out[3] */ 522 TRIG_IN_MUX_5_EVTGEN_TR_OUT4 = 0x00000574u, /* evtgen[0].tr_out[4] */ 523 TRIG_IN_MUX_5_EVTGEN_TR_OUT5 = 0x00000575u, /* evtgen[0].tr_out[5] */ 524 TRIG_IN_MUX_5_EVTGEN_TR_OUT6 = 0x00000576u, /* evtgen[0].tr_out[6] */ 525 TRIG_IN_MUX_5_EVTGEN_TR_OUT7 = 0x00000577u, /* evtgen[0].tr_out[7] */ 526 TRIG_IN_MUX_5_EVTGEN_TR_OUT8 = 0x00000578u, /* evtgen[0].tr_out[8] */ 527 TRIG_IN_MUX_5_EVTGEN_TR_OUT9 = 0x00000579u, /* evtgen[0].tr_out[9] */ 528 TRIG_IN_MUX_5_EVTGEN_TR_OUT10 = 0x0000057Au, /* evtgen[0].tr_out[10] */ 529 TRIG_IN_MUX_5_EVTGEN_TR_OUT11 = 0x0000057Bu, /* evtgen[0].tr_out[11] */ 530 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x0000057Cu, /* cpuss.dw0_tr_out[0] */ 531 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x0000057Du, /* cpuss.dw0_tr_out[1] */ 532 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x0000057Eu, /* cpuss.dw0_tr_out[2] */ 533 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x0000057Fu, /* cpuss.dw0_tr_out[3] */ 534 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000580u, /* cpuss.dw0_tr_out[4] */ 535 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000581u, /* cpuss.dw0_tr_out[5] */ 536 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000582u, /* cpuss.dw0_tr_out[6] */ 537 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000583u, /* cpuss.dw0_tr_out[7] */ 538 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000584u, /* cpuss.dw0_tr_out[8] */ 539 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x00000585u, /* cpuss.dw0_tr_out[9] */ 540 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x00000586u, /* cpuss.dw0_tr_out[10] */ 541 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x00000587u, /* cpuss.dw0_tr_out[11] */ 542 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x00000588u, /* cpuss.dw0_tr_out[12] */ 543 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x00000589u, /* cpuss.dw0_tr_out[13] */ 544 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000058Au, /* cpuss.dw0_tr_out[14] */ 545 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x0000058Bu, /* cpuss.dw0_tr_out[15] */ 546 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000058Cu, /* cpuss.dw1_tr_out[0] */ 547 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000058Du, /* cpuss.dw1_tr_out[1] */ 548 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x0000058Eu, /* cpuss.dw1_tr_out[2] */ 549 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x0000058Fu, /* cpuss.dw1_tr_out[3] */ 550 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000590u, /* cpuss.dw1_tr_out[4] */ 551 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000591u, /* cpuss.dw1_tr_out[5] */ 552 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000592u, /* cpuss.dw1_tr_out[6] */ 553 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000593u, /* cpuss.dw1_tr_out[7] */ 554 TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000594u, /* cpuss.dw1_tr_out[8] */ 555 TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000595u, /* cpuss.dw1_tr_out[9] */ 556 TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000596u, /* cpuss.dw1_tr_out[10] */ 557 TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000597u, /* cpuss.dw1_tr_out[11] */ 558 TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x00000598u, /* cpuss.dw1_tr_out[12] */ 559 TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x00000599u, /* cpuss.dw1_tr_out[13] */ 560 TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000059Au, /* cpuss.dw1_tr_out[14] */ 561 TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000059Bu, /* cpuss.dw1_tr_out[15] */ 562 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Cu, /* cpuss.dmac_tr_out[0] */ 563 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Du, /* cpuss.dmac_tr_out[1] */ 564 TRIG_IN_MUX_5_MDMA_TR_OUT2 = 0x0000059Eu, /* cpuss.dmac_tr_out[2] */ 565 TRIG_IN_MUX_5_MDMA_TR_OUT3 = 0x0000059Fu, /* cpuss.dmac_tr_out[3] */ 566 TRIG_IN_MUX_5_MDMA_TR_OUT4 = 0x000005A0u, /* cpuss.dmac_tr_out[4] */ 567 TRIG_IN_MUX_5_MDMA_TR_OUT5 = 0x000005A1u, /* cpuss.dmac_tr_out[5] */ 568 TRIG_IN_MUX_5_MDMA_TR_OUT6 = 0x000005A2u, /* cpuss.dmac_tr_out[6] */ 569 TRIG_IN_MUX_5_MDMA_TR_OUT7 = 0x000005A3u, /* cpuss.dmac_tr_out[7] */ 570 TRIG_IN_MUX_5_SMIF_TX_TR_OUT = 0x000005A4u, /* smif[0].tr_tx_req */ 571 TRIG_IN_MUX_5_SMIF_RX_TR_OUT = 0x000005A5u, /* smif[0].tr_rx_req */ 572 TRIG_IN_MUX_5_I2S0_TX_TR_OUT = 0x000005A6u, /* audioss[0].tr_i2s_tx_req */ 573 TRIG_IN_MUX_5_I2S0_RX_TR_OUT = 0x000005A7u, /* audioss[0].tr_i2s_rx_req */ 574 TRIG_IN_MUX_5_I2S1_TX_TR_OUT = 0x000005A8u, /* audioss[1].tr_i2s_tx_req */ 575 TRIG_IN_MUX_5_I2S1_RX_TR_OUT = 0x000005A9u, /* audioss[1].tr_i2s_rx_req */ 576 TRIG_IN_MUX_5_I2S2_TX_TR_OUT = 0x000005AAu, /* audioss[2].tr_i2s_tx_req */ 577 TRIG_IN_MUX_5_I2S2_RX_TR_OUT = 0x000005ABu /* audioss[2].tr_i2s_rx_req */ 578 } en_trig_input_tcpwm_out_t; 579 580 /* Trigger Input Group 6 - TCPWM trigger inputs */ 581 typedef enum 582 { 583 TRIG_IN_MUX_6_TCPWM_16_TR_OUT10 = 0x00000601u, /* tcpwm[0].tr_out1[0] */ 584 TRIG_IN_MUX_6_TCPWM_16_TR_OUT11 = 0x00000602u, /* tcpwm[0].tr_out1[1] */ 585 TRIG_IN_MUX_6_TCPWM_16_TR_OUT12 = 0x00000603u, /* tcpwm[0].tr_out1[2] */ 586 TRIG_IN_MUX_6_TCPWM_16_TR_OUT13 = 0x00000604u, /* tcpwm[0].tr_out1[3] */ 587 TRIG_IN_MUX_6_TCPWM_16_TR_OUT14 = 0x00000605u, /* tcpwm[0].tr_out1[4] */ 588 TRIG_IN_MUX_6_TCPWM_16_TR_OUT15 = 0x00000606u, /* tcpwm[0].tr_out1[5] */ 589 TRIG_IN_MUX_6_TCPWM_16_TR_OUT16 = 0x00000607u, /* tcpwm[0].tr_out1[6] */ 590 TRIG_IN_MUX_6_TCPWM_16_TR_OUT17 = 0x00000608u, /* tcpwm[0].tr_out1[7] */ 591 TRIG_IN_MUX_6_TCPWM_16_TR_OUT18 = 0x00000609u, /* tcpwm[0].tr_out1[8] */ 592 TRIG_IN_MUX_6_TCPWM_16_TR_OUT19 = 0x0000060Au, /* tcpwm[0].tr_out1[9] */ 593 TRIG_IN_MUX_6_TCPWM_16_TR_OUT110 = 0x0000060Bu, /* tcpwm[0].tr_out1[10] */ 594 TRIG_IN_MUX_6_TCPWM_16_TR_OUT111 = 0x0000060Cu, /* tcpwm[0].tr_out1[11] */ 595 TRIG_IN_MUX_6_TCPWM_16_TR_OUT112 = 0x0000060Du, /* tcpwm[0].tr_out1[12] */ 596 TRIG_IN_MUX_6_TCPWM_16_TR_OUT113 = 0x0000060Eu, /* tcpwm[0].tr_out1[13] */ 597 TRIG_IN_MUX_6_TCPWM_16_TR_OUT114 = 0x0000060Fu, /* tcpwm[0].tr_out1[14] */ 598 TRIG_IN_MUX_6_TCPWM_16_TR_OUT115 = 0x00000610u, /* tcpwm[0].tr_out1[15] */ 599 TRIG_IN_MUX_6_SCB_TX_TR_OUT0 = 0x00000611u, /* scb[0].tr_tx_req */ 600 TRIG_IN_MUX_6_SCB_RX_TR_OUT0 = 0x00000612u, /* scb[0].tr_rx_req */ 601 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT0 = 0x00000613u, /* scb[0].tr_i2c_scl_filtered */ 602 TRIG_IN_MUX_6_SCB_TX_TR_OUT1 = 0x00000614u, /* scb[1].tr_tx_req */ 603 TRIG_IN_MUX_6_SCB_RX_TR_OUT1 = 0x00000615u, /* scb[1].tr_rx_req */ 604 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT1 = 0x00000616u, /* scb[1].tr_i2c_scl_filtered */ 605 TRIG_IN_MUX_6_SCB_TX_TR_OUT2 = 0x00000617u, /* scb[2].tr_tx_req */ 606 TRIG_IN_MUX_6_SCB_RX_TR_OUT2 = 0x00000618u, /* scb[2].tr_rx_req */ 607 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT2 = 0x00000619u, /* scb[2].tr_i2c_scl_filtered */ 608 TRIG_IN_MUX_6_SCB_TX_TR_OUT3 = 0x0000061Au, /* scb[3].tr_tx_req */ 609 TRIG_IN_MUX_6_SCB_RX_TR_OUT3 = 0x0000061Bu, /* scb[3].tr_rx_req */ 610 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT3 = 0x0000061Cu, /* scb[3].tr_i2c_scl_filtered */ 611 TRIG_IN_MUX_6_SCB_TX_TR_OUT4 = 0x0000061Du, /* scb[4].tr_tx_req */ 612 TRIG_IN_MUX_6_SCB_RX_TR_OUT4 = 0x0000061Eu, /* scb[4].tr_rx_req */ 613 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT4 = 0x0000061Fu, /* scb[4].tr_i2c_scl_filtered */ 614 TRIG_IN_MUX_6_SCB_TX_TR_OUT5 = 0x00000620u, /* scb[5].tr_tx_req */ 615 TRIG_IN_MUX_6_SCB_RX_TR_OUT5 = 0x00000621u, /* scb[5].tr_rx_req */ 616 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT5 = 0x00000622u, /* scb[5].tr_i2c_scl_filtered */ 617 TRIG_IN_MUX_6_SCB_TX_TR_OUT6 = 0x00000623u, /* scb[6].tr_tx_req */ 618 TRIG_IN_MUX_6_SCB_RX_TR_OUT6 = 0x00000624u, /* scb[6].tr_rx_req */ 619 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT6 = 0x00000625u, /* scb[6].tr_i2c_scl_filtered */ 620 TRIG_IN_MUX_6_SCB_TX_TR_OUT7 = 0x00000626u, /* scb[7].tr_tx_req */ 621 TRIG_IN_MUX_6_SCB_RX_TR_OUT7 = 0x00000627u, /* scb[7].tr_rx_req */ 622 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT7 = 0x00000628u, /* scb[7].tr_i2c_scl_filtered */ 623 TRIG_IN_MUX_6_SCB_TX_TR_OUT8 = 0x00000629u, /* scb[8].tr_tx_req */ 624 TRIG_IN_MUX_6_SCB_RX_TR_OUT8 = 0x0000062Au, /* scb[8].tr_rx_req */ 625 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT8 = 0x0000062Bu, /* scb[8].tr_i2c_scl_filtered */ 626 TRIG_IN_MUX_6_SCB_TX_TR_OUT9 = 0x0000062Cu, /* scb[9].tr_tx_req */ 627 TRIG_IN_MUX_6_SCB_RX_TR_OUT9 = 0x0000062Du, /* scb[9].tr_rx_req */ 628 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT9 = 0x0000062Eu, /* scb[9].tr_i2c_scl_filtered */ 629 TRIG_IN_MUX_6_SCB_TX_TR_OUT10 = 0x0000062Fu, /* scb[10].tr_tx_req */ 630 TRIG_IN_MUX_6_SCB_RX_TR_OUT10 = 0x00000630u, /* scb[10].tr_rx_req */ 631 TRIG_IN_MUX_6_SCB_I2C_SCL_TR_OUT10 = 0x00000631u, /* scb[10].tr_i2c_scl_filtered */ 632 TRIG_IN_MUX_6_PASS_GEN_TR_OUT0 = 0x00000632u, /* pass[0].tr_sar_gen_out[0] */ 633 TRIG_IN_MUX_6_PASS_GEN_TR_OUT1 = 0x00000633u, /* pass[0].tr_sar_gen_out[1] */ 634 TRIG_IN_MUX_6_PASS_GEN_TR_OUT2 = 0x00000634u, /* pass[0].tr_sar_gen_out[2] */ 635 TRIG_IN_MUX_6_PASS_GEN_TR_OUT3 = 0x00000635u, /* pass[0].tr_sar_gen_out[3] */ 636 TRIG_IN_MUX_6_PASS_GEN_TR_OUT4 = 0x00000636u, /* pass[0].tr_sar_gen_out[4] */ 637 TRIG_IN_MUX_6_PASS_GEN_TR_OUT5 = 0x00000637u, /* pass[0].tr_sar_gen_out[5] */ 638 TRIG_IN_MUX_6_HSIOM_IO_INPUT0 = 0x00000638u, /* peri.tr_io_input[0] */ 639 TRIG_IN_MUX_6_HSIOM_IO_INPUT1 = 0x00000639u, /* peri.tr_io_input[1] */ 640 TRIG_IN_MUX_6_HSIOM_IO_INPUT2 = 0x0000063Au, /* peri.tr_io_input[2] */ 641 TRIG_IN_MUX_6_HSIOM_IO_INPUT3 = 0x0000063Bu, /* peri.tr_io_input[3] */ 642 TRIG_IN_MUX_6_HSIOM_IO_INPUT4 = 0x0000063Cu, /* peri.tr_io_input[4] */ 643 TRIG_IN_MUX_6_HSIOM_IO_INPUT5 = 0x0000063Du, /* peri.tr_io_input[5] */ 644 TRIG_IN_MUX_6_HSIOM_IO_INPUT6 = 0x0000063Eu, /* peri.tr_io_input[6] */ 645 TRIG_IN_MUX_6_HSIOM_IO_INPUT7 = 0x0000063Fu, /* peri.tr_io_input[7] */ 646 TRIG_IN_MUX_6_HSIOM_IO_INPUT8 = 0x00000640u, /* peri.tr_io_input[8] */ 647 TRIG_IN_MUX_6_HSIOM_IO_INPUT9 = 0x00000641u, /* peri.tr_io_input[9] */ 648 TRIG_IN_MUX_6_HSIOM_IO_INPUT10 = 0x00000642u, /* peri.tr_io_input[10] */ 649 TRIG_IN_MUX_6_HSIOM_IO_INPUT11 = 0x00000643u, /* peri.tr_io_input[11] */ 650 TRIG_IN_MUX_6_HSIOM_IO_INPUT12 = 0x00000644u, /* peri.tr_io_input[12] */ 651 TRIG_IN_MUX_6_HSIOM_IO_INPUT13 = 0x00000645u, /* peri.tr_io_input[13] */ 652 TRIG_IN_MUX_6_HSIOM_IO_INPUT14 = 0x00000646u, /* peri.tr_io_input[14] */ 653 TRIG_IN_MUX_6_HSIOM_IO_INPUT15 = 0x00000647u, /* peri.tr_io_input[15] */ 654 TRIG_IN_MUX_6_HSIOM_IO_INPUT16 = 0x00000648u, /* peri.tr_io_input[16] */ 655 TRIG_IN_MUX_6_HSIOM_IO_INPUT17 = 0x00000649u, /* peri.tr_io_input[17] */ 656 TRIG_IN_MUX_6_HSIOM_IO_INPUT18 = 0x0000064Au, /* peri.tr_io_input[18] */ 657 TRIG_IN_MUX_6_HSIOM_IO_INPUT19 = 0x0000064Bu, /* peri.tr_io_input[19] */ 658 TRIG_IN_MUX_6_HSIOM_IO_INPUT20 = 0x0000064Cu, /* peri.tr_io_input[20] */ 659 TRIG_IN_MUX_6_HSIOM_IO_INPUT21 = 0x0000064Du, /* peri.tr_io_input[21] */ 660 TRIG_IN_MUX_6_HSIOM_IO_INPUT22 = 0x0000064Eu, /* peri.tr_io_input[22] */ 661 TRIG_IN_MUX_6_HSIOM_IO_INPUT23 = 0x0000064Fu, /* peri.tr_io_input[23] */ 662 TRIG_IN_MUX_6_HSIOM_IO_INPUT24 = 0x00000650u, /* peri.tr_io_input[24] */ 663 TRIG_IN_MUX_6_HSIOM_IO_INPUT25 = 0x00000651u, /* peri.tr_io_input[25] */ 664 TRIG_IN_MUX_6_HSIOM_IO_INPUT26 = 0x00000652u, /* peri.tr_io_input[26] */ 665 TRIG_IN_MUX_6_HSIOM_IO_INPUT27 = 0x00000653u, /* peri.tr_io_input[27] */ 666 TRIG_IN_MUX_6_HSIOM_IO_INPUT28 = 0x00000654u, /* peri.tr_io_input[28] */ 667 TRIG_IN_MUX_6_HSIOM_IO_INPUT29 = 0x00000655u, /* peri.tr_io_input[29] */ 668 TRIG_IN_MUX_6_HSIOM_IO_INPUT30 = 0x00000656u, /* peri.tr_io_input[30] */ 669 TRIG_IN_MUX_6_HSIOM_IO_INPUT31 = 0x00000657u, /* peri.tr_io_input[31] */ 670 TRIG_IN_MUX_6_CTI_TR_IN0 = 0x00000658u, /* cpuss.cti_tr_out[0] */ 671 TRIG_IN_MUX_6_CTI_TR_IN1 = 0x00000659u, /* cpuss.cti_tr_out[1] */ 672 TRIG_IN_MUX_6_FAULT_TR_OUT0 = 0x0000065Au, /* cpuss.tr_fault[0] */ 673 TRIG_IN_MUX_6_FAULT_TR_OUT1 = 0x0000065Bu, /* cpuss.tr_fault[1] */ 674 TRIG_IN_MUX_6_FAULT_TR_OUT2 = 0x0000065Cu, /* cpuss.tr_fault[2] */ 675 TRIG_IN_MUX_6_FAULT_TR_OUT3 = 0x0000065Du /* cpuss.tr_fault[3] */ 676 } en_trig_input_tcpwm_in_t; 677 678 /* Trigger Input Group 7 - PASS trigger multiplexer */ 679 typedef enum 680 { 681 TRIG_IN_MUX_7_PDMA0_TR_OUT0 = 0x00000701u, /* cpuss.dw0_tr_out[0] */ 682 TRIG_IN_MUX_7_PDMA0_TR_OUT1 = 0x00000702u, /* cpuss.dw0_tr_out[1] */ 683 TRIG_IN_MUX_7_PDMA0_TR_OUT2 = 0x00000703u, /* cpuss.dw0_tr_out[2] */ 684 TRIG_IN_MUX_7_PDMA0_TR_OUT3 = 0x00000704u, /* cpuss.dw0_tr_out[3] */ 685 TRIG_IN_MUX_7_PDMA0_TR_OUT4 = 0x00000705u, /* cpuss.dw0_tr_out[4] */ 686 TRIG_IN_MUX_7_PDMA0_TR_OUT5 = 0x00000706u, /* cpuss.dw0_tr_out[5] */ 687 TRIG_IN_MUX_7_PDMA0_TR_OUT6 = 0x00000707u, /* cpuss.dw0_tr_out[6] */ 688 TRIG_IN_MUX_7_PDMA0_TR_OUT7 = 0x00000708u, /* cpuss.dw0_tr_out[7] */ 689 TRIG_IN_MUX_7_PDMA0_TR_OUT8 = 0x00000709u, /* cpuss.dw0_tr_out[8] */ 690 TRIG_IN_MUX_7_PDMA0_TR_OUT9 = 0x0000070Au, /* cpuss.dw0_tr_out[9] */ 691 TRIG_IN_MUX_7_PDMA0_TR_OUT10 = 0x0000070Bu, /* cpuss.dw0_tr_out[10] */ 692 TRIG_IN_MUX_7_PDMA0_TR_OUT11 = 0x0000070Cu, /* cpuss.dw0_tr_out[11] */ 693 TRIG_IN_MUX_7_PDMA0_TR_OUT12 = 0x0000070Du, /* cpuss.dw0_tr_out[12] */ 694 TRIG_IN_MUX_7_PDMA0_TR_OUT13 = 0x0000070Eu, /* cpuss.dw0_tr_out[13] */ 695 TRIG_IN_MUX_7_PDMA0_TR_OUT14 = 0x0000070Fu, /* cpuss.dw0_tr_out[14] */ 696 TRIG_IN_MUX_7_PDMA0_TR_OUT15 = 0x00000710u, /* cpuss.dw0_tr_out[15] */ 697 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT00 = 0x00000711u, /* tcpwm[0].tr_out0[256] */ 698 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT01 = 0x00000712u, /* tcpwm[0].tr_out0[257] */ 699 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT02 = 0x00000713u, /* tcpwm[0].tr_out0[258] */ 700 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT03 = 0x00000714u, /* tcpwm[0].tr_out0[259] */ 701 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT04 = 0x00000715u, /* tcpwm[0].tr_out0[260] */ 702 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT05 = 0x00000716u, /* tcpwm[0].tr_out0[261] */ 703 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT06 = 0x00000717u, /* tcpwm[0].tr_out0[262] */ 704 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT07 = 0x00000718u, /* tcpwm[0].tr_out0[263] */ 705 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT08 = 0x00000719u, /* tcpwm[0].tr_out0[264] */ 706 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT09 = 0x0000071Au, /* tcpwm[0].tr_out0[265] */ 707 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT010 = 0x0000071Bu, /* tcpwm[0].tr_out0[266] */ 708 TRIG_IN_MUX_7_TCPWM_16M_TR_OUT011 = 0x0000071Cu, /* tcpwm[0].tr_out0[267] */ 709 TRIG_IN_MUX_7_TCPWM_32_TR_OUT00 = 0x0000071Du, /* tcpwm[0].tr_out0[512] */ 710 TRIG_IN_MUX_7_TCPWM_32_TR_OUT01 = 0x0000071Eu, /* tcpwm[0].tr_out0[513] */ 711 TRIG_IN_MUX_7_TCPWM_32_TR_OUT02 = 0x0000071Fu, /* tcpwm[0].tr_out0[514] */ 712 TRIG_IN_MUX_7_TCPWM_32_TR_OUT03 = 0x00000720u, /* tcpwm[0].tr_out0[515] */ 713 TRIG_IN_MUX_7_TCPWM_32_TR_OUT04 = 0x00000721u, /* tcpwm[0].tr_out0[516] */ 714 TRIG_IN_MUX_7_TCPWM_32_TR_OUT05 = 0x00000722u, /* tcpwm[0].tr_out0[517] */ 715 TRIG_IN_MUX_7_TCPWM_32_TR_OUT06 = 0x00000723u, /* tcpwm[0].tr_out0[518] */ 716 TRIG_IN_MUX_7_TCPWM_32_TR_OUT07 = 0x00000724u, /* tcpwm[0].tr_out0[519] */ 717 TRIG_IN_MUX_7_TCPWM_16_TR_OUT160 = 0x00000725u, /* tcpwm[0].tr_out1[60] */ 718 TRIG_IN_MUX_7_TCPWM_16_TR_OUT161 = 0x00000726u, /* tcpwm[0].tr_out1[61] */ 719 TRIG_IN_MUX_7_HSIOM_IO_INPUT0 = 0x00000727u, /* peri.tr_io_input[0] */ 720 TRIG_IN_MUX_7_HSIOM_IO_INPUT1 = 0x00000728u, /* peri.tr_io_input[1] */ 721 TRIG_IN_MUX_7_HSIOM_IO_INPUT2 = 0x00000729u, /* peri.tr_io_input[2] */ 722 TRIG_IN_MUX_7_HSIOM_IO_INPUT3 = 0x0000072Au, /* peri.tr_io_input[3] */ 723 TRIG_IN_MUX_7_HSIOM_IO_INPUT4 = 0x0000072Bu, /* peri.tr_io_input[4] */ 724 TRIG_IN_MUX_7_HSIOM_IO_INPUT5 = 0x0000072Cu, /* peri.tr_io_input[5] */ 725 TRIG_IN_MUX_7_HSIOM_IO_INPUT6 = 0x0000072Du, /* peri.tr_io_input[6] */ 726 TRIG_IN_MUX_7_HSIOM_IO_INPUT7 = 0x0000072Eu, /* peri.tr_io_input[7] */ 727 TRIG_IN_MUX_7_EVTGEN_TR_OUT12 = 0x0000072Fu, /* evtgen[0].tr_out[12] */ 728 TRIG_IN_MUX_7_EVTGEN_TR_OUT13 = 0x00000730u, /* evtgen[0].tr_out[13] */ 729 TRIG_IN_MUX_7_EVTGEN_TR_OUT14 = 0x00000731u /* evtgen[0].tr_out[14] */ 730 } en_trig_input_pass_t; 731 732 /* Trigger Input Group 8 - CAN TT Synchronization triggers */ 733 typedef enum 734 { 735 TRIG_IN_MUX_8_CAN0_TT_TR_OUT0 = 0x00000801u, /* canfd[0].tr_tmp_rtp_out[0] */ 736 TRIG_IN_MUX_8_CAN0_TT_TR_OUT1 = 0x00000802u, /* canfd[0].tr_tmp_rtp_out[1] */ 737 TRIG_IN_MUX_8_CAN0_TT_TR_OUT2 = 0x00000803u, /* canfd[0].tr_tmp_rtp_out[2] */ 738 TRIG_IN_MUX_8_CAN0_TT_TR_OUT3 = 0x00000804u, /* canfd[0].tr_tmp_rtp_out[3] */ 739 TRIG_IN_MUX_8_CAN1_TT_TR_OUT0 = 0x00000805u, /* canfd[1].tr_tmp_rtp_out[0] */ 740 TRIG_IN_MUX_8_CAN1_TT_TR_OUT1 = 0x00000806u, /* canfd[1].tr_tmp_rtp_out[1] */ 741 TRIG_IN_MUX_8_CAN1_TT_TR_OUT2 = 0x00000807u, /* canfd[1].tr_tmp_rtp_out[2] */ 742 TRIG_IN_MUX_8_CAN1_TT_TR_OUT3 = 0x00000808u /* canfd[1].tr_tmp_rtp_out[3] */ 743 } en_trig_input_cantt_t; 744 745 /* Trigger Input Group 9 - 2nd level MUX using input from MUX_9/10/11 */ 746 typedef enum 747 { 748 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT0 = 0x00000901u, /* tr_group[10].output[0] */ 749 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT1 = 0x00000902u, /* tr_group[10].output[1] */ 750 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT2 = 0x00000903u, /* tr_group[10].output[2] */ 751 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT3 = 0x00000904u, /* tr_group[10].output[3] */ 752 TRIG_IN_MUX_9_TR_GROUP10_OUTPUT4 = 0x00000905u, /* tr_group[10].output[4] */ 753 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT0 = 0x00000906u, /* tr_group[11].output[0] */ 754 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT1 = 0x00000907u, /* tr_group[11].output[1] */ 755 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT2 = 0x00000908u, /* tr_group[11].output[2] */ 756 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT3 = 0x00000909u, /* tr_group[11].output[3] */ 757 TRIG_IN_MUX_9_TR_GROUP11_OUTPUT4 = 0x0000090Au, /* tr_group[11].output[4] */ 758 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT0 = 0x0000090Bu, /* tr_group[12].output[0] */ 759 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT1 = 0x0000090Cu, /* tr_group[12].output[1] */ 760 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT2 = 0x0000090Du, /* tr_group[12].output[2] */ 761 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT3 = 0x0000090Eu, /* tr_group[12].output[3] */ 762 TRIG_IN_MUX_9_TR_GROUP12_OUTPUT4 = 0x0000090Fu /* tr_group[12].output[4] */ 763 } en_trig_input_debugmain_t; 764 765 /* Trigger Input Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 766 typedef enum 767 { 768 TRIG_IN_MUX_10_PDMA0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */ 769 TRIG_IN_MUX_10_PDMA0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */ 770 TRIG_IN_MUX_10_PDMA0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */ 771 TRIG_IN_MUX_10_PDMA0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */ 772 TRIG_IN_MUX_10_PDMA0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */ 773 TRIG_IN_MUX_10_PDMA0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */ 774 TRIG_IN_MUX_10_PDMA0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */ 775 TRIG_IN_MUX_10_PDMA0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */ 776 TRIG_IN_MUX_10_PDMA0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */ 777 TRIG_IN_MUX_10_PDMA0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */ 778 TRIG_IN_MUX_10_PDMA0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */ 779 TRIG_IN_MUX_10_PDMA0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */ 780 TRIG_IN_MUX_10_PDMA0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */ 781 TRIG_IN_MUX_10_PDMA0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */ 782 TRIG_IN_MUX_10_PDMA0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */ 783 TRIG_IN_MUX_10_PDMA0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */ 784 TRIG_IN_MUX_10_PDMA0_TR_OUT16 = 0x00000A11u, /* cpuss.dw0_tr_out[16] */ 785 TRIG_IN_MUX_10_PDMA0_TR_OUT17 = 0x00000A12u, /* cpuss.dw0_tr_out[17] */ 786 TRIG_IN_MUX_10_PDMA0_TR_OUT18 = 0x00000A13u, /* cpuss.dw0_tr_out[18] */ 787 TRIG_IN_MUX_10_PDMA0_TR_OUT19 = 0x00000A14u, /* cpuss.dw0_tr_out[19] */ 788 TRIG_IN_MUX_10_PDMA0_TR_OUT20 = 0x00000A15u, /* cpuss.dw0_tr_out[20] */ 789 TRIG_IN_MUX_10_PDMA0_TR_OUT21 = 0x00000A16u, /* cpuss.dw0_tr_out[21] */ 790 TRIG_IN_MUX_10_PDMA0_TR_OUT22 = 0x00000A17u, /* cpuss.dw0_tr_out[22] */ 791 TRIG_IN_MUX_10_PDMA0_TR_OUT23 = 0x00000A18u, /* cpuss.dw0_tr_out[23] */ 792 TRIG_IN_MUX_10_PDMA0_TR_OUT24 = 0x00000A19u, /* cpuss.dw0_tr_out[24] */ 793 TRIG_IN_MUX_10_PDMA0_TR_OUT25 = 0x00000A1Au, /* cpuss.dw0_tr_out[25] */ 794 TRIG_IN_MUX_10_PDMA0_TR_OUT26 = 0x00000A1Bu, /* cpuss.dw0_tr_out[26] */ 795 TRIG_IN_MUX_10_PDMA0_TR_OUT27 = 0x00000A1Cu, /* cpuss.dw0_tr_out[27] */ 796 TRIG_IN_MUX_10_PDMA0_TR_OUT28 = 0x00000A1Du, /* cpuss.dw0_tr_out[28] */ 797 TRIG_IN_MUX_10_PDMA0_TR_OUT29 = 0x00000A1Eu, /* cpuss.dw0_tr_out[29] */ 798 TRIG_IN_MUX_10_PDMA0_TR_OUT30 = 0x00000A1Fu, /* cpuss.dw0_tr_out[30] */ 799 TRIG_IN_MUX_10_PDMA0_TR_OUT31 = 0x00000A20u, /* cpuss.dw0_tr_out[31] */ 800 TRIG_IN_MUX_10_PDMA0_TR_OUT32 = 0x00000A21u, /* cpuss.dw0_tr_out[32] */ 801 TRIG_IN_MUX_10_PDMA0_TR_OUT33 = 0x00000A22u, /* cpuss.dw0_tr_out[33] */ 802 TRIG_IN_MUX_10_PDMA0_TR_OUT34 = 0x00000A23u, /* cpuss.dw0_tr_out[34] */ 803 TRIG_IN_MUX_10_PDMA0_TR_OUT35 = 0x00000A24u, /* cpuss.dw0_tr_out[35] */ 804 TRIG_IN_MUX_10_PDMA0_TR_OUT36 = 0x00000A25u, /* cpuss.dw0_tr_out[36] */ 805 TRIG_IN_MUX_10_PDMA0_TR_OUT37 = 0x00000A26u, /* cpuss.dw0_tr_out[37] */ 806 TRIG_IN_MUX_10_PDMA0_TR_OUT38 = 0x00000A27u, /* cpuss.dw0_tr_out[38] */ 807 TRIG_IN_MUX_10_PDMA0_TR_OUT39 = 0x00000A28u, /* cpuss.dw0_tr_out[39] */ 808 TRIG_IN_MUX_10_PDMA0_TR_OUT40 = 0x00000A29u, /* cpuss.dw0_tr_out[40] */ 809 TRIG_IN_MUX_10_PDMA0_TR_OUT41 = 0x00000A2Au, /* cpuss.dw0_tr_out[41] */ 810 TRIG_IN_MUX_10_PDMA0_TR_OUT42 = 0x00000A2Bu, /* cpuss.dw0_tr_out[42] */ 811 TRIG_IN_MUX_10_PDMA0_TR_OUT43 = 0x00000A2Cu, /* cpuss.dw0_tr_out[43] */ 812 TRIG_IN_MUX_10_PDMA0_TR_OUT44 = 0x00000A2Du, /* cpuss.dw0_tr_out[44] */ 813 TRIG_IN_MUX_10_PDMA0_TR_OUT45 = 0x00000A2Eu, /* cpuss.dw0_tr_out[45] */ 814 TRIG_IN_MUX_10_PDMA0_TR_OUT46 = 0x00000A2Fu, /* cpuss.dw0_tr_out[46] */ 815 TRIG_IN_MUX_10_PDMA0_TR_OUT47 = 0x00000A30u, /* cpuss.dw0_tr_out[47] */ 816 TRIG_IN_MUX_10_PDMA0_TR_OUT48 = 0x00000A31u, /* cpuss.dw0_tr_out[48] */ 817 TRIG_IN_MUX_10_PDMA0_TR_OUT49 = 0x00000A32u, /* cpuss.dw0_tr_out[49] */ 818 TRIG_IN_MUX_10_PDMA0_TR_OUT50 = 0x00000A33u, /* cpuss.dw0_tr_out[50] */ 819 TRIG_IN_MUX_10_PDMA0_TR_OUT51 = 0x00000A34u, /* cpuss.dw0_tr_out[51] */ 820 TRIG_IN_MUX_10_PDMA0_TR_OUT52 = 0x00000A35u, /* cpuss.dw0_tr_out[52] */ 821 TRIG_IN_MUX_10_PDMA0_TR_OUT53 = 0x00000A36u, /* cpuss.dw0_tr_out[53] */ 822 TRIG_IN_MUX_10_PDMA0_TR_OUT54 = 0x00000A37u, /* cpuss.dw0_tr_out[54] */ 823 TRIG_IN_MUX_10_PDMA0_TR_OUT55 = 0x00000A38u, /* cpuss.dw0_tr_out[55] */ 824 TRIG_IN_MUX_10_PDMA0_TR_OUT56 = 0x00000A39u, /* cpuss.dw0_tr_out[56] */ 825 TRIG_IN_MUX_10_PDMA0_TR_OUT57 = 0x00000A3Au, /* cpuss.dw0_tr_out[57] */ 826 TRIG_IN_MUX_10_PDMA0_TR_OUT58 = 0x00000A3Bu, /* cpuss.dw0_tr_out[58] */ 827 TRIG_IN_MUX_10_PDMA0_TR_OUT59 = 0x00000A3Cu, /* cpuss.dw0_tr_out[59] */ 828 TRIG_IN_MUX_10_PDMA0_TR_OUT60 = 0x00000A3Du, /* cpuss.dw0_tr_out[60] */ 829 TRIG_IN_MUX_10_PDMA0_TR_OUT61 = 0x00000A3Eu, /* cpuss.dw0_tr_out[61] */ 830 TRIG_IN_MUX_10_PDMA0_TR_OUT62 = 0x00000A3Fu, /* cpuss.dw0_tr_out[62] */ 831 TRIG_IN_MUX_10_PDMA0_TR_OUT63 = 0x00000A40u, /* cpuss.dw0_tr_out[63] */ 832 TRIG_IN_MUX_10_PDMA0_TR_OUT64 = 0x00000A41u, /* cpuss.dw0_tr_out[64] */ 833 TRIG_IN_MUX_10_PDMA0_TR_OUT65 = 0x00000A42u, /* cpuss.dw0_tr_out[65] */ 834 TRIG_IN_MUX_10_PDMA0_TR_OUT66 = 0x00000A43u, /* cpuss.dw0_tr_out[66] */ 835 TRIG_IN_MUX_10_PDMA0_TR_OUT67 = 0x00000A44u, /* cpuss.dw0_tr_out[67] */ 836 TRIG_IN_MUX_10_PDMA0_TR_OUT68 = 0x00000A45u, /* cpuss.dw0_tr_out[68] */ 837 TRIG_IN_MUX_10_PDMA0_TR_OUT69 = 0x00000A46u, /* cpuss.dw0_tr_out[69] */ 838 TRIG_IN_MUX_10_PDMA0_TR_OUT70 = 0x00000A47u, /* cpuss.dw0_tr_out[70] */ 839 TRIG_IN_MUX_10_PDMA0_TR_OUT71 = 0x00000A48u, /* cpuss.dw0_tr_out[71] */ 840 TRIG_IN_MUX_10_PDMA0_TR_OUT72 = 0x00000A49u, /* cpuss.dw0_tr_out[72] */ 841 TRIG_IN_MUX_10_PDMA0_TR_OUT73 = 0x00000A4Au, /* cpuss.dw0_tr_out[73] */ 842 TRIG_IN_MUX_10_PDMA0_TR_OUT74 = 0x00000A4Bu, /* cpuss.dw0_tr_out[74] */ 843 TRIG_IN_MUX_10_PDMA0_TR_OUT75 = 0x00000A4Cu, /* cpuss.dw0_tr_out[75] */ 844 TRIG_IN_MUX_10_PDMA0_TR_OUT76 = 0x00000A4Du, /* cpuss.dw0_tr_out[76] */ 845 TRIG_IN_MUX_10_PDMA0_TR_OUT77 = 0x00000A4Eu, /* cpuss.dw0_tr_out[77] */ 846 TRIG_IN_MUX_10_PDMA0_TR_OUT78 = 0x00000A4Fu, /* cpuss.dw0_tr_out[78] */ 847 TRIG_IN_MUX_10_PDMA0_TR_OUT79 = 0x00000A50u, /* cpuss.dw0_tr_out[79] */ 848 TRIG_IN_MUX_10_PDMA0_TR_OUT80 = 0x00000A51u, /* cpuss.dw0_tr_out[80] */ 849 TRIG_IN_MUX_10_PDMA0_TR_OUT81 = 0x00000A52u, /* cpuss.dw0_tr_out[81] */ 850 TRIG_IN_MUX_10_PDMA0_TR_OUT82 = 0x00000A53u, /* cpuss.dw0_tr_out[82] */ 851 TRIG_IN_MUX_10_PDMA0_TR_OUT83 = 0x00000A54u, /* cpuss.dw0_tr_out[83] */ 852 TRIG_IN_MUX_10_PDMA0_TR_OUT84 = 0x00000A55u, /* cpuss.dw0_tr_out[84] */ 853 TRIG_IN_MUX_10_PDMA0_TR_OUT85 = 0x00000A56u, /* cpuss.dw0_tr_out[85] */ 854 TRIG_IN_MUX_10_PDMA0_TR_OUT86 = 0x00000A57u, /* cpuss.dw0_tr_out[86] */ 855 TRIG_IN_MUX_10_PDMA0_TR_OUT87 = 0x00000A58u, /* cpuss.dw0_tr_out[87] */ 856 TRIG_IN_MUX_10_PDMA0_TR_OUT88 = 0x00000A59u, /* cpuss.dw0_tr_out[88] */ 857 TRIG_IN_MUX_10_PDMA0_TR_OUT89 = 0x00000A5Au, /* cpuss.dw0_tr_out[89] */ 858 TRIG_IN_MUX_10_PDMA0_TR_OUT90 = 0x00000A5Bu, /* cpuss.dw0_tr_out[90] */ 859 TRIG_IN_MUX_10_PDMA0_TR_OUT91 = 0x00000A5Cu, /* cpuss.dw0_tr_out[91] */ 860 TRIG_IN_MUX_10_PDMA0_TR_OUT92 = 0x00000A5Du, /* cpuss.dw0_tr_out[92] */ 861 TRIG_IN_MUX_10_PDMA0_TR_OUT93 = 0x00000A5Eu, /* cpuss.dw0_tr_out[93] */ 862 TRIG_IN_MUX_10_PDMA0_TR_OUT94 = 0x00000A5Fu, /* cpuss.dw0_tr_out[94] */ 863 TRIG_IN_MUX_10_PDMA0_TR_OUT95 = 0x00000A60u, /* cpuss.dw0_tr_out[95] */ 864 TRIG_IN_MUX_10_PDMA0_TR_OUT96 = 0x00000A61u, /* cpuss.dw0_tr_out[96] */ 865 TRIG_IN_MUX_10_PDMA0_TR_OUT97 = 0x00000A62u, /* cpuss.dw0_tr_out[97] */ 866 TRIG_IN_MUX_10_PDMA0_TR_OUT98 = 0x00000A63u, /* cpuss.dw0_tr_out[98] */ 867 TRIG_IN_MUX_10_PDMA0_TR_OUT99 = 0x00000A64u, /* cpuss.dw0_tr_out[99] */ 868 TRIG_IN_MUX_10_SCB_TX_TR_OUT0 = 0x00000A65u, /* scb[0].tr_tx_req */ 869 TRIG_IN_MUX_10_SCB_TX_TR_OUT1 = 0x00000A66u, /* scb[1].tr_tx_req */ 870 TRIG_IN_MUX_10_SCB_TX_TR_OUT2 = 0x00000A67u, /* scb[2].tr_tx_req */ 871 TRIG_IN_MUX_10_SCB_TX_TR_OUT3 = 0x00000A68u, /* scb[3].tr_tx_req */ 872 TRIG_IN_MUX_10_SCB_TX_TR_OUT4 = 0x00000A69u, /* scb[4].tr_tx_req */ 873 TRIG_IN_MUX_10_SCB_TX_TR_OUT5 = 0x00000A6Au, /* scb[5].tr_tx_req */ 874 TRIG_IN_MUX_10_SCB_TX_TR_OUT6 = 0x00000A6Bu, /* scb[6].tr_tx_req */ 875 TRIG_IN_MUX_10_SCB_TX_TR_OUT7 = 0x00000A6Cu, /* scb[7].tr_tx_req */ 876 TRIG_IN_MUX_10_SCB_TX_TR_OUT8 = 0x00000A6Du, /* scb[8].tr_tx_req */ 877 TRIG_IN_MUX_10_SCB_TX_TR_OUT9 = 0x00000A6Eu, /* scb[9].tr_tx_req */ 878 TRIG_IN_MUX_10_SCB_TX_TR_OUT10 = 0x00000A6Fu, /* scb[10].tr_tx_req */ 879 TRIG_IN_MUX_10_SCB_RX_TR_OUT0 = 0x00000A70u, /* scb[0].tr_rx_req */ 880 TRIG_IN_MUX_10_SCB_RX_TR_OUT1 = 0x00000A71u, /* scb[1].tr_rx_req */ 881 TRIG_IN_MUX_10_SCB_RX_TR_OUT2 = 0x00000A72u, /* scb[2].tr_rx_req */ 882 TRIG_IN_MUX_10_SCB_RX_TR_OUT3 = 0x00000A73u, /* scb[3].tr_rx_req */ 883 TRIG_IN_MUX_10_SCB_RX_TR_OUT4 = 0x00000A74u, /* scb[4].tr_rx_req */ 884 TRIG_IN_MUX_10_SCB_RX_TR_OUT5 = 0x00000A75u, /* scb[5].tr_rx_req */ 885 TRIG_IN_MUX_10_SCB_RX_TR_OUT6 = 0x00000A76u, /* scb[6].tr_rx_req */ 886 TRIG_IN_MUX_10_SCB_RX_TR_OUT7 = 0x00000A77u, /* scb[7].tr_rx_req */ 887 TRIG_IN_MUX_10_SCB_RX_TR_OUT8 = 0x00000A78u, /* scb[8].tr_rx_req */ 888 TRIG_IN_MUX_10_SCB_RX_TR_OUT9 = 0x00000A79u, /* scb[9].tr_rx_req */ 889 TRIG_IN_MUX_10_SCB_RX_TR_OUT10 = 0x00000A7Au, /* scb[10].tr_rx_req */ 890 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT0 = 0x00000A7Bu, /* scb[0].tr_i2c_scl_filtered */ 891 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT1 = 0x00000A7Cu, /* scb[1].tr_i2c_scl_filtered */ 892 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT2 = 0x00000A7Du, /* scb[2].tr_i2c_scl_filtered */ 893 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT3 = 0x00000A7Eu, /* scb[3].tr_i2c_scl_filtered */ 894 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT4 = 0x00000A7Fu, /* scb[4].tr_i2c_scl_filtered */ 895 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT5 = 0x00000A80u, /* scb[5].tr_i2c_scl_filtered */ 896 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT6 = 0x00000A81u, /* scb[6].tr_i2c_scl_filtered */ 897 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT7 = 0x00000A82u, /* scb[7].tr_i2c_scl_filtered */ 898 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT8 = 0x00000A83u, /* scb[8].tr_i2c_scl_filtered */ 899 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT9 = 0x00000A84u, /* scb[9].tr_i2c_scl_filtered */ 900 TRIG_IN_MUX_10_SCB_I2C_SCL_TR_OUT10 = 0x00000A85u, /* scb[10].tr_i2c_scl_filtered */ 901 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT0 = 0x00000A86u, /* canfd[0].tr_dbg_dma_req[0] */ 902 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT1 = 0x00000A87u, /* canfd[0].tr_dbg_dma_req[1] */ 903 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT2 = 0x00000A88u, /* canfd[0].tr_dbg_dma_req[2] */ 904 TRIG_IN_MUX_10_CAN0_DBG_TR_OUT3 = 0x00000A89u, /* canfd[0].tr_dbg_dma_req[3] */ 905 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT0 = 0x00000A8Au, /* canfd[0].tr_fifo0[0] */ 906 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT1 = 0x00000A8Bu, /* canfd[0].tr_fifo0[1] */ 907 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT2 = 0x00000A8Cu, /* canfd[0].tr_fifo0[2] */ 908 TRIG_IN_MUX_10_CAN0_FIFO0_TR_OUT3 = 0x00000A8Du, /* canfd[0].tr_fifo0[3] */ 909 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT0 = 0x00000A8Eu, /* canfd[0].tr_fifo1[0] */ 910 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT1 = 0x00000A8Fu, /* canfd[0].tr_fifo1[1] */ 911 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT2 = 0x00000A90u, /* canfd[0].tr_fifo1[2] */ 912 TRIG_IN_MUX_10_CAN0_FIFO1_TR_OUT3 = 0x00000A91u, /* canfd[0].tr_fifo1[3] */ 913 TRIG_IN_MUX_10_CAN0_TT_TR_OUT0 = 0x00000A92u, /* canfd[0].tr_tmp_rtp_out[0] */ 914 TRIG_IN_MUX_10_CAN0_TT_TR_OUT1 = 0x00000A93u, /* canfd[0].tr_tmp_rtp_out[1] */ 915 TRIG_IN_MUX_10_CAN0_TT_TR_OUT2 = 0x00000A94u, /* canfd[0].tr_tmp_rtp_out[2] */ 916 TRIG_IN_MUX_10_CAN0_TT_TR_OUT3 = 0x00000A95u, /* canfd[0].tr_tmp_rtp_out[3] */ 917 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT0 = 0x00000A96u, /* canfd[1].tr_dbg_dma_req[0] */ 918 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT1 = 0x00000A97u, /* canfd[1].tr_dbg_dma_req[1] */ 919 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT2 = 0x00000A98u, /* canfd[1].tr_dbg_dma_req[2] */ 920 TRIG_IN_MUX_10_CAN1_DBG_TR_OUT3 = 0x00000A99u, /* canfd[1].tr_dbg_dma_req[3] */ 921 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT0 = 0x00000A9Au, /* canfd[1].tr_fifo0[0] */ 922 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT1 = 0x00000A9Bu, /* canfd[1].tr_fifo0[1] */ 923 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT2 = 0x00000A9Cu, /* canfd[1].tr_fifo0[2] */ 924 TRIG_IN_MUX_10_CAN1_FIFO0_TR_OUT3 = 0x00000A9Du, /* canfd[1].tr_fifo0[3] */ 925 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT0 = 0x00000A9Eu, /* canfd[1].tr_fifo1[0] */ 926 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT1 = 0x00000A9Fu, /* canfd[1].tr_fifo1[1] */ 927 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT2 = 0x00000AA0u, /* canfd[1].tr_fifo1[2] */ 928 TRIG_IN_MUX_10_CAN1_FIFO1_TR_OUT3 = 0x00000AA1u, /* canfd[1].tr_fifo1[3] */ 929 TRIG_IN_MUX_10_CAN1_TT_TR_OUT0 = 0x00000AA2u, /* canfd[1].tr_tmp_rtp_out[0] */ 930 TRIG_IN_MUX_10_CAN1_TT_TR_OUT1 = 0x00000AA3u, /* canfd[1].tr_tmp_rtp_out[1] */ 931 TRIG_IN_MUX_10_CAN1_TT_TR_OUT2 = 0x00000AA4u, /* canfd[1].tr_tmp_rtp_out[2] */ 932 TRIG_IN_MUX_10_CAN1_TT_TR_OUT3 = 0x00000AA5u, /* canfd[1].tr_tmp_rtp_out[3] */ 933 TRIG_IN_MUX_10_CTI_TR_OUT0 = 0x00000AA6u, /* cpuss.cti_tr_out[0] */ 934 TRIG_IN_MUX_10_CTI_TR_OUT1 = 0x00000AA7u, /* cpuss.cti_tr_out[1] */ 935 TRIG_IN_MUX_10_FAULT_TR_OU0 = 0x00000AA8u, /* cpuss.tr_fault[0] */ 936 TRIG_IN_MUX_10_FAULT_TR_OU1 = 0x00000AA9u, /* cpuss.tr_fault[1] */ 937 TRIG_IN_MUX_10_FAULT_TR_OU2 = 0x00000AAAu, /* cpuss.tr_fault[2] */ 938 TRIG_IN_MUX_10_FAULT_TR_OU3 = 0x00000AABu, /* cpuss.tr_fault[3] */ 939 TRIG_IN_MUX_10_EVTGEN_TR_OUT0 = 0x00000AACu, /* evtgen[0].tr_out[0] */ 940 TRIG_IN_MUX_10_EVTGEN_TR_OUT1 = 0x00000AADu, /* evtgen[0].tr_out[1] */ 941 TRIG_IN_MUX_10_EVTGEN_TR_OUT2 = 0x00000AAEu, /* evtgen[0].tr_out[2] */ 942 TRIG_IN_MUX_10_EVTGEN_TR_OUT3 = 0x00000AAFu, /* evtgen[0].tr_out[3] */ 943 TRIG_IN_MUX_10_EVTGEN_TR_OUT4 = 0x00000AB0u, /* evtgen[0].tr_out[4] */ 944 TRIG_IN_MUX_10_EVTGEN_TR_OUT5 = 0x00000AB1u, /* evtgen[0].tr_out[5] */ 945 TRIG_IN_MUX_10_EVTGEN_TR_OUT6 = 0x00000AB2u, /* evtgen[0].tr_out[6] */ 946 TRIG_IN_MUX_10_EVTGEN_TR_OUT7 = 0x00000AB3u, /* evtgen[0].tr_out[7] */ 947 TRIG_IN_MUX_10_EVTGEN_TR_OUT8 = 0x00000AB4u, /* evtgen[0].tr_out[8] */ 948 TRIG_IN_MUX_10_EVTGEN_TR_OUT9 = 0x00000AB5u, /* evtgen[0].tr_out[9] */ 949 TRIG_IN_MUX_10_EVTGEN_TR_OUT10 = 0x00000AB6u, /* evtgen[0].tr_out[10] */ 950 TRIG_IN_MUX_10_EVTGEN_TR_OUT11 = 0x00000AB7u, /* evtgen[0].tr_out[11] */ 951 TRIG_IN_MUX_10_EVTGEN_TR_OUT12 = 0x00000AB8u, /* evtgen[0].tr_out[12] */ 952 TRIG_IN_MUX_10_EVTGEN_TR_OUT13 = 0x00000AB9u, /* evtgen[0].tr_out[13] */ 953 TRIG_IN_MUX_10_EVTGEN_TR_OUT14 = 0x00000ABAu, /* evtgen[0].tr_out[14] */ 954 TRIG_IN_MUX_10_EVTGEN_TR_OUT15 = 0x00000ABBu /* evtgen[0].tr_out[15] */ 955 } en_trig_input_debugreduction1_t; 956 957 /* Trigger Input Group 11 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 958 typedef enum 959 { 960 TRIG_IN_MUX_11_TCPWM_32_TR_OUT00 = 0x00000B01u, /* tcpwm[0].tr_out0[512] */ 961 TRIG_IN_MUX_11_TCPWM_32_TR_OUT01 = 0x00000B02u, /* tcpwm[0].tr_out0[513] */ 962 TRIG_IN_MUX_11_TCPWM_32_TR_OUT02 = 0x00000B03u, /* tcpwm[0].tr_out0[514] */ 963 TRIG_IN_MUX_11_TCPWM_32_TR_OUT03 = 0x00000B04u, /* tcpwm[0].tr_out0[515] */ 964 TRIG_IN_MUX_11_TCPWM_32_TR_OUT04 = 0x00000B05u, /* tcpwm[0].tr_out0[516] */ 965 TRIG_IN_MUX_11_TCPWM_32_TR_OUT05 = 0x00000B06u, /* tcpwm[0].tr_out0[517] */ 966 TRIG_IN_MUX_11_TCPWM_32_TR_OUT06 = 0x00000B07u, /* tcpwm[0].tr_out0[518] */ 967 TRIG_IN_MUX_11_TCPWM_32_TR_OUT07 = 0x00000B08u, /* tcpwm[0].tr_out0[519] */ 968 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT00 = 0x00000B09u, /* tcpwm[0].tr_out0[256] */ 969 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT01 = 0x00000B0Au, /* tcpwm[0].tr_out0[257] */ 970 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT02 = 0x00000B0Bu, /* tcpwm[0].tr_out0[258] */ 971 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT03 = 0x00000B0Cu, /* tcpwm[0].tr_out0[259] */ 972 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT04 = 0x00000B0Du, /* tcpwm[0].tr_out0[260] */ 973 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT05 = 0x00000B0Eu, /* tcpwm[0].tr_out0[261] */ 974 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT06 = 0x00000B0Fu, /* tcpwm[0].tr_out0[262] */ 975 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT07 = 0x00000B10u, /* tcpwm[0].tr_out0[263] */ 976 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT08 = 0x00000B11u, /* tcpwm[0].tr_out0[264] */ 977 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT09 = 0x00000B12u, /* tcpwm[0].tr_out0[265] */ 978 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT010 = 0x00000B13u, /* tcpwm[0].tr_out0[266] */ 979 TRIG_IN_MUX_11_TCPWM_16M_TR_OUT011 = 0x00000B14u, /* tcpwm[0].tr_out0[267] */ 980 TRIG_IN_MUX_11_TCPWM_16_TR_OUT00 = 0x00000B15u, /* tcpwm[0].tr_out0[0] */ 981 TRIG_IN_MUX_11_TCPWM_16_TR_OUT01 = 0x00000B16u, /* tcpwm[0].tr_out0[1] */ 982 TRIG_IN_MUX_11_TCPWM_16_TR_OUT02 = 0x00000B17u, /* tcpwm[0].tr_out0[2] */ 983 TRIG_IN_MUX_11_TCPWM_16_TR_OUT03 = 0x00000B18u, /* tcpwm[0].tr_out0[3] */ 984 TRIG_IN_MUX_11_TCPWM_16_TR_OUT04 = 0x00000B19u, /* tcpwm[0].tr_out0[4] */ 985 TRIG_IN_MUX_11_TCPWM_16_TR_OUT05 = 0x00000B1Au, /* tcpwm[0].tr_out0[5] */ 986 TRIG_IN_MUX_11_TCPWM_16_TR_OUT06 = 0x00000B1Bu, /* tcpwm[0].tr_out0[6] */ 987 TRIG_IN_MUX_11_TCPWM_16_TR_OUT07 = 0x00000B1Cu, /* tcpwm[0].tr_out0[7] */ 988 TRIG_IN_MUX_11_TCPWM_16_TR_OUT08 = 0x00000B1Du, /* tcpwm[0].tr_out0[8] */ 989 TRIG_IN_MUX_11_TCPWM_16_TR_OUT09 = 0x00000B1Eu, /* tcpwm[0].tr_out0[9] */ 990 TRIG_IN_MUX_11_TCPWM_16_TR_OUT010 = 0x00000B1Fu, /* tcpwm[0].tr_out0[10] */ 991 TRIG_IN_MUX_11_TCPWM_16_TR_OUT011 = 0x00000B20u, /* tcpwm[0].tr_out0[11] */ 992 TRIG_IN_MUX_11_TCPWM_16_TR_OUT012 = 0x00000B21u, /* tcpwm[0].tr_out0[12] */ 993 TRIG_IN_MUX_11_TCPWM_16_TR_OUT013 = 0x00000B22u, /* tcpwm[0].tr_out0[13] */ 994 TRIG_IN_MUX_11_TCPWM_16_TR_OUT014 = 0x00000B23u, /* tcpwm[0].tr_out0[14] */ 995 TRIG_IN_MUX_11_TCPWM_16_TR_OUT015 = 0x00000B24u, /* tcpwm[0].tr_out0[15] */ 996 TRIG_IN_MUX_11_TCPWM_16_TR_OUT016 = 0x00000B25u, /* tcpwm[0].tr_out0[16] */ 997 TRIG_IN_MUX_11_TCPWM_16_TR_OUT017 = 0x00000B26u, /* tcpwm[0].tr_out0[17] */ 998 TRIG_IN_MUX_11_TCPWM_16_TR_OUT018 = 0x00000B27u, /* tcpwm[0].tr_out0[18] */ 999 TRIG_IN_MUX_11_TCPWM_16_TR_OUT019 = 0x00000B28u, /* tcpwm[0].tr_out0[19] */ 1000 TRIG_IN_MUX_11_TCPWM_16_TR_OUT020 = 0x00000B29u, /* tcpwm[0].tr_out0[20] */ 1001 TRIG_IN_MUX_11_TCPWM_16_TR_OUT021 = 0x00000B2Au, /* tcpwm[0].tr_out0[21] */ 1002 TRIG_IN_MUX_11_TCPWM_16_TR_OUT022 = 0x00000B2Bu, /* tcpwm[0].tr_out0[22] */ 1003 TRIG_IN_MUX_11_TCPWM_16_TR_OUT023 = 0x00000B2Cu, /* tcpwm[0].tr_out0[23] */ 1004 TRIG_IN_MUX_11_TCPWM_16_TR_OUT024 = 0x00000B2Du, /* tcpwm[0].tr_out0[24] */ 1005 TRIG_IN_MUX_11_TCPWM_16_TR_OUT025 = 0x00000B2Eu, /* tcpwm[0].tr_out0[25] */ 1006 TRIG_IN_MUX_11_TCPWM_16_TR_OUT026 = 0x00000B2Fu, /* tcpwm[0].tr_out0[26] */ 1007 TRIG_IN_MUX_11_TCPWM_16_TR_OUT027 = 0x00000B30u, /* tcpwm[0].tr_out0[27] */ 1008 TRIG_IN_MUX_11_TCPWM_16_TR_OUT028 = 0x00000B31u, /* tcpwm[0].tr_out0[28] */ 1009 TRIG_IN_MUX_11_TCPWM_16_TR_OUT029 = 0x00000B32u, /* tcpwm[0].tr_out0[29] */ 1010 TRIG_IN_MUX_11_TCPWM_16_TR_OUT030 = 0x00000B33u, /* tcpwm[0].tr_out0[30] */ 1011 TRIG_IN_MUX_11_TCPWM_16_TR_OUT031 = 0x00000B34u, /* tcpwm[0].tr_out0[31] */ 1012 TRIG_IN_MUX_11_TCPWM_16_TR_OUT032 = 0x00000B35u, /* tcpwm[0].tr_out0[32] */ 1013 TRIG_IN_MUX_11_TCPWM_16_TR_OUT033 = 0x00000B36u, /* tcpwm[0].tr_out0[33] */ 1014 TRIG_IN_MUX_11_TCPWM_16_TR_OUT034 = 0x00000B37u, /* tcpwm[0].tr_out0[34] */ 1015 TRIG_IN_MUX_11_TCPWM_16_TR_OUT035 = 0x00000B38u, /* tcpwm[0].tr_out0[35] */ 1016 TRIG_IN_MUX_11_TCPWM_16_TR_OUT036 = 0x00000B39u, /* tcpwm[0].tr_out0[36] */ 1017 TRIG_IN_MUX_11_TCPWM_16_TR_OUT037 = 0x00000B3Au, /* tcpwm[0].tr_out0[37] */ 1018 TRIG_IN_MUX_11_TCPWM_16_TR_OUT038 = 0x00000B3Bu, /* tcpwm[0].tr_out0[38] */ 1019 TRIG_IN_MUX_11_TCPWM_16_TR_OUT039 = 0x00000B3Cu, /* tcpwm[0].tr_out0[39] */ 1020 TRIG_IN_MUX_11_TCPWM_16_TR_OUT040 = 0x00000B3Du, /* tcpwm[0].tr_out0[40] */ 1021 TRIG_IN_MUX_11_TCPWM_16_TR_OUT041 = 0x00000B3Eu, /* tcpwm[0].tr_out0[41] */ 1022 TRIG_IN_MUX_11_TCPWM_16_TR_OUT042 = 0x00000B3Fu, /* tcpwm[0].tr_out0[42] */ 1023 TRIG_IN_MUX_11_TCPWM_16_TR_OUT043 = 0x00000B40u, /* tcpwm[0].tr_out0[43] */ 1024 TRIG_IN_MUX_11_TCPWM_16_TR_OUT044 = 0x00000B41u, /* tcpwm[0].tr_out0[44] */ 1025 TRIG_IN_MUX_11_TCPWM_16_TR_OUT045 = 0x00000B42u, /* tcpwm[0].tr_out0[45] */ 1026 TRIG_IN_MUX_11_TCPWM_16_TR_OUT046 = 0x00000B43u, /* tcpwm[0].tr_out0[46] */ 1027 TRIG_IN_MUX_11_TCPWM_16_TR_OUT047 = 0x00000B44u, /* tcpwm[0].tr_out0[47] */ 1028 TRIG_IN_MUX_11_TCPWM_16_TR_OUT048 = 0x00000B45u, /* tcpwm[0].tr_out0[48] */ 1029 TRIG_IN_MUX_11_TCPWM_16_TR_OUT049 = 0x00000B46u, /* tcpwm[0].tr_out0[49] */ 1030 TRIG_IN_MUX_11_TCPWM_16_TR_OUT050 = 0x00000B47u, /* tcpwm[0].tr_out0[50] */ 1031 TRIG_IN_MUX_11_TCPWM_16_TR_OUT051 = 0x00000B48u, /* tcpwm[0].tr_out0[51] */ 1032 TRIG_IN_MUX_11_TCPWM_16_TR_OUT052 = 0x00000B49u, /* tcpwm[0].tr_out0[52] */ 1033 TRIG_IN_MUX_11_TCPWM_16_TR_OUT053 = 0x00000B4Au, /* tcpwm[0].tr_out0[53] */ 1034 TRIG_IN_MUX_11_TCPWM_16_TR_OUT054 = 0x00000B4Bu, /* tcpwm[0].tr_out0[54] */ 1035 TRIG_IN_MUX_11_TCPWM_16_TR_OUT055 = 0x00000B4Cu, /* tcpwm[0].tr_out0[55] */ 1036 TRIG_IN_MUX_11_TCPWM_16_TR_OUT056 = 0x00000B4Du, /* tcpwm[0].tr_out0[56] */ 1037 TRIG_IN_MUX_11_TCPWM_16_TR_OUT057 = 0x00000B4Eu, /* tcpwm[0].tr_out0[57] */ 1038 TRIG_IN_MUX_11_TCPWM_16_TR_OUT058 = 0x00000B4Fu, /* tcpwm[0].tr_out0[58] */ 1039 TRIG_IN_MUX_11_TCPWM_16_TR_OUT059 = 0x00000B50u, /* tcpwm[0].tr_out0[59] */ 1040 TRIG_IN_MUX_11_TCPWM_16_TR_OUT060 = 0x00000B51u, /* tcpwm[0].tr_out0[60] */ 1041 TRIG_IN_MUX_11_TCPWM_16_TR_OUT061 = 0x00000B52u, /* tcpwm[0].tr_out0[61] */ 1042 TRIG_IN_MUX_11_TCPWM_16_TR_OUT062 = 0x00000B53u, /* tcpwm[0].tr_out0[62] */ 1043 TRIG_IN_MUX_11_SMIF_TX_TR_OUT = 0x00000B54u, /* smif[0].tr_tx_req */ 1044 TRIG_IN_MUX_11_SMIF_RX_TR_OUT = 0x00000B55u, /* smif[0].tr_rx_req */ 1045 TRIG_IN_MUX_11_I2S0_TX_TR_OUT = 0x00000B56u, /* audioss[0].tr_i2s_tx_req */ 1046 TRIG_IN_MUX_11_I2S0_RX_TR_OUT = 0x00000B57u, /* audioss[0].tr_i2s_rx_req */ 1047 TRIG_IN_MUX_11_I2S1_TX_TR_OUT = 0x00000B58u, /* audioss[1].tr_i2s_tx_req */ 1048 TRIG_IN_MUX_11_I2S1_RX_TR_OUT = 0x00000B59u, /* audioss[1].tr_i2s_rx_req */ 1049 TRIG_IN_MUX_11_I2S2_TX_TR_OUT = 0x00000B5Au, /* audioss[2].tr_i2s_tx_req */ 1050 TRIG_IN_MUX_11_I2S2_RX_TR_OUT = 0x00000B5Bu, /* audioss[2].tr_i2s_rx_req */ 1051 TRIG_IN_MUX_11_HSIOM_IO_INPUT0 = 0x00000B5Cu, /* peri.tr_io_input[0] */ 1052 TRIG_IN_MUX_11_HSIOM_IO_INPUT1 = 0x00000B5Du, /* peri.tr_io_input[1] */ 1053 TRIG_IN_MUX_11_HSIOM_IO_INPUT2 = 0x00000B5Eu, /* peri.tr_io_input[2] */ 1054 TRIG_IN_MUX_11_HSIOM_IO_INPUT3 = 0x00000B5Fu, /* peri.tr_io_input[3] */ 1055 TRIG_IN_MUX_11_HSIOM_IO_INPUT4 = 0x00000B60u, /* peri.tr_io_input[4] */ 1056 TRIG_IN_MUX_11_HSIOM_IO_INPUT5 = 0x00000B61u, /* peri.tr_io_input[5] */ 1057 TRIG_IN_MUX_11_HSIOM_IO_INPUT6 = 0x00000B62u, /* peri.tr_io_input[6] */ 1058 TRIG_IN_MUX_11_HSIOM_IO_INPUT7 = 0x00000B63u, /* peri.tr_io_input[7] */ 1059 TRIG_IN_MUX_11_HSIOM_IO_INPUT8 = 0x00000B64u, /* peri.tr_io_input[8] */ 1060 TRIG_IN_MUX_11_HSIOM_IO_INPUT9 = 0x00000B65u, /* peri.tr_io_input[9] */ 1061 TRIG_IN_MUX_11_HSIOM_IO_INPUT10 = 0x00000B66u, /* peri.tr_io_input[10] */ 1062 TRIG_IN_MUX_11_HSIOM_IO_INPUT11 = 0x00000B67u, /* peri.tr_io_input[11] */ 1063 TRIG_IN_MUX_11_HSIOM_IO_INPUT12 = 0x00000B68u, /* peri.tr_io_input[12] */ 1064 TRIG_IN_MUX_11_HSIOM_IO_INPUT13 = 0x00000B69u, /* peri.tr_io_input[13] */ 1065 TRIG_IN_MUX_11_HSIOM_IO_INPUT14 = 0x00000B6Au, /* peri.tr_io_input[14] */ 1066 TRIG_IN_MUX_11_HSIOM_IO_INPUT15 = 0x00000B6Bu, /* peri.tr_io_input[15] */ 1067 TRIG_IN_MUX_11_HSIOM_IO_INPUT16 = 0x00000B6Cu, /* peri.tr_io_input[16] */ 1068 TRIG_IN_MUX_11_HSIOM_IO_INPUT17 = 0x00000B6Du, /* peri.tr_io_input[17] */ 1069 TRIG_IN_MUX_11_HSIOM_IO_INPUT18 = 0x00000B6Eu, /* peri.tr_io_input[18] */ 1070 TRIG_IN_MUX_11_HSIOM_IO_INPUT19 = 0x00000B6Fu, /* peri.tr_io_input[19] */ 1071 TRIG_IN_MUX_11_HSIOM_IO_INPUT20 = 0x00000B70u, /* peri.tr_io_input[20] */ 1072 TRIG_IN_MUX_11_HSIOM_IO_INPUT21 = 0x00000B71u, /* peri.tr_io_input[21] */ 1073 TRIG_IN_MUX_11_HSIOM_IO_INPUT22 = 0x00000B72u, /* peri.tr_io_input[22] */ 1074 TRIG_IN_MUX_11_HSIOM_IO_INPUT23 = 0x00000B73u, /* peri.tr_io_input[23] */ 1075 TRIG_IN_MUX_11_HSIOM_IO_INPUT24 = 0x00000B74u, /* peri.tr_io_input[24] */ 1076 TRIG_IN_MUX_11_HSIOM_IO_INPUT25 = 0x00000B75u, /* peri.tr_io_input[25] */ 1077 TRIG_IN_MUX_11_HSIOM_IO_INPUT26 = 0x00000B76u, /* peri.tr_io_input[26] */ 1078 TRIG_IN_MUX_11_HSIOM_IO_INPUT27 = 0x00000B77u, /* peri.tr_io_input[27] */ 1079 TRIG_IN_MUX_11_HSIOM_IO_INPUT28 = 0x00000B78u, /* peri.tr_io_input[28] */ 1080 TRIG_IN_MUX_11_HSIOM_IO_INPUT29 = 0x00000B79u, /* peri.tr_io_input[29] */ 1081 TRIG_IN_MUX_11_HSIOM_IO_INPUT30 = 0x00000B7Au, /* peri.tr_io_input[30] */ 1082 TRIG_IN_MUX_11_HSIOM_IO_INPUT31 = 0x00000B7Bu /* peri.tr_io_input[31] */ 1083 } en_trig_input_debugreduction2_t; 1084 1085 /* Trigger Input Group 12 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1086 typedef enum 1087 { 1088 TRIG_IN_MUX_12_PDMA1_TR_OUT0 = 0x00000C01u, /* cpuss.dw1_tr_out[0] */ 1089 TRIG_IN_MUX_12_PDMA1_TR_OUT1 = 0x00000C02u, /* cpuss.dw1_tr_out[1] */ 1090 TRIG_IN_MUX_12_PDMA1_TR_OUT2 = 0x00000C03u, /* cpuss.dw1_tr_out[2] */ 1091 TRIG_IN_MUX_12_PDMA1_TR_OUT3 = 0x00000C04u, /* cpuss.dw1_tr_out[3] */ 1092 TRIG_IN_MUX_12_PDMA1_TR_OUT4 = 0x00000C05u, /* cpuss.dw1_tr_out[4] */ 1093 TRIG_IN_MUX_12_PDMA1_TR_OUT5 = 0x00000C06u, /* cpuss.dw1_tr_out[5] */ 1094 TRIG_IN_MUX_12_PDMA1_TR_OUT6 = 0x00000C07u, /* cpuss.dw1_tr_out[6] */ 1095 TRIG_IN_MUX_12_PDMA1_TR_OUT7 = 0x00000C08u, /* cpuss.dw1_tr_out[7] */ 1096 TRIG_IN_MUX_12_PDMA1_TR_OUT8 = 0x00000C09u, /* cpuss.dw1_tr_out[8] */ 1097 TRIG_IN_MUX_12_PDMA1_TR_OUT9 = 0x00000C0Au, /* cpuss.dw1_tr_out[9] */ 1098 TRIG_IN_MUX_12_PDMA1_TR_OUT10 = 0x00000C0Bu, /* cpuss.dw1_tr_out[10] */ 1099 TRIG_IN_MUX_12_PDMA1_TR_OUT11 = 0x00000C0Cu, /* cpuss.dw1_tr_out[11] */ 1100 TRIG_IN_MUX_12_PDMA1_TR_OUT12 = 0x00000C0Du, /* cpuss.dw1_tr_out[12] */ 1101 TRIG_IN_MUX_12_PDMA1_TR_OUT13 = 0x00000C0Eu, /* cpuss.dw1_tr_out[13] */ 1102 TRIG_IN_MUX_12_PDMA1_TR_OUT14 = 0x00000C0Fu, /* cpuss.dw1_tr_out[14] */ 1103 TRIG_IN_MUX_12_PDMA1_TR_OUT15 = 0x00000C10u, /* cpuss.dw1_tr_out[15] */ 1104 TRIG_IN_MUX_12_PDMA1_TR_OUT16 = 0x00000C11u, /* cpuss.dw1_tr_out[16] */ 1105 TRIG_IN_MUX_12_PDMA1_TR_OUT17 = 0x00000C12u, /* cpuss.dw1_tr_out[17] */ 1106 TRIG_IN_MUX_12_PDMA1_TR_OUT18 = 0x00000C13u, /* cpuss.dw1_tr_out[18] */ 1107 TRIG_IN_MUX_12_PDMA1_TR_OUT19 = 0x00000C14u, /* cpuss.dw1_tr_out[19] */ 1108 TRIG_IN_MUX_12_PDMA1_TR_OUT20 = 0x00000C15u, /* cpuss.dw1_tr_out[20] */ 1109 TRIG_IN_MUX_12_PDMA1_TR_OUT21 = 0x00000C16u, /* cpuss.dw1_tr_out[21] */ 1110 TRIG_IN_MUX_12_PDMA1_TR_OUT22 = 0x00000C17u, /* cpuss.dw1_tr_out[22] */ 1111 TRIG_IN_MUX_12_PDMA1_TR_OUT23 = 0x00000C18u, /* cpuss.dw1_tr_out[23] */ 1112 TRIG_IN_MUX_12_PDMA1_TR_OUT24 = 0x00000C19u, /* cpuss.dw1_tr_out[24] */ 1113 TRIG_IN_MUX_12_PDMA1_TR_OUT25 = 0x00000C1Au, /* cpuss.dw1_tr_out[25] */ 1114 TRIG_IN_MUX_12_PDMA1_TR_OUT26 = 0x00000C1Bu, /* cpuss.dw1_tr_out[26] */ 1115 TRIG_IN_MUX_12_PDMA1_TR_OUT27 = 0x00000C1Cu, /* cpuss.dw1_tr_out[27] */ 1116 TRIG_IN_MUX_12_PDMA1_TR_OUT28 = 0x00000C1Du, /* cpuss.dw1_tr_out[28] */ 1117 TRIG_IN_MUX_12_PDMA1_TR_OUT29 = 0x00000C1Eu, /* cpuss.dw1_tr_out[29] */ 1118 TRIG_IN_MUX_12_PDMA1_TR_OUT30 = 0x00000C1Fu, /* cpuss.dw1_tr_out[30] */ 1119 TRIG_IN_MUX_12_PDMA1_TR_OUT31 = 0x00000C20u, /* cpuss.dw1_tr_out[31] */ 1120 TRIG_IN_MUX_12_PDMA1_TR_OUT32 = 0x00000C21u, /* cpuss.dw1_tr_out[32] */ 1121 TRIG_IN_MUX_12_PDMA1_TR_OUT33 = 0x00000C22u, /* cpuss.dw1_tr_out[33] */ 1122 TRIG_IN_MUX_12_PDMA1_TR_OUT34 = 0x00000C23u, /* cpuss.dw1_tr_out[34] */ 1123 TRIG_IN_MUX_12_PDMA1_TR_OUT35 = 0x00000C24u, /* cpuss.dw1_tr_out[35] */ 1124 TRIG_IN_MUX_12_PDMA1_TR_OUT36 = 0x00000C25u, /* cpuss.dw1_tr_out[36] */ 1125 TRIG_IN_MUX_12_PDMA1_TR_OUT37 = 0x00000C26u, /* cpuss.dw1_tr_out[37] */ 1126 TRIG_IN_MUX_12_PDMA1_TR_OUT38 = 0x00000C27u, /* cpuss.dw1_tr_out[38] */ 1127 TRIG_IN_MUX_12_PDMA1_TR_OUT39 = 0x00000C28u, /* cpuss.dw1_tr_out[39] */ 1128 TRIG_IN_MUX_12_PDMA1_TR_OUT40 = 0x00000C29u, /* cpuss.dw1_tr_out[40] */ 1129 TRIG_IN_MUX_12_PDMA1_TR_OUT41 = 0x00000C2Au, /* cpuss.dw1_tr_out[41] */ 1130 TRIG_IN_MUX_12_PDMA1_TR_OUT42 = 0x00000C2Bu, /* cpuss.dw1_tr_out[42] */ 1131 TRIG_IN_MUX_12_PDMA1_TR_OUT43 = 0x00000C2Cu, /* cpuss.dw1_tr_out[43] */ 1132 TRIG_IN_MUX_12_PDMA1_TR_OUT44 = 0x00000C2Du, /* cpuss.dw1_tr_out[44] */ 1133 TRIG_IN_MUX_12_PDMA1_TR_OUT45 = 0x00000C2Eu, /* cpuss.dw1_tr_out[45] */ 1134 TRIG_IN_MUX_12_PDMA1_TR_OUT46 = 0x00000C2Fu, /* cpuss.dw1_tr_out[46] */ 1135 TRIG_IN_MUX_12_PDMA1_TR_OUT47 = 0x00000C30u, /* cpuss.dw1_tr_out[47] */ 1136 TRIG_IN_MUX_12_PDMA1_TR_OUT48 = 0x00000C31u, /* cpuss.dw1_tr_out[48] */ 1137 TRIG_IN_MUX_12_PDMA1_TR_OUT49 = 0x00000C32u, /* cpuss.dw1_tr_out[49] */ 1138 TRIG_IN_MUX_12_PDMA1_TR_OUT50 = 0x00000C33u, /* cpuss.dw1_tr_out[50] */ 1139 TRIG_IN_MUX_12_PDMA1_TR_OUT51 = 0x00000C34u, /* cpuss.dw1_tr_out[51] */ 1140 TRIG_IN_MUX_12_PDMA1_TR_OUT52 = 0x00000C35u, /* cpuss.dw1_tr_out[52] */ 1141 TRIG_IN_MUX_12_PDMA1_TR_OUT53 = 0x00000C36u, /* cpuss.dw1_tr_out[53] */ 1142 TRIG_IN_MUX_12_PDMA1_TR_OUT54 = 0x00000C37u, /* cpuss.dw1_tr_out[54] */ 1143 TRIG_IN_MUX_12_PDMA1_TR_OUT55 = 0x00000C38u, /* cpuss.dw1_tr_out[55] */ 1144 TRIG_IN_MUX_12_PDMA1_TR_OUT56 = 0x00000C39u, /* cpuss.dw1_tr_out[56] */ 1145 TRIG_IN_MUX_12_PDMA1_TR_OUT57 = 0x00000C3Au, /* cpuss.dw1_tr_out[57] */ 1146 TRIG_IN_MUX_12_MDMA_TR_OUT0 = 0x00000C3Bu, /* cpuss.dmac_tr_out[0] */ 1147 TRIG_IN_MUX_12_MDMA_TR_OUT1 = 0x00000C3Cu, /* cpuss.dmac_tr_out[1] */ 1148 TRIG_IN_MUX_12_MDMA_TR_OUT2 = 0x00000C3Du, /* cpuss.dmac_tr_out[2] */ 1149 TRIG_IN_MUX_12_MDMA_TR_OUT3 = 0x00000C3Eu, /* cpuss.dmac_tr_out[3] */ 1150 TRIG_IN_MUX_12_MDMA_TR_OUT4 = 0x00000C3Fu, /* cpuss.dmac_tr_out[4] */ 1151 TRIG_IN_MUX_12_MDMA_TR_OUT5 = 0x00000C40u, /* cpuss.dmac_tr_out[5] */ 1152 TRIG_IN_MUX_12_MDMA_TR_OUT6 = 0x00000C41u, /* cpuss.dmac_tr_out[6] */ 1153 TRIG_IN_MUX_12_MDMA_TR_OUT7 = 0x00000C42u, /* cpuss.dmac_tr_out[7] */ 1154 TRIG_IN_MUX_12_TCPWM_16_TR_OUT10 = 0x00000C43u, /* tcpwm[0].tr_out1[0] */ 1155 TRIG_IN_MUX_12_TCPWM_16_TR_OUT11 = 0x00000C44u, /* tcpwm[0].tr_out1[1] */ 1156 TRIG_IN_MUX_12_TCPWM_16_TR_OUT12 = 0x00000C45u, /* tcpwm[0].tr_out1[2] */ 1157 TRIG_IN_MUX_12_TCPWM_16_TR_OUT13 = 0x00000C46u, /* tcpwm[0].tr_out1[3] */ 1158 TRIG_IN_MUX_12_TCPWM_16_TR_OUT14 = 0x00000C47u, /* tcpwm[0].tr_out1[4] */ 1159 TRIG_IN_MUX_12_TCPWM_16_TR_OUT15 = 0x00000C48u, /* tcpwm[0].tr_out1[5] */ 1160 TRIG_IN_MUX_12_TCPWM_16_TR_OUT16 = 0x00000C49u, /* tcpwm[0].tr_out1[6] */ 1161 TRIG_IN_MUX_12_TCPWM_16_TR_OUT17 = 0x00000C4Au, /* tcpwm[0].tr_out1[7] */ 1162 TRIG_IN_MUX_12_TCPWM_16_TR_OUT18 = 0x00000C4Bu, /* tcpwm[0].tr_out1[8] */ 1163 TRIG_IN_MUX_12_TCPWM_16_TR_OUT19 = 0x00000C4Cu, /* tcpwm[0].tr_out1[9] */ 1164 TRIG_IN_MUX_12_TCPWM_16_TR_OUT110 = 0x00000C4Du, /* tcpwm[0].tr_out1[10] */ 1165 TRIG_IN_MUX_12_TCPWM_16_TR_OUT111 = 0x00000C4Eu, /* tcpwm[0].tr_out1[11] */ 1166 TRIG_IN_MUX_12_TCPWM_16_TR_OUT112 = 0x00000C4Fu, /* tcpwm[0].tr_out1[12] */ 1167 TRIG_IN_MUX_12_TCPWM_16_TR_OUT113 = 0x00000C50u, /* tcpwm[0].tr_out1[13] */ 1168 TRIG_IN_MUX_12_TCPWM_16_TR_OUT114 = 0x00000C51u, /* tcpwm[0].tr_out1[14] */ 1169 TRIG_IN_MUX_12_TCPWM_16_TR_OUT115 = 0x00000C52u, /* tcpwm[0].tr_out1[15] */ 1170 TRIG_IN_MUX_12_TCPWM_16_TR_OUT116 = 0x00000C53u, /* tcpwm[0].tr_out1[16] */ 1171 TRIG_IN_MUX_12_TCPWM_16_TR_OUT117 = 0x00000C54u, /* tcpwm[0].tr_out1[17] */ 1172 TRIG_IN_MUX_12_TCPWM_16_TR_OUT118 = 0x00000C55u, /* tcpwm[0].tr_out1[18] */ 1173 TRIG_IN_MUX_12_TCPWM_16_TR_OUT119 = 0x00000C56u, /* tcpwm[0].tr_out1[19] */ 1174 TRIG_IN_MUX_12_TCPWM_16_TR_OUT120 = 0x00000C57u, /* tcpwm[0].tr_out1[20] */ 1175 TRIG_IN_MUX_12_TCPWM_16_TR_OUT121 = 0x00000C58u, /* tcpwm[0].tr_out1[21] */ 1176 TRIG_IN_MUX_12_TCPWM_16_TR_OUT122 = 0x00000C59u, /* tcpwm[0].tr_out1[22] */ 1177 TRIG_IN_MUX_12_TCPWM_16_TR_OUT123 = 0x00000C5Au, /* tcpwm[0].tr_out1[23] */ 1178 TRIG_IN_MUX_12_TCPWM_16_TR_OUT124 = 0x00000C5Bu, /* tcpwm[0].tr_out1[24] */ 1179 TRIG_IN_MUX_12_TCPWM_16_TR_OUT125 = 0x00000C5Cu, /* tcpwm[0].tr_out1[25] */ 1180 TRIG_IN_MUX_12_TCPWM_16_TR_OUT126 = 0x00000C5Du, /* tcpwm[0].tr_out1[26] */ 1181 TRIG_IN_MUX_12_TCPWM_16_TR_OUT127 = 0x00000C5Eu, /* tcpwm[0].tr_out1[27] */ 1182 TRIG_IN_MUX_12_TCPWM_16_TR_OUT128 = 0x00000C5Fu, /* tcpwm[0].tr_out1[28] */ 1183 TRIG_IN_MUX_12_TCPWM_16_TR_OUT129 = 0x00000C60u, /* tcpwm[0].tr_out1[29] */ 1184 TRIG_IN_MUX_12_TCPWM_16_TR_OUT130 = 0x00000C61u, /* tcpwm[0].tr_out1[30] */ 1185 TRIG_IN_MUX_12_TCPWM_16_TR_OUT131 = 0x00000C62u, /* tcpwm[0].tr_out1[31] */ 1186 TRIG_IN_MUX_12_TCPWM_16_TR_OUT132 = 0x00000C63u, /* tcpwm[0].tr_out1[32] */ 1187 TRIG_IN_MUX_12_TCPWM_16_TR_OUT133 = 0x00000C64u, /* tcpwm[0].tr_out1[33] */ 1188 TRIG_IN_MUX_12_TCPWM_16_TR_OUT134 = 0x00000C65u, /* tcpwm[0].tr_out1[34] */ 1189 TRIG_IN_MUX_12_TCPWM_16_TR_OUT135 = 0x00000C66u, /* tcpwm[0].tr_out1[35] */ 1190 TRIG_IN_MUX_12_TCPWM_16_TR_OUT136 = 0x00000C67u, /* tcpwm[0].tr_out1[36] */ 1191 TRIG_IN_MUX_12_TCPWM_16_TR_OUT137 = 0x00000C68u, /* tcpwm[0].tr_out1[37] */ 1192 TRIG_IN_MUX_12_TCPWM_16_TR_OUT138 = 0x00000C69u, /* tcpwm[0].tr_out1[38] */ 1193 TRIG_IN_MUX_12_TCPWM_16_TR_OUT139 = 0x00000C6Au, /* tcpwm[0].tr_out1[39] */ 1194 TRIG_IN_MUX_12_TCPWM_16_TR_OUT140 = 0x00000C6Bu, /* tcpwm[0].tr_out1[40] */ 1195 TRIG_IN_MUX_12_TCPWM_16_TR_OUT141 = 0x00000C6Cu, /* tcpwm[0].tr_out1[41] */ 1196 TRIG_IN_MUX_12_TCPWM_16_TR_OUT142 = 0x00000C6Du, /* tcpwm[0].tr_out1[42] */ 1197 TRIG_IN_MUX_12_TCPWM_16_TR_OUT143 = 0x00000C6Eu, /* tcpwm[0].tr_out1[43] */ 1198 TRIG_IN_MUX_12_TCPWM_16_TR_OUT144 = 0x00000C6Fu, /* tcpwm[0].tr_out1[44] */ 1199 TRIG_IN_MUX_12_TCPWM_16_TR_OUT145 = 0x00000C70u, /* tcpwm[0].tr_out1[45] */ 1200 TRIG_IN_MUX_12_TCPWM_16_TR_OUT146 = 0x00000C71u, /* tcpwm[0].tr_out1[46] */ 1201 TRIG_IN_MUX_12_TCPWM_16_TR_OUT147 = 0x00000C72u, /* tcpwm[0].tr_out1[47] */ 1202 TRIG_IN_MUX_12_TCPWM_16_TR_OUT148 = 0x00000C73u, /* tcpwm[0].tr_out1[48] */ 1203 TRIG_IN_MUX_12_TCPWM_16_TR_OUT149 = 0x00000C74u, /* tcpwm[0].tr_out1[49] */ 1204 TRIG_IN_MUX_12_TCPWM_16_TR_OUT150 = 0x00000C75u, /* tcpwm[0].tr_out1[50] */ 1205 TRIG_IN_MUX_12_TCPWM_16_TR_OUT151 = 0x00000C76u, /* tcpwm[0].tr_out1[51] */ 1206 TRIG_IN_MUX_12_TCPWM_16_TR_OUT152 = 0x00000C77u, /* tcpwm[0].tr_out1[52] */ 1207 TRIG_IN_MUX_12_TCPWM_16_TR_OUT153 = 0x00000C78u, /* tcpwm[0].tr_out1[53] */ 1208 TRIG_IN_MUX_12_TCPWM_16_TR_OUT154 = 0x00000C79u, /* tcpwm[0].tr_out1[54] */ 1209 TRIG_IN_MUX_12_TCPWM_16_TR_OUT155 = 0x00000C7Au, /* tcpwm[0].tr_out1[55] */ 1210 TRIG_IN_MUX_12_TCPWM_16_TR_OUT156 = 0x00000C7Bu, /* tcpwm[0].tr_out1[56] */ 1211 TRIG_IN_MUX_12_TCPWM_16_TR_OUT157 = 0x00000C7Cu, /* tcpwm[0].tr_out1[57] */ 1212 TRIG_IN_MUX_12_TCPWM_16_TR_OUT158 = 0x00000C7Du, /* tcpwm[0].tr_out1[58] */ 1213 TRIG_IN_MUX_12_TCPWM_16_TR_OUT159 = 0x00000C7Eu, /* tcpwm[0].tr_out1[59] */ 1214 TRIG_IN_MUX_12_TCPWM_16_TR_OUT160 = 0x00000C7Fu, /* tcpwm[0].tr_out1[60] */ 1215 TRIG_IN_MUX_12_TCPWM_16_TR_OUT161 = 0x00000C80u, /* tcpwm[0].tr_out1[61] */ 1216 TRIG_IN_MUX_12_TCPWM_16_TR_OUT162 = 0x00000C81u, /* tcpwm[0].tr_out1[62] */ 1217 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT10 = 0x00000C82u, /* tcpwm[0].tr_out1[256] */ 1218 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT11 = 0x00000C83u, /* tcpwm[0].tr_out1[257] */ 1219 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT12 = 0x00000C84u, /* tcpwm[0].tr_out1[258] */ 1220 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT13 = 0x00000C85u, /* tcpwm[0].tr_out1[259] */ 1221 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT14 = 0x00000C86u, /* tcpwm[0].tr_out1[260] */ 1222 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT15 = 0x00000C87u, /* tcpwm[0].tr_out1[261] */ 1223 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT16 = 0x00000C88u, /* tcpwm[0].tr_out1[262] */ 1224 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT17 = 0x00000C89u, /* tcpwm[0].tr_out1[263] */ 1225 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT18 = 0x00000C8Au, /* tcpwm[0].tr_out1[264] */ 1226 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT19 = 0x00000C8Bu, /* tcpwm[0].tr_out1[265] */ 1227 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT110 = 0x00000C8Cu, /* tcpwm[0].tr_out1[266] */ 1228 TRIG_IN_MUX_12_TCPWM_16M_TR_OUT111 = 0x00000C8Du, /* tcpwm[0].tr_out1[267] */ 1229 TRIG_IN_MUX_12_TCPWM_32_TR_OUT10 = 0x00000C8Eu, /* tcpwm[0].tr_out1[512] */ 1230 TRIG_IN_MUX_12_TCPWM_32_TR_OUT11 = 0x00000C8Fu, /* tcpwm[0].tr_out1[513] */ 1231 TRIG_IN_MUX_12_TCPWM_32_TR_OUT12 = 0x00000C90u, /* tcpwm[0].tr_out1[514] */ 1232 TRIG_IN_MUX_12_TCPWM_32_TR_OUT13 = 0x00000C91u, /* tcpwm[0].tr_out1[515] */ 1233 TRIG_IN_MUX_12_TCPWM_32_TR_OUT14 = 0x00000C92u, /* tcpwm[0].tr_out1[516] */ 1234 TRIG_IN_MUX_12_TCPWM_32_TR_OUT15 = 0x00000C93u, /* tcpwm[0].tr_out1[517] */ 1235 TRIG_IN_MUX_12_TCPWM_32_TR_OUT16 = 0x00000C94u, /* tcpwm[0].tr_out1[518] */ 1236 TRIG_IN_MUX_12_TCPWM_32_TR_OUT17 = 0x00000C95u, /* tcpwm[0].tr_out1[519] */ 1237 TRIG_IN_MUX_12_PASS_GEN_TR_OUT0 = 0x00000C96u, /* pass[0].tr_sar_gen_out[0] */ 1238 TRIG_IN_MUX_12_PASS_GEN_TR_OUT1 = 0x00000C97u, /* pass[0].tr_sar_gen_out[1] */ 1239 TRIG_IN_MUX_12_PASS_GEN_TR_OUT2 = 0x00000C98u, /* pass[0].tr_sar_gen_out[2] */ 1240 TRIG_IN_MUX_12_PASS_GEN_TR_OUT3 = 0x00000C99u, /* pass[0].tr_sar_gen_out[3] */ 1241 TRIG_IN_MUX_12_PASS_GEN_TR_OUT4 = 0x00000C9Au, /* pass[0].tr_sar_gen_out[4] */ 1242 TRIG_IN_MUX_12_PASS_GEN_TR_OUT5 = 0x00000C9Bu /* pass[0].tr_sar_gen_out[5] */ 1243 } en_trig_input_debugreduction3_t; 1244 1245 /* Trigger Group Outputs */ 1246 /* Trigger Output Group 0 - P-DMA0[0:7] Request Assignments */ 1247 typedef enum 1248 { 1249 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1250 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1251 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1252 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1253 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1254 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1255 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1256 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ 1257 } en_trig_output_pdma0_tr_0_t; 1258 1259 /* Trigger Output Group 1 - P-DMA0[8:15] Request Assignments */ 1260 typedef enum 1261 { 1262 TRIG_OUT_MUX_1_PDMA0_TR_IN8 = 0x40000100u, /* cpuss.dw0_tr_in[8] */ 1263 TRIG_OUT_MUX_1_PDMA0_TR_IN9 = 0x40000101u, /* cpuss.dw0_tr_in[9] */ 1264 TRIG_OUT_MUX_1_PDMA0_TR_IN10 = 0x40000102u, /* cpuss.dw0_tr_in[10] */ 1265 TRIG_OUT_MUX_1_PDMA0_TR_IN11 = 0x40000103u, /* cpuss.dw0_tr_in[11] */ 1266 TRIG_OUT_MUX_1_PDMA0_TR_IN12 = 0x40000104u, /* cpuss.dw0_tr_in[12] */ 1267 TRIG_OUT_MUX_1_PDMA0_TR_IN13 = 0x40000105u, /* cpuss.dw0_tr_in[13] */ 1268 TRIG_OUT_MUX_1_PDMA0_TR_IN14 = 0x40000106u, /* cpuss.dw0_tr_in[14] */ 1269 TRIG_OUT_MUX_1_PDMA0_TR_IN15 = 0x40000107u /* cpuss.dw0_tr_in[15] */ 1270 } en_trig_output_pdma0_tr_1_t; 1271 1272 /* Trigger Output Group 2 - P-DMA1[0:15] Request Assignments */ 1273 typedef enum 1274 { 1275 TRIG_OUT_MUX_2_PDMA1_TR_IN0 = 0x40000200u, /* cpuss.dw1_tr_in[0] */ 1276 TRIG_OUT_MUX_2_PDMA1_TR_IN1 = 0x40000201u, /* cpuss.dw1_tr_in[1] */ 1277 TRIG_OUT_MUX_2_PDMA1_TR_IN2 = 0x40000202u, /* cpuss.dw1_tr_in[2] */ 1278 TRIG_OUT_MUX_2_PDMA1_TR_IN3 = 0x40000203u, /* cpuss.dw1_tr_in[3] */ 1279 TRIG_OUT_MUX_2_PDMA1_TR_IN4 = 0x40000204u, /* cpuss.dw1_tr_in[4] */ 1280 TRIG_OUT_MUX_2_PDMA1_TR_IN5 = 0x40000205u, /* cpuss.dw1_tr_in[5] */ 1281 TRIG_OUT_MUX_2_PDMA1_TR_IN6 = 0x40000206u, /* cpuss.dw1_tr_in[6] */ 1282 TRIG_OUT_MUX_2_PDMA1_TR_IN7 = 0x40000207u, /* cpuss.dw1_tr_in[7] */ 1283 TRIG_OUT_MUX_2_PDMA1_TR_IN8 = 0x40000208u, /* cpuss.dw1_tr_in[8] */ 1284 TRIG_OUT_MUX_2_PDMA1_TR_IN9 = 0x40000209u, /* cpuss.dw1_tr_in[9] */ 1285 TRIG_OUT_MUX_2_PDMA1_TR_IN10 = 0x4000020Au, /* cpuss.dw1_tr_in[10] */ 1286 TRIG_OUT_MUX_2_PDMA1_TR_IN11 = 0x4000020Bu, /* cpuss.dw1_tr_in[11] */ 1287 TRIG_OUT_MUX_2_PDMA1_TR_IN12 = 0x4000020Cu, /* cpuss.dw1_tr_in[12] */ 1288 TRIG_OUT_MUX_2_PDMA1_TR_IN13 = 0x4000020Du, /* cpuss.dw1_tr_in[13] */ 1289 TRIG_OUT_MUX_2_PDMA1_TR_IN14 = 0x4000020Eu, /* cpuss.dw1_tr_in[14] */ 1290 TRIG_OUT_MUX_2_PDMA1_TR_IN15 = 0x4000020Fu /* cpuss.dw1_tr_in[15] */ 1291 } en_trig_output_pdma1_tr_t; 1292 1293 /* Trigger Output Group 3 - M-DMA Request Assignments */ 1294 typedef enum 1295 { 1296 TRIG_OUT_MUX_3_MDMA_TR_IN0 = 0x40000300u, /* cpuss.dmac_tr_in[0] */ 1297 TRIG_OUT_MUX_3_MDMA_TR_IN1 = 0x40000301u, /* cpuss.dmac_tr_in[1] */ 1298 TRIG_OUT_MUX_3_MDMA_TR_IN2 = 0x40000302u, /* cpuss.dmac_tr_in[2] */ 1299 TRIG_OUT_MUX_3_MDMA_TR_IN3 = 0x40000303u, /* cpuss.dmac_tr_in[3] */ 1300 TRIG_OUT_MUX_3_MDMA_TR_IN4 = 0x40000304u, /* cpuss.dmac_tr_in[4] */ 1301 TRIG_OUT_MUX_3_MDMA_TR_IN5 = 0x40000305u, /* cpuss.dmac_tr_in[5] */ 1302 TRIG_OUT_MUX_3_MDMA_TR_IN6 = 0x40000306u, /* cpuss.dmac_tr_in[6] */ 1303 TRIG_OUT_MUX_3_MDMA_TR_IN7 = 0x40000307u /* cpuss.dmac_tr_in[7] */ 1304 } en_trig_output_mdma_t; 1305 1306 /* Trigger Output Group 5 - */ 1307 typedef enum 1308 { 1309 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN0 = 0x40000500u, /* tcpwm[0].tr_all_cnt_in[0] */ 1310 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN1 = 0x40000501u, /* tcpwm[0].tr_all_cnt_in[1] */ 1311 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN2 = 0x40000502u, /* tcpwm[0].tr_all_cnt_in[2] */ 1312 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN3 = 0x40000503u, /* tcpwm[0].tr_all_cnt_in[3] */ 1313 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN4 = 0x40000504u, /* tcpwm[0].tr_all_cnt_in[4] */ 1314 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN5 = 0x40000505u, /* tcpwm[0].tr_all_cnt_in[5] */ 1315 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN6 = 0x40000506u, /* tcpwm[0].tr_all_cnt_in[6] */ 1316 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN7 = 0x40000507u, /* tcpwm[0].tr_all_cnt_in[7] */ 1317 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN8 = 0x40000508u, /* tcpwm[0].tr_all_cnt_in[8] */ 1318 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN9 = 0x40000509u, /* tcpwm[0].tr_all_cnt_in[9] */ 1319 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN10 = 0x4000050Au, /* tcpwm[0].tr_all_cnt_in[10] */ 1320 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN11 = 0x4000050Bu /* tcpwm[0].tr_all_cnt_in[11] */ 1321 } en_trig_output_tcpwm_out_t; 1322 1323 /* Trigger Output Group 6 - TCPWM trigger inputs */ 1324 typedef enum 1325 { 1326 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN12 = 0x40000600u, /* tcpwm[0].tr_all_cnt_in[12] */ 1327 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN13 = 0x40000601u, /* tcpwm[0].tr_all_cnt_in[13] */ 1328 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN14 = 0x40000602u, /* tcpwm[0].tr_all_cnt_in[14] */ 1329 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN15 = 0x40000603u, /* tcpwm[0].tr_all_cnt_in[15] */ 1330 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN16 = 0x40000604u, /* tcpwm[0].tr_all_cnt_in[16] */ 1331 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN17 = 0x40000605u, /* tcpwm[0].tr_all_cnt_in[17] */ 1332 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN18 = 0x40000606u, /* tcpwm[0].tr_all_cnt_in[18] */ 1333 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN19 = 0x40000607u, /* tcpwm[0].tr_all_cnt_in[19] */ 1334 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN20 = 0x40000608u, /* tcpwm[0].tr_all_cnt_in[20] */ 1335 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN21 = 0x40000609u, /* tcpwm[0].tr_all_cnt_in[21] */ 1336 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN22 = 0x4000060Au, /* tcpwm[0].tr_all_cnt_in[22] */ 1337 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN23 = 0x4000060Bu, /* tcpwm[0].tr_all_cnt_in[23] */ 1338 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN24 = 0x4000060Cu, /* tcpwm[0].tr_all_cnt_in[24] */ 1339 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN25 = 0x4000060Du, /* tcpwm[0].tr_all_cnt_in[25] */ 1340 TRIG_OUT_MUX_6_TCPWM_ALL_CNT_TR_IN26 = 0x4000060Eu /* tcpwm[0].tr_all_cnt_in[26] */ 1341 } en_trig_output_tcpwm_in_t; 1342 1343 /* Trigger Output Group 7 - PASS trigger multiplexer */ 1344 typedef enum 1345 { 1346 TRIG_OUT_MUX_7_PASS_GEN_TR_IN0 = 0x40000700u, /* pass[0].tr_sar_gen_in[0] */ 1347 TRIG_OUT_MUX_7_PASS_GEN_TR_IN1 = 0x40000701u, /* pass[0].tr_sar_gen_in[1] */ 1348 TRIG_OUT_MUX_7_PASS_GEN_TR_IN2 = 0x40000702u, /* pass[0].tr_sar_gen_in[2] */ 1349 TRIG_OUT_MUX_7_PASS_GEN_TR_IN3 = 0x40000703u, /* pass[0].tr_sar_gen_in[3] */ 1350 TRIG_OUT_MUX_7_PASS_GEN_TR_IN4 = 0x40000704u, /* pass[0].tr_sar_gen_in[4] */ 1351 TRIG_OUT_MUX_7_PASS_GEN_TR_IN5 = 0x40000705u, /* pass[0].tr_sar_gen_in[5] */ 1352 TRIG_OUT_MUX_7_PASS_GEN_TR_IN6 = 0x40000706u, /* pass[0].tr_sar_gen_in[6] */ 1353 TRIG_OUT_MUX_7_PASS_GEN_TR_IN7 = 0x40000707u, /* pass[0].tr_sar_gen_in[7] */ 1354 TRIG_OUT_MUX_7_PASS_GEN_TR_IN8 = 0x40000708u, /* pass[0].tr_sar_gen_in[8] */ 1355 TRIG_OUT_MUX_7_PASS_GEN_TR_IN9 = 0x40000709u, /* pass[0].tr_sar_gen_in[9] */ 1356 TRIG_OUT_MUX_7_PASS_GEN_TR_IN10 = 0x4000070Au, /* pass[0].tr_sar_gen_in[10] */ 1357 TRIG_OUT_MUX_7_PASS_GEN_TR_IN11 = 0x4000070Bu /* pass[0].tr_sar_gen_in[11] */ 1358 } en_trig_output_pass_t; 1359 1360 /* Trigger Output Group 8 - CAN TT Synchronization triggers */ 1361 typedef enum 1362 { 1363 TRIG_OUT_MUX_8_CAN0_TT_TR_IN0 = 0x40000800u, /* canfd[0].tr_evt_swt_in[0] */ 1364 TRIG_OUT_MUX_8_CAN0_TT_TR_IN1 = 0x40000801u, /* canfd[0].tr_evt_swt_in[1] */ 1365 TRIG_OUT_MUX_8_CAN0_TT_TR_IN2 = 0x40000802u, /* canfd[0].tr_evt_swt_in[2] */ 1366 TRIG_OUT_MUX_8_CAN0_TT_TR_IN3 = 0x40000803u, /* canfd[0].tr_evt_swt_in[3] */ 1367 TRIG_OUT_MUX_8_CAN1_TT_TR_IN0 = 0x40000804u, /* canfd[1].tr_evt_swt_in[0] */ 1368 TRIG_OUT_MUX_8_CAN1_TT_TR_IN1 = 0x40000805u, /* canfd[1].tr_evt_swt_in[1] */ 1369 TRIG_OUT_MUX_8_CAN1_TT_TR_IN2 = 0x40000806u, /* canfd[1].tr_evt_swt_in[2] */ 1370 TRIG_OUT_MUX_8_CAN1_TT_TR_IN3 = 0x40000807u /* canfd[1].tr_evt_swt_in[3] */ 1371 } en_trig_output_cantt_t; 1372 1373 /* Trigger Output Group 9 - 2nd level MUX using input from MUX_9/10/11 */ 1374 typedef enum 1375 { 1376 TRIG_OUT_MUX_9_HSIOM_IO_OUTPUT0 = 0x40000900u, /* peri.tr_io_output[0] */ 1377 TRIG_OUT_MUX_9_HSIOM_IO_OUTPUT1 = 0x40000901u, /* peri.tr_io_output[1] */ 1378 TRIG_OUT_MUX_9_CTI_TR_IN0 = 0x40000902u, /* cpuss.cti_tr_in[0] */ 1379 TRIG_OUT_MUX_9_CTI_TR_IN1 = 0x40000903u, /* cpuss.cti_tr_in[1] */ 1380 TRIG_OUT_MUX_9_PERI_DEBUG_FREEZE_TR_IN = 0x40000904u, /* peri.tr_dbg_freeze */ 1381 TRIG_OUT_MUX_9_PASS_DEBUG_FREEZE_TR_IN = 0x40000905u, /* pass[0].tr_debug_freeze */ 1382 TRIG_OUT_MUX_9_SRSS_WDT_DEBUG_FREEZE_TR_IN = 0x40000906u, /* srss.tr_debug_freeze_wdt */ 1383 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN2 = 0x40000907u, /* srss.tr_debug_freeze_mcwdt[2] */ 1384 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN1 = 0x40000908u, /* srss.tr_debug_freeze_mcwdt[1] */ 1385 TRIG_OUT_MUX_9_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000909u, /* srss.tr_debug_freeze_mcwdt[0] */ 1386 TRIG_OUT_MUX_9_TCPWM_DEBUG_FREEZE_TR_IN = 0x4000090Au /* tcpwm[0].tr_debug_freeze */ 1387 } en_trig_output_debugmain_t; 1388 1389 /* Trigger Output Group 10 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1390 typedef enum 1391 { 1392 TRIG_OUT_MUX_10_TR_GROUP9_INPUT1 = 0x40000A00u, /* tr_group[9].input[1] */ 1393 TRIG_OUT_MUX_10_TR_GROUP9_INPUT2 = 0x40000A01u, /* tr_group[9].input[2] */ 1394 TRIG_OUT_MUX_10_TR_GROUP9_INPUT3 = 0x40000A02u, /* tr_group[9].input[3] */ 1395 TRIG_OUT_MUX_10_TR_GROUP9_INPUT4 = 0x40000A03u, /* tr_group[9].input[4] */ 1396 TRIG_OUT_MUX_10_TR_GROUP9_INPUT5 = 0x40000A04u /* tr_group[9].input[5] */ 1397 } en_trig_output_debugreduction1_t; 1398 1399 /* Trigger Output Group 11 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1400 typedef enum 1401 { 1402 TRIG_OUT_MUX_11_TR_GROUP9_INPUT6 = 0x40000B00u, /* tr_group[9].input[6] */ 1403 TRIG_OUT_MUX_11_TR_GROUP9_INPUT7 = 0x40000B01u, /* tr_group[9].input[7] */ 1404 TRIG_OUT_MUX_11_TR_GROUP9_INPUT8 = 0x40000B02u, /* tr_group[9].input[8] */ 1405 TRIG_OUT_MUX_11_TR_GROUP9_INPUT9 = 0x40000B03u, /* tr_group[9].input[9] */ 1406 TRIG_OUT_MUX_11_TR_GROUP9_INPUT10 = 0x40000B04u /* tr_group[9].input[10] */ 1407 } en_trig_output_debugreduction2_t; 1408 1409 /* Trigger Output Group 12 - Makes all possible triggers visible as I/O signals for debug purposes, or to build external circuitry */ 1410 typedef enum 1411 { 1412 TRIG_OUT_MUX_12_TR_GROUP9_INPUT11 = 0x40000C00u, /* tr_group[9].input[11] */ 1413 TRIG_OUT_MUX_12_TR_GROUP9_INPUT12 = 0x40000C01u, /* tr_group[9].input[12] */ 1414 TRIG_OUT_MUX_12_TR_GROUP9_INPUT13 = 0x40000C02u, /* tr_group[9].input[13] */ 1415 TRIG_OUT_MUX_12_TR_GROUP9_INPUT14 = 0x40000C03u, /* tr_group[9].input[14] */ 1416 TRIG_OUT_MUX_12_TR_GROUP9_INPUT15 = 0x40000C04u /* tr_group[9].input[15] */ 1417 } en_trig_output_debugreduction3_t; 1418 1419 /* Trigger Output Group 0 - CAN DW Triggers (OneToOne) */ 1420 typedef enum 1421 { 1422 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_0 = 0x40001000u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw0_tr_in[16] */ 1423 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_0 = 0x40001001u, /* From canfd[0].tr_fifo0[0] to cpuss.dw0_tr_in[17] */ 1424 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_0 = 0x40001002u, /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[18] */ 1425 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_1 = 0x40001003u, /* From canfd[0].tr_dbg_dma_req[1] to cpuss.dw0_tr_in[19] */ 1426 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_1 = 0x40001004u, /* From canfd[0].tr_fifo0[1] to cpuss.dw0_tr_in[20] */ 1427 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_1 = 0x40001005u, /* From canfd[0].tr_fifo1[1] to cpuss.dw0_tr_in[21] */ 1428 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_2 = 0x40001006u, /* From canfd[0].tr_dbg_dma_req[2] to cpuss.dw0_tr_in[22] */ 1429 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_2 = 0x40001007u, /* From canfd[0].tr_fifo0[2] to cpuss.dw0_tr_in[23] */ 1430 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_2 = 0x40001008u, /* From canfd[0].tr_fifo1[2] to cpuss.dw0_tr_in[24] */ 1431 TRIG_OUT_1TO1_0_CAN0_DBG_TO_PDMA0_3 = 0x40001009u, /* From canfd[0].tr_dbg_dma_req[3] to cpuss.dw0_tr_in[25] */ 1432 TRIG_OUT_1TO1_0_CAN0_FIFO0_TO_PDMA0_3 = 0x4000100Au, /* From canfd[0].tr_fifo0[3] to cpuss.dw0_tr_in[26] */ 1433 TRIG_OUT_1TO1_0_CAN0_FIFO1_TO_PDMA0_3 = 0x4000100Bu /* From canfd[0].tr_fifo1[3] to cpuss.dw0_tr_in[27] */ 1434 } en_trig_output_1to1_can0_dw0_tr_t; 1435 1436 /* Trigger Output Group 1 - PASS to DW0 direct connect (OneToOne) */ 1437 typedef enum 1438 { 1439 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA00 = 0x40001100u, /* From pass[0].tr_sar_ch_done[0] to cpuss.dw0_tr_in[28] */ 1440 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA01 = 0x40001101u, /* From pass[0].tr_sar_ch_done[1] to cpuss.dw0_tr_in[29] */ 1441 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA02 = 0x40001102u, /* From pass[0].tr_sar_ch_done[2] to cpuss.dw0_tr_in[30] */ 1442 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA03 = 0x40001103u, /* From pass[0].tr_sar_ch_done[3] to cpuss.dw0_tr_in[31] */ 1443 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA04 = 0x40001104u, /* From pass[0].tr_sar_ch_done[4] to cpuss.dw0_tr_in[32] */ 1444 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA05 = 0x40001105u, /* From pass[0].tr_sar_ch_done[5] to cpuss.dw0_tr_in[33] */ 1445 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA06 = 0x40001106u, /* From pass[0].tr_sar_ch_done[6] to cpuss.dw0_tr_in[34] */ 1446 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA07 = 0x40001107u, /* From pass[0].tr_sar_ch_done[7] to cpuss.dw0_tr_in[35] */ 1447 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA08 = 0x40001108u, /* From pass[0].tr_sar_ch_done[8] to cpuss.dw0_tr_in[36] */ 1448 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA09 = 0x40001109u, /* From pass[0].tr_sar_ch_done[9] to cpuss.dw0_tr_in[37] */ 1449 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA010 = 0x4000110Au, /* From pass[0].tr_sar_ch_done[10] to cpuss.dw0_tr_in[38] */ 1450 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA011 = 0x4000110Bu, /* From pass[0].tr_sar_ch_done[11] to cpuss.dw0_tr_in[39] */ 1451 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA012 = 0x4000110Cu, /* From pass[0].tr_sar_ch_done[12] to cpuss.dw0_tr_in[40] */ 1452 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA013 = 0x4000110Du, /* From pass[0].tr_sar_ch_done[13] to cpuss.dw0_tr_in[41] */ 1453 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA014 = 0x4000110Eu, /* From pass[0].tr_sar_ch_done[14] to cpuss.dw0_tr_in[42] */ 1454 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA015 = 0x4000110Fu, /* From pass[0].tr_sar_ch_done[15] to cpuss.dw0_tr_in[43] */ 1455 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA016 = 0x40001110u, /* From pass[0].tr_sar_ch_done[16] to cpuss.dw0_tr_in[44] */ 1456 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA017 = 0x40001111u, /* From pass[0].tr_sar_ch_done[17] to cpuss.dw0_tr_in[45] */ 1457 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA018 = 0x40001112u, /* From pass[0].tr_sar_ch_done[18] to cpuss.dw0_tr_in[46] */ 1458 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA019 = 0x40001113u, /* From pass[0].tr_sar_ch_done[19] to cpuss.dw0_tr_in[47] */ 1459 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA020 = 0x40001114u, /* From pass[0].tr_sar_ch_done[20] to cpuss.dw0_tr_in[48] */ 1460 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA021 = 0x40001115u, /* From pass[0].tr_sar_ch_done[21] to cpuss.dw0_tr_in[49] */ 1461 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA022 = 0x40001116u, /* From pass[0].tr_sar_ch_done[22] to cpuss.dw0_tr_in[50] */ 1462 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA023 = 0x40001117u, /* From pass[0].tr_sar_ch_done[23] to cpuss.dw0_tr_in[51] */ 1463 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA024 = 0x40001118u, /* From pass[0].tr_sar_ch_done[24] to cpuss.dw0_tr_in[52] */ 1464 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA025 = 0x40001119u, /* From pass[0].tr_sar_ch_done[25] to cpuss.dw0_tr_in[53] */ 1465 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA026 = 0x4000111Au, /* From pass[0].tr_sar_ch_done[26] to cpuss.dw0_tr_in[54] */ 1466 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA027 = 0x4000111Bu, /* From pass[0].tr_sar_ch_done[27] to cpuss.dw0_tr_in[55] */ 1467 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA028 = 0x4000111Cu, /* From pass[0].tr_sar_ch_done[28] to cpuss.dw0_tr_in[56] */ 1468 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA029 = 0x4000111Du, /* From pass[0].tr_sar_ch_done[29] to cpuss.dw0_tr_in[57] */ 1469 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA030 = 0x4000111Eu, /* From pass[0].tr_sar_ch_done[30] to cpuss.dw0_tr_in[58] */ 1470 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA031 = 0x4000111Fu, /* From pass[0].tr_sar_ch_done[31] to cpuss.dw0_tr_in[59] */ 1471 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA032 = 0x40001120u, /* From pass[0].tr_sar_ch_done[32] to cpuss.dw0_tr_in[60] */ 1472 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA033 = 0x40001121u, /* From pass[0].tr_sar_ch_done[33] to cpuss.dw0_tr_in[61] */ 1473 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA034 = 0x40001122u, /* From pass[0].tr_sar_ch_done[34] to cpuss.dw0_tr_in[62] */ 1474 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA035 = 0x40001123u, /* From pass[0].tr_sar_ch_done[35] to cpuss.dw0_tr_in[63] */ 1475 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA036 = 0x40001124u, /* From pass[0].tr_sar_ch_done[36] to cpuss.dw0_tr_in[64] */ 1476 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA037 = 0x40001125u, /* From pass[0].tr_sar_ch_done[37] to cpuss.dw0_tr_in[65] */ 1477 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA038 = 0x40001126u, /* From pass[0].tr_sar_ch_done[38] to cpuss.dw0_tr_in[66] */ 1478 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA039 = 0x40001127u, /* From pass[0].tr_sar_ch_done[39] to cpuss.dw0_tr_in[67] */ 1479 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA040 = 0x40001128u, /* From pass[0].tr_sar_ch_done[40] to cpuss.dw0_tr_in[68] */ 1480 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA041 = 0x40001129u, /* From pass[0].tr_sar_ch_done[41] to cpuss.dw0_tr_in[69] */ 1481 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA042 = 0x4000112Au, /* From pass[0].tr_sar_ch_done[42] to cpuss.dw0_tr_in[70] */ 1482 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA043 = 0x4000112Bu, /* From pass[0].tr_sar_ch_done[43] to cpuss.dw0_tr_in[71] */ 1483 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA044 = 0x4000112Cu, /* From pass[0].tr_sar_ch_done[44] to cpuss.dw0_tr_in[72] */ 1484 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA045 = 0x4000112Du, /* From pass[0].tr_sar_ch_done[45] to cpuss.dw0_tr_in[73] */ 1485 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA046 = 0x4000112Eu, /* From pass[0].tr_sar_ch_done[46] to cpuss.dw0_tr_in[74] */ 1486 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA047 = 0x4000112Fu, /* From pass[0].tr_sar_ch_done[47] to cpuss.dw0_tr_in[75] */ 1487 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA048 = 0x40001130u, /* From pass[0].tr_sar_ch_done[48] to cpuss.dw0_tr_in[76] */ 1488 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA049 = 0x40001131u, /* From pass[0].tr_sar_ch_done[49] to cpuss.dw0_tr_in[77] */ 1489 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA050 = 0x40001132u, /* From pass[0].tr_sar_ch_done[50] to cpuss.dw0_tr_in[78] */ 1490 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA051 = 0x40001133u, /* From pass[0].tr_sar_ch_done[51] to cpuss.dw0_tr_in[79] */ 1491 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA052 = 0x40001134u, /* From pass[0].tr_sar_ch_done[52] to cpuss.dw0_tr_in[80] */ 1492 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA053 = 0x40001135u, /* From pass[0].tr_sar_ch_done[53] to cpuss.dw0_tr_in[81] */ 1493 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA054 = 0x40001136u, /* From pass[0].tr_sar_ch_done[54] to cpuss.dw0_tr_in[82] */ 1494 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA055 = 0x40001137u, /* From pass[0].tr_sar_ch_done[55] to cpuss.dw0_tr_in[83] */ 1495 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA056 = 0x40001138u, /* From pass[0].tr_sar_ch_done[56] to cpuss.dw0_tr_in[84] */ 1496 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA057 = 0x40001139u, /* From pass[0].tr_sar_ch_done[57] to cpuss.dw0_tr_in[85] */ 1497 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA058 = 0x4000113Au, /* From pass[0].tr_sar_ch_done[58] to cpuss.dw0_tr_in[86] */ 1498 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA059 = 0x4000113Bu, /* From pass[0].tr_sar_ch_done[59] to cpuss.dw0_tr_in[87] */ 1499 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA060 = 0x4000113Cu, /* From pass[0].tr_sar_ch_done[60] to cpuss.dw0_tr_in[88] */ 1500 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA061 = 0x4000113Du, /* From pass[0].tr_sar_ch_done[61] to cpuss.dw0_tr_in[89] */ 1501 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA062 = 0x4000113Eu, /* From pass[0].tr_sar_ch_done[62] to cpuss.dw0_tr_in[90] */ 1502 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA063 = 0x4000113Fu, /* From pass[0].tr_sar_ch_done[63] to cpuss.dw0_tr_in[91] */ 1503 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA064 = 0x40001140u, /* From pass[0].tr_sar_ch_done[64] to cpuss.dw0_tr_in[92] */ 1504 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA065 = 0x40001141u, /* From pass[0].tr_sar_ch_done[65] to cpuss.dw0_tr_in[93] */ 1505 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA066 = 0x40001142u, /* From pass[0].tr_sar_ch_done[66] to cpuss.dw0_tr_in[94] */ 1506 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA067 = 0x40001143u, /* From pass[0].tr_sar_ch_done[67] to cpuss.dw0_tr_in[95] */ 1507 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA068 = 0x40001144u, /* From pass[0].tr_sar_ch_done[68] to cpuss.dw0_tr_in[96] */ 1508 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA069 = 0x40001145u, /* From pass[0].tr_sar_ch_done[69] to cpuss.dw0_tr_in[97] */ 1509 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA070 = 0x40001146u, /* From pass[0].tr_sar_ch_done[70] to cpuss.dw0_tr_in[98] */ 1510 TRIG_OUT_1TO1_1_PASS_CH_DONE_TO_PDMA071 = 0x40001147u /* From pass[0].tr_sar_ch_done[71] to cpuss.dw0_tr_in[99] */ 1511 } en_trig_output_1to1_pass_to_dw0_t; 1512 1513 /* Trigger Output Group 2 - SCB DW Triggers (OneToOne) */ 1514 typedef enum 1515 { 1516 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA10 = 0x40001200u, /* From scb[0].tr_tx_req to cpuss.dw1_tr_in[16] */ 1517 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA10 = 0x40001201u, /* From scb[0].tr_rx_req to cpuss.dw1_tr_in[17] */ 1518 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA11 = 0x40001202u, /* From scb[1].tr_tx_req to cpuss.dw1_tr_in[18] */ 1519 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA11 = 0x40001203u, /* From scb[1].tr_rx_req to cpuss.dw1_tr_in[19] */ 1520 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA12 = 0x40001204u, /* From scb[2].tr_tx_req to cpuss.dw1_tr_in[20] */ 1521 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA12 = 0x40001205u, /* From scb[2].tr_rx_req to cpuss.dw1_tr_in[21] */ 1522 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA13 = 0x40001206u, /* From scb[3].tr_tx_req to cpuss.dw1_tr_in[22] */ 1523 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA13 = 0x40001207u, /* From scb[3].tr_rx_req to cpuss.dw1_tr_in[23] */ 1524 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA14 = 0x40001208u, /* From scb[4].tr_tx_req to cpuss.dw1_tr_in[24] */ 1525 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA14 = 0x40001209u, /* From scb[4].tr_rx_req to cpuss.dw1_tr_in[25] */ 1526 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA15 = 0x4000120Au, /* From scb[5].tr_tx_req to cpuss.dw1_tr_in[26] */ 1527 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA15 = 0x4000120Bu, /* From scb[5].tr_rx_req to cpuss.dw1_tr_in[27] */ 1528 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA16 = 0x4000120Cu, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[28] */ 1529 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA16 = 0x4000120Du, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[29] */ 1530 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA17 = 0x4000120Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[30] */ 1531 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA17 = 0x4000120Fu, /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[31] */ 1532 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA18 = 0x40001210u, /* From scb[8].tr_tx_req to cpuss.dw1_tr_in[32] */ 1533 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA18 = 0x40001211u, /* From scb[8].tr_rx_req to cpuss.dw1_tr_in[33] */ 1534 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA19 = 0x40001212u, /* From scb[9].tr_tx_req to cpuss.dw1_tr_in[34] */ 1535 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA19 = 0x40001213u, /* From scb[9].tr_rx_req to cpuss.dw1_tr_in[35] */ 1536 TRIG_OUT_1TO1_2_SCB_TX_TO_PDMA110 = 0x40001214u, /* From scb[10].tr_tx_req to cpuss.dw1_tr_in[36] */ 1537 TRIG_OUT_1TO1_2_SCB_RX_TO_PDMA110 = 0x40001215u /* From scb[10].tr_rx_req to cpuss.dw1_tr_in[37] */ 1538 } en_trig_output_1to1_scb_dw1_tr_t; 1539 1540 /* Trigger Output Group 3 - SMIF DW Triggers (OneToOne) */ 1541 typedef enum 1542 { 1543 TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1 = 0x40001300u, /* From smif[0].tr_tx_req to cpuss.dw1_tr_in[50] */ 1544 TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1 = 0x40001301u /* From smif[0].tr_rx_req to cpuss.dw1_tr_in[51] */ 1545 } en_trig_output_1to1_smif_dw1_tr_t; 1546 1547 /* Trigger Output Group 4 - More CAN DW triggers (on DW1 for max BW) (OneToOne) */ 1548 typedef enum 1549 { 1550 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_0 = 0x40001400u, /* From canfd[1].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[38] */ 1551 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_0 = 0x40001401u, /* From canfd[1].tr_fifo0[0] to cpuss.dw1_tr_in[39] */ 1552 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_0 = 0x40001402u, /* From canfd[1].tr_fifo1[0] to cpuss.dw1_tr_in[40] */ 1553 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_1 = 0x40001403u, /* From canfd[1].tr_dbg_dma_req[1] to cpuss.dw1_tr_in[41] */ 1554 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_1 = 0x40001404u, /* From canfd[1].tr_fifo0[1] to cpuss.dw1_tr_in[42] */ 1555 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_1 = 0x40001405u, /* From canfd[1].tr_fifo1[1] to cpuss.dw1_tr_in[43] */ 1556 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_2 = 0x40001406u, /* From canfd[1].tr_dbg_dma_req[2] to cpuss.dw1_tr_in[44] */ 1557 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_2 = 0x40001407u, /* From canfd[1].tr_fifo0[2] to cpuss.dw1_tr_in[45] */ 1558 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_2 = 0x40001408u, /* From canfd[1].tr_fifo1[2] to cpuss.dw1_tr_in[46] */ 1559 TRIG_OUT_1TO1_4_CAN1_DBG_TO_PDMA1_3 = 0x40001409u, /* From canfd[1].tr_dbg_dma_req[3] to cpuss.dw1_tr_in[47] */ 1560 TRIG_OUT_1TO1_4_CAN1_FIFO0_TO_PDMA1_3 = 0x4000140Au, /* From canfd[1].tr_fifo0[3] to cpuss.dw1_tr_in[48] */ 1561 TRIG_OUT_1TO1_4_CAN1_FIFO1_TO_PDMA1_3 = 0x4000140Bu /* From canfd[1].tr_fifo1[3] to cpuss.dw1_tr_in[49] */ 1562 } en_trig_output_1to1_can1_dw1_tr_t; 1563 1564 /* Trigger Output Group 5 - I2S DW Triggers (OneToOne) */ 1565 typedef enum 1566 { 1567 TRIG_OUT_1TO1_5_I2S_TX_TO_PDMA10 = 0x40001500u, /* From audioss[0].tr_i2s_tx_req to cpuss.dw1_tr_in[52] */ 1568 TRIG_OUT_1TO1_5_I2S_RX_TO_PDMA10 = 0x40001501u, /* From audioss[0].tr_i2s_rx_req to cpuss.dw1_tr_in[53] */ 1569 TRIG_OUT_1TO1_5_I2S_TX_TO_PDMA11 = 0x40001502u, /* From audioss[1].tr_i2s_tx_req to cpuss.dw1_tr_in[54] */ 1570 TRIG_OUT_1TO1_5_I2S_RX_TO_PDMA11 = 0x40001503u, /* From audioss[1].tr_i2s_rx_req to cpuss.dw1_tr_in[55] */ 1571 TRIG_OUT_1TO1_5_I2S_TX_TO_PDMA12 = 0x40001504u, /* From audioss[2].tr_i2s_tx_req to cpuss.dw1_tr_in[56] */ 1572 TRIG_OUT_1TO1_5_I2S_RX_TO_PDMA12 = 0x40001505u /* From audioss[2].tr_i2s_rx_req to cpuss.dw1_tr_in[57] */ 1573 } en_trig_output_1to1_i2s_dw1_tr_t; 1574 1575 /* Trigger Output Group 6 - PASS to PWM direct connect (OneToOne) */ 1576 typedef enum 1577 { 1578 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL0 = 0x40001600u, /* From pass[0].tr_sar_ch_rangevio[0] to tcpwm[0].tr_one_cnt_in[770] */ 1579 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL1 = 0x40001601u, /* From pass[0].tr_sar_ch_rangevio[1] to tcpwm[0].tr_one_cnt_in[779] */ 1580 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL2 = 0x40001602u, /* From pass[0].tr_sar_ch_rangevio[2] to tcpwm[0].tr_one_cnt_in[788] */ 1581 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL3 = 0x40001603u, /* From pass[0].tr_sar_ch_rangevio[3] to tcpwm[0].tr_one_cnt_in[797] */ 1582 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL4 = 0x40001604u, /* From pass[0].tr_sar_ch_rangevio[4] to tcpwm[0].tr_one_cnt_in[2] */ 1583 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL5 = 0x40001605u, /* From pass[0].tr_sar_ch_rangevio[5] to tcpwm[0].tr_one_cnt_in[5] */ 1584 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL6 = 0x40001606u, /* From pass[0].tr_sar_ch_rangevio[6] to tcpwm[0].tr_one_cnt_in[8] */ 1585 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL7 = 0x40001607u, /* From pass[0].tr_sar_ch_rangevio[7] to tcpwm[0].tr_one_cnt_in[11] */ 1586 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL8 = 0x40001608u, /* From pass[0].tr_sar_ch_rangevio[8] to tcpwm[0].tr_one_cnt_in[14] */ 1587 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL9 = 0x40001609u, /* From pass[0].tr_sar_ch_rangevio[9] to tcpwm[0].tr_one_cnt_in[17] */ 1588 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL10 = 0x4000160Au, /* From pass[0].tr_sar_ch_rangevio[10] to tcpwm[0].tr_one_cnt_in[20] */ 1589 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL11 = 0x4000160Bu, /* From pass[0].tr_sar_ch_rangevio[11] to tcpwm[0].tr_one_cnt_in[23] */ 1590 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL12 = 0x4000160Cu, /* From pass[0].tr_sar_ch_rangevio[12] to tcpwm[0].tr_one_cnt_in[26] */ 1591 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL13 = 0x4000160Du, /* From pass[0].tr_sar_ch_rangevio[13] to tcpwm[0].tr_one_cnt_in[29] */ 1592 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL14 = 0x4000160Eu, /* From pass[0].tr_sar_ch_rangevio[14] to tcpwm[0].tr_one_cnt_in[32] */ 1593 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL15 = 0x4000160Fu, /* From pass[0].tr_sar_ch_rangevio[15] to tcpwm[0].tr_one_cnt_in[35] */ 1594 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL16 = 0x40001610u, /* From pass[0].tr_sar_ch_rangevio[16] to tcpwm[0].tr_one_cnt_in[38] */ 1595 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL17 = 0x40001611u, /* From pass[0].tr_sar_ch_rangevio[17] to tcpwm[0].tr_one_cnt_in[41] */ 1596 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL18 = 0x40001612u, /* From pass[0].tr_sar_ch_rangevio[18] to tcpwm[0].tr_one_cnt_in[44] */ 1597 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL19 = 0x40001613u, /* From pass[0].tr_sar_ch_rangevio[19] to tcpwm[0].tr_one_cnt_in[47] */ 1598 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL20 = 0x40001614u, /* From pass[0].tr_sar_ch_rangevio[20] to tcpwm[0].tr_one_cnt_in[50] */ 1599 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL21 = 0x40001615u, /* From pass[0].tr_sar_ch_rangevio[21] to tcpwm[0].tr_one_cnt_in[53] */ 1600 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL22 = 0x40001616u, /* From pass[0].tr_sar_ch_rangevio[22] to tcpwm[0].tr_one_cnt_in[56] */ 1601 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL23 = 0x40001617u, /* From pass[0].tr_sar_ch_rangevio[23] to tcpwm[0].tr_one_cnt_in[59] */ 1602 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL24 = 0x40001618u, /* From pass[0].tr_sar_ch_rangevio[24] to tcpwm[0].tr_one_cnt_in[62] */ 1603 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL25 = 0x40001619u, /* From pass[0].tr_sar_ch_rangevio[25] to tcpwm[0].tr_one_cnt_in[65] */ 1604 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL26 = 0x4000161Au, /* From pass[0].tr_sar_ch_rangevio[26] to tcpwm[0].tr_one_cnt_in[68] */ 1605 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL27 = 0x4000161Bu, /* From pass[0].tr_sar_ch_rangevio[27] to tcpwm[0].tr_one_cnt_in[71] */ 1606 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL28 = 0x4000161Cu, /* From pass[0].tr_sar_ch_rangevio[28] to tcpwm[0].tr_one_cnt_in[74] */ 1607 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL29 = 0x4000161Du, /* From pass[0].tr_sar_ch_rangevio[29] to tcpwm[0].tr_one_cnt_in[77] */ 1608 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL30 = 0x4000161Eu, /* From pass[0].tr_sar_ch_rangevio[30] to tcpwm[0].tr_one_cnt_in[80] */ 1609 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL31 = 0x4000161Fu, /* From pass[0].tr_sar_ch_rangevio[31] to tcpwm[0].tr_one_cnt_in[83] */ 1610 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL32 = 0x40001620u, /* From pass[0].tr_sar_ch_rangevio[32] to tcpwm[0].tr_one_cnt_in[773] */ 1611 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL33 = 0x40001621u, /* From pass[0].tr_sar_ch_rangevio[33] to tcpwm[0].tr_one_cnt_in[782] */ 1612 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL34 = 0x40001622u, /* From pass[0].tr_sar_ch_rangevio[34] to tcpwm[0].tr_one_cnt_in[791] */ 1613 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL35 = 0x40001623u, /* From pass[0].tr_sar_ch_rangevio[35] to tcpwm[0].tr_one_cnt_in[800] */ 1614 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL36 = 0x40001624u, /* From pass[0].tr_sar_ch_rangevio[36] to tcpwm[0].tr_one_cnt_in[86] */ 1615 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL37 = 0x40001625u, /* From pass[0].tr_sar_ch_rangevio[37] to tcpwm[0].tr_one_cnt_in[89] */ 1616 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL38 = 0x40001626u, /* From pass[0].tr_sar_ch_rangevio[38] to tcpwm[0].tr_one_cnt_in[92] */ 1617 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL39 = 0x40001627u, /* From pass[0].tr_sar_ch_rangevio[39] to tcpwm[0].tr_one_cnt_in[95] */ 1618 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL40 = 0x40001628u, /* From pass[0].tr_sar_ch_rangevio[40] to tcpwm[0].tr_one_cnt_in[98] */ 1619 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL41 = 0x40001629u, /* From pass[0].tr_sar_ch_rangevio[41] to tcpwm[0].tr_one_cnt_in[101] */ 1620 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL42 = 0x4000162Au, /* From pass[0].tr_sar_ch_rangevio[42] to tcpwm[0].tr_one_cnt_in[104] */ 1621 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL43 = 0x4000162Bu, /* From pass[0].tr_sar_ch_rangevio[43] to tcpwm[0].tr_one_cnt_in[107] */ 1622 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL44 = 0x4000162Cu, /* From pass[0].tr_sar_ch_rangevio[44] to tcpwm[0].tr_one_cnt_in[110] */ 1623 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL45 = 0x4000162Du, /* From pass[0].tr_sar_ch_rangevio[45] to tcpwm[0].tr_one_cnt_in[113] */ 1624 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL46 = 0x4000162Eu, /* From pass[0].tr_sar_ch_rangevio[46] to tcpwm[0].tr_one_cnt_in[116] */ 1625 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL47 = 0x4000162Fu, /* From pass[0].tr_sar_ch_rangevio[47] to tcpwm[0].tr_one_cnt_in[119] */ 1626 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL48 = 0x40001630u, /* From pass[0].tr_sar_ch_rangevio[48] to tcpwm[0].tr_one_cnt_in[122] */ 1627 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL49 = 0x40001631u, /* From pass[0].tr_sar_ch_rangevio[49] to tcpwm[0].tr_one_cnt_in[125] */ 1628 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL50 = 0x40001632u, /* From pass[0].tr_sar_ch_rangevio[50] to tcpwm[0].tr_one_cnt_in[128] */ 1629 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL51 = 0x40001633u, /* From pass[0].tr_sar_ch_rangevio[51] to tcpwm[0].tr_one_cnt_in[131] */ 1630 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL52 = 0x40001634u, /* From pass[0].tr_sar_ch_rangevio[52] to tcpwm[0].tr_one_cnt_in[134] */ 1631 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL53 = 0x40001635u, /* From pass[0].tr_sar_ch_rangevio[53] to tcpwm[0].tr_one_cnt_in[137] */ 1632 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL54 = 0x40001636u, /* From pass[0].tr_sar_ch_rangevio[54] to tcpwm[0].tr_one_cnt_in[140] */ 1633 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL55 = 0x40001637u, /* From pass[0].tr_sar_ch_rangevio[55] to tcpwm[0].tr_one_cnt_in[143] */ 1634 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL56 = 0x40001638u, /* From pass[0].tr_sar_ch_rangevio[56] to tcpwm[0].tr_one_cnt_in[146] */ 1635 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL57 = 0x40001639u, /* From pass[0].tr_sar_ch_rangevio[57] to tcpwm[0].tr_one_cnt_in[149] */ 1636 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL58 = 0x4000163Au, /* From pass[0].tr_sar_ch_rangevio[58] to tcpwm[0].tr_one_cnt_in[152] */ 1637 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL59 = 0x4000163Bu, /* From pass[0].tr_sar_ch_rangevio[59] to tcpwm[0].tr_one_cnt_in[155] */ 1638 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL60 = 0x4000163Cu, /* From pass[0].tr_sar_ch_rangevio[60] to tcpwm[0].tr_one_cnt_in[158] */ 1639 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL61 = 0x4000163Du, /* From pass[0].tr_sar_ch_rangevio[61] to tcpwm[0].tr_one_cnt_in[161] */ 1640 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL62 = 0x4000163Eu, /* From pass[0].tr_sar_ch_rangevio[62] to tcpwm[0].tr_one_cnt_in[164] */ 1641 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL63 = 0x4000163Fu, /* From pass[0].tr_sar_ch_rangevio[63] to tcpwm[0].tr_one_cnt_in[167] */ 1642 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL64 = 0x40001640u, /* From pass[0].tr_sar_ch_rangevio[64] to tcpwm[0].tr_one_cnt_in[776] */ 1643 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL65 = 0x40001641u, /* From pass[0].tr_sar_ch_rangevio[65] to tcpwm[0].tr_one_cnt_in[785] */ 1644 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL66 = 0x40001642u, /* From pass[0].tr_sar_ch_rangevio[66] to tcpwm[0].tr_one_cnt_in[794] */ 1645 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL67 = 0x40001643u, /* From pass[0].tr_sar_ch_rangevio[67] to tcpwm[0].tr_one_cnt_in[803] */ 1646 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL68 = 0x40001644u, /* From pass[0].tr_sar_ch_rangevio[68] to tcpwm[0].tr_one_cnt_in[170] */ 1647 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL69 = 0x40001645u, /* From pass[0].tr_sar_ch_rangevio[69] to tcpwm[0].tr_one_cnt_in[173] */ 1648 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL70 = 0x40001646u, /* From pass[0].tr_sar_ch_rangevio[70] to tcpwm[0].tr_one_cnt_in[176] */ 1649 TRIG_OUT_1TO1_6_PASS_CH_RANGEVIO_TO_PWM_KILL71 = 0x40001647u /* From pass[0].tr_sar_ch_rangevio[71] to tcpwm[0].tr_one_cnt_in[179] */ 1650 } en_trig_output_1to1_pass_to_pwm_t; 1651 1652 /* Trigger Output Group 7 - (OneToOne) */ 1653 typedef enum 1654 { 1655 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR0 = 0x40001700u, /* From tcpwm[0].tr_out1[256] to pass[0].tr_sar_ch_in[0] */ 1656 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR1 = 0x40001701u, /* From tcpwm[0].tr_out1[259] to pass[0].tr_sar_ch_in[1] */ 1657 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR2 = 0x40001702u, /* From tcpwm[0].tr_out1[262] to pass[0].tr_sar_ch_in[2] */ 1658 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR3 = 0x40001703u, /* From tcpwm[0].tr_out1[265] to pass[0].tr_sar_ch_in[3] */ 1659 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR4 = 0x40001704u, /* From tcpwm[0].tr_out1[0] to pass[0].tr_sar_ch_in[4] */ 1660 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR5 = 0x40001705u, /* From tcpwm[0].tr_out1[1] to pass[0].tr_sar_ch_in[5] */ 1661 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR6 = 0x40001706u, /* From tcpwm[0].tr_out1[2] to pass[0].tr_sar_ch_in[6] */ 1662 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR7 = 0x40001707u, /* From tcpwm[0].tr_out1[3] to pass[0].tr_sar_ch_in[7] */ 1663 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR8 = 0x40001708u, /* From tcpwm[0].tr_out1[4] to pass[0].tr_sar_ch_in[8] */ 1664 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR9 = 0x40001709u, /* From tcpwm[0].tr_out1[5] to pass[0].tr_sar_ch_in[9] */ 1665 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR10 = 0x4000170Au, /* From tcpwm[0].tr_out1[6] to pass[0].tr_sar_ch_in[10] */ 1666 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR11 = 0x4000170Bu, /* From tcpwm[0].tr_out1[7] to pass[0].tr_sar_ch_in[11] */ 1667 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR12 = 0x4000170Cu, /* From tcpwm[0].tr_out1[8] to pass[0].tr_sar_ch_in[12] */ 1668 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR13 = 0x4000170Du, /* From tcpwm[0].tr_out1[9] to pass[0].tr_sar_ch_in[13] */ 1669 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR14 = 0x4000170Eu, /* From tcpwm[0].tr_out1[10] to pass[0].tr_sar_ch_in[14] */ 1670 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR15 = 0x4000170Fu, /* From tcpwm[0].tr_out1[11] to pass[0].tr_sar_ch_in[15] */ 1671 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR16 = 0x40001710u, /* From tcpwm[0].tr_out1[12] to pass[0].tr_sar_ch_in[16] */ 1672 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR17 = 0x40001711u, /* From tcpwm[0].tr_out1[13] to pass[0].tr_sar_ch_in[17] */ 1673 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR18 = 0x40001712u, /* From tcpwm[0].tr_out1[14] to pass[0].tr_sar_ch_in[18] */ 1674 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR19 = 0x40001713u, /* From tcpwm[0].tr_out1[15] to pass[0].tr_sar_ch_in[19] */ 1675 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR20 = 0x40001714u, /* From tcpwm[0].tr_out1[16] to pass[0].tr_sar_ch_in[20] */ 1676 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR21 = 0x40001715u, /* From tcpwm[0].tr_out1[17] to pass[0].tr_sar_ch_in[21] */ 1677 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR22 = 0x40001716u, /* From tcpwm[0].tr_out1[18] to pass[0].tr_sar_ch_in[22] */ 1678 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR23 = 0x40001717u, /* From tcpwm[0].tr_out1[19] to pass[0].tr_sar_ch_in[23] */ 1679 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR24 = 0x40001718u, /* From tcpwm[0].tr_out1[20] to pass[0].tr_sar_ch_in[24] */ 1680 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR25 = 0x40001719u, /* From tcpwm[0].tr_out1[21] to pass[0].tr_sar_ch_in[25] */ 1681 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR26 = 0x4000171Au, /* From tcpwm[0].tr_out1[22] to pass[0].tr_sar_ch_in[26] */ 1682 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR27 = 0x4000171Bu, /* From tcpwm[0].tr_out1[23] to pass[0].tr_sar_ch_in[27] */ 1683 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR28 = 0x4000171Cu, /* From tcpwm[0].tr_out1[24] to pass[0].tr_sar_ch_in[28] */ 1684 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR29 = 0x4000171Du, /* From tcpwm[0].tr_out1[25] to pass[0].tr_sar_ch_in[29] */ 1685 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR30 = 0x4000171Eu, /* From tcpwm[0].tr_out1[26] to pass[0].tr_sar_ch_in[30] */ 1686 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR31 = 0x4000171Fu, /* From tcpwm[0].tr_out1[27] to pass[0].tr_sar_ch_in[31] */ 1687 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR32 = 0x40001720u, /* From tcpwm[0].tr_out1[257] to pass[0].tr_sar_ch_in[32] */ 1688 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR33 = 0x40001721u, /* From tcpwm[0].tr_out1[260] to pass[0].tr_sar_ch_in[33] */ 1689 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR34 = 0x40001722u, /* From tcpwm[0].tr_out1[263] to pass[0].tr_sar_ch_in[34] */ 1690 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR35 = 0x40001723u, /* From tcpwm[0].tr_out1[266] to pass[0].tr_sar_ch_in[35] */ 1691 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR36 = 0x40001724u, /* From tcpwm[0].tr_out1[28] to pass[0].tr_sar_ch_in[36] */ 1692 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR37 = 0x40001725u, /* From tcpwm[0].tr_out1[29] to pass[0].tr_sar_ch_in[37] */ 1693 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR38 = 0x40001726u, /* From tcpwm[0].tr_out1[30] to pass[0].tr_sar_ch_in[38] */ 1694 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR39 = 0x40001727u, /* From tcpwm[0].tr_out1[31] to pass[0].tr_sar_ch_in[39] */ 1695 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR40 = 0x40001728u, /* From tcpwm[0].tr_out1[32] to pass[0].tr_sar_ch_in[40] */ 1696 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR41 = 0x40001729u, /* From tcpwm[0].tr_out1[33] to pass[0].tr_sar_ch_in[41] */ 1697 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR42 = 0x4000172Au, /* From tcpwm[0].tr_out1[34] to pass[0].tr_sar_ch_in[42] */ 1698 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR43 = 0x4000172Bu, /* From tcpwm[0].tr_out1[35] to pass[0].tr_sar_ch_in[43] */ 1699 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR44 = 0x4000172Cu, /* From tcpwm[0].tr_out1[36] to pass[0].tr_sar_ch_in[44] */ 1700 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR45 = 0x4000172Du, /* From tcpwm[0].tr_out1[37] to pass[0].tr_sar_ch_in[45] */ 1701 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR46 = 0x4000172Eu, /* From tcpwm[0].tr_out1[38] to pass[0].tr_sar_ch_in[46] */ 1702 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR47 = 0x4000172Fu, /* From tcpwm[0].tr_out1[39] to pass[0].tr_sar_ch_in[47] */ 1703 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR48 = 0x40001730u, /* From tcpwm[0].tr_out1[40] to pass[0].tr_sar_ch_in[48] */ 1704 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR49 = 0x40001731u, /* From tcpwm[0].tr_out1[41] to pass[0].tr_sar_ch_in[49] */ 1705 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR50 = 0x40001732u, /* From tcpwm[0].tr_out1[42] to pass[0].tr_sar_ch_in[50] */ 1706 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR51 = 0x40001733u, /* From tcpwm[0].tr_out1[43] to pass[0].tr_sar_ch_in[51] */ 1707 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR52 = 0x40001734u, /* From tcpwm[0].tr_out1[44] to pass[0].tr_sar_ch_in[52] */ 1708 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR53 = 0x40001735u, /* From tcpwm[0].tr_out1[45] to pass[0].tr_sar_ch_in[53] */ 1709 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR54 = 0x40001736u, /* From tcpwm[0].tr_out1[46] to pass[0].tr_sar_ch_in[54] */ 1710 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR55 = 0x40001737u, /* From tcpwm[0].tr_out1[47] to pass[0].tr_sar_ch_in[55] */ 1711 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR56 = 0x40001738u, /* From tcpwm[0].tr_out1[48] to pass[0].tr_sar_ch_in[56] */ 1712 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR57 = 0x40001739u, /* From tcpwm[0].tr_out1[49] to pass[0].tr_sar_ch_in[57] */ 1713 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR58 = 0x4000173Au, /* From tcpwm[0].tr_out1[50] to pass[0].tr_sar_ch_in[58] */ 1714 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR59 = 0x4000173Bu, /* From tcpwm[0].tr_out1[51] to pass[0].tr_sar_ch_in[59] */ 1715 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR60 = 0x4000173Cu, /* From tcpwm[0].tr_out1[52] to pass[0].tr_sar_ch_in[60] */ 1716 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR61 = 0x4000173Du, /* From tcpwm[0].tr_out1[53] to pass[0].tr_sar_ch_in[61] */ 1717 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR62 = 0x4000173Eu, /* From tcpwm[0].tr_out1[54] to pass[0].tr_sar_ch_in[62] */ 1718 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR63 = 0x4000173Fu, /* From tcpwm[0].tr_out1[55] to pass[0].tr_sar_ch_in[63] */ 1719 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR64 = 0x40001740u, /* From tcpwm[0].tr_out1[258] to pass[0].tr_sar_ch_in[64] */ 1720 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR65 = 0x40001741u, /* From tcpwm[0].tr_out1[261] to pass[0].tr_sar_ch_in[65] */ 1721 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR66 = 0x40001742u, /* From tcpwm[0].tr_out1[264] to pass[0].tr_sar_ch_in[66] */ 1722 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR67 = 0x40001743u, /* From tcpwm[0].tr_out1[267] to pass[0].tr_sar_ch_in[67] */ 1723 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR68 = 0x40001744u, /* From tcpwm[0].tr_out1[56] to pass[0].tr_sar_ch_in[68] */ 1724 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR69 = 0x40001745u, /* From tcpwm[0].tr_out1[57] to pass[0].tr_sar_ch_in[69] */ 1725 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR70 = 0x40001746u, /* From tcpwm[0].tr_out1[58] to pass[0].tr_sar_ch_in[70] */ 1726 TRIG_OUT_1TO1_7_TCPWM_TO_PASS_CH_TR71 = 0x40001747u /* From tcpwm[0].tr_out1[59] to pass[0].tr_sar_ch_in[71] */ 1727 } en_trig_output_1to1_pwm_to_pass_t; 1728 1729 /* Trigger Output Group 8 - Acknowledge triggers from DW1 to CAN (OneToOne) */ 1730 typedef enum 1731 { 1732 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_0 = 0x40001800u, /* From cpuss.dw1_tr_out[38] to canfd[1].tr_dbg_dma_ack[0] */ 1733 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_1 = 0x40001801u, /* From cpuss.dw1_tr_out[41] to canfd[1].tr_dbg_dma_ack[1] */ 1734 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_2 = 0x40001802u, /* From cpuss.dw1_tr_out[44] to canfd[1].tr_dbg_dma_ack[2] */ 1735 TRIG_OUT_1TO1_8_PDMA1_ACK_TO_CAN1_3 = 0x40001803u /* From cpuss.dw1_tr_out[47] to canfd[1].tr_dbg_dma_ack[3] */ 1736 } en_trig_output_1to1_can1_dw1_ack_t; 1737 1738 /* Trigger Output Group 9 - Acknowledge triggers from DW0 to CAN (OneToOne) */ 1739 typedef enum 1740 { 1741 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_0 = 0x40001900u, /* From cpuss.dw0_tr_out[16] to canfd[0].tr_dbg_dma_ack[0] */ 1742 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_1 = 0x40001901u, /* From cpuss.dw0_tr_out[19] to canfd[0].tr_dbg_dma_ack[1] */ 1743 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_2 = 0x40001902u, /* From cpuss.dw0_tr_out[22] to canfd[0].tr_dbg_dma_ack[2] */ 1744 TRIG_OUT_1TO1_9_PDMA0_ACK_TO_CAN0_3 = 0x40001903u /* From cpuss.dw0_tr_out[25] to canfd[0].tr_dbg_dma_ack[3] */ 1745 } en_trig_output_1to1_can0_dw0_ack_t; 1746 1747 /* Trigger Output Group 10 - (OneToOne) */ 1748 typedef enum 1749 { 1750 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR0 = 0x40001A00u, /* From tcpwm[0].tr_out0[0] to lin[0].tr_cmd_tx_header[0] */ 1751 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR1 = 0x40001A01u, /* From tcpwm[0].tr_out0[1] to lin[0].tr_cmd_tx_header[1] */ 1752 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR2 = 0x40001A02u, /* From tcpwm[0].tr_out0[2] to lin[0].tr_cmd_tx_header[2] */ 1753 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR3 = 0x40001A03u, /* From tcpwm[0].tr_out0[3] to lin[0].tr_cmd_tx_header[3] */ 1754 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR4 = 0x40001A04u, /* From tcpwm[0].tr_out0[4] to lin[0].tr_cmd_tx_header[4] */ 1755 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR5 = 0x40001A05u, /* From tcpwm[0].tr_out0[5] to lin[0].tr_cmd_tx_header[5] */ 1756 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR6 = 0x40001A06u, /* From tcpwm[0].tr_out0[6] to lin[0].tr_cmd_tx_header[6] */ 1757 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR7 = 0x40001A07u, /* From tcpwm[0].tr_out0[7] to lin[0].tr_cmd_tx_header[7] */ 1758 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR8 = 0x40001A08u, /* From tcpwm[0].tr_out0[8] to lin[0].tr_cmd_tx_header[8] */ 1759 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR9 = 0x40001A09u, /* From tcpwm[0].tr_out0[9] to lin[0].tr_cmd_tx_header[9] */ 1760 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR10 = 0x40001A0Au, /* From tcpwm[0].tr_out0[10] to lin[0].tr_cmd_tx_header[10] */ 1761 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR11 = 0x40001A0Bu, /* From tcpwm[0].tr_out0[11] to lin[0].tr_cmd_tx_header[11] */ 1762 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR12 = 0x40001A0Cu, /* From tcpwm[0].tr_out0[12] to lin[0].tr_cmd_tx_header[12] */ 1763 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR13 = 0x40001A0Du, /* From tcpwm[0].tr_out0[13] to lin[0].tr_cmd_tx_header[13] */ 1764 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR14 = 0x40001A0Eu, /* From tcpwm[0].tr_out0[14] to lin[0].tr_cmd_tx_header[14] */ 1765 TRIG_OUT_1TO1_10_TCPWM_TO_LIN_TR15 = 0x40001A0Fu /* From tcpwm[0].tr_out0[15] to lin[0].tr_cmd_tx_header[15] */ 1766 } en_trig_output_1to1_tcpwm_to_lin_t; 1767 1768 /* Level or edge detection setting for a trigger mux */ 1769 typedef enum 1770 { 1771 /* The trigger is a simple level output */ 1772 TRIGGER_TYPE_LEVEL = 0u, 1773 /* The trigger is synchronized to the consumer blocks clock 1774 and a two cycle pulse is generated on this clock */ 1775 TRIGGER_TYPE_EDGE = 1u 1776 } en_trig_type_t; 1777 1778 /* Trigger Type Defines */ 1779 /* AUDIOSS Trigger Types */ 1780 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL 1781 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL 1782 /* CANFD Trigger Types */ 1783 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1784 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1785 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1786 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1787 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1788 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1789 /* CPUSS Trigger Types */ 1790 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1791 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1792 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1793 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1794 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1795 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1796 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1797 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1798 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1799 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1800 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1801 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1802 /* LIN Trigger Types */ 1803 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 1804 /* PASS Trigger Types */ 1805 #define TRIGGER_TYPE_PASS_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1806 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__LEVEL TRIGGER_TYPE_LEVEL 1807 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__EDGE TRIGGER_TYPE_EDGE 1808 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__LEVEL TRIGGER_TYPE_LEVEL 1809 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__EDGE TRIGGER_TYPE_EDGE 1810 #define TRIGGER_TYPE_PASS_TR_SAR_CH_RANGEVIO TRIGGER_TYPE_EDGE 1811 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__LEVEL TRIGGER_TYPE_LEVEL 1812 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__EDGE TRIGGER_TYPE_EDGE 1813 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__LEVEL TRIGGER_TYPE_LEVEL 1814 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__EDGE TRIGGER_TYPE_EDGE 1815 /* PERI Trigger Types */ 1816 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1817 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1818 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1819 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1820 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1821 /* SCB Trigger Types */ 1822 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1823 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1824 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1825 /* SMIF Trigger Types */ 1826 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 1827 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 1828 /* SRSS Trigger Types */ 1829 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 1830 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_WDT TRIGGER_TYPE_LEVEL 1831 /* TCPWM Trigger Types */ 1832 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1833 /* TR_GROUP Trigger Types */ 1834 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1835 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1836 #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1837 #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE 1838 1839 /* Fault connections */ 1840 typedef enum 1841 { 1842 CPUSS_MPU_VIO_0 = 0x0000u, 1843 CPUSS_MPU_VIO_1 = 0x0001u, 1844 CPUSS_MPU_VIO_2 = 0x0002u, 1845 CPUSS_MPU_VIO_3 = 0x0003u, 1846 CPUSS_MPU_VIO_4 = 0x0004u, 1847 CPUSS_MPU_VIO_5 = 0x0005u, 1848 CPUSS_MPU_VIO_6 = 0x0006u, 1849 CPUSS_MPU_VIO_13 = 0x000Du, 1850 CPUSS_MPU_VIO_14 = 0x000Eu, 1851 CPUSS_MPU_VIO_15 = 0x000Fu, 1852 CPUSS_CM7_1_TCM_C_ECC = 0x0010u, 1853 CPUSS_CM7_1_TCM_NC_ECC = 0x0011u, 1854 CPUSS_CM7_0_CACHE_C_ECC = 0x0012u, 1855 CPUSS_CM7_0_CACHE_NC_ECC = 0x0013u, 1856 CPUSS_CM7_1_CACHE_C_ECC = 0x0014u, 1857 CPUSS_CM7_1_CACHE_NC_ECC = 0x0015u, 1858 PERI_MS_VIO_4 = 0x0019u, 1859 PERI_PERI_C_ECC = 0x001Au, 1860 PERI_PERI_NC_ECC = 0x001Bu, 1861 PERI_MS_VIO_0 = 0x001Cu, 1862 PERI_MS_VIO_1 = 0x001Du, 1863 PERI_MS_VIO_2 = 0x001Eu, 1864 PERI_MS_VIO_3 = 0x001Fu, 1865 PERI_GROUP_VIO_0 = 0x0020u, 1866 PERI_GROUP_VIO_1 = 0x0021u, 1867 PERI_GROUP_VIO_2 = 0x0022u, 1868 PERI_GROUP_VIO_3 = 0x0023u, 1869 PERI_GROUP_VIO_4 = 0x0024u, 1870 PERI_GROUP_VIO_5 = 0x0025u, 1871 PERI_GROUP_VIO_6 = 0x0026u, 1872 PERI_GROUP_VIO_8 = 0x0028u, 1873 PERI_GROUP_VIO_9 = 0x0029u, 1874 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u, 1875 CPUSS_FLASHC_MAIN_C_ECC = 0x0031u, 1876 CPUSS_FLASHC_MAIN_NC_ECC = 0x0032u, 1877 CPUSS_FLASHC_WORK_BUS_ERR = 0x0033u, 1878 CPUSS_FLASHC_WORK_C_ECC = 0x0034u, 1879 CPUSS_FLASHC_WORK_NC_ECC = 0x0035u, 1880 CPUSS_FLASHC_CM0_CA_C_ECC = 0x0036u, 1881 CPUSS_FLASHC_CM0_CA_NC_ECC = 0x0037u, 1882 CPUSS_CM7_0_TCM_C_ECC = 0x0038u, 1883 CPUSS_CM7_0_TCM_NC_ECC = 0x0039u, 1884 CPUSS_RAMC0_C_ECC = 0x003Au, 1885 CPUSS_RAMC0_NC_ECC = 0x003Bu, 1886 CPUSS_RAMC1_C_ECC = 0x003Cu, 1887 CPUSS_RAMC1_NC_ECC = 0x003Du, 1888 CPUSS_CRYPTO_C_ECC = 0x0040u, 1889 CPUSS_CRYPTO_NC_ECC = 0x0041u, 1890 CPUSS_DW0_C_ECC = 0x0046u, 1891 CPUSS_DW0_NC_ECC = 0x0047u, 1892 CPUSS_DW1_C_ECC = 0x0048u, 1893 CPUSS_DW1_NC_ECC = 0x0049u, 1894 CPUSS_FM_SRAM_C_ECC = 0x004Au, 1895 CPUSS_FM_SRAM_NC_ECC = 0x004Bu, 1896 CANFD_0_CAN_C_ECC = 0x0050u, 1897 CANFD_0_CAN_NC_ECC = 0x0051u, 1898 CANFD_1_CAN_C_ECC = 0x0052u, 1899 CANFD_1_CAN_NC_ECC = 0x0053u, 1900 SRSS_FAULT_CSV = 0x005Au, 1901 SRSS_FAULT_SSV = 0x005Bu, 1902 SRSS_FAULT_MCWDT0 = 0x005Cu, 1903 SRSS_FAULT_MCWDT1 = 0x005Du, 1904 SRSS_FAULT_MCWDT2 = 0x005Eu 1905 } en_sysfault_source_t; 1906 1907 /* Bus masters */ 1908 typedef enum 1909 { 1910 CPUSS_MS_ID_CM0 = 0, 1911 CPUSS_MS_ID_CRYPTO = 1, 1912 CPUSS_MS_ID_DW0 = 2, 1913 CPUSS_MS_ID_DW1 = 3, 1914 CPUSS_MS_ID_DMAC = 4, 1915 CPUSS_MS_ID_SLOW0 = 5, 1916 CPUSS_MS_ID_SLOW1 = 6, 1917 CPUSS_MS_ID_FAST0 = 9, 1918 CPUSS_MS_ID_FAST1 = 10, 1919 CPUSS_MS_ID_FAST2 = 11, 1920 CPUSS_MS_ID_FAST3 = 12, 1921 CPUSS_MS_ID_CM7_1 = 13, 1922 CPUSS_MS_ID_CM7_0 = 14, 1923 CPUSS_MS_ID_TC = 15 1924 } en_prot_master_t; 1925 1926 /* Include IP definitions */ 1927 #include "ip/cyip_sflash_xmc7100.h" 1928 #include "ip/cyip_peri_v3.h" 1929 #include "ip/cyip_peri_ms_v3.h" 1930 #include "ip/cyip_peri_pclk_v3.h" 1931 #include "ip/cyip_crypto_v2.h" 1932 #include "ip/cyip_cpuss.h" 1933 #include "ip/cyip_fault.h" 1934 #include "ip/cyip_ipc.h" 1935 #include "ip/cyip_prot.h" 1936 #include "ip/cyip_flashc_ect.h" 1937 #include "ip/cyip_srss_v3_2.h" 1938 #include "ip/cyip_backup_v3_2.h" 1939 #include "ip/cyip_dw.h" 1940 #include "ip/cyip_dmac.h" 1941 #include "ip/cyip_efuse_v2.h" 1942 #include "ip/cyip_efuse_data_v2_xmc7100.h" 1943 #include "ip/cyip_hsiom_v3.h" 1944 #include "ip/cyip_gpio_v3.h" 1945 #include "ip/cyip_smartio_v3.h" 1946 #include "ip/cyip_evtgen.h" 1947 #include "ip/cyip_smif_v2.h" 1948 #include "ip/cyip_sdhc.h" 1949 #include "ip/cyip_eth_v2.h" 1950 #include "ip/cyip_lin.h" 1951 #include "ip/cyip_canfd.h" 1952 #include "ip/cyip_tcpwm_v2.h" 1953 #include "ip/cyip_scb_v2.h" 1954 #include "ip/cyip_i2s_v2.h" 1955 #include "ip/cyip_pass.h" 1956 1957 /* IP type definitions */ 1958 typedef CRYPTO_V2_Type CRYPTO_Type; 1959 1960 /* Parameter Defines */ 1961 /* I2S capable? (0=No,1=Yes) */ 1962 #define AUDIOSS0_I2S_I2S 1u 1963 /* I2S instantiates both RX and TX. 0=TX Only 1=RX Plus TX present */ 1964 #define AUDIOSS0_I2S_I2S_RX_TX 1u 1965 /* PDM capable? (0=No,1=Yes) */ 1966 #define AUDIOSS0_PDM_PDM 0u 1967 /* I2S capable? (0=No,1=Yes) */ 1968 #define AUDIOSS1_I2S_I2S 1u 1969 /* I2S instantiates both RX and TX. 0=TX Only 1=RX Plus TX present */ 1970 #define AUDIOSS1_I2S_I2S_RX_TX 1u 1971 /* PDM capable? (0=No,1=Yes) */ 1972 #define AUDIOSS1_PDM_PDM 0u 1973 /* I2S capable? (0=No,1=Yes) */ 1974 #define AUDIOSS2_I2S_I2S 1u 1975 /* I2S instantiates both RX and TX. 0=TX Only 1=RX Plus TX present */ 1976 #define AUDIOSS2_I2S_I2S_RX_TX 1u 1977 /* PDM capable? (0=No,1=Yes) */ 1978 #define AUDIOSS2_PDM_PDM 0u 1979 /* Number of TTCAN instances */ 1980 #define CANFD0_CAN_NR 4u 1981 /* ECC logic present or not */ 1982 #define CANFD0_ECC_PRESENT 1u 1983 /* address included in ECC logic or not */ 1984 #define CANFD0_ECC_ADDR_PRESENT 1u 1985 /* Time Stamp counter present or not (required for instance 0, otherwise not 1986 allowed) */ 1987 #define CANFD0_TS_PRESENT 1u 1988 /* Message RAM size in KB */ 1989 #define CANFD0_MRAM_SIZE 32u 1990 /* Message RAM address width */ 1991 #define CANFD0_MRAM_ADDR_WIDTH 13u 1992 /* Number of TTCAN instances */ 1993 #define CANFD1_CAN_NR 4u 1994 /* ECC logic present or not */ 1995 #define CANFD1_ECC_PRESENT 1u 1996 /* address included in ECC logic or not */ 1997 #define CANFD1_ECC_ADDR_PRESENT 1u 1998 /* Time Stamp counter present or not (required for instance 0, otherwise not 1999 allowed) */ 2000 #define CANFD1_TS_PRESENT 0u 2001 /* Message RAM size in KB */ 2002 #define CANFD1_MRAM_SIZE 32u 2003 /* Message RAM address width */ 2004 #define CANFD1_MRAM_ADDR_WIDTH 13u 2005 /* UDB present or not ('0': no, '1': yes) */ 2006 #define CPUSS_UDB_PRESENT 0u 2007 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 2008 chips which doesn't use mxdft. */ 2009 #define CPUSS_MBIST_MMIO_PRESENT 0u 2010 /* System RAM 0 size in KB */ 2011 #define CPUSS_SRAM0_SIZE 512u 2012 /* Number of macros used to implement system RAM 0. Example: 8 if 256 KB system 2013 SRAM 0 is implemented with 8 32KB macros. */ 2014 #define CPUSS_RAMC0_MACRO_NR 16u 2015 /* System RAM 1 present or not ('0': no, '1': yes) */ 2016 #define CPUSS_RAMC1_PRESENT 1u 2017 /* System RAM 1 size in KB */ 2018 #define CPUSS_SRAM1_SIZE 256u 2019 /* Number of macros used to implement system RAM 1. */ 2020 #define CPUSS_RAMC1_MACRO_NR 8u 2021 /* System RAM 2 present or not ('0': no, '1': yes) */ 2022 #define CPUSS_RAMC2_PRESENT 0u 2023 /* System RAM 2 size in KB */ 2024 #define CPUSS_SRAM2_SIZE 256u 2025 /* Number of macros used to implement System RAM 2. */ 2026 #define CPUSS_RAMC2_MACRO_NR 8u 2027 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 2028 #define CPUSS_RAMC_ECC_PRESENT 1u 2029 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 2030 #define CPUSS_RAMC_ECC_ADDR_PRESENT 1u 2031 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 2032 #define CPUSS_ECC_PRESENT 1u 2033 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2034 #define CPUSS_DW_ECC_PRESENT 1u 2035 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 2036 #define CPUSS_DW_ECC_ADDR_PRESENT 1u 2037 /* System ROM size in KB */ 2038 #define CPUSS_ROM_SIZE 64u 2039 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 2040 is implemented with 4 128KB macros. */ 2041 #define CPUSS_ROMC_MACRO_NR 1u 2042 /* Flash memory present or not ('0': no, '1': yes) */ 2043 #define CPUSS_FLASHC_PRESENT 1u 2044 /* Flash memory type ('0' : SONOS, '1': ECT) */ 2045 #define CPUSS_FLASHC_ECT 1u 2046 /* Flash main region size in KB */ 2047 #define CPUSS_FLASH_SIZE 0x00001000u 2048 /* Flash work region size in KB (EEPROM emulation, data) */ 2049 #define CPUSS_WFLASH_SIZE 256u 2050 /* Flash supervisory region size in KB */ 2051 #define CPUSS_SFLASH_SIZE 32u 2052 /* Flash data output word size (in Bits) Example: 256 for 256-bit Flash data 2053 output */ 2054 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 256u 2055 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 2056 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 2057 Flash, and no Work Flash present. */ 2058 #define CPUSS_FLASHC_SONOS_RWW 0u 2059 /* SONOS Flash, number of main sectors. */ 2060 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 0u 2061 /* SONOS Flash, number of rows per main sector. */ 2062 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 0u 2063 /* SONOS Flash, number of words per row of main sector. */ 2064 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 0u 2065 /* SONOS Flash, number of special sectors. */ 2066 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 0u 2067 /* SONOS Flash, number of rows per special sector. */ 2068 #define CPUSS_FLASHC_SONOS_SPL_ROWS 0u 2069 /* Flash memory ECC present or not ('0': no, '1': yes) */ 2070 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 1u 2071 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 2072 #define CPUSS_FLASHC_RAM_ECC_PRESENT 1u 2073 /* Number of external AHB-Lite slaves directly connected to slow AHB-Lite 2074 infrastructure. Maximum nubmer of slave supported is 6. Width of this 2075 parameter is 6-bits. 1-bit mask for each slave indicating present or not. 2076 Example: 6'b00_0011 - slave 0 and slave 1 are present. Note: The 2077 SLOW_SLx_ADDR and SLOW_SLx_MASK parameters (for the slaves present) should be 2078 derived from the Memory Map. */ 2079 #define CPUSS_SLOW_SL_PRESENT 1u 2080 /* Number of external AXI slaves directly connected to fast AXI infrastructure. 2081 Maximum nubmer of slave supported is 8. Width of this parameter is 8-bits. 2082 1-bit mask for each slave indicating present or not. Example: 8'b0000_0011 - 2083 slave 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 2084 parameters (for the slaves present) should be derived from the Memory Map. */ 2085 #define CPUSS_FAST_SL_PRESENT 1u 2086 /* Number of external AHB-Lite masters driving the slow AHB-Lite infrastructure. 2087 Maximum number of masters supported is 2. Width of this parameter is 2-bits. 2088 1-bit mask for each master indicating present or not. Example: 2'b01 - master 2089 0 is present. */ 2090 #define CPUSS_SLOW_MS_PRESENT 3u 2091 /* Number of external AXI masters driving the fast AXI infrastructure. Maximum 2092 number of masters supported is 4. Width of this parameter is 4-bits. 1-bit 2093 mask for each master indicating present or not. Example: 4'b0001 - master 0 2094 is present. */ 2095 #define CPUSS_FAST_MS_PRESENT 0u 2096 /* Retain 'protection context' (PC), 'privileged' (P), 'Non Secure' (NS) 2097 attributes coming from external AXI master or use it from CPUSS protection 2098 MMIO (PROT_MPU.MS_CTL.PC, PROT_SMPU.MSx_CTL.P, PROT_SMPU.MSx_CTL.NS). Width 2099 of this parameter is 4-bits. 1-bit mask for each master indicating retain PC 2100 or not. */ 2101 #define CPUSS_AXIM_RETAIN_PROT 0u 2102 /* Width of external AXI master ID signals. Legal range [3,8] */ 2103 #define CPUSS_AXIM_ID_WIDTH 3u 2104 /* Width of external AXI slave ID signals (AXIM_ID_WIDTH + MASTER_WIDTH + 1). 2105 Legal range [12,17] */ 2106 #define CPUSS_AXIS_ID_WIDTH 12u 2107 /* IRQ expander present ('0': no, '1': yes) */ 2108 #define CPUSS_SYSTEM_IRQ_PRESENT 1u 2109 /* Number of system interrupt inputs to CPUSS */ 2110 #define CPUSS_SYSTEM_INT_NR 443u 2111 /* Number of DeepSleep system interrupt inputs to CPUSS */ 2112 #define CPUSS_SYSTEM_DPSLP_INT_NR 51u 2113 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 2114 levels of priority 8 = 256 levels of priority */ 2115 #define CPUSS_CM7_LVL_WIDTH 3u 2116 /* Number of CM7 CPU Interrupts. Legal values 8 or 16. */ 2117 #define CPUSS_CM7_INT_NR 8u 2118 /* CM7 Cache SRAMs ECC present or not ('0': no, '1': yes) */ 2119 #define CPUSS_CM7_CACHE_ECC_PRESENT 1u 2120 /* CM7 TCM SRAMs ECC present or not ('0': no, '1': yes) */ 2121 #define CPUSS_CM7_TCM_ECC_PRESENT 1u 2122 /* CM7 TCM SRAMs address ECC present or not ('0': no, '1': yes) */ 2123 #define CPUSS_CM7_TCM_ECC_ADDR_PRESENT 0u 2124 /* CM7_0 Floating point unit configuration. Legal range [0,2] 0 - No FPU 1 - 2125 Single precision FPU 2 - Single and Double precision FPU */ 2126 #define CPUSS_CM7_0_FPU_LVL 2u 2127 /* Number of MPU regions in CM7_0. Legal values [0, 8, 16] */ 2128 #define CPUSS_CM7_0_MPU_NR 16u 2129 /* CM7_0 Instruction cache (ICACHE) size in KB */ 2130 #define CPUSS_CM7_0_ICACHE_SIZE 16u 2131 /* CM7_0 Data cache size (DCACHE) in KB */ 2132 #define CPUSS_CM7_0_DCACHE_SIZE 16u 2133 /* CM7_0 Instruction TCM (ITCM) size in KB */ 2134 #define CPUSS_CM7_0_ITCM_SIZE 16u 2135 /* CM7_0 Data TCM (DTCM) size in KB */ 2136 #define CPUSS_CM7_0_DTCM_SIZE 16u 2137 /* CM7_1 CPU present or not ('0': no, '1': yes) */ 2138 #define CPUSS_CM7_1_PRESENT 1u 2139 /* System interrupt functionality present or not ('0': no; '1': yes) for CM7_1. 2140 Not used for CM0+ CPU, which always uses system interrupt functionality. */ 2141 #define CPUSS_CM7_1_SYSTEM_IRQ_PRESENT 1u 2142 /* CM7_1 Floating point unit configuration. Legal range [0,2] 0 - No FPU 1 - 2143 Single precision FPU 2 - Single and Double precision FPU */ 2144 #define CPUSS_CM7_1_FPU_LVL 2u 2145 /* Number of MPU regions in CM7_1. Legal values [0, 8, 16] */ 2146 #define CPUSS_CM7_1_MPU_NR 16u 2147 /* CM7_1 Instruction cache (ICACHE) size in KB */ 2148 #define CPUSS_CM7_1_ICACHE_SIZE 16u 2149 /* CM7_1 Data cache size (DCACHE) in KB */ 2150 #define CPUSS_CM7_1_DCACHE_SIZE 16u 2151 /* CM7_1 Instruction TCM (ITCM) size in KB */ 2152 #define CPUSS_CM7_1_ITCM_SIZE 16u 2153 /* CM7_1 Data TCM (DTCM) size in KB */ 2154 #define CPUSS_CM7_1_DTCM_SIZE 16u 2155 /* Debug level. Legal range [0,3] */ 2156 #define CPUSS_DEBUG_LVL 3u 2157 /* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 2158 for trace level is not supported in CPUSS. // CPUSS_TRACE_LVL: // 0 = no 2159 tracing // 1 = only ITM source and TPIU sink (no ETM, Funnel, Replicator or 2160 ETB) // 2 = ITM and ETM sources, Funnel and TPIU (no Replicator or ETB) // 3 2161 = ITM and ETM sources, Funnel, Replicator, TPIU and ET */ 2162 #define CPUSS_TRACE_LVL 2u 2163 /* Embedded Trace Buffer present or not ('0': no, '1': yes) */ 2164 #define CPUSS_ETB_PRESENT 1u 2165 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2166 #define CPUSS_MTB_SRAM_SIZE 4u 2167 /* CM7 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2168 #define CPUSS_ETB_SRAM_SIZE 8u 2169 /* PTM interface present (0=No, 1=Yes) */ 2170 #define CPUSS_PTM_PRESENT 0u 2171 /* Width of the PTM interface in bits ([2,32]) */ 2172 #define CPUSS_PTM_WIDTH 1u 2173 /* Width of the TPIU interface in bits ([1,4]) */ 2174 #define CPUSS_TPIU_WIDTH 4u 2175 /* CoreSight Part Identification Number */ 2176 #define CPUSS_JEPID 52u 2177 /* CoreSight Part Identification Number */ 2178 #define CPUSS_JEPCONTINUATION 0u 2179 /* CoreSight Part Identification Number */ 2180 #define CPUSS_FAMILYID 263u 2181 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 2182 #define CPUSS_ROM_TRIM_WIDTH 3u 2183 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002) */ 2184 #define CPUSS_ROM_TRIM_DEFAULT 2u 2185 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 2186 #define CPUSS_RAM_TRIM_WIDTH 8u 2187 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 2188 #define CPUSS_RAM_TRIM_DEFAULT 98u 2189 /* Cryptography IP present or not ('0': no, '1': yes) */ 2190 #define CPUSS_CRYPTO_PRESENT 1u 2191 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2192 #define CPUSS_SW_TR_PRESENT 1u 2193 /* DataWire 0 present or not ('0': no, '1': yes) */ 2194 #define CPUSS_DW0_PRESENT 1u 2195 /* Number of DataWire 0 channels ([1, 1024]) */ 2196 #define CPUSS_DW0_CH_NR 100u 2197 /* DataWire 1 present or not ('0': no, '1': yes) */ 2198 #define CPUSS_DW1_PRESENT 1u 2199 /* Number of DataWire 1 channels ([1, 1024]) */ 2200 #define CPUSS_DW1_CH_NR 58u 2201 /* DMA controller present or not ('0': no, '1': yes) */ 2202 #define CPUSS_DMAC_PRESENT 1u 2203 /* Number of DMA controller channels ([1, 8]) */ 2204 #define CPUSS_DMAC_CH_NR 8u 2205 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2206 #define CPUSS_CH_SW_TR_PRESENT 1u 2207 /* See MMIO2 instantiation or not */ 2208 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 2209 /* ETAS Calibration support pin out present (automotive only) */ 2210 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 1u 2211 /* TRACE_LVL>0 */ 2212 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 2213 /* PTM_PRESENT ? PTM_WIDTH : 0 */ 2214 #define CPUSS_CHIP_TOP_PTM_PRESENT_WIDTH 0u 2215 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 2216 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 1u 2217 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 2218 #define CPUSS_CPUSS_DW_DW_NR 2u 2219 /* Number of channels in each DataWire controller */ 2220 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 100u 2221 /* Width of a channel number in bits */ 2222 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 7u 2223 /* Number of channels in each DataWire controller */ 2224 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 58u 2225 /* Width of a channel number in bits */ 2226 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 6u 2227 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 2228 #define CPUSS_CRYPTO_ECC_PRESENT 1u 2229 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 2230 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 1u 2231 /* AES cipher support ('0': no, '1': yes) */ 2232 #define CPUSS_CRYPTO_AES 1u 2233 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 2234 #define CPUSS_CRYPTO_DES 1u 2235 /* Chacha support ('0': no, '1': yes) */ 2236 #define CPUSS_CRYPTO_CHACHA 1u 2237 /* Pseudo random number generation support ('0': no, '1': yes) */ 2238 #define CPUSS_CRYPTO_PR 1u 2239 /* SHA1 hash support ('0': no, '1': yes) */ 2240 #define CPUSS_CRYPTO_SHA1 1u 2241 /* SHA2 hash support ('0': no, '1': yes) */ 2242 #define CPUSS_CRYPTO_SHA2 1u 2243 /* SHA3 hash support ('0': no, '1': yes) */ 2244 #define CPUSS_CRYPTO_SHA3 1u 2245 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 2246 #define CPUSS_CRYPTO_CRC 1u 2247 /* True random number generation support ('0': no, '1': yes) */ 2248 #define CPUSS_CRYPTO_TR 1u 2249 /* Vector unit support ('0': no, '1': yes) */ 2250 #define CPUSS_CRYPTO_VU 1u 2251 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 2252 #define CPUSS_CRYPTO_GCM 1u 2253 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 2254 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 2255 kB and 16 kB memory buffer) */ 2256 #define CPUSS_CRYPTO_BUFF_SIZE 2048u 2257 /* Number of DMA controller channels ([1, 8]) */ 2258 #define CPUSS_DMAC_CH_NR 8u 2259 /* Number of DataWire controllers present (max 2) */ 2260 #define CPUSS_DW_NR 2u 2261 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2262 #define CPUSS_DW_ECC_PRESENT 1u 2263 /* Number of fault structures. Legal range [1, 4] */ 2264 #define CPUSS_FAULT_FAULT_NR 4u 2265 /* Number of Flash BIST_DATA registers */ 2266 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 8u 2267 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 2268 #define CPUSS_FLASHC_PA_SIZE 128u 2269 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2270 #define CPUSS_FLASHC_FLASHC_IS_SONOS 0u 2271 /* eCT Flash is used or not ('0': no, '1': yes) */ 2272 #define CPUSS_FLASHC_FLASHC_IS_ECT 1u 2273 /* Sequential Work Flash read feature for the FLASHC AXI port present or not ('0': 2274 no, '1': yes) */ 2275 #define CPUSS_FLASHC_FLASHC_WORK_SEQ_PRESENT 1u 2276 /* CM7_1 CPU present or not ('0': no, '1': yes) */ 2277 #define CPUSS_FLASHC_CM7_1_PRESENT 1u 2278 /* External AHB-Lite master0 Present */ 2279 #define CPUSS_FLASHC_SLOW0_MS_PRESENT 1u 2280 /* External AHB-Lite master1 Present */ 2281 #define CPUSS_FLASHC_SLOW1_MS_PRESENT 1u 2282 /* Number of IPC structures. Legal range [1, 16] */ 2283 #define CPUSS_IPC_IPC_NR 8u 2284 /* Number of IPC interrupt structures. Legal range [1, 16] */ 2285 #define CPUSS_IPC_IPC_IRQ_NR 8u 2286 /* Master 0 protect contexts minus one */ 2287 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 2288 /* Master 1 protect contexts minus one */ 2289 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 2290 /* Master 2 protect contexts minus one */ 2291 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 2292 /* Master 3 protect contexts minus one */ 2293 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 2294 /* Master 4 protect contexts minus one */ 2295 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 2296 /* Master 5 protect contexts minus one */ 2297 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u 2298 /* Master 6 protect contexts minus one */ 2299 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 7u 2300 /* Master 7 protect contexts minus one */ 2301 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 2302 /* Master 8 protect contexts minus one */ 2303 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 2304 /* Master 9 protect contexts minus one */ 2305 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 2306 /* Master 10 protect contexts minus one */ 2307 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 2308 /* Master 11 protect contexts minus one */ 2309 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 2310 /* Master 12 protect contexts minus one */ 2311 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 2312 /* Master 13 protect contexts minus one */ 2313 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 7u 2314 /* Master 14 protect contexts minus one */ 2315 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2316 /* Master 15 protect contexts minus one */ 2317 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2318 /* Number of SMPU protection structures */ 2319 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2320 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2321 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2322 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 2323 #define DFT_NUM_HFROOT 8u 2324 /* Width of clk_occ_fast output bus (number of external OCCs) */ 2325 #define DFT_EXT_OCC 2u 2326 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 2327 signals. Value defined by CIC during Pass 1 */ 2328 #define DFT_MBIST_C_NUM 11u 2329 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2330 #define EFUSE_EFUSE_NR 4u 2331 /* AXI Master present ([0,1]): 0 - AHB master interface is present 1 - AXI master 2332 interface is present. */ 2333 #define ETH_AXI_MASTER_PRESENT 0u 2334 /* TX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 16KB to support four 2335 queues with capacity for two jumbo frames; 01: 8KB to support two queues with 2336 capacity for two jumbo frames or four queues with capacity for one jumbo 2337 frame; 10: 4KB to support one queue with capacity for two jumbo frames or two 2338 queues with capacity for one jumbo frame; 11: 2KB to support one queue with 2339 capacity for one jumbo frame; */ 2340 #define ETH_TX_PACKET_BUFFER_SIZE 1u 2341 /* RX Packet Buffer Size (jumbo frame size is 1.5KB): 00: 4KB to support capacity 2342 for two jumbo frames; 01: 2KB to support capacity for one jumbo frames; */ 2343 #define ETH_RX_PACKET_BUFFER_SIZE 0u 2344 /* Selects the clock source to use for the tsu_clk. A value of 0=Internal PCLK, , 2345 1=clk_hf */ 2346 #define ETH_TSU_CLK_SOURCE 1u 2347 /* This parameter is used to specify if mxeth should contain a clock divider. The 2348 clock divider is useful for chips where multiple mxeth are instantiated as it 2349 allows a single source PLL to be used 0=No Divider, ref_clk_int_in is used as 2350 is 1=Divider instantiated, ref_clk_int_in should be 125MHz */ 2351 #define ETH_SRC_CLOCK_DIVIDER 1u 2352 /* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ 2353 #define ETH_SPARE_EN 1u 2354 /* Number of Priority Queues. */ 2355 #define ETH_ETH_NPQ 3u 2356 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2357 #define ETH_MASTER_WIDTH 8u 2358 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2359 #define ETH_PLATFORM_VARIANT 2u 2360 /* RAM vendor (0=CYP, 1=SNPS, 2=ARM) */ 2361 #define ETH_RAM_VEND 2u 2362 /* Width of external AXI master ID signals. Legal range [3,8] */ 2363 #define ETH_AXIM_ID_WIDTH 3u 2364 /* RMII internal clock mode support */ 2365 #define ETH_CHIP_TOP_MXETH_RMII_INT_MODE_EN 0u 2366 /* RGMII internal clock mode support */ 2367 #define ETH_CHIP_TOP_MXETH_RGMII_INT_MODE_EN 1u 2368 /* Number of comparator structures ([1, 32]) */ 2369 #define EVTGEN_COMP_STRUCT_NR 16u 2370 /* Number of GPIO ports in range 0..31 */ 2371 #define IOSS_GPIO_GPIO_PORT_NR_0_31 32u 2372 /* Number of GPIO ports in range 32..63 */ 2373 #define IOSS_GPIO_GPIO_PORT_NR_32_63 1u 2374 /* Number of GPIO ports in range 64..95 */ 2375 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2376 /* Number of GPIO ports in range 96..127 */ 2377 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2378 /* Number of GPIO ports in device */ 2379 #define IOSS_GPIO_GPIO_PORT_NR 33u 2380 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2381 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2382 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2383 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2384 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2385 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 2386 /* Indicates that pin #0 exists for this port with slew control feature */ 2387 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 2388 /* Indicates that pin #1 exists for this port with slew control feature */ 2389 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 2390 /* Indicates that pin #2 exists for this port with slew control feature */ 2391 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 2392 /* Indicates that pin #3 exists for this port with slew control feature */ 2393 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 2394 /* Indicates that pin #4 exists for this port with slew control feature */ 2395 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 2396 /* Indicates that pin #5 exists for this port with slew control feature */ 2397 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 2398 /* Indicates that pin #6 exists for this port with slew control feature */ 2399 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 2400 /* Indicates that pin #7 exists for this port with slew control feature */ 2401 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 2402 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2403 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 2404 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2405 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 2406 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2407 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 1u 2408 /* Indicates that pin #0 exists for this port with slew control feature */ 2409 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 2410 /* Indicates that pin #1 exists for this port with slew control feature */ 2411 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 2412 /* Indicates that pin #2 exists for this port with slew control feature */ 2413 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 2414 /* Indicates that pin #3 exists for this port with slew control feature */ 2415 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 2416 /* Indicates that pin #4 exists for this port with slew control feature */ 2417 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 2418 /* Indicates that pin #5 exists for this port with slew control feature */ 2419 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 2420 /* Indicates that pin #6 exists for this port with slew control feature */ 2421 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 2422 /* Indicates that pin #7 exists for this port with slew control feature */ 2423 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 2424 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2425 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 2426 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2427 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 2428 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2429 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 1u 2430 /* Indicates that pin #0 exists for this port with slew control feature */ 2431 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 2432 /* Indicates that pin #1 exists for this port with slew control feature */ 2433 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 2434 /* Indicates that pin #2 exists for this port with slew control feature */ 2435 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 2436 /* Indicates that pin #3 exists for this port with slew control feature */ 2437 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 2438 /* Indicates that pin #4 exists for this port with slew control feature */ 2439 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 2440 /* Indicates that pin #5 exists for this port with slew control feature */ 2441 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 2442 /* Indicates that pin #6 exists for this port with slew control feature */ 2443 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 2444 /* Indicates that pin #7 exists for this port with slew control feature */ 2445 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 2446 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2447 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 2448 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2449 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 2450 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2451 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 1u 2452 /* Indicates that pin #0 exists for this port with slew control feature */ 2453 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 2454 /* Indicates that pin #1 exists for this port with slew control feature */ 2455 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 2456 /* Indicates that pin #2 exists for this port with slew control feature */ 2457 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 2458 /* Indicates that pin #3 exists for this port with slew control feature */ 2459 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 2460 /* Indicates that pin #4 exists for this port with slew control feature */ 2461 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 2462 /* Indicates that pin #5 exists for this port with slew control feature */ 2463 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 2464 /* Indicates that pin #6 exists for this port with slew control feature */ 2465 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 2466 /* Indicates that pin #7 exists for this port with slew control feature */ 2467 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 2468 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2469 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 2470 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2471 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 2472 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2473 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 1u 2474 /* Indicates that pin #0 exists for this port with slew control feature */ 2475 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 2476 /* Indicates that pin #1 exists for this port with slew control feature */ 2477 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 2478 /* Indicates that pin #2 exists for this port with slew control feature */ 2479 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 2480 /* Indicates that pin #3 exists for this port with slew control feature */ 2481 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 2482 /* Indicates that pin #4 exists for this port with slew control feature */ 2483 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 2484 /* Indicates that pin #5 exists for this port with slew control feature */ 2485 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 2486 /* Indicates that pin #6 exists for this port with slew control feature */ 2487 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 2488 /* Indicates that pin #7 exists for this port with slew control feature */ 2489 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 2490 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2491 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 2492 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2493 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 2494 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2495 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 2496 /* Indicates that pin #0 exists for this port with slew control feature */ 2497 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 2498 /* Indicates that pin #1 exists for this port with slew control feature */ 2499 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 2500 /* Indicates that pin #2 exists for this port with slew control feature */ 2501 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 2502 /* Indicates that pin #3 exists for this port with slew control feature */ 2503 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 2504 /* Indicates that pin #4 exists for this port with slew control feature */ 2505 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 2506 /* Indicates that pin #5 exists for this port with slew control feature */ 2507 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 2508 /* Indicates that pin #6 exists for this port with slew control feature */ 2509 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 2510 /* Indicates that pin #7 exists for this port with slew control feature */ 2511 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 2512 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2513 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 2514 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2515 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 2516 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2517 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 1u 2518 /* Indicates that pin #0 exists for this port with slew control feature */ 2519 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u 2520 /* Indicates that pin #1 exists for this port with slew control feature */ 2521 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u 2522 /* Indicates that pin #2 exists for this port with slew control feature */ 2523 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 0u 2524 /* Indicates that pin #3 exists for this port with slew control feature */ 2525 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 0u 2526 /* Indicates that pin #4 exists for this port with slew control feature */ 2527 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 0u 2528 /* Indicates that pin #5 exists for this port with slew control feature */ 2529 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 0u 2530 /* Indicates that pin #6 exists for this port with slew control feature */ 2531 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 0u 2532 /* Indicates that pin #7 exists for this port with slew control feature */ 2533 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 0u 2534 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2535 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 2536 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2537 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 2538 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2539 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 1u 2540 /* Indicates that pin #0 exists for this port with slew control feature */ 2541 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 0u 2542 /* Indicates that pin #1 exists for this port with slew control feature */ 2543 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 0u 2544 /* Indicates that pin #2 exists for this port with slew control feature */ 2545 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 0u 2546 /* Indicates that pin #3 exists for this port with slew control feature */ 2547 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 0u 2548 /* Indicates that pin #4 exists for this port with slew control feature */ 2549 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 0u 2550 /* Indicates that pin #5 exists for this port with slew control feature */ 2551 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 0u 2552 /* Indicates that pin #6 exists for this port with slew control feature */ 2553 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u 2554 /* Indicates that pin #7 exists for this port with slew control feature */ 2555 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 0u 2556 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2557 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 2558 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2559 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 2560 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2561 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 2562 /* Indicates that pin #0 exists for this port with slew control feature */ 2563 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 0u 2564 /* Indicates that pin #1 exists for this port with slew control feature */ 2565 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 0u 2566 /* Indicates that pin #2 exists for this port with slew control feature */ 2567 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 2568 /* Indicates that pin #3 exists for this port with slew control feature */ 2569 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 2570 /* Indicates that pin #4 exists for this port with slew control feature */ 2571 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 2572 /* Indicates that pin #5 exists for this port with slew control feature */ 2573 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 2574 /* Indicates that pin #6 exists for this port with slew control feature */ 2575 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 2576 /* Indicates that pin #7 exists for this port with slew control feature */ 2577 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 2578 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2579 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 2580 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2581 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 2582 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2583 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 2584 /* Indicates that pin #0 exists for this port with slew control feature */ 2585 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 0u 2586 /* Indicates that pin #1 exists for this port with slew control feature */ 2587 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 0u 2588 /* Indicates that pin #2 exists for this port with slew control feature */ 2589 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 0u 2590 /* Indicates that pin #3 exists for this port with slew control feature */ 2591 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 0u 2592 /* Indicates that pin #4 exists for this port with slew control feature */ 2593 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u 2594 /* Indicates that pin #5 exists for this port with slew control feature */ 2595 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u 2596 /* Indicates that pin #6 exists for this port with slew control feature */ 2597 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 2598 /* Indicates that pin #7 exists for this port with slew control feature */ 2599 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 2600 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2601 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 2602 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2603 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 2604 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2605 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 2606 /* Indicates that pin #0 exists for this port with slew control feature */ 2607 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 0u 2608 /* Indicates that pin #1 exists for this port with slew control feature */ 2609 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 0u 2610 /* Indicates that pin #2 exists for this port with slew control feature */ 2611 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 0u 2612 /* Indicates that pin #3 exists for this port with slew control feature */ 2613 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 0u 2614 /* Indicates that pin #4 exists for this port with slew control feature */ 2615 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 0u 2616 /* Indicates that pin #5 exists for this port with slew control feature */ 2617 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 0u 2618 /* Indicates that pin #6 exists for this port with slew control feature */ 2619 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 0u 2620 /* Indicates that pin #7 exists for this port with slew control feature */ 2621 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 0u 2622 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2623 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 2624 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2625 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 2626 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2627 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 2628 /* Indicates that pin #0 exists for this port with slew control feature */ 2629 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u 2630 /* Indicates that pin #1 exists for this port with slew control feature */ 2631 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 0u 2632 /* Indicates that pin #2 exists for this port with slew control feature */ 2633 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 0u 2634 /* Indicates that pin #3 exists for this port with slew control feature */ 2635 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 0u 2636 /* Indicates that pin #4 exists for this port with slew control feature */ 2637 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 0u 2638 /* Indicates that pin #5 exists for this port with slew control feature */ 2639 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 0u 2640 /* Indicates that pin #6 exists for this port with slew control feature */ 2641 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 0u 2642 /* Indicates that pin #7 exists for this port with slew control feature */ 2643 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 0u 2644 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2645 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 2646 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2647 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 2648 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2649 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 1u 2650 /* Indicates that pin #0 exists for this port with slew control feature */ 2651 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u 2652 /* Indicates that pin #1 exists for this port with slew control feature */ 2653 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u 2654 /* Indicates that pin #2 exists for this port with slew control feature */ 2655 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 2656 /* Indicates that pin #3 exists for this port with slew control feature */ 2657 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 2658 /* Indicates that pin #4 exists for this port with slew control feature */ 2659 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 2660 /* Indicates that pin #5 exists for this port with slew control feature */ 2661 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 2662 /* Indicates that pin #6 exists for this port with slew control feature */ 2663 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 0u 2664 /* Indicates that pin #7 exists for this port with slew control feature */ 2665 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 0u 2666 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2667 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 2668 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2669 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 2670 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2671 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 1u 2672 /* Indicates that pin #0 exists for this port with slew control feature */ 2673 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 2674 /* Indicates that pin #1 exists for this port with slew control feature */ 2675 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 2676 /* Indicates that pin #2 exists for this port with slew control feature */ 2677 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 2678 /* Indicates that pin #3 exists for this port with slew control feature */ 2679 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 2680 /* Indicates that pin #4 exists for this port with slew control feature */ 2681 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 2682 /* Indicates that pin #5 exists for this port with slew control feature */ 2683 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 2684 /* Indicates that pin #6 exists for this port with slew control feature */ 2685 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 2686 /* Indicates that pin #7 exists for this port with slew control feature */ 2687 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 2688 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2689 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 1u 2690 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2691 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 2692 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2693 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 1u 2694 /* Indicates that pin #0 exists for this port with slew control feature */ 2695 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 0u 2696 /* Indicates that pin #1 exists for this port with slew control feature */ 2697 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 0u 2698 /* Indicates that pin #2 exists for this port with slew control feature */ 2699 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 2700 /* Indicates that pin #3 exists for this port with slew control feature */ 2701 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 2702 /* Indicates that pin #4 exists for this port with slew control feature */ 2703 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 2704 /* Indicates that pin #5 exists for this port with slew control feature */ 2705 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 2706 /* Indicates that pin #6 exists for this port with slew control feature */ 2707 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 2708 /* Indicates that pin #7 exists for this port with slew control feature */ 2709 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 2710 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2711 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_GPIO 1u 2712 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2713 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SIO 0u 2714 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2715 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_AUTOLVL 1u 2716 /* Indicates that pin #0 exists for this port with slew control feature */ 2717 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO0 0u 2718 /* Indicates that pin #1 exists for this port with slew control feature */ 2719 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO1 0u 2720 /* Indicates that pin #2 exists for this port with slew control feature */ 2721 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO2 0u 2722 /* Indicates that pin #3 exists for this port with slew control feature */ 2723 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO3 0u 2724 /* Indicates that pin #4 exists for this port with slew control feature */ 2725 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO4 0u 2726 /* Indicates that pin #5 exists for this port with slew control feature */ 2727 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO5 0u 2728 /* Indicates that pin #6 exists for this port with slew control feature */ 2729 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO6 0u 2730 /* Indicates that pin #7 exists for this port with slew control feature */ 2731 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO7 0u 2732 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2733 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_GPIO 1u 2734 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2735 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SIO 0u 2736 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2737 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_AUTOLVL 1u 2738 /* Indicates that pin #0 exists for this port with slew control feature */ 2739 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO0 0u 2740 /* Indicates that pin #1 exists for this port with slew control feature */ 2741 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO1 0u 2742 /* Indicates that pin #2 exists for this port with slew control feature */ 2743 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO2 0u 2744 /* Indicates that pin #3 exists for this port with slew control feature */ 2745 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO3 0u 2746 /* Indicates that pin #4 exists for this port with slew control feature */ 2747 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO4 0u 2748 /* Indicates that pin #5 exists for this port with slew control feature */ 2749 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO5 0u 2750 /* Indicates that pin #6 exists for this port with slew control feature */ 2751 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO6 0u 2752 /* Indicates that pin #7 exists for this port with slew control feature */ 2753 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO7 0u 2754 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2755 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_GPIO 1u 2756 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2757 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SIO 0u 2758 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2759 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_AUTOLVL 1u 2760 /* Indicates that pin #0 exists for this port with slew control feature */ 2761 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO0 0u 2762 /* Indicates that pin #1 exists for this port with slew control feature */ 2763 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO1 0u 2764 /* Indicates that pin #2 exists for this port with slew control feature */ 2765 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO2 0u 2766 /* Indicates that pin #3 exists for this port with slew control feature */ 2767 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO3 0u 2768 /* Indicates that pin #4 exists for this port with slew control feature */ 2769 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO4 0u 2770 /* Indicates that pin #5 exists for this port with slew control feature */ 2771 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO5 0u 2772 /* Indicates that pin #6 exists for this port with slew control feature */ 2773 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO6 0u 2774 /* Indicates that pin #7 exists for this port with slew control feature */ 2775 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO7 0u 2776 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2777 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_GPIO 1u 2778 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2779 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SIO 0u 2780 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2781 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_AUTOLVL 1u 2782 /* Indicates that pin #0 exists for this port with slew control feature */ 2783 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO0 0u 2784 /* Indicates that pin #1 exists for this port with slew control feature */ 2785 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO1 0u 2786 /* Indicates that pin #2 exists for this port with slew control feature */ 2787 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO2 0u 2788 /* Indicates that pin #3 exists for this port with slew control feature */ 2789 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO3 0u 2790 /* Indicates that pin #4 exists for this port with slew control feature */ 2791 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO4 0u 2792 /* Indicates that pin #5 exists for this port with slew control feature */ 2793 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO5 0u 2794 /* Indicates that pin #6 exists for this port with slew control feature */ 2795 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO6 0u 2796 /* Indicates that pin #7 exists for this port with slew control feature */ 2797 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO7 0u 2798 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2799 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_GPIO 1u 2800 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2801 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SIO 0u 2802 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2803 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_AUTOLVL 1u 2804 /* Indicates that pin #0 exists for this port with slew control feature */ 2805 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO0 0u 2806 /* Indicates that pin #1 exists for this port with slew control feature */ 2807 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO1 0u 2808 /* Indicates that pin #2 exists for this port with slew control feature */ 2809 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO2 0u 2810 /* Indicates that pin #3 exists for this port with slew control feature */ 2811 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO3 0u 2812 /* Indicates that pin #4 exists for this port with slew control feature */ 2813 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO4 0u 2814 /* Indicates that pin #5 exists for this port with slew control feature */ 2815 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO5 0u 2816 /* Indicates that pin #6 exists for this port with slew control feature */ 2817 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO6 0u 2818 /* Indicates that pin #7 exists for this port with slew control feature */ 2819 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO7 0u 2820 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2821 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_GPIO 1u 2822 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2823 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SIO 0u 2824 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2825 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_AUTOLVL 1u 2826 /* Indicates that pin #0 exists for this port with slew control feature */ 2827 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO0 0u 2828 /* Indicates that pin #1 exists for this port with slew control feature */ 2829 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO1 0u 2830 /* Indicates that pin #2 exists for this port with slew control feature */ 2831 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO2 0u 2832 /* Indicates that pin #3 exists for this port with slew control feature */ 2833 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO3 0u 2834 /* Indicates that pin #4 exists for this port with slew control feature */ 2835 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO4 0u 2836 /* Indicates that pin #5 exists for this port with slew control feature */ 2837 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO5 0u 2838 /* Indicates that pin #6 exists for this port with slew control feature */ 2839 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO6 0u 2840 /* Indicates that pin #7 exists for this port with slew control feature */ 2841 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO7 0u 2842 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2843 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_GPIO 1u 2844 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2845 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SIO 0u 2846 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2847 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_AUTOLVL 1u 2848 /* Indicates that pin #0 exists for this port with slew control feature */ 2849 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO0 0u 2850 /* Indicates that pin #1 exists for this port with slew control feature */ 2851 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO1 0u 2852 /* Indicates that pin #2 exists for this port with slew control feature */ 2853 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO2 0u 2854 /* Indicates that pin #3 exists for this port with slew control feature */ 2855 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO3 0u 2856 /* Indicates that pin #4 exists for this port with slew control feature */ 2857 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO4 0u 2858 /* Indicates that pin #5 exists for this port with slew control feature */ 2859 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO5 0u 2860 /* Indicates that pin #6 exists for this port with slew control feature */ 2861 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO6 0u 2862 /* Indicates that pin #7 exists for this port with slew control feature */ 2863 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO7 0u 2864 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2865 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_GPIO 1u 2866 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2867 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SIO 0u 2868 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2869 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_AUTOLVL 1u 2870 /* Indicates that pin #0 exists for this port with slew control feature */ 2871 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO0 0u 2872 /* Indicates that pin #1 exists for this port with slew control feature */ 2873 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO1 0u 2874 /* Indicates that pin #2 exists for this port with slew control feature */ 2875 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO2 0u 2876 /* Indicates that pin #3 exists for this port with slew control feature */ 2877 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO3 0u 2878 /* Indicates that pin #4 exists for this port with slew control feature */ 2879 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO4 0u 2880 /* Indicates that pin #5 exists for this port with slew control feature */ 2881 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO5 0u 2882 /* Indicates that pin #6 exists for this port with slew control feature */ 2883 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO6 0u 2884 /* Indicates that pin #7 exists for this port with slew control feature */ 2885 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO7 0u 2886 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2887 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_GPIO 1u 2888 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2889 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SIO 0u 2890 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2891 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_AUTOLVL 1u 2892 /* Indicates that pin #0 exists for this port with slew control feature */ 2893 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO0 0u 2894 /* Indicates that pin #1 exists for this port with slew control feature */ 2895 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO1 0u 2896 /* Indicates that pin #2 exists for this port with slew control feature */ 2897 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO2 0u 2898 /* Indicates that pin #3 exists for this port with slew control feature */ 2899 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO3 0u 2900 /* Indicates that pin #4 exists for this port with slew control feature */ 2901 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO4 0u 2902 /* Indicates that pin #5 exists for this port with slew control feature */ 2903 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO5 0u 2904 /* Indicates that pin #6 exists for this port with slew control feature */ 2905 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO6 0u 2906 /* Indicates that pin #7 exists for this port with slew control feature */ 2907 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO7 0u 2908 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2909 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_GPIO 1u 2910 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2911 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SIO 0u 2912 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2913 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_AUTOLVL 1u 2914 /* Indicates that pin #0 exists for this port with slew control feature */ 2915 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO0 0u 2916 /* Indicates that pin #1 exists for this port with slew control feature */ 2917 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO1 0u 2918 /* Indicates that pin #2 exists for this port with slew control feature */ 2919 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO2 0u 2920 /* Indicates that pin #3 exists for this port with slew control feature */ 2921 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO3 0u 2922 /* Indicates that pin #4 exists for this port with slew control feature */ 2923 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO4 0u 2924 /* Indicates that pin #5 exists for this port with slew control feature */ 2925 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO5 0u 2926 /* Indicates that pin #6 exists for this port with slew control feature */ 2927 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO6 0u 2928 /* Indicates that pin #7 exists for this port with slew control feature */ 2929 #define IOSS_GPIO_GPIO_PORT_NR24_GPIO_PRT_SLOW_IO7 0u 2930 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2931 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_GPIO 1u 2932 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2933 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SIO 0u 2934 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2935 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_AUTOLVL 1u 2936 /* Indicates that pin #0 exists for this port with slew control feature */ 2937 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO0 0u 2938 /* Indicates that pin #1 exists for this port with slew control feature */ 2939 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO1 0u 2940 /* Indicates that pin #2 exists for this port with slew control feature */ 2941 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO2 0u 2942 /* Indicates that pin #3 exists for this port with slew control feature */ 2943 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO3 0u 2944 /* Indicates that pin #4 exists for this port with slew control feature */ 2945 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO4 0u 2946 /* Indicates that pin #5 exists for this port with slew control feature */ 2947 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO5 0u 2948 /* Indicates that pin #6 exists for this port with slew control feature */ 2949 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO6 0u 2950 /* Indicates that pin #7 exists for this port with slew control feature */ 2951 #define IOSS_GPIO_GPIO_PORT_NR25_GPIO_PRT_SLOW_IO7 0u 2952 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2953 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_GPIO 1u 2954 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2955 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SIO 0u 2956 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2957 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_AUTOLVL 1u 2958 /* Indicates that pin #0 exists for this port with slew control feature */ 2959 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO0 0u 2960 /* Indicates that pin #1 exists for this port with slew control feature */ 2961 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO1 0u 2962 /* Indicates that pin #2 exists for this port with slew control feature */ 2963 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO2 0u 2964 /* Indicates that pin #3 exists for this port with slew control feature */ 2965 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO3 0u 2966 /* Indicates that pin #4 exists for this port with slew control feature */ 2967 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO4 0u 2968 /* Indicates that pin #5 exists for this port with slew control feature */ 2969 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO5 0u 2970 /* Indicates that pin #6 exists for this port with slew control feature */ 2971 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO6 0u 2972 /* Indicates that pin #7 exists for this port with slew control feature */ 2973 #define IOSS_GPIO_GPIO_PORT_NR26_GPIO_PRT_SLOW_IO7 0u 2974 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2975 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_GPIO 1u 2976 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2977 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SIO 0u 2978 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2979 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_AUTOLVL 1u 2980 /* Indicates that pin #0 exists for this port with slew control feature */ 2981 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO0 0u 2982 /* Indicates that pin #1 exists for this port with slew control feature */ 2983 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO1 0u 2984 /* Indicates that pin #2 exists for this port with slew control feature */ 2985 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO2 0u 2986 /* Indicates that pin #3 exists for this port with slew control feature */ 2987 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO3 0u 2988 /* Indicates that pin #4 exists for this port with slew control feature */ 2989 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO4 0u 2990 /* Indicates that pin #5 exists for this port with slew control feature */ 2991 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO5 0u 2992 /* Indicates that pin #6 exists for this port with slew control feature */ 2993 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO6 0u 2994 /* Indicates that pin #7 exists for this port with slew control feature */ 2995 #define IOSS_GPIO_GPIO_PORT_NR27_GPIO_PRT_SLOW_IO7 0u 2996 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2997 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_GPIO 1u 2998 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2999 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SIO 0u 3000 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3001 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_AUTOLVL 1u 3002 /* Indicates that pin #0 exists for this port with slew control feature */ 3003 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO0 0u 3004 /* Indicates that pin #1 exists for this port with slew control feature */ 3005 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO1 0u 3006 /* Indicates that pin #2 exists for this port with slew control feature */ 3007 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO2 0u 3008 /* Indicates that pin #3 exists for this port with slew control feature */ 3009 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO3 0u 3010 /* Indicates that pin #4 exists for this port with slew control feature */ 3011 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO4 0u 3012 /* Indicates that pin #5 exists for this port with slew control feature */ 3013 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO5 0u 3014 /* Indicates that pin #6 exists for this port with slew control feature */ 3015 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO6 0u 3016 /* Indicates that pin #7 exists for this port with slew control feature */ 3017 #define IOSS_GPIO_GPIO_PORT_NR28_GPIO_PRT_SLOW_IO7 0u 3018 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3019 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_GPIO 1u 3020 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3021 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SIO 0u 3022 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3023 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_AUTOLVL 1u 3024 /* Indicates that pin #0 exists for this port with slew control feature */ 3025 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO0 0u 3026 /* Indicates that pin #1 exists for this port with slew control feature */ 3027 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO1 0u 3028 /* Indicates that pin #2 exists for this port with slew control feature */ 3029 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO2 0u 3030 /* Indicates that pin #3 exists for this port with slew control feature */ 3031 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO3 0u 3032 /* Indicates that pin #4 exists for this port with slew control feature */ 3033 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO4 0u 3034 /* Indicates that pin #5 exists for this port with slew control feature */ 3035 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO5 0u 3036 /* Indicates that pin #6 exists for this port with slew control feature */ 3037 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO6 0u 3038 /* Indicates that pin #7 exists for this port with slew control feature */ 3039 #define IOSS_GPIO_GPIO_PORT_NR29_GPIO_PRT_SLOW_IO7 0u 3040 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3041 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_GPIO 1u 3042 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3043 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SIO 0u 3044 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3045 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_AUTOLVL 1u 3046 /* Indicates that pin #0 exists for this port with slew control feature */ 3047 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO0 0u 3048 /* Indicates that pin #1 exists for this port with slew control feature */ 3049 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO1 0u 3050 /* Indicates that pin #2 exists for this port with slew control feature */ 3051 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO2 0u 3052 /* Indicates that pin #3 exists for this port with slew control feature */ 3053 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO3 0u 3054 /* Indicates that pin #4 exists for this port with slew control feature */ 3055 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO4 0u 3056 /* Indicates that pin #5 exists for this port with slew control feature */ 3057 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO5 0u 3058 /* Indicates that pin #6 exists for this port with slew control feature */ 3059 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO6 0u 3060 /* Indicates that pin #7 exists for this port with slew control feature */ 3061 #define IOSS_GPIO_GPIO_PORT_NR30_GPIO_PRT_SLOW_IO7 0u 3062 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3063 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_GPIO 1u 3064 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3065 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SIO 0u 3066 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3067 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_AUTOLVL 1u 3068 /* Indicates that pin #0 exists for this port with slew control feature */ 3069 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO0 0u 3070 /* Indicates that pin #1 exists for this port with slew control feature */ 3071 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO1 0u 3072 /* Indicates that pin #2 exists for this port with slew control feature */ 3073 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO2 0u 3074 /* Indicates that pin #3 exists for this port with slew control feature */ 3075 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO3 0u 3076 /* Indicates that pin #4 exists for this port with slew control feature */ 3077 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO4 0u 3078 /* Indicates that pin #5 exists for this port with slew control feature */ 3079 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO5 0u 3080 /* Indicates that pin #6 exists for this port with slew control feature */ 3081 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO6 0u 3082 /* Indicates that pin #7 exists for this port with slew control feature */ 3083 #define IOSS_GPIO_GPIO_PORT_NR31_GPIO_PRT_SLOW_IO7 0u 3084 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 3085 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_GPIO 1u 3086 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 3087 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SIO 0u 3088 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 3089 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_AUTOLVL 1u 3090 /* Indicates that pin #0 exists for this port with slew control feature */ 3091 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO0 0u 3092 /* Indicates that pin #1 exists for this port with slew control feature */ 3093 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO1 0u 3094 /* Indicates that pin #2 exists for this port with slew control feature */ 3095 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO2 0u 3096 /* Indicates that pin #3 exists for this port with slew control feature */ 3097 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO3 0u 3098 /* Indicates that pin #4 exists for this port with slew control feature */ 3099 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO4 0u 3100 /* Indicates that pin #5 exists for this port with slew control feature */ 3101 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO5 0u 3102 /* Indicates that pin #6 exists for this port with slew control feature */ 3103 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO6 0u 3104 /* Indicates that pin #7 exists for this port with slew control feature */ 3105 #define IOSS_GPIO_GPIO_PORT_NR32_GPIO_PRT_SLOW_IO7 0u 3106 /* Number of AMUX splitter cells */ 3107 #define IOSS_HSIOM_AMUX_SPLIT_NR 3u 3108 /* Number of HSIOM ports in device */ 3109 #define IOSS_HSIOM_HSIOM_PORT_NR 33u 3110 /* Number of PWR/GND MONITOR CELLs in the device */ 3111 #define IOSS_HSIOM_MONITOR_NR 22u 3112 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 3113 #define IOSS_HSIOM_MONITOR_NR_0_31 22u 3114 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 3115 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 3116 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 3117 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 3118 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 3119 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 3120 /* Indicates the presence of alternate JTAG interface */ 3121 #define IOSS_HSIOM_ALTJTAG_PRESENT 1u 3122 /* Mask of SMARTIO instances presence */ 3123 #define IOSS_SMARTIO_SMARTIO_MASK 0x0002F000u 3124 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 3125 connected), the minimal number of LIN channels is 2. */ 3126 #define LIN_CH_NR 16u 3127 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3128 #define LIN_MASTER_WIDTH 8u 3129 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 3130 #define LIN_CHIP_TOP_PLATFORM_VARIANT 2u 3131 /* Number of SAR blocks */ 3132 #define PASS_SAR_ADC_NR 3u 3133 /* Number of ADC slices. Each slice will contain one SARMUX block and optionally a 3134 SAR and associated sequencer logic. */ 3135 #define PASS_SAR_SLICE_NR 3u 3136 /* Number of SAR sequencer channels (per SAR) */ 3137 #define PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR 32u 3138 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 3139 #define PASS_SAR_SLICE_NR0_SAR_SAR_MUX_IN 32u 3140 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3141 that lower numbered slices contain the ADCs that are present. */ 3142 #define PASS_SAR_SLICE_NR0_SAR_SAR_ADC_PRESENT 1u 3143 /* Averaging logic present in SAR */ 3144 #define PASS_SAR_SLICE_NR0_SAR_SAR_AVERAGE 1u 3145 /* Range detect logic present in SAR */ 3146 #define PASS_SAR_SLICE_NR0_SAR_SAR_RANGEDET 1u 3147 /* Pulse detect logic present in SAR */ 3148 #define PASS_SAR_SLICE_NR0_SAR_SAR_PULSEDET 1u 3149 /* Number of SAR sequencer channels (per SAR) */ 3150 #define PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR 32u 3151 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 3152 #define PASS_SAR_SLICE_NR1_SAR_SAR_MUX_IN 32u 3153 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3154 that lower numbered slices contain the ADCs that are present. */ 3155 #define PASS_SAR_SLICE_NR1_SAR_SAR_ADC_PRESENT 1u 3156 /* Averaging logic present in SAR */ 3157 #define PASS_SAR_SLICE_NR1_SAR_SAR_AVERAGE 1u 3158 /* Range detect logic present in SAR */ 3159 #define PASS_SAR_SLICE_NR1_SAR_SAR_RANGEDET 1u 3160 /* Pulse detect logic present in SAR */ 3161 #define PASS_SAR_SLICE_NR1_SAR_SAR_PULSEDET 1u 3162 /* Number of SAR sequencer channels (per SAR) */ 3163 #define PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR 8u 3164 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 3165 #define PASS_SAR_SLICE_NR2_SAR_SAR_MUX_IN 8u 3166 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 3167 that lower numbered slices contain the ADCs that are present. */ 3168 #define PASS_SAR_SLICE_NR2_SAR_SAR_ADC_PRESENT 1u 3169 /* Averaging logic present in SAR */ 3170 #define PASS_SAR_SLICE_NR2_SAR_SAR_AVERAGE 1u 3171 /* Range detect logic present in SAR */ 3172 #define PASS_SAR_SLICE_NR2_SAR_SAR_RANGEDET 1u 3173 /* Pulse detect logic present in SAR */ 3174 #define PASS_SAR_SLICE_NR2_SAR_SAR_PULSEDET 1u 3175 /* Parameter that is 1 for ADC0 only if ADC1 or, if SAR_SLICE_NR > SAR_ADC_NR */ 3176 #define PASS_SAR_SAR_ADC0 1u 3177 /* The number of protection contexts ([2, 16]). */ 3178 #define PERI_PC_NR 8u 3179 /* Master interface presence mask (5 bits) */ 3180 #define PERI_MS_PRESENT 31u 3181 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 3182 #define PERI_ECC_PRESENT 1u 3183 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 3184 #define PERI_ECC_ADDR_PRESENT 1u 3185 /* Peripheral group PCLK root select */ 3186 #define PERI_GROUP_PRESENT0_PERI_GROUP_PCLK_ROOT_SEL 0u 3187 /* Clock control functionality present ('0': no, '1': yes) */ 3188 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3189 /* Slave present ('0': no, '1': yes) */ 3190 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3191 /* Slave present ('0': no, '1': yes) */ 3192 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3193 /* Slave present ('0': no, '1': yes) */ 3194 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3195 /* Slave present ('0': no, '1': yes) */ 3196 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3197 /* Slave present ('0': no, '1': yes) */ 3198 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3199 /* Slave present ('0': no, '1': yes) */ 3200 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3201 /* Slave present ('0': no, '1': yes) */ 3202 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3203 /* Slave present ('0': no, '1': yes) */ 3204 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3205 /* Slave present ('0': no, '1': yes) */ 3206 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3207 /* Slave present ('0': no, '1': yes) */ 3208 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3209 /* Slave present ('0': no, '1': yes) */ 3210 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3211 /* Slave present ('0': no, '1': yes) */ 3212 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3213 /* Slave present ('0': no, '1': yes) */ 3214 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3215 /* Slave present ('0': no, '1': yes) */ 3216 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3217 /* Slave present ('0': no, '1': yes) */ 3218 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3219 /* Slave present ('0': no, '1': yes) */ 3220 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3221 /* Peripheral group PCLK root select */ 3222 #define PERI_GROUP_PRESENT1_PERI_GROUP_PCLK_ROOT_SEL 0u 3223 /* Clock control functionality present ('0': no, '1': yes) */ 3224 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3225 /* Slave present ('0': no, '1': yes) */ 3226 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3227 /* Slave present ('0': no, '1': yes) */ 3228 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3229 /* Slave present ('0': no, '1': yes) */ 3230 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3231 /* Slave present ('0': no, '1': yes) */ 3232 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3233 /* Slave present ('0': no, '1': yes) */ 3234 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3235 /* Slave present ('0': no, '1': yes) */ 3236 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3237 /* Slave present ('0': no, '1': yes) */ 3238 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3239 /* Slave present ('0': no, '1': yes) */ 3240 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3241 /* Slave present ('0': no, '1': yes) */ 3242 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3243 /* Slave present ('0': no, '1': yes) */ 3244 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3245 /* Slave present ('0': no, '1': yes) */ 3246 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3247 /* Slave present ('0': no, '1': yes) */ 3248 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3249 /* Slave present ('0': no, '1': yes) */ 3250 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3251 /* Slave present ('0': no, '1': yes) */ 3252 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3253 /* Slave present ('0': no, '1': yes) */ 3254 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3255 /* Slave present ('0': no, '1': yes) */ 3256 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3257 /* Peripheral group PCLK root select */ 3258 #define PERI_GROUP_PRESENT2_PERI_GROUP_PCLK_ROOT_SEL 0u 3259 /* Clock control functionality present ('0': no, '1': yes) */ 3260 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3261 /* Slave present ('0': no, '1': yes) */ 3262 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3263 /* Slave present ('0': no, '1': yes) */ 3264 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3265 /* Slave present ('0': no, '1': yes) */ 3266 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3267 /* Slave present ('0': no, '1': yes) */ 3268 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3269 /* Slave present ('0': no, '1': yes) */ 3270 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3271 /* Slave present ('0': no, '1': yes) */ 3272 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u 3273 /* Slave present ('0': no, '1': yes) */ 3274 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 3275 /* Slave present ('0': no, '1': yes) */ 3276 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 3277 /* Slave present ('0': no, '1': yes) */ 3278 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 3279 /* Slave present ('0': no, '1': yes) */ 3280 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 3281 /* Slave present ('0': no, '1': yes) */ 3282 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 3283 /* Slave present ('0': no, '1': yes) */ 3284 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 1u 3285 /* Slave present ('0': no, '1': yes) */ 3286 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3287 /* Slave present ('0': no, '1': yes) */ 3288 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3289 /* Slave present ('0': no, '1': yes) */ 3290 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3291 /* Slave present ('0': no, '1': yes) */ 3292 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3293 /* Peripheral group PCLK root select */ 3294 #define PERI_GROUP_PRESENT3_PERI_GROUP_PCLK_ROOT_SEL 0u 3295 /* Clock control functionality present ('0': no, '1': yes) */ 3296 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3297 /* Slave present ('0': no, '1': yes) */ 3298 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3299 /* Slave present ('0': no, '1': yes) */ 3300 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3301 /* Slave present ('0': no, '1': yes) */ 3302 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3303 /* Slave present ('0': no, '1': yes) */ 3304 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3305 /* Slave present ('0': no, '1': yes) */ 3306 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3307 /* Slave present ('0': no, '1': yes) */ 3308 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3309 /* Slave present ('0': no, '1': yes) */ 3310 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3311 /* Slave present ('0': no, '1': yes) */ 3312 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3313 /* Slave present ('0': no, '1': yes) */ 3314 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3315 /* Slave present ('0': no, '1': yes) */ 3316 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3317 /* Slave present ('0': no, '1': yes) */ 3318 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3319 /* Slave present ('0': no, '1': yes) */ 3320 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3321 /* Slave present ('0': no, '1': yes) */ 3322 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3323 /* Slave present ('0': no, '1': yes) */ 3324 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3325 /* Slave present ('0': no, '1': yes) */ 3326 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3327 /* Slave present ('0': no, '1': yes) */ 3328 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3329 /* Peripheral group PCLK root select */ 3330 #define PERI_GROUP_PRESENT4_PERI_GROUP_PCLK_ROOT_SEL 0u 3331 /* Clock control functionality present ('0': no, '1': yes) */ 3332 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3333 /* Slave present ('0': no, '1': yes) */ 3334 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3335 /* Slave present ('0': no, '1': yes) */ 3336 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3337 /* Slave present ('0': no, '1': yes) */ 3338 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3339 /* Slave present ('0': no, '1': yes) */ 3340 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3341 /* Slave present ('0': no, '1': yes) */ 3342 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3343 /* Slave present ('0': no, '1': yes) */ 3344 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3345 /* Slave present ('0': no, '1': yes) */ 3346 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3347 /* Slave present ('0': no, '1': yes) */ 3348 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3349 /* Slave present ('0': no, '1': yes) */ 3350 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3351 /* Slave present ('0': no, '1': yes) */ 3352 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3353 /* Slave present ('0': no, '1': yes) */ 3354 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3355 /* Slave present ('0': no, '1': yes) */ 3356 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3357 /* Slave present ('0': no, '1': yes) */ 3358 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3359 /* Slave present ('0': no, '1': yes) */ 3360 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3361 /* Slave present ('0': no, '1': yes) */ 3362 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3363 /* Slave present ('0': no, '1': yes) */ 3364 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3365 /* Peripheral group PCLK root select */ 3366 #define PERI_GROUP_PRESENT5_PERI_GROUP_PCLK_ROOT_SEL 1u 3367 /* Clock control functionality present ('0': no, '1': yes) */ 3368 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3369 /* Slave present ('0': no, '1': yes) */ 3370 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3371 /* Slave present ('0': no, '1': yes) */ 3372 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3373 /* Slave present ('0': no, '1': yes) */ 3374 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3375 /* Slave present ('0': no, '1': yes) */ 3376 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3377 /* Slave present ('0': no, '1': yes) */ 3378 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3379 /* Slave present ('0': no, '1': yes) */ 3380 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3381 /* Slave present ('0': no, '1': yes) */ 3382 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3383 /* Slave present ('0': no, '1': yes) */ 3384 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3385 /* Slave present ('0': no, '1': yes) */ 3386 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3387 /* Slave present ('0': no, '1': yes) */ 3388 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3389 /* Slave present ('0': no, '1': yes) */ 3390 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3391 /* Slave present ('0': no, '1': yes) */ 3392 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3393 /* Slave present ('0': no, '1': yes) */ 3394 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3395 /* Slave present ('0': no, '1': yes) */ 3396 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3397 /* Slave present ('0': no, '1': yes) */ 3398 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3399 /* Slave present ('0': no, '1': yes) */ 3400 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3401 /* Peripheral group PCLK root select */ 3402 #define PERI_GROUP_PRESENT6_PERI_GROUP_PCLK_ROOT_SEL 1u 3403 /* Clock control functionality present ('0': no, '1': yes) */ 3404 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3405 /* Slave present ('0': no, '1': yes) */ 3406 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3407 /* Slave present ('0': no, '1': yes) */ 3408 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3409 /* Slave present ('0': no, '1': yes) */ 3410 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3411 /* Slave present ('0': no, '1': yes) */ 3412 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3413 /* Slave present ('0': no, '1': yes) */ 3414 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3415 /* Slave present ('0': no, '1': yes) */ 3416 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 3417 /* Slave present ('0': no, '1': yes) */ 3418 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 3419 /* Slave present ('0': no, '1': yes) */ 3420 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u 3421 /* Slave present ('0': no, '1': yes) */ 3422 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u 3423 /* Slave present ('0': no, '1': yes) */ 3424 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u 3425 /* Slave present ('0': no, '1': yes) */ 3426 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 1u 3427 /* Slave present ('0': no, '1': yes) */ 3428 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3429 /* Slave present ('0': no, '1': yes) */ 3430 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3431 /* Slave present ('0': no, '1': yes) */ 3432 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3433 /* Slave present ('0': no, '1': yes) */ 3434 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3435 /* Slave present ('0': no, '1': yes) */ 3436 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3437 /* Peripheral group PCLK root select */ 3438 #define PERI_GROUP_PRESENT7_PERI_GROUP_PCLK_ROOT_SEL 0u 3439 /* Clock control functionality present ('0': no, '1': yes) */ 3440 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3441 /* Slave present ('0': no, '1': yes) */ 3442 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3443 /* Slave present ('0': no, '1': yes) */ 3444 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3445 /* Slave present ('0': no, '1': yes) */ 3446 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3447 /* Slave present ('0': no, '1': yes) */ 3448 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3449 /* Slave present ('0': no, '1': yes) */ 3450 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3451 /* Slave present ('0': no, '1': yes) */ 3452 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3453 /* Slave present ('0': no, '1': yes) */ 3454 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3455 /* Slave present ('0': no, '1': yes) */ 3456 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3457 /* Slave present ('0': no, '1': yes) */ 3458 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3459 /* Slave present ('0': no, '1': yes) */ 3460 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3461 /* Slave present ('0': no, '1': yes) */ 3462 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3463 /* Slave present ('0': no, '1': yes) */ 3464 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3465 /* Slave present ('0': no, '1': yes) */ 3466 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3467 /* Slave present ('0': no, '1': yes) */ 3468 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3469 /* Slave present ('0': no, '1': yes) */ 3470 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3471 /* Slave present ('0': no, '1': yes) */ 3472 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3473 /* Peripheral group PCLK root select */ 3474 #define PERI_GROUP_PRESENT8_PERI_GROUP_PCLK_ROOT_SEL 0u 3475 /* Clock control functionality present ('0': no, '1': yes) */ 3476 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3477 /* Slave present ('0': no, '1': yes) */ 3478 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3479 /* Slave present ('0': no, '1': yes) */ 3480 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3481 /* Slave present ('0': no, '1': yes) */ 3482 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3483 /* Slave present ('0': no, '1': yes) */ 3484 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3485 /* Slave present ('0': no, '1': yes) */ 3486 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3487 /* Slave present ('0': no, '1': yes) */ 3488 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3489 /* Slave present ('0': no, '1': yes) */ 3490 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3491 /* Slave present ('0': no, '1': yes) */ 3492 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3493 /* Slave present ('0': no, '1': yes) */ 3494 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3495 /* Slave present ('0': no, '1': yes) */ 3496 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3497 /* Slave present ('0': no, '1': yes) */ 3498 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3499 /* Slave present ('0': no, '1': yes) */ 3500 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3501 /* Slave present ('0': no, '1': yes) */ 3502 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3503 /* Slave present ('0': no, '1': yes) */ 3504 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3505 /* Slave present ('0': no, '1': yes) */ 3506 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3507 /* Slave present ('0': no, '1': yes) */ 3508 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3509 /* Peripheral group PCLK root select */ 3510 #define PERI_GROUP_PRESENT9_PERI_GROUP_PCLK_ROOT_SEL 1u 3511 /* Clock control functionality present ('0': no, '1': yes) */ 3512 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3513 /* Slave present ('0': no, '1': yes) */ 3514 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3515 /* Slave present ('0': no, '1': yes) */ 3516 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3517 /* Slave present ('0': no, '1': yes) */ 3518 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3519 /* Slave present ('0': no, '1': yes) */ 3520 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3521 /* Slave present ('0': no, '1': yes) */ 3522 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3523 /* Slave present ('0': no, '1': yes) */ 3524 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3525 /* Slave present ('0': no, '1': yes) */ 3526 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3527 /* Slave present ('0': no, '1': yes) */ 3528 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3529 /* Slave present ('0': no, '1': yes) */ 3530 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3531 /* Slave present ('0': no, '1': yes) */ 3532 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3533 /* Slave present ('0': no, '1': yes) */ 3534 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3535 /* Slave present ('0': no, '1': yes) */ 3536 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3537 /* Slave present ('0': no, '1': yes) */ 3538 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3539 /* Slave present ('0': no, '1': yes) */ 3540 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3541 /* Slave present ('0': no, '1': yes) */ 3542 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3543 /* Slave present ('0': no, '1': yes) */ 3544 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3545 /* Peripheral group PCLK root select */ 3546 #define PERI_GROUP_PRESENT10_PERI_GROUP_PCLK_ROOT_SEL 0u 3547 /* Clock control functionality present ('0': no, '1': yes) */ 3548 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3549 /* Slave present ('0': no, '1': yes) */ 3550 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3551 /* Slave present ('0': no, '1': yes) */ 3552 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3553 /* Slave present ('0': no, '1': yes) */ 3554 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3555 /* Slave present ('0': no, '1': yes) */ 3556 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3557 /* Slave present ('0': no, '1': yes) */ 3558 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3559 /* Slave present ('0': no, '1': yes) */ 3560 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3561 /* Slave present ('0': no, '1': yes) */ 3562 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3563 /* Slave present ('0': no, '1': yes) */ 3564 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3565 /* Slave present ('0': no, '1': yes) */ 3566 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3567 /* Slave present ('0': no, '1': yes) */ 3568 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3569 /* Slave present ('0': no, '1': yes) */ 3570 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3571 /* Slave present ('0': no, '1': yes) */ 3572 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3573 /* Slave present ('0': no, '1': yes) */ 3574 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3575 /* Slave present ('0': no, '1': yes) */ 3576 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3577 /* Slave present ('0': no, '1': yes) */ 3578 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3579 /* Slave present ('0': no, '1': yes) */ 3580 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3581 /* Peripheral group PCLK root select */ 3582 #define PERI_GROUP_PRESENT11_PERI_GROUP_PCLK_ROOT_SEL 0u 3583 /* Clock control functionality present ('0': no, '1': yes) */ 3584 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3585 /* Slave present ('0': no, '1': yes) */ 3586 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3587 /* Slave present ('0': no, '1': yes) */ 3588 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3589 /* Slave present ('0': no, '1': yes) */ 3590 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3591 /* Slave present ('0': no, '1': yes) */ 3592 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3593 /* Slave present ('0': no, '1': yes) */ 3594 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3595 /* Slave present ('0': no, '1': yes) */ 3596 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3597 /* Slave present ('0': no, '1': yes) */ 3598 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3599 /* Slave present ('0': no, '1': yes) */ 3600 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3601 /* Slave present ('0': no, '1': yes) */ 3602 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3603 /* Slave present ('0': no, '1': yes) */ 3604 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3605 /* Slave present ('0': no, '1': yes) */ 3606 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3607 /* Slave present ('0': no, '1': yes) */ 3608 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3609 /* Slave present ('0': no, '1': yes) */ 3610 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3611 /* Slave present ('0': no, '1': yes) */ 3612 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3613 /* Slave present ('0': no, '1': yes) */ 3614 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3615 /* Slave present ('0': no, '1': yes) */ 3616 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3617 /* Peripheral group PCLK root select */ 3618 #define PERI_GROUP_PRESENT12_PERI_GROUP_PCLK_ROOT_SEL 0u 3619 /* Clock control functionality present ('0': no, '1': yes) */ 3620 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3621 /* Slave present ('0': no, '1': yes) */ 3622 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3623 /* Slave present ('0': no, '1': yes) */ 3624 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3625 /* Slave present ('0': no, '1': yes) */ 3626 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3627 /* Slave present ('0': no, '1': yes) */ 3628 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3629 /* Slave present ('0': no, '1': yes) */ 3630 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3631 /* Slave present ('0': no, '1': yes) */ 3632 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3633 /* Slave present ('0': no, '1': yes) */ 3634 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3635 /* Slave present ('0': no, '1': yes) */ 3636 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3637 /* Slave present ('0': no, '1': yes) */ 3638 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3639 /* Slave present ('0': no, '1': yes) */ 3640 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3641 /* Slave present ('0': no, '1': yes) */ 3642 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3643 /* Slave present ('0': no, '1': yes) */ 3644 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3645 /* Slave present ('0': no, '1': yes) */ 3646 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3647 /* Slave present ('0': no, '1': yes) */ 3648 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3649 /* Slave present ('0': no, '1': yes) */ 3650 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3651 /* Slave present ('0': no, '1': yes) */ 3652 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3653 /* Peripheral group PCLK root select */ 3654 #define PERI_GROUP_PRESENT13_PERI_GROUP_PCLK_ROOT_SEL 0u 3655 /* Clock control functionality present ('0': no, '1': yes) */ 3656 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3657 /* Slave present ('0': no, '1': yes) */ 3658 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3659 /* Slave present ('0': no, '1': yes) */ 3660 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3661 /* Slave present ('0': no, '1': yes) */ 3662 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3663 /* Slave present ('0': no, '1': yes) */ 3664 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3665 /* Slave present ('0': no, '1': yes) */ 3666 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3667 /* Slave present ('0': no, '1': yes) */ 3668 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3669 /* Slave present ('0': no, '1': yes) */ 3670 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3671 /* Slave present ('0': no, '1': yes) */ 3672 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3673 /* Slave present ('0': no, '1': yes) */ 3674 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3675 /* Slave present ('0': no, '1': yes) */ 3676 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3677 /* Slave present ('0': no, '1': yes) */ 3678 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3679 /* Slave present ('0': no, '1': yes) */ 3680 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3681 /* Slave present ('0': no, '1': yes) */ 3682 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3683 /* Slave present ('0': no, '1': yes) */ 3684 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3685 /* Slave present ('0': no, '1': yes) */ 3686 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3687 /* Slave present ('0': no, '1': yes) */ 3688 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3689 /* Peripheral group PCLK root select */ 3690 #define PERI_GROUP_PRESENT14_PERI_GROUP_PCLK_ROOT_SEL 0u 3691 /* Clock control functionality present ('0': no, '1': yes) */ 3692 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3693 /* Slave present ('0': no, '1': yes) */ 3694 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3695 /* Slave present ('0': no, '1': yes) */ 3696 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3697 /* Slave present ('0': no, '1': yes) */ 3698 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3699 /* Slave present ('0': no, '1': yes) */ 3700 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3701 /* Slave present ('0': no, '1': yes) */ 3702 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3703 /* Slave present ('0': no, '1': yes) */ 3704 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3705 /* Slave present ('0': no, '1': yes) */ 3706 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3707 /* Slave present ('0': no, '1': yes) */ 3708 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3709 /* Slave present ('0': no, '1': yes) */ 3710 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3711 /* Slave present ('0': no, '1': yes) */ 3712 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3713 /* Slave present ('0': no, '1': yes) */ 3714 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3715 /* Slave present ('0': no, '1': yes) */ 3716 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3717 /* Slave present ('0': no, '1': yes) */ 3718 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3719 /* Slave present ('0': no, '1': yes) */ 3720 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3721 /* Slave present ('0': no, '1': yes) */ 3722 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3723 /* Slave present ('0': no, '1': yes) */ 3724 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3725 /* Peripheral group PCLK root select */ 3726 #define PERI_GROUP_PRESENT15_PERI_GROUP_PCLK_ROOT_SEL 0u 3727 /* Clock control functionality present ('0': no, '1': yes) */ 3728 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3729 /* Slave present ('0': no, '1': yes) */ 3730 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3731 /* Slave present ('0': no, '1': yes) */ 3732 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3733 /* Slave present ('0': no, '1': yes) */ 3734 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3735 /* Slave present ('0': no, '1': yes) */ 3736 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3737 /* Slave present ('0': no, '1': yes) */ 3738 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3739 /* Slave present ('0': no, '1': yes) */ 3740 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3741 /* Slave present ('0': no, '1': yes) */ 3742 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3743 /* Slave present ('0': no, '1': yes) */ 3744 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3745 /* Slave present ('0': no, '1': yes) */ 3746 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3747 /* Slave present ('0': no, '1': yes) */ 3748 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3749 /* Slave present ('0': no, '1': yes) */ 3750 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3751 /* Slave present ('0': no, '1': yes) */ 3752 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3753 /* Slave present ('0': no, '1': yes) */ 3754 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3755 /* Slave present ('0': no, '1': yes) */ 3756 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3757 /* Slave present ('0': no, '1': yes) */ 3758 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3759 /* Slave present ('0': no, '1': yes) */ 3760 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3761 /* Number of asynchronous PCLK groups */ 3762 #define PERI_PCLK_GROUP_NR 2u 3763 /* Timeout functionality present ('0': no, '1': yes) */ 3764 #define PERI_TIMEOUT_PRESENT 1u 3765 /* Trigger module present ('0': no, '1': yes) */ 3766 #define PERI_TR 1u 3767 /* Number of trigger groups */ 3768 #define PERI_TR_GROUP_NR 13u 3769 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3770 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3771 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3772 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3773 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3774 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3775 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3776 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3777 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3778 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3779 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3780 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3781 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3782 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3783 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3784 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3785 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3786 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3787 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3788 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3789 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3790 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3791 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3792 #define PERI_TR_GROUP_NR11_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3793 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3794 #define PERI_TR_GROUP_NR12_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3795 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3796 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3797 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3798 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3799 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3800 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3801 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3802 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3803 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3804 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3805 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3806 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3807 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3808 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3809 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3810 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3811 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3812 #define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3813 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3814 #define PERI_TR_1TO1_GROUP_NR9_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3815 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3816 #define PERI_TR_1TO1_GROUP_NR10_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3817 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 3818 #define PERI_GR_DIV_ADDR_WIDTH 5u 3819 /* Number of asynchronous PCLK groups */ 3820 #define PERI_PERI_PCLK_PCLK_GROUP_NR 2u 3821 /* Number of 8.0 dividers */ 3822 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 3u 3823 /* Number of 16.0 dividers */ 3824 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 1u 3825 /* Number of 16.5 (fractional) dividers */ 3826 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0u 3827 /* Number of 24.5 (fractional) dividers */ 3828 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 0u 3829 /* Number of programmable clocks [1, 256] */ 3830 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT 6u 3831 /* Number of 8.0 dividers */ 3832 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 16u 3833 /* Number of 16.0 dividers */ 3834 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 17u 3835 /* Number of 16.5 (fractional) dividers */ 3836 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0u 3837 /* Number of 24.5 (fractional) dividers */ 3838 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 16u 3839 /* Number of programmable clocks [1, 256] */ 3840 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT 121u 3841 /* DeepSleep support ('0':no, '1': yes) */ 3842 #define SCB0_DEEPSLEEP 1u 3843 /* Externally clocked support? ('0': no, '1': yes) */ 3844 #define SCB0_EC 1u 3845 /* I2C master support? ('0': no, '1': yes) */ 3846 #define SCB0_I2C_M 1u 3847 /* I2C slave support? ('0': no, '1': yes) */ 3848 #define SCB0_I2C_S 1u 3849 /* I2C glitch filters present? ('0': no, '1': yes) */ 3850 #define SCB0_I2C_GLITCH 1u 3851 /* I2C support? (I2C_M | I2C_S) */ 3852 #define SCB0_I2C 1u 3853 /* I2C externally clocked support? ('0': no, '1': yes) */ 3854 #define SCB0_I2C_EC 1u 3855 /* I2C master and slave support? (I2C_M & I2C_S) */ 3856 #define SCB0_I2C_M_S 1u 3857 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3858 #define SCB0_I2C_S_EC 1u 3859 /* SPI master support? ('0': no, '1': yes) */ 3860 #define SCB0_SPI_M 1u 3861 /* SPI slave support? ('0': no, '1': yes) */ 3862 #define SCB0_SPI_S 1u 3863 /* SPI support? (SPI_M | SPI_S) */ 3864 #define SCB0_SPI 1u 3865 /* SPI externally clocked support? ('0': no, '1': yes) */ 3866 #define SCB0_SPI_EC 1u 3867 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3868 #define SCB0_SPI_S_EC 1u 3869 /* UART support? ('0': no, '1': yes) */ 3870 #define SCB0_UART 1u 3871 /* SPI or UART (SPI | UART) */ 3872 #define SCB0_SPI_UART 1u 3873 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3874 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3875 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3876 #define SCB0_EZ_DATA_NR 256u 3877 /* Command/response mode support? ('0': no, '1': yes) */ 3878 #define SCB0_CMD_RESP 1u 3879 /* EZ mode support? ('0': no, '1': yes) */ 3880 #define SCB0_EZ 1u 3881 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3882 #define SCB0_EZ_CMD_RESP 1u 3883 /* I2C slave with EZ mode (I2C_S & EZ) */ 3884 #define SCB0_I2C_S_EZ 1u 3885 /* SPI slave with EZ mode (SPI_S & EZ) */ 3886 #define SCB0_SPI_S_EZ 1u 3887 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3888 #define SCB0_MASTER_WIDTH 8u 3889 /* Number of used spi_select signals (max 4) */ 3890 #define SCB0_CHIP_TOP_SPI_SEL_NR 4u 3891 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3892 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 3893 /* DeepSleep support ('0':no, '1': yes) */ 3894 #define SCB1_DEEPSLEEP 0u 3895 /* Externally clocked support? ('0': no, '1': yes) */ 3896 #define SCB1_EC 1u 3897 /* I2C master support? ('0': no, '1': yes) */ 3898 #define SCB1_I2C_M 1u 3899 /* I2C slave support? ('0': no, '1': yes) */ 3900 #define SCB1_I2C_S 1u 3901 /* I2C glitch filters present? ('0': no, '1': yes) */ 3902 #define SCB1_I2C_GLITCH 1u 3903 /* I2C support? (I2C_M | I2C_S) */ 3904 #define SCB1_I2C 1u 3905 /* I2C externally clocked support? ('0': no, '1': yes) */ 3906 #define SCB1_I2C_EC 0u 3907 /* I2C master and slave support? (I2C_M & I2C_S) */ 3908 #define SCB1_I2C_M_S 1u 3909 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3910 #define SCB1_I2C_S_EC 0u 3911 /* SPI master support? ('0': no, '1': yes) */ 3912 #define SCB1_SPI_M 1u 3913 /* SPI slave support? ('0': no, '1': yes) */ 3914 #define SCB1_SPI_S 1u 3915 /* SPI support? (SPI_M | SPI_S) */ 3916 #define SCB1_SPI 1u 3917 /* SPI externally clocked support? ('0': no, '1': yes) */ 3918 #define SCB1_SPI_EC 1u 3919 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3920 #define SCB1_SPI_S_EC 1u 3921 /* UART support? ('0': no, '1': yes) */ 3922 #define SCB1_UART 1u 3923 /* SPI or UART (SPI | UART) */ 3924 #define SCB1_SPI_UART 1u 3925 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3926 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3927 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3928 #define SCB1_EZ_DATA_NR 256u 3929 /* Command/response mode support? ('0': no, '1': yes) */ 3930 #define SCB1_CMD_RESP 0u 3931 /* EZ mode support? ('0': no, '1': yes) */ 3932 #define SCB1_EZ 1u 3933 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3934 #define SCB1_EZ_CMD_RESP 1u 3935 /* I2C slave with EZ mode (I2C_S & EZ) */ 3936 #define SCB1_I2C_S_EZ 1u 3937 /* SPI slave with EZ mode (SPI_S & EZ) */ 3938 #define SCB1_SPI_S_EZ 1u 3939 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3940 #define SCB1_MASTER_WIDTH 8u 3941 /* Number of used spi_select signals (max 4) */ 3942 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 3943 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3944 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 3945 /* DeepSleep support ('0':no, '1': yes) */ 3946 #define SCB2_DEEPSLEEP 0u 3947 /* Externally clocked support? ('0': no, '1': yes) */ 3948 #define SCB2_EC 1u 3949 /* I2C master support? ('0': no, '1': yes) */ 3950 #define SCB2_I2C_M 1u 3951 /* I2C slave support? ('0': no, '1': yes) */ 3952 #define SCB2_I2C_S 1u 3953 /* I2C glitch filters present? ('0': no, '1': yes) */ 3954 #define SCB2_I2C_GLITCH 1u 3955 /* I2C support? (I2C_M | I2C_S) */ 3956 #define SCB2_I2C 1u 3957 /* I2C externally clocked support? ('0': no, '1': yes) */ 3958 #define SCB2_I2C_EC 0u 3959 /* I2C master and slave support? (I2C_M & I2C_S) */ 3960 #define SCB2_I2C_M_S 1u 3961 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3962 #define SCB2_I2C_S_EC 0u 3963 /* SPI master support? ('0': no, '1': yes) */ 3964 #define SCB2_SPI_M 1u 3965 /* SPI slave support? ('0': no, '1': yes) */ 3966 #define SCB2_SPI_S 1u 3967 /* SPI support? (SPI_M | SPI_S) */ 3968 #define SCB2_SPI 1u 3969 /* SPI externally clocked support? ('0': no, '1': yes) */ 3970 #define SCB2_SPI_EC 1u 3971 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3972 #define SCB2_SPI_S_EC 1u 3973 /* UART support? ('0': no, '1': yes) */ 3974 #define SCB2_UART 1u 3975 /* SPI or UART (SPI | UART) */ 3976 #define SCB2_SPI_UART 1u 3977 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3978 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3979 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3980 #define SCB2_EZ_DATA_NR 256u 3981 /* Command/response mode support? ('0': no, '1': yes) */ 3982 #define SCB2_CMD_RESP 0u 3983 /* EZ mode support? ('0': no, '1': yes) */ 3984 #define SCB2_EZ 1u 3985 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3986 #define SCB2_EZ_CMD_RESP 1u 3987 /* I2C slave with EZ mode (I2C_S & EZ) */ 3988 #define SCB2_I2C_S_EZ 1u 3989 /* SPI slave with EZ mode (SPI_S & EZ) */ 3990 #define SCB2_SPI_S_EZ 1u 3991 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3992 #define SCB2_MASTER_WIDTH 8u 3993 /* Number of used spi_select signals (max 4) */ 3994 #define SCB2_CHIP_TOP_SPI_SEL_NR 4u 3995 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3996 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 3997 /* DeepSleep support ('0':no, '1': yes) */ 3998 #define SCB3_DEEPSLEEP 0u 3999 /* Externally clocked support? ('0': no, '1': yes) */ 4000 #define SCB3_EC 1u 4001 /* I2C master support? ('0': no, '1': yes) */ 4002 #define SCB3_I2C_M 1u 4003 /* I2C slave support? ('0': no, '1': yes) */ 4004 #define SCB3_I2C_S 1u 4005 /* I2C glitch filters present? ('0': no, '1': yes) */ 4006 #define SCB3_I2C_GLITCH 1u 4007 /* I2C support? (I2C_M | I2C_S) */ 4008 #define SCB3_I2C 1u 4009 /* I2C externally clocked support? ('0': no, '1': yes) */ 4010 #define SCB3_I2C_EC 0u 4011 /* I2C master and slave support? (I2C_M & I2C_S) */ 4012 #define SCB3_I2C_M_S 1u 4013 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4014 #define SCB3_I2C_S_EC 0u 4015 /* SPI master support? ('0': no, '1': yes) */ 4016 #define SCB3_SPI_M 1u 4017 /* SPI slave support? ('0': no, '1': yes) */ 4018 #define SCB3_SPI_S 1u 4019 /* SPI support? (SPI_M | SPI_S) */ 4020 #define SCB3_SPI 1u 4021 /* SPI externally clocked support? ('0': no, '1': yes) */ 4022 #define SCB3_SPI_EC 1u 4023 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4024 #define SCB3_SPI_S_EC 1u 4025 /* UART support? ('0': no, '1': yes) */ 4026 #define SCB3_UART 1u 4027 /* SPI or UART (SPI | UART) */ 4028 #define SCB3_SPI_UART 1u 4029 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4030 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4031 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4032 #define SCB3_EZ_DATA_NR 256u 4033 /* Command/response mode support? ('0': no, '1': yes) */ 4034 #define SCB3_CMD_RESP 0u 4035 /* EZ mode support? ('0': no, '1': yes) */ 4036 #define SCB3_EZ 1u 4037 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4038 #define SCB3_EZ_CMD_RESP 1u 4039 /* I2C slave with EZ mode (I2C_S & EZ) */ 4040 #define SCB3_I2C_S_EZ 1u 4041 /* SPI slave with EZ mode (SPI_S & EZ) */ 4042 #define SCB3_SPI_S_EZ 1u 4043 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4044 #define SCB3_MASTER_WIDTH 8u 4045 /* Number of used spi_select signals (max 4) */ 4046 #define SCB3_CHIP_TOP_SPI_SEL_NR 4u 4047 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4048 #define SCB3_CHIP_TOP_I2C_FAST_PLUS 1u 4049 /* DeepSleep support ('0':no, '1': yes) */ 4050 #define SCB4_DEEPSLEEP 0u 4051 /* Externally clocked support? ('0': no, '1': yes) */ 4052 #define SCB4_EC 1u 4053 /* I2C master support? ('0': no, '1': yes) */ 4054 #define SCB4_I2C_M 1u 4055 /* I2C slave support? ('0': no, '1': yes) */ 4056 #define SCB4_I2C_S 1u 4057 /* I2C glitch filters present? ('0': no, '1': yes) */ 4058 #define SCB4_I2C_GLITCH 1u 4059 /* I2C support? (I2C_M | I2C_S) */ 4060 #define SCB4_I2C 1u 4061 /* I2C externally clocked support? ('0': no, '1': yes) */ 4062 #define SCB4_I2C_EC 0u 4063 /* I2C master and slave support? (I2C_M & I2C_S) */ 4064 #define SCB4_I2C_M_S 1u 4065 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4066 #define SCB4_I2C_S_EC 0u 4067 /* SPI master support? ('0': no, '1': yes) */ 4068 #define SCB4_SPI_M 1u 4069 /* SPI slave support? ('0': no, '1': yes) */ 4070 #define SCB4_SPI_S 1u 4071 /* SPI support? (SPI_M | SPI_S) */ 4072 #define SCB4_SPI 1u 4073 /* SPI externally clocked support? ('0': no, '1': yes) */ 4074 #define SCB4_SPI_EC 1u 4075 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4076 #define SCB4_SPI_S_EC 1u 4077 /* UART support? ('0': no, '1': yes) */ 4078 #define SCB4_UART 1u 4079 /* SPI or UART (SPI | UART) */ 4080 #define SCB4_SPI_UART 1u 4081 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4082 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4083 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4084 #define SCB4_EZ_DATA_NR 256u 4085 /* Command/response mode support? ('0': no, '1': yes) */ 4086 #define SCB4_CMD_RESP 0u 4087 /* EZ mode support? ('0': no, '1': yes) */ 4088 #define SCB4_EZ 1u 4089 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4090 #define SCB4_EZ_CMD_RESP 1u 4091 /* I2C slave with EZ mode (I2C_S & EZ) */ 4092 #define SCB4_I2C_S_EZ 1u 4093 /* SPI slave with EZ mode (SPI_S & EZ) */ 4094 #define SCB4_SPI_S_EZ 1u 4095 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4096 #define SCB4_MASTER_WIDTH 8u 4097 /* Number of used spi_select signals (max 4) */ 4098 #define SCB4_CHIP_TOP_SPI_SEL_NR 4u 4099 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4100 #define SCB4_CHIP_TOP_I2C_FAST_PLUS 1u 4101 /* DeepSleep support ('0':no, '1': yes) */ 4102 #define SCB5_DEEPSLEEP 0u 4103 /* Externally clocked support? ('0': no, '1': yes) */ 4104 #define SCB5_EC 1u 4105 /* I2C master support? ('0': no, '1': yes) */ 4106 #define SCB5_I2C_M 1u 4107 /* I2C slave support? ('0': no, '1': yes) */ 4108 #define SCB5_I2C_S 1u 4109 /* I2C glitch filters present? ('0': no, '1': yes) */ 4110 #define SCB5_I2C_GLITCH 1u 4111 /* I2C support? (I2C_M | I2C_S) */ 4112 #define SCB5_I2C 1u 4113 /* I2C externally clocked support? ('0': no, '1': yes) */ 4114 #define SCB5_I2C_EC 0u 4115 /* I2C master and slave support? (I2C_M & I2C_S) */ 4116 #define SCB5_I2C_M_S 1u 4117 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4118 #define SCB5_I2C_S_EC 0u 4119 /* SPI master support? ('0': no, '1': yes) */ 4120 #define SCB5_SPI_M 1u 4121 /* SPI slave support? ('0': no, '1': yes) */ 4122 #define SCB5_SPI_S 1u 4123 /* SPI support? (SPI_M | SPI_S) */ 4124 #define SCB5_SPI 1u 4125 /* SPI externally clocked support? ('0': no, '1': yes) */ 4126 #define SCB5_SPI_EC 1u 4127 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4128 #define SCB5_SPI_S_EC 1u 4129 /* UART support? ('0': no, '1': yes) */ 4130 #define SCB5_UART 1u 4131 /* SPI or UART (SPI | UART) */ 4132 #define SCB5_SPI_UART 1u 4133 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4134 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4135 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4136 #define SCB5_EZ_DATA_NR 256u 4137 /* Command/response mode support? ('0': no, '1': yes) */ 4138 #define SCB5_CMD_RESP 0u 4139 /* EZ mode support? ('0': no, '1': yes) */ 4140 #define SCB5_EZ 1u 4141 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4142 #define SCB5_EZ_CMD_RESP 1u 4143 /* I2C slave with EZ mode (I2C_S & EZ) */ 4144 #define SCB5_I2C_S_EZ 1u 4145 /* SPI slave with EZ mode (SPI_S & EZ) */ 4146 #define SCB5_SPI_S_EZ 1u 4147 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4148 #define SCB5_MASTER_WIDTH 8u 4149 /* Number of used spi_select signals (max 4) */ 4150 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 4151 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4152 #define SCB5_CHIP_TOP_I2C_FAST_PLUS 1u 4153 /* DeepSleep support ('0':no, '1': yes) */ 4154 #define SCB6_DEEPSLEEP 0u 4155 /* Externally clocked support? ('0': no, '1': yes) */ 4156 #define SCB6_EC 1u 4157 /* I2C master support? ('0': no, '1': yes) */ 4158 #define SCB6_I2C_M 1u 4159 /* I2C slave support? ('0': no, '1': yes) */ 4160 #define SCB6_I2C_S 1u 4161 /* I2C glitch filters present? ('0': no, '1': yes) */ 4162 #define SCB6_I2C_GLITCH 1u 4163 /* I2C support? (I2C_M | I2C_S) */ 4164 #define SCB6_I2C 1u 4165 /* I2C externally clocked support? ('0': no, '1': yes) */ 4166 #define SCB6_I2C_EC 0u 4167 /* I2C master and slave support? (I2C_M & I2C_S) */ 4168 #define SCB6_I2C_M_S 1u 4169 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4170 #define SCB6_I2C_S_EC 0u 4171 /* SPI master support? ('0': no, '1': yes) */ 4172 #define SCB6_SPI_M 1u 4173 /* SPI slave support? ('0': no, '1': yes) */ 4174 #define SCB6_SPI_S 1u 4175 /* SPI support? (SPI_M | SPI_S) */ 4176 #define SCB6_SPI 1u 4177 /* SPI externally clocked support? ('0': no, '1': yes) */ 4178 #define SCB6_SPI_EC 1u 4179 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4180 #define SCB6_SPI_S_EC 1u 4181 /* UART support? ('0': no, '1': yes) */ 4182 #define SCB6_UART 1u 4183 /* SPI or UART (SPI | UART) */ 4184 #define SCB6_SPI_UART 1u 4185 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4186 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4187 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4188 #define SCB6_EZ_DATA_NR 256u 4189 /* Command/response mode support? ('0': no, '1': yes) */ 4190 #define SCB6_CMD_RESP 0u 4191 /* EZ mode support? ('0': no, '1': yes) */ 4192 #define SCB6_EZ 1u 4193 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4194 #define SCB6_EZ_CMD_RESP 1u 4195 /* I2C slave with EZ mode (I2C_S & EZ) */ 4196 #define SCB6_I2C_S_EZ 1u 4197 /* SPI slave with EZ mode (SPI_S & EZ) */ 4198 #define SCB6_SPI_S_EZ 1u 4199 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4200 #define SCB6_MASTER_WIDTH 8u 4201 /* Number of used spi_select signals (max 4) */ 4202 #define SCB6_CHIP_TOP_SPI_SEL_NR 4u 4203 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4204 #define SCB6_CHIP_TOP_I2C_FAST_PLUS 1u 4205 /* DeepSleep support ('0':no, '1': yes) */ 4206 #define SCB7_DEEPSLEEP 0u 4207 /* Externally clocked support? ('0': no, '1': yes) */ 4208 #define SCB7_EC 1u 4209 /* I2C master support? ('0': no, '1': yes) */ 4210 #define SCB7_I2C_M 1u 4211 /* I2C slave support? ('0': no, '1': yes) */ 4212 #define SCB7_I2C_S 1u 4213 /* I2C glitch filters present? ('0': no, '1': yes) */ 4214 #define SCB7_I2C_GLITCH 1u 4215 /* I2C support? (I2C_M | I2C_S) */ 4216 #define SCB7_I2C 1u 4217 /* I2C externally clocked support? ('0': no, '1': yes) */ 4218 #define SCB7_I2C_EC 0u 4219 /* I2C master and slave support? (I2C_M & I2C_S) */ 4220 #define SCB7_I2C_M_S 1u 4221 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4222 #define SCB7_I2C_S_EC 0u 4223 /* SPI master support? ('0': no, '1': yes) */ 4224 #define SCB7_SPI_M 1u 4225 /* SPI slave support? ('0': no, '1': yes) */ 4226 #define SCB7_SPI_S 1u 4227 /* SPI support? (SPI_M | SPI_S) */ 4228 #define SCB7_SPI 1u 4229 /* SPI externally clocked support? ('0': no, '1': yes) */ 4230 #define SCB7_SPI_EC 1u 4231 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4232 #define SCB7_SPI_S_EC 1u 4233 /* UART support? ('0': no, '1': yes) */ 4234 #define SCB7_UART 1u 4235 /* SPI or UART (SPI | UART) */ 4236 #define SCB7_SPI_UART 1u 4237 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4238 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4239 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4240 #define SCB7_EZ_DATA_NR 256u 4241 /* Command/response mode support? ('0': no, '1': yes) */ 4242 #define SCB7_CMD_RESP 0u 4243 /* EZ mode support? ('0': no, '1': yes) */ 4244 #define SCB7_EZ 1u 4245 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4246 #define SCB7_EZ_CMD_RESP 1u 4247 /* I2C slave with EZ mode (I2C_S & EZ) */ 4248 #define SCB7_I2C_S_EZ 1u 4249 /* SPI slave with EZ mode (SPI_S & EZ) */ 4250 #define SCB7_SPI_S_EZ 1u 4251 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4252 #define SCB7_MASTER_WIDTH 8u 4253 /* Number of used spi_select signals (max 4) */ 4254 #define SCB7_CHIP_TOP_SPI_SEL_NR 4u 4255 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4256 #define SCB7_CHIP_TOP_I2C_FAST_PLUS 1u 4257 /* DeepSleep support ('0':no, '1': yes) */ 4258 #define SCB8_DEEPSLEEP 0u 4259 /* Externally clocked support? ('0': no, '1': yes) */ 4260 #define SCB8_EC 1u 4261 /* I2C master support? ('0': no, '1': yes) */ 4262 #define SCB8_I2C_M 1u 4263 /* I2C slave support? ('0': no, '1': yes) */ 4264 #define SCB8_I2C_S 1u 4265 /* I2C glitch filters present? ('0': no, '1': yes) */ 4266 #define SCB8_I2C_GLITCH 1u 4267 /* I2C support? (I2C_M | I2C_S) */ 4268 #define SCB8_I2C 1u 4269 /* I2C externally clocked support? ('0': no, '1': yes) */ 4270 #define SCB8_I2C_EC 0u 4271 /* I2C master and slave support? (I2C_M & I2C_S) */ 4272 #define SCB8_I2C_M_S 1u 4273 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4274 #define SCB8_I2C_S_EC 0u 4275 /* SPI master support? ('0': no, '1': yes) */ 4276 #define SCB8_SPI_M 1u 4277 /* SPI slave support? ('0': no, '1': yes) */ 4278 #define SCB8_SPI_S 1u 4279 /* SPI support? (SPI_M | SPI_S) */ 4280 #define SCB8_SPI 1u 4281 /* SPI externally clocked support? ('0': no, '1': yes) */ 4282 #define SCB8_SPI_EC 1u 4283 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4284 #define SCB8_SPI_S_EC 1u 4285 /* UART support? ('0': no, '1': yes) */ 4286 #define SCB8_UART 1u 4287 /* SPI or UART (SPI | UART) */ 4288 #define SCB8_SPI_UART 1u 4289 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4290 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4291 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4292 #define SCB8_EZ_DATA_NR 256u 4293 /* Command/response mode support? ('0': no, '1': yes) */ 4294 #define SCB8_CMD_RESP 0u 4295 /* EZ mode support? ('0': no, '1': yes) */ 4296 #define SCB8_EZ 1u 4297 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4298 #define SCB8_EZ_CMD_RESP 1u 4299 /* I2C slave with EZ mode (I2C_S & EZ) */ 4300 #define SCB8_I2C_S_EZ 1u 4301 /* SPI slave with EZ mode (SPI_S & EZ) */ 4302 #define SCB8_SPI_S_EZ 1u 4303 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4304 #define SCB8_MASTER_WIDTH 8u 4305 /* Number of used spi_select signals (max 4) */ 4306 #define SCB8_CHIP_TOP_SPI_SEL_NR 4u 4307 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4308 #define SCB8_CHIP_TOP_I2C_FAST_PLUS 1u 4309 /* DeepSleep support ('0':no, '1': yes) */ 4310 #define SCB9_DEEPSLEEP 0u 4311 /* Externally clocked support? ('0': no, '1': yes) */ 4312 #define SCB9_EC 1u 4313 /* I2C master support? ('0': no, '1': yes) */ 4314 #define SCB9_I2C_M 1u 4315 /* I2C slave support? ('0': no, '1': yes) */ 4316 #define SCB9_I2C_S 1u 4317 /* I2C glitch filters present? ('0': no, '1': yes) */ 4318 #define SCB9_I2C_GLITCH 1u 4319 /* I2C support? (I2C_M | I2C_S) */ 4320 #define SCB9_I2C 1u 4321 /* I2C externally clocked support? ('0': no, '1': yes) */ 4322 #define SCB9_I2C_EC 0u 4323 /* I2C master and slave support? (I2C_M & I2C_S) */ 4324 #define SCB9_I2C_M_S 1u 4325 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4326 #define SCB9_I2C_S_EC 0u 4327 /* SPI master support? ('0': no, '1': yes) */ 4328 #define SCB9_SPI_M 1u 4329 /* SPI slave support? ('0': no, '1': yes) */ 4330 #define SCB9_SPI_S 1u 4331 /* SPI support? (SPI_M | SPI_S) */ 4332 #define SCB9_SPI 1u 4333 /* SPI externally clocked support? ('0': no, '1': yes) */ 4334 #define SCB9_SPI_EC 1u 4335 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4336 #define SCB9_SPI_S_EC 1u 4337 /* UART support? ('0': no, '1': yes) */ 4338 #define SCB9_UART 1u 4339 /* SPI or UART (SPI | UART) */ 4340 #define SCB9_SPI_UART 1u 4341 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4342 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4343 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4344 #define SCB9_EZ_DATA_NR 256u 4345 /* Command/response mode support? ('0': no, '1': yes) */ 4346 #define SCB9_CMD_RESP 0u 4347 /* EZ mode support? ('0': no, '1': yes) */ 4348 #define SCB9_EZ 1u 4349 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4350 #define SCB9_EZ_CMD_RESP 1u 4351 /* I2C slave with EZ mode (I2C_S & EZ) */ 4352 #define SCB9_I2C_S_EZ 1u 4353 /* SPI slave with EZ mode (SPI_S & EZ) */ 4354 #define SCB9_SPI_S_EZ 1u 4355 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4356 #define SCB9_MASTER_WIDTH 8u 4357 /* Number of used spi_select signals (max 4) */ 4358 #define SCB9_CHIP_TOP_SPI_SEL_NR 4u 4359 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4360 #define SCB9_CHIP_TOP_I2C_FAST_PLUS 1u 4361 /* DeepSleep support ('0':no, '1': yes) */ 4362 #define SCB10_DEEPSLEEP 0u 4363 /* Externally clocked support? ('0': no, '1': yes) */ 4364 #define SCB10_EC 1u 4365 /* I2C master support? ('0': no, '1': yes) */ 4366 #define SCB10_I2C_M 1u 4367 /* I2C slave support? ('0': no, '1': yes) */ 4368 #define SCB10_I2C_S 1u 4369 /* I2C glitch filters present? ('0': no, '1': yes) */ 4370 #define SCB10_I2C_GLITCH 1u 4371 /* I2C support? (I2C_M | I2C_S) */ 4372 #define SCB10_I2C 1u 4373 /* I2C externally clocked support? ('0': no, '1': yes) */ 4374 #define SCB10_I2C_EC 0u 4375 /* I2C master and slave support? (I2C_M & I2C_S) */ 4376 #define SCB10_I2C_M_S 1u 4377 /* I2C slave with EC? (I2C_S & I2C_EC) */ 4378 #define SCB10_I2C_S_EC 0u 4379 /* SPI master support? ('0': no, '1': yes) */ 4380 #define SCB10_SPI_M 1u 4381 /* SPI slave support? ('0': no, '1': yes) */ 4382 #define SCB10_SPI_S 1u 4383 /* SPI support? (SPI_M | SPI_S) */ 4384 #define SCB10_SPI 1u 4385 /* SPI externally clocked support? ('0': no, '1': yes) */ 4386 #define SCB10_SPI_EC 1u 4387 /* SPI slave with EC? (SPI_S & SPI_EC) */ 4388 #define SCB10_SPI_S_EC 1u 4389 /* UART support? ('0': no, '1': yes) */ 4390 #define SCB10_UART 1u 4391 /* SPI or UART (SPI | UART) */ 4392 #define SCB10_SPI_UART 1u 4393 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 4394 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 4395 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 4396 #define SCB10_EZ_DATA_NR 256u 4397 /* Command/response mode support? ('0': no, '1': yes) */ 4398 #define SCB10_CMD_RESP 0u 4399 /* EZ mode support? ('0': no, '1': yes) */ 4400 #define SCB10_EZ 1u 4401 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 4402 #define SCB10_EZ_CMD_RESP 1u 4403 /* I2C slave with EZ mode (I2C_S & EZ) */ 4404 #define SCB10_I2C_S_EZ 1u 4405 /* SPI slave with EZ mode (SPI_S & EZ) */ 4406 #define SCB10_SPI_S_EZ 1u 4407 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4408 #define SCB10_MASTER_WIDTH 8u 4409 /* Number of used spi_select signals (max 4) */ 4410 #define SCB10_CHIP_TOP_SPI_SEL_NR 4u 4411 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 4412 #define SCB10_CHIP_TOP_I2C_FAST_PLUS 1u 4413 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 4414 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 4415 data) */ 4416 #define SDHC_MAX_BLK_SIZE 0u 4417 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 4418 adds 288 bytes of space to the RAM for this purpose. */ 4419 #define SDHC_CQE_PRESENT 0u 4420 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 4421 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 4422 parameter) */ 4423 #define SDHC_RETENTION_PRESENT 0u 4424 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 4425 pins) */ 4426 #define SDHC_CHIP_TOP_DATA8_PRESENT 1u 4427 /* Chip top connect card_detect */ 4428 #define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u 4429 /* Chip top connect card_mech_write_prot_in */ 4430 #define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u 4431 /* Chip top connect led_ctrl_out and led_ctrl_out_en */ 4432 #define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u 4433 /* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ 4434 #define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 0u 4435 /* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ 4436 #define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u 4437 /* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ 4438 #define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u 4439 /* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ 4440 #define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u 4441 /* Chip top connect interrupt_wakeup (not used for eMMC) */ 4442 #define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u 4443 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 4444 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 4445 data) */ 4446 #define SDHC_CORE_MAX_BLK_SIZE 0u 4447 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 4448 adds 288 bytes of space to the RAM for this purpose. */ 4449 #define SDHC_CORE_CQE_PRESENT 0u 4450 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 4451 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 4452 parameter) */ 4453 #define SDHC_CORE_RETENTION_PRESENT 0u 4454 /* SONOS Flash is used or not ('0': no, '1': yes) */ 4455 #define SFLASH_FLASHC_IS_SONOS 0u 4456 /* WOUND_PRESENT or not ('0': no, '1': yes) */ 4457 #define SFLASH_WOUND_PRESENT 1u 4458 /* Base address of the SMIF XIP memory region. This address must be a multiple of 4459 the SMIF XIP memory capacity. This address must be a multiple of the SMIF XIP 4460 memory region capacity (see SMIP_XIP_MASK below). The SMIF XIP memory region 4461 should NOT overlap with other memory regions. This adress must be in the 4462 [0x0000:0000, 0xffff:0000] memory region. However, for MXS40 CM4 based 4463 platform variant, this address must be in the [0x0000:0000, 0x1fff:0000] 4464 memory region (to ensure a connection to the ARM CM4 CPU ICode/DCode memory 4465 region [0x0000:0000, 0x1fff:ffff]). The external memory devices are located 4466 within the SMIF XIP memory region. */ 4467 #define SMIF_SMIF_XIP_ADDR 0x60000000u 4468 /* Capacity of the SMIF XIP memory region. The capacity must be a power of 2 and 4469 greater or equal than 64 KB). The more significant bits of this parameter are 4470 '1' and the lesser significant bits of this parameter are '0'. E.g., 4471 0xfff0:0000 specifies a 1 MB memory region. Legal values are {0xffff:0000, 4472 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 0xffe0:0000, ..., 4473 0x8000:0000, 0x0000:0000}. */ 4474 #define SMIF_SMIF_XIP_MASK 0xF8000000u 4475 /* Cryptography (AES) support. This is a 1-bit parameter: '0' = no support, '1' = 4476 support. */ 4477 #define SMIF_CRYPTO 1u 4478 /* Bus CRC support is present ([0,1]) Note: In MXS40 SMIF version 2 this option is 4479 currently not available (BUS_CRC_PRESENT=0). Based on project schedules this 4480 feature may be added already to MXS40 SMIF version 2 or to a later SMIF 4481 version. */ 4482 #define SMIF_BUS_CRC_PRESENT 0u 4483 /* Number of external memory devices supported. This parameter is in the range 4484 [1,4]. */ 4485 #define SMIF_DEVICE_NR 2u 4486 /* External memory devices write support. This is a 4-bit field. Each external 4487 memory device has a dedicated bit. E.g., if bit 2 is '1', external device 2 4488 has write support. */ 4489 #define SMIF_DEVICE_WR_EN 3u 4490 /* Number of delay lines ([1..8]). */ 4491 #define SMIF_DELAY_LINES_NR 4u 4492 /* Number of delay taps in clock delay line. */ 4493 #define SMIF_DELAY_TAPS_NR 32u 4494 /* AXI ID width. Legal range [11,16] */ 4495 #define SMIF_AXIS_ID_WIDTH 12u 4496 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4497 #define SMIF_MASTER_WIDTH 8u 4498 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 4499 pins) */ 4500 #define SMIF_CHIP_TOP_DATA8_PRESENT 1u 4501 /* Number of used spi_select signals (max 4) */ 4502 #define SMIF_CHIP_TOP_SPI_SEL_NR 2u 4503 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 4504 #define SRSS_ULP_VARIANT 0u 4505 /* HT variant. Must be 1 when targeting S40E and 0 otherwise. */ 4506 #define SRSS_HT_VARIANT 1u 4507 /* Number of regulator modules instantiated within SRSS. Must be > 0. */ 4508 #define SRSS_NUM_ACTREG_PWRMOD 6u 4509 /* Number of shorting switches between vccd and vccact. Must be > 0. */ 4510 #define SRSS_NUM_ACTIVE_SWITCH 6u 4511 /* ULP linear regulator system is present */ 4512 #define SRSS_ULPLINREG_PRESENT 0u 4513 /* HT linear regulator system is present */ 4514 #define SRSS_HTLINREG_PRESENT 1u 4515 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 4516 system (ULPLINREG_PRESENT==1). */ 4517 #define SRSS_SIMOBUCK_PRESENT 0u 4518 /* Precision ILO (PILO) is present */ 4519 #define SRSS_PILO_PRESENT 0u 4520 /* External Crystal Oscillator is present (high frequency) */ 4521 #define SRSS_ECO_PRESENT 1u 4522 /* System Buck-Boost is present */ 4523 #define SRSS_SYSBB_PRESENT 0u 4524 /* Number of PWR_HIB_DATA registers. Min is zero. */ 4525 #define SRSS_NUM_HIBDATA 1u 4526 /* Number of clock paths. Must be > 0. Recommend 4527 NUM_CLKPATH>=NUM_TOTAL_PLL+CSV_PRESENT+2. CSV and FLL requires special paths, 4528 and one extra is recommended for programming flexibility. */ 4529 #define SRSS_NUM_CLKPATH 7u 4530 /* Number of 200MHz PLLs present. */ 4531 #define SRSS_NUM_PLL 2u 4532 /* Number of HFCLK roots present. Must be > 0. Recommend NUM_HFROOT=<# chipwide 4533 roots>+CSV_PRESENT. */ 4534 #define SRSS_NUM_HFROOT 8u 4535 /* Number of DSI inputs into clock muxes. This is used for logic optimization. 4536 Must be > 0 */ 4537 #define SRSS_NUM_DSI 0u 4538 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 4539 #define SRSS_ALTHF_PRESENT 0u 4540 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 4541 #define SRSS_ALTLF_PRESENT 0u 4542 /* Backup domain is present. See VBCK_PRESENT for whether it is supplied by vddd 4543 or by an independent vbackup supply. */ 4544 #define SRSS_BACKUP_PRESENT 1u 4545 /* CSV present. User must add one NUM_CLKPATH and one NUM_HFROOT to monitor ILO0 4546 with CSV_HF_REF clock. */ 4547 #define SRSS_CSV_PRESENT 1u 4548 /* Number of multi-counter watchdog timers. Min is zero. */ 4549 #define SRSS_NUM_MCWDT 3u 4550 /* Use the hardened clkactfllmux block */ 4551 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 4552 /* Number of clock paths, including direct paths in hardened clkactfllmux block */ 4553 #define SRSS_HARD_CLKPATH 8u 4554 /* Number of clock paths with muxes in hardened clkactfllmux block */ 4555 #define SRSS_HARD_CLKPATHMUX 8u 4556 /* Number of HFCLKS present in hardened clkactfllmux block */ 4557 #define SRSS_HARD_HFROOT 8u 4558 /* ECO mux is present in hardened clkactfllmux block */ 4559 #define SRSS_HARD_ECOMUX_PRESENT 1u 4560 /* ALTHF mux is present in hardened clkactfllmux block */ 4561 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 4562 /* POR present. */ 4563 #define SRSS_POR_PRESENT 1u 4564 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 4565 or SIMOBUCK_PRESENT. */ 4566 #define SRSS_BUCKCTL_PRESENT 0u 4567 /* Low-current SISO buck core regulator is present. Only compatible with ULP 4568 linear regulator system (ULPLINREG_PRESENT==1). */ 4569 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 4570 /* HT linear regulator system is present */ 4571 #define SRSS_S40E_HTREGHC_PRESENT 1u 4572 /* LPECO mux is present in hardened clkactfllmux block */ 4573 #define SRSS_HARD_LPECOMUX_PRESENT 1u 4574 /* Number of 400MHz PLLs present. */ 4575 #define SRSS_NUM_PLL400M 2u 4576 /* Mask of DIRECT_MUX defaults. For each clock root i, if bit[i] is low the 4577 DIRECT_MUX defaults to IMO. If bit[0] is high, the DIRECT_MUX selects the 4578 output of ROOT_MUX. For backward compatibility, M4 systems can have all mask 4579 bits high. BootROM needs either Bit0 high or a code change to pick predivider 4580 output before using the FLL. */ 4581 #define SRSS_MASK_DIRECTMUX_DEF 1u 4582 /* Mask of which HFCLK roots are enabled when the debugger requests power up 4583 (CDBGPWRUPREQ). For each clock root i, SRSS enables the clock in response to 4584 CDBGPWRUPREQ, if bit[i] of mask is high. SRSS automatically enables clk_hf0, 4585 regardless of setting of mask bit0. */ 4586 #define SRSS_MASK_DEBUG_CLK 0x0000FFFFu 4587 /* Total number of PLLs present. Must be calculated (NUM_PLL+NUM_PLL400M). Cannot 4588 exceed max or NUM_CLKPATH. */ 4589 #define SRSS_NUM_TOTAL_PLL 4u 4590 /* PMIC control of vccd is present (without REGHC). */ 4591 #define SRSS_S40E_PMIC_PRESENT 0u 4592 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 4593 #define SRSS_BACKUP_VBCK_PRESENT 0u 4594 /* Alarm1 present in RTC */ 4595 #define SRSS_BACKUP_ALM1_PRESENT 1u 4596 /* Alarm2 present in RTC */ 4597 #define SRSS_BACKUP_ALM2_PRESENT 1u 4598 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 4599 #define SRSS_BACKUP_BMEM_PRESENT 0u 4600 /* Number of Backup registers to include (each is 32b). Only used when 4601 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 4602 #define SRSS_BACKUP_NUM_BREG 4u 4603 /* Low power external crystal oscillator (LPECO) is present. */ 4604 #define SRSS_BACKUP_S40E_LPECO_PRESENT 0u 4605 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 4606 #define SRSS_CLK_TRIM_PLL400M_ULP_VARIANT 0u 4607 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 4608 mask indicates presence of a CSV. */ 4609 #define SRSS_CSV_HF_MASK_HFCSV 255u 4610 /* Number of input triggers per counter only routed to one counter (0..8) */ 4611 #define TCPWM_TR_ONE_CNT_NR 3u 4612 /* Number of input triggers routed to all counters (0..254), 4613 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 4614 #define TCPWM_TR_ALL_CNT_NR 27u 4615 /* Number of TCPWM counter groups (1..4) */ 4616 #define TCPWM_GRP_NR 3u 4617 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 4618 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 16u 4619 /* Second Capture / Compare Unit is present (0, 1) */ 4620 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 1u 4621 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 4622 GRP_CC1_PRESENT = 1 */ 4623 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 4624 /* Stepper Motor Control features are present (0, 1). */ 4625 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 4626 /* Number of counters per TCPWM group (1..256) */ 4627 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 63u 4628 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 4629 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 4630 /* Second Capture / Compare Unit is present (0, 1) */ 4631 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 4632 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 4633 GRP_CC1_PRESENT = 1 */ 4634 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 4635 /* Stepper Motor Control features are present (0, 1). */ 4636 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 1u 4637 /* Number of counters per TCPWM group (1..256) */ 4638 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 12u 4639 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 4640 #define TCPWM_GRP_NR2_CNT_GRP_CNT_WIDTH 32u 4641 /* Second Capture / Compare Unit is present (0, 1) */ 4642 #define TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT 1u 4643 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 4644 GRP_CC1_PRESENT = 1 */ 4645 #define TCPWM_GRP_NR2_CNT_GRP_AMC_PRESENT 0u 4646 /* Stepper Motor Control features are present (0, 1). */ 4647 #define TCPWM_GRP_NR2_CNT_GRP_SMC_PRESENT 0u 4648 /* Number of counters per TCPWM group (1..256) */ 4649 #define TCPWM_GRP_NR2_GRP_GRP_CNT_NR 8u 4650 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4651 #define TCPWM_MASTER_WIDTH 8u 4652 4653 /* MMIO Targets Defines */ 4654 /* MMIO1.CRYPTO */ 4655 #define CY_MMIO_CRYPTO_GROUP_NR 1u 4656 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 4657 /* MMIO2.CPUSS */ 4658 #define CY_MMIO_CPUSS_GROUP_NR 2u 4659 #define CY_MMIO_CPUSS_SLAVE_NR 0u 4660 /* MMIO2.FAULT */ 4661 #define CY_MMIO_FAULT_GROUP_NR 2u 4662 #define CY_MMIO_FAULT_SLAVE_NR 1u 4663 /* MMIO2.IPC */ 4664 #define CY_MMIO_IPC_GROUP_NR 2u 4665 #define CY_MMIO_IPC_SLAVE_NR 2u 4666 /* MMIO2.PROT */ 4667 #define CY_MMIO_PROT_GROUP_NR 2u 4668 #define CY_MMIO_PROT_SLAVE_NR 3u 4669 /* MMIO2.FLASHC */ 4670 #define CY_MMIO_FLASHC_GROUP_NR 2u 4671 #define CY_MMIO_FLASHC_SLAVE_NR 4u 4672 /* MMIO2.SRSS */ 4673 #define CY_MMIO_SRSS_GROUP_NR 2u 4674 #define CY_MMIO_SRSS_SLAVE_NR 5u 4675 /* MMIO2.BACKUP */ 4676 #define CY_MMIO_BACKUP_GROUP_NR 2u 4677 #define CY_MMIO_BACKUP_SLAVE_NR 6u 4678 /* MMIO2.DW */ 4679 #define CY_MMIO_DW_GROUP_NR 2u 4680 #define CY_MMIO_DW_SLAVE_NR 7u 4681 /* MMIO2.DMAC */ 4682 #define CY_MMIO_DMAC_GROUP_NR 2u 4683 #define CY_MMIO_DMAC_SLAVE_NR 9u 4684 /* MMIO2.EFUSE */ 4685 #define CY_MMIO_EFUSE_GROUP_NR 2u 4686 #define CY_MMIO_EFUSE_SLAVE_NR 10u 4687 /* MMIO2.DFT */ 4688 #define CY_MMIO_DFT_GROUP_NR 2u 4689 #define CY_MMIO_DFT_SLAVE_NR 11u 4690 /* MMIO3.HSIOM */ 4691 #define CY_MMIO_HSIOM_GROUP_NR 3u 4692 #define CY_MMIO_HSIOM_SLAVE_NR 0u 4693 /* MMIO3.GPIO */ 4694 #define CY_MMIO_GPIO_GROUP_NR 3u 4695 #define CY_MMIO_GPIO_SLAVE_NR 1u 4696 /* MMIO3.SMARTIO */ 4697 #define CY_MMIO_SMARTIO_GROUP_NR 3u 4698 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 4699 /* MMIO3.EVTGEN0 */ 4700 #define CY_MMIO_EVTGEN0_GROUP_NR 3u 4701 #define CY_MMIO_EVTGEN0_SLAVE_NR 3u 4702 /* MMIO4.SMIF0 */ 4703 #define CY_MMIO_SMIF0_GROUP_NR 4u 4704 #define CY_MMIO_SMIF0_SLAVE_NR 0u 4705 /* MMIO4.SDHC0 */ 4706 #define CY_MMIO_SDHC0_GROUP_NR 4u 4707 #define CY_MMIO_SDHC0_SLAVE_NR 1u 4708 /* MMIO4.ETH0 */ 4709 #define CY_MMIO_ETH0_GROUP_NR 4u 4710 #define CY_MMIO_ETH0_SLAVE_NR 2u 4711 /* MMIO5.LIN0 */ 4712 #define CY_MMIO_LIN0_GROUP_NR 5u 4713 #define CY_MMIO_LIN0_SLAVE_NR 0u 4714 /* MMIO5.CANFD0 */ 4715 #define CY_MMIO_CANFD0_GROUP_NR 5u 4716 #define CY_MMIO_CANFD0_SLAVE_NR 1u 4717 /* MMIO5.CANFD1 */ 4718 #define CY_MMIO_CANFD1_GROUP_NR 5u 4719 #define CY_MMIO_CANFD1_SLAVE_NR 2u 4720 /* MMIO5.TCPWM0 */ 4721 #define CY_MMIO_TCPWM0_GROUP_NR 5u 4722 #define CY_MMIO_TCPWM0_SLAVE_NR 3u 4723 /* MMIO6.SCB0 */ 4724 #define CY_MMIO_SCB0_GROUP_NR 6u 4725 #define CY_MMIO_SCB0_SLAVE_NR 0u 4726 /* MMIO6.SCB1 */ 4727 #define CY_MMIO_SCB1_GROUP_NR 6u 4728 #define CY_MMIO_SCB1_SLAVE_NR 1u 4729 /* MMIO6.SCB2 */ 4730 #define CY_MMIO_SCB2_GROUP_NR 6u 4731 #define CY_MMIO_SCB2_SLAVE_NR 2u 4732 /* MMIO6.SCB3 */ 4733 #define CY_MMIO_SCB3_GROUP_NR 6u 4734 #define CY_MMIO_SCB3_SLAVE_NR 3u 4735 /* MMIO6.SCB4 */ 4736 #define CY_MMIO_SCB4_GROUP_NR 6u 4737 #define CY_MMIO_SCB4_SLAVE_NR 4u 4738 /* MMIO6.SCB5 */ 4739 #define CY_MMIO_SCB5_GROUP_NR 6u 4740 #define CY_MMIO_SCB5_SLAVE_NR 5u 4741 /* MMIO6.SCB6 */ 4742 #define CY_MMIO_SCB6_GROUP_NR 6u 4743 #define CY_MMIO_SCB6_SLAVE_NR 6u 4744 /* MMIO6.SCB7 */ 4745 #define CY_MMIO_SCB7_GROUP_NR 6u 4746 #define CY_MMIO_SCB7_SLAVE_NR 7u 4747 /* MMIO6.SCB8 */ 4748 #define CY_MMIO_SCB8_GROUP_NR 6u 4749 #define CY_MMIO_SCB8_SLAVE_NR 8u 4750 /* MMIO6.SCB9 */ 4751 #define CY_MMIO_SCB9_GROUP_NR 6u 4752 #define CY_MMIO_SCB9_SLAVE_NR 9u 4753 /* MMIO6.SCB10 */ 4754 #define CY_MMIO_SCB10_GROUP_NR 6u 4755 #define CY_MMIO_SCB10_SLAVE_NR 10u 4756 /* MMIO8.I2S0 */ 4757 #define CY_MMIO_I2S0_GROUP_NR 8u 4758 #define CY_MMIO_I2S0_SLAVE_NR 0u 4759 /* MMIO8.I2S1 */ 4760 #define CY_MMIO_I2S1_GROUP_NR 8u 4761 #define CY_MMIO_I2S1_SLAVE_NR 1u 4762 /* MMIO8.I2S2 */ 4763 #define CY_MMIO_I2S2_GROUP_NR 8u 4764 #define CY_MMIO_I2S2_SLAVE_NR 2u 4765 /* MMIO9.PASS0 */ 4766 #define CY_MMIO_PASS0_GROUP_NR 9u 4767 #define CY_MMIO_PASS0_SLAVE_NR 0u 4768 4769 /* Protection regions */ 4770 typedef enum 4771 { 4772 PROT_PERI_MAIN = 0, /* Address 0x40000200, size 0x00000040 */ 4773 PROT_PERI_SECURE = 1, /* Address 0x40002000, size 0x00000004 */ 4774 PROT_PERI_GR0_GROUP = 2, /* Address 0x40004010, size 0x00000004 */ 4775 PROT_PERI_GR1_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 4776 PROT_PERI_GR2_GROUP = 4, /* Address 0x40004090, size 0x00000004 */ 4777 PROT_PERI_GR3_GROUP = 5, /* Address 0x400040c0, size 0x00000020 */ 4778 PROT_PERI_GR4_GROUP = 6, /* Address 0x40004100, size 0x00000020 */ 4779 PROT_PERI_GR5_GROUP = 7, /* Address 0x40004140, size 0x00000020 */ 4780 PROT_PERI_GR6_GROUP = 8, /* Address 0x40004180, size 0x00000020 */ 4781 PROT_PERI_GR8_GROUP = 9, /* Address 0x40004200, size 0x00000020 */ 4782 PROT_PERI_GR9_GROUP = 10, /* Address 0x40004240, size 0x00000020 */ 4783 PROT_PERI_GR0_BOOT = 11, /* Address 0x40004020, size 0x00000004 */ 4784 PROT_PERI_GR1_BOOT = 12, /* Address 0x40004060, size 0x00000004 */ 4785 PROT_PERI_GR2_BOOT = 13, /* Address 0x400040a0, size 0x00000004 */ 4786 PROT_PERI_GR3_BOOT = 14, /* Address 0x400040e0, size 0x00000004 */ 4787 PROT_PERI_GR4_BOOT = 15, /* Address 0x40004120, size 0x00000004 */ 4788 PROT_PERI_GR5_BOOT = 16, /* Address 0x40004160, size 0x00000004 */ 4789 PROT_PERI_GR6_BOOT = 17, /* Address 0x400041a0, size 0x00000004 */ 4790 PROT_PERI_GR8_BOOT = 18, /* Address 0x40004220, size 0x00000004 */ 4791 PROT_PERI_GR9_BOOT = 19, /* Address 0x40004260, size 0x00000004 */ 4792 PROT_PERI_TR = 20, /* Address 0x40008000, size 0x00008000 */ 4793 PROT_PERI_MS_BOOT = 21, /* Address 0x40030000, size 0x00001000 */ 4794 PROT_PERI_PCLK_MAIN = 22, /* Address 0x40040000, size 0x00004000 */ 4795 PROT_CRYPTO_MAIN = 23, /* Address 0x40100000, size 0x00000400 */ 4796 PROT_CRYPTO_CRYPTO = 24, /* Address 0x40101000, size 0x00000800 */ 4797 PROT_CRYPTO_BOOT = 25, /* Address 0x40102000, size 0x00000100 */ 4798 PROT_CRYPTO_KEY0 = 26, /* Address 0x40102100, size 0x00000004 */ 4799 PROT_CRYPTO_KEY1 = 27, /* Address 0x40102120, size 0x00000004 */ 4800 PROT_CRYPTO_BUF = 28, /* Address 0x40108000, size 0x00002000 */ 4801 PROT_CPUSS_CM7_0 = 29, /* Address 0x40200000, size 0x00000400 */ 4802 PROT_CPUSS_CM7_1 = 30, /* Address 0x40200400, size 0x00000400 */ 4803 PROT_CPUSS_CM0 = 31, /* Address 0x40201000, size 0x00001000 */ 4804 PROT_CPUSS_BOOT = 32, /* Address 0x40202000, size 0x00000200 */ 4805 PROT_CPUSS_CM0_INT = 33, /* Address 0x40208000, size 0x00000800 */ 4806 PROT_CPUSS_CM7_0_INT = 34, /* Address 0x4020a000, size 0x00000800 */ 4807 PROT_CPUSS_CM7_1_INT = 35, /* Address 0x4020c000, size 0x00000800 */ 4808 PROT_FAULT_STRUCT0_MAIN = 36, /* Address 0x40210000, size 0x00000100 */ 4809 PROT_FAULT_STRUCT1_MAIN = 37, /* Address 0x40210100, size 0x00000100 */ 4810 PROT_FAULT_STRUCT2_MAIN = 38, /* Address 0x40210200, size 0x00000100 */ 4811 PROT_FAULT_STRUCT3_MAIN = 39, /* Address 0x40210300, size 0x00000100 */ 4812 PROT_IPC_STRUCT0_IPC = 40, /* Address 0x40220000, size 0x00000020 */ 4813 PROT_IPC_STRUCT1_IPC = 41, /* Address 0x40220020, size 0x00000020 */ 4814 PROT_IPC_STRUCT2_IPC = 42, /* Address 0x40220040, size 0x00000020 */ 4815 PROT_IPC_STRUCT3_IPC = 43, /* Address 0x40220060, size 0x00000020 */ 4816 PROT_IPC_STRUCT4_IPC = 44, /* Address 0x40220080, size 0x00000020 */ 4817 PROT_IPC_STRUCT5_IPC = 45, /* Address 0x402200a0, size 0x00000020 */ 4818 PROT_IPC_STRUCT6_IPC = 46, /* Address 0x402200c0, size 0x00000020 */ 4819 PROT_IPC_STRUCT7_IPC = 47, /* Address 0x402200e0, size 0x00000020 */ 4820 PROT_IPC_INTR_STRUCT0_INTR = 48, /* Address 0x40221000, size 0x00000010 */ 4821 PROT_IPC_INTR_STRUCT1_INTR = 49, /* Address 0x40221020, size 0x00000010 */ 4822 PROT_IPC_INTR_STRUCT2_INTR = 50, /* Address 0x40221040, size 0x00000010 */ 4823 PROT_IPC_INTR_STRUCT3_INTR = 51, /* Address 0x40221060, size 0x00000010 */ 4824 PROT_IPC_INTR_STRUCT4_INTR = 52, /* Address 0x40221080, size 0x00000010 */ 4825 PROT_IPC_INTR_STRUCT5_INTR = 53, /* Address 0x402210a0, size 0x00000010 */ 4826 PROT_IPC_INTR_STRUCT6_INTR = 54, /* Address 0x402210c0, size 0x00000010 */ 4827 PROT_IPC_INTR_STRUCT7_INTR = 55, /* Address 0x402210e0, size 0x00000010 */ 4828 PROT_PROT_SMPU_MAIN = 56, /* Address 0x40230000, size 0x00000040 */ 4829 PROT_PROT_MPU0_MAIN = 57, /* Address 0x40234000, size 0x00000004 */ 4830 PROT_PROT_MPU5_MAIN = 58, /* Address 0x40235400, size 0x00000400 */ 4831 PROT_PROT_MPU6_MAIN = 59, /* Address 0x40235800, size 0x00000400 */ 4832 PROT_PROT_MPU13_MAIN = 60, /* Address 0x40237400, size 0x00000004 */ 4833 PROT_PROT_MPU14_MAIN = 61, /* Address 0x40237800, size 0x00000004 */ 4834 PROT_PROT_MPU15_MAIN = 62, /* Address 0x40237c00, size 0x00000400 */ 4835 PROT_FLASHC_MAIN = 63, /* Address 0x40240000, size 0x00000008 */ 4836 PROT_FLASHC_CMD = 64, /* Address 0x40240008, size 0x00000004 */ 4837 PROT_FLASHC_DFT = 65, /* Address 0x40240200, size 0x00000100 */ 4838 PROT_FLASHC_CM0 = 66, /* Address 0x40240400, size 0x00000080 */ 4839 PROT_FLASHC_CM7_0 = 67, /* Address 0x402404e0, size 0x00000004 */ 4840 PROT_FLASHC_CM7_1 = 68, /* Address 0x40240560, size 0x00000004 */ 4841 PROT_FLASHC_CRYPTO = 69, /* Address 0x40240580, size 0x00000004 */ 4842 PROT_FLASHC_DW0 = 70, /* Address 0x40240600, size 0x00000004 */ 4843 PROT_FLASHC_DW1 = 71, /* Address 0x40240680, size 0x00000004 */ 4844 PROT_FLASHC_DMAC = 72, /* Address 0x40240700, size 0x00000004 */ 4845 PROT_FLASHC_SLOW0 = 73, /* Address 0x40240780, size 0x00000004 */ 4846 PROT_FLASHC_SLOW1 = 74, /* Address 0x40240800, size 0x00000004 */ 4847 PROT_FLASHC_FlashMgmt = 75, /* Address 0x4024f000, size 0x00000080 */ 4848 PROT_FLASHC_MainSafety = 76, /* Address 0x4024f400, size 0x00000008 */ 4849 PROT_FLASHC_WorkSafety = 77, /* Address 0x4024f500, size 0x00000004 */ 4850 PROT_SRSS_GENERAL = 78, /* Address 0x40260000, size 0x00000400 */ 4851 PROT_SRSS_MAIN = 79, /* Address 0x40261000, size 0x00001000 */ 4852 PROT_SRSS_SECURE = 80, /* Address 0x40262000, size 0x00002000 */ 4853 PROT_MCWDT0_CONFIG = 81, /* Address 0x40268000, size 0x00000080 */ 4854 PROT_MCWDT1_CONFIG = 82, /* Address 0x40268100, size 0x00000080 */ 4855 PROT_MCWDT2_CONFIG = 83, /* Address 0x40268200, size 0x00000080 */ 4856 PROT_MCWDT0_MAIN = 84, /* Address 0x40268080, size 0x00000040 */ 4857 PROT_MCWDT1_MAIN = 85, /* Address 0x40268180, size 0x00000040 */ 4858 PROT_MCWDT2_MAIN = 86, /* Address 0x40268280, size 0x00000040 */ 4859 PROT_WDT_CONFIG = 87, /* Address 0x4026c000, size 0x00000020 */ 4860 PROT_WDT_MAIN = 88, /* Address 0x4026c040, size 0x00000020 */ 4861 PROT_BACKUP_BACKUP = 89, /* Address 0x40270000, size 0x00010000 */ 4862 PROT_DW0_DW = 90, /* Address 0x40280000, size 0x00000100 */ 4863 PROT_DW1_DW = 91, /* Address 0x40290000, size 0x00000100 */ 4864 PROT_DW0_DW_CRC = 92, /* Address 0x40280100, size 0x00000080 */ 4865 PROT_DW1_DW_CRC = 93, /* Address 0x40290100, size 0x00000080 */ 4866 PROT_DW0_CH_STRUCT0_CH = 94, /* Address 0x40288000, size 0x00000040 */ 4867 PROT_DW0_CH_STRUCT1_CH = 95, /* Address 0x40288040, size 0x00000040 */ 4868 PROT_DW0_CH_STRUCT2_CH = 96, /* Address 0x40288080, size 0x00000040 */ 4869 PROT_DW0_CH_STRUCT3_CH = 97, /* Address 0x402880c0, size 0x00000040 */ 4870 PROT_DW0_CH_STRUCT4_CH = 98, /* Address 0x40288100, size 0x00000040 */ 4871 PROT_DW0_CH_STRUCT5_CH = 99, /* Address 0x40288140, size 0x00000040 */ 4872 PROT_DW0_CH_STRUCT6_CH = 100, /* Address 0x40288180, size 0x00000040 */ 4873 PROT_DW0_CH_STRUCT7_CH = 101, /* Address 0x402881c0, size 0x00000040 */ 4874 PROT_DW0_CH_STRUCT8_CH = 102, /* Address 0x40288200, size 0x00000040 */ 4875 PROT_DW0_CH_STRUCT9_CH = 103, /* Address 0x40288240, size 0x00000040 */ 4876 PROT_DW0_CH_STRUCT10_CH = 104, /* Address 0x40288280, size 0x00000040 */ 4877 PROT_DW0_CH_STRUCT11_CH = 105, /* Address 0x402882c0, size 0x00000040 */ 4878 PROT_DW0_CH_STRUCT12_CH = 106, /* Address 0x40288300, size 0x00000040 */ 4879 PROT_DW0_CH_STRUCT13_CH = 107, /* Address 0x40288340, size 0x00000040 */ 4880 PROT_DW0_CH_STRUCT14_CH = 108, /* Address 0x40288380, size 0x00000040 */ 4881 PROT_DW0_CH_STRUCT15_CH = 109, /* Address 0x402883c0, size 0x00000040 */ 4882 PROT_DW0_CH_STRUCT16_CH = 110, /* Address 0x40288400, size 0x00000040 */ 4883 PROT_DW0_CH_STRUCT17_CH = 111, /* Address 0x40288440, size 0x00000040 */ 4884 PROT_DW0_CH_STRUCT18_CH = 112, /* Address 0x40288480, size 0x00000040 */ 4885 PROT_DW0_CH_STRUCT19_CH = 113, /* Address 0x402884c0, size 0x00000040 */ 4886 PROT_DW0_CH_STRUCT20_CH = 114, /* Address 0x40288500, size 0x00000040 */ 4887 PROT_DW0_CH_STRUCT21_CH = 115, /* Address 0x40288540, size 0x00000040 */ 4888 PROT_DW0_CH_STRUCT22_CH = 116, /* Address 0x40288580, size 0x00000040 */ 4889 PROT_DW0_CH_STRUCT23_CH = 117, /* Address 0x402885c0, size 0x00000040 */ 4890 PROT_DW0_CH_STRUCT24_CH = 118, /* Address 0x40288600, size 0x00000040 */ 4891 PROT_DW0_CH_STRUCT25_CH = 119, /* Address 0x40288640, size 0x00000040 */ 4892 PROT_DW0_CH_STRUCT26_CH = 120, /* Address 0x40288680, size 0x00000040 */ 4893 PROT_DW0_CH_STRUCT27_CH = 121, /* Address 0x402886c0, size 0x00000040 */ 4894 PROT_DW0_CH_STRUCT28_CH = 122, /* Address 0x40288700, size 0x00000040 */ 4895 PROT_DW0_CH_STRUCT29_CH = 123, /* Address 0x40288740, size 0x00000040 */ 4896 PROT_DW0_CH_STRUCT30_CH = 124, /* Address 0x40288780, size 0x00000040 */ 4897 PROT_DW0_CH_STRUCT31_CH = 125, /* Address 0x402887c0, size 0x00000040 */ 4898 PROT_DW0_CH_STRUCT32_CH = 126, /* Address 0x40288800, size 0x00000040 */ 4899 PROT_DW0_CH_STRUCT33_CH = 127, /* Address 0x40288840, size 0x00000040 */ 4900 PROT_DW0_CH_STRUCT34_CH = 128, /* Address 0x40288880, size 0x00000040 */ 4901 PROT_DW0_CH_STRUCT35_CH = 129, /* Address 0x402888c0, size 0x00000040 */ 4902 PROT_DW0_CH_STRUCT36_CH = 130, /* Address 0x40288900, size 0x00000040 */ 4903 PROT_DW0_CH_STRUCT37_CH = 131, /* Address 0x40288940, size 0x00000040 */ 4904 PROT_DW0_CH_STRUCT38_CH = 132, /* Address 0x40288980, size 0x00000040 */ 4905 PROT_DW0_CH_STRUCT39_CH = 133, /* Address 0x402889c0, size 0x00000040 */ 4906 PROT_DW0_CH_STRUCT40_CH = 134, /* Address 0x40288a00, size 0x00000040 */ 4907 PROT_DW0_CH_STRUCT41_CH = 135, /* Address 0x40288a40, size 0x00000040 */ 4908 PROT_DW0_CH_STRUCT42_CH = 136, /* Address 0x40288a80, size 0x00000040 */ 4909 PROT_DW0_CH_STRUCT43_CH = 137, /* Address 0x40288ac0, size 0x00000040 */ 4910 PROT_DW0_CH_STRUCT44_CH = 138, /* Address 0x40288b00, size 0x00000040 */ 4911 PROT_DW0_CH_STRUCT45_CH = 139, /* Address 0x40288b40, size 0x00000040 */ 4912 PROT_DW0_CH_STRUCT46_CH = 140, /* Address 0x40288b80, size 0x00000040 */ 4913 PROT_DW0_CH_STRUCT47_CH = 141, /* Address 0x40288bc0, size 0x00000040 */ 4914 PROT_DW0_CH_STRUCT48_CH = 142, /* Address 0x40288c00, size 0x00000040 */ 4915 PROT_DW0_CH_STRUCT49_CH = 143, /* Address 0x40288c40, size 0x00000040 */ 4916 PROT_DW0_CH_STRUCT50_CH = 144, /* Address 0x40288c80, size 0x00000040 */ 4917 PROT_DW0_CH_STRUCT51_CH = 145, /* Address 0x40288cc0, size 0x00000040 */ 4918 PROT_DW0_CH_STRUCT52_CH = 146, /* Address 0x40288d00, size 0x00000040 */ 4919 PROT_DW0_CH_STRUCT53_CH = 147, /* Address 0x40288d40, size 0x00000040 */ 4920 PROT_DW0_CH_STRUCT54_CH = 148, /* Address 0x40288d80, size 0x00000040 */ 4921 PROT_DW0_CH_STRUCT55_CH = 149, /* Address 0x40288dc0, size 0x00000040 */ 4922 PROT_DW0_CH_STRUCT56_CH = 150, /* Address 0x40288e00, size 0x00000040 */ 4923 PROT_DW0_CH_STRUCT57_CH = 151, /* Address 0x40288e40, size 0x00000040 */ 4924 PROT_DW0_CH_STRUCT58_CH = 152, /* Address 0x40288e80, size 0x00000040 */ 4925 PROT_DW0_CH_STRUCT59_CH = 153, /* Address 0x40288ec0, size 0x00000040 */ 4926 PROT_DW0_CH_STRUCT60_CH = 154, /* Address 0x40288f00, size 0x00000040 */ 4927 PROT_DW0_CH_STRUCT61_CH = 155, /* Address 0x40288f40, size 0x00000040 */ 4928 PROT_DW0_CH_STRUCT62_CH = 156, /* Address 0x40288f80, size 0x00000040 */ 4929 PROT_DW0_CH_STRUCT63_CH = 157, /* Address 0x40288fc0, size 0x00000040 */ 4930 PROT_DW0_CH_STRUCT64_CH = 158, /* Address 0x40289000, size 0x00000040 */ 4931 PROT_DW0_CH_STRUCT65_CH = 159, /* Address 0x40289040, size 0x00000040 */ 4932 PROT_DW0_CH_STRUCT66_CH = 160, /* Address 0x40289080, size 0x00000040 */ 4933 PROT_DW0_CH_STRUCT67_CH = 161, /* Address 0x402890c0, size 0x00000040 */ 4934 PROT_DW0_CH_STRUCT68_CH = 162, /* Address 0x40289100, size 0x00000040 */ 4935 PROT_DW0_CH_STRUCT69_CH = 163, /* Address 0x40289140, size 0x00000040 */ 4936 PROT_DW0_CH_STRUCT70_CH = 164, /* Address 0x40289180, size 0x00000040 */ 4937 PROT_DW0_CH_STRUCT71_CH = 165, /* Address 0x402891c0, size 0x00000040 */ 4938 PROT_DW0_CH_STRUCT72_CH = 166, /* Address 0x40289200, size 0x00000040 */ 4939 PROT_DW0_CH_STRUCT73_CH = 167, /* Address 0x40289240, size 0x00000040 */ 4940 PROT_DW0_CH_STRUCT74_CH = 168, /* Address 0x40289280, size 0x00000040 */ 4941 PROT_DW0_CH_STRUCT75_CH = 169, /* Address 0x402892c0, size 0x00000040 */ 4942 PROT_DW0_CH_STRUCT76_CH = 170, /* Address 0x40289300, size 0x00000040 */ 4943 PROT_DW0_CH_STRUCT77_CH = 171, /* Address 0x40289340, size 0x00000040 */ 4944 PROT_DW0_CH_STRUCT78_CH = 172, /* Address 0x40289380, size 0x00000040 */ 4945 PROT_DW0_CH_STRUCT79_CH = 173, /* Address 0x402893c0, size 0x00000040 */ 4946 PROT_DW0_CH_STRUCT80_CH = 174, /* Address 0x40289400, size 0x00000040 */ 4947 PROT_DW0_CH_STRUCT81_CH = 175, /* Address 0x40289440, size 0x00000040 */ 4948 PROT_DW0_CH_STRUCT82_CH = 176, /* Address 0x40289480, size 0x00000040 */ 4949 PROT_DW0_CH_STRUCT83_CH = 177, /* Address 0x402894c0, size 0x00000040 */ 4950 PROT_DW0_CH_STRUCT84_CH = 178, /* Address 0x40289500, size 0x00000040 */ 4951 PROT_DW0_CH_STRUCT85_CH = 179, /* Address 0x40289540, size 0x00000040 */ 4952 PROT_DW0_CH_STRUCT86_CH = 180, /* Address 0x40289580, size 0x00000040 */ 4953 PROT_DW0_CH_STRUCT87_CH = 181, /* Address 0x402895c0, size 0x00000040 */ 4954 PROT_DW0_CH_STRUCT88_CH = 182, /* Address 0x40289600, size 0x00000040 */ 4955 PROT_DW0_CH_STRUCT89_CH = 183, /* Address 0x40289640, size 0x00000040 */ 4956 PROT_DW0_CH_STRUCT90_CH = 184, /* Address 0x40289680, size 0x00000040 */ 4957 PROT_DW0_CH_STRUCT91_CH = 185, /* Address 0x402896c0, size 0x00000040 */ 4958 PROT_DW0_CH_STRUCT92_CH = 186, /* Address 0x40289700, size 0x00000040 */ 4959 PROT_DW0_CH_STRUCT93_CH = 187, /* Address 0x40289740, size 0x00000040 */ 4960 PROT_DW0_CH_STRUCT94_CH = 188, /* Address 0x40289780, size 0x00000040 */ 4961 PROT_DW0_CH_STRUCT95_CH = 189, /* Address 0x402897c0, size 0x00000040 */ 4962 PROT_DW0_CH_STRUCT96_CH = 190, /* Address 0x40289800, size 0x00000040 */ 4963 PROT_DW0_CH_STRUCT97_CH = 191, /* Address 0x40289840, size 0x00000040 */ 4964 PROT_DW0_CH_STRUCT98_CH = 192, /* Address 0x40289880, size 0x00000040 */ 4965 PROT_DW0_CH_STRUCT99_CH = 193, /* Address 0x402898c0, size 0x00000040 */ 4966 PROT_DW1_CH_STRUCT0_CH = 194, /* Address 0x40298000, size 0x00000040 */ 4967 PROT_DW1_CH_STRUCT1_CH = 195, /* Address 0x40298040, size 0x00000040 */ 4968 PROT_DW1_CH_STRUCT2_CH = 196, /* Address 0x40298080, size 0x00000040 */ 4969 PROT_DW1_CH_STRUCT3_CH = 197, /* Address 0x402980c0, size 0x00000040 */ 4970 PROT_DW1_CH_STRUCT4_CH = 198, /* Address 0x40298100, size 0x00000040 */ 4971 PROT_DW1_CH_STRUCT5_CH = 199, /* Address 0x40298140, size 0x00000040 */ 4972 PROT_DW1_CH_STRUCT6_CH = 200, /* Address 0x40298180, size 0x00000040 */ 4973 PROT_DW1_CH_STRUCT7_CH = 201, /* Address 0x402981c0, size 0x00000040 */ 4974 PROT_DW1_CH_STRUCT8_CH = 202, /* Address 0x40298200, size 0x00000040 */ 4975 PROT_DW1_CH_STRUCT9_CH = 203, /* Address 0x40298240, size 0x00000040 */ 4976 PROT_DW1_CH_STRUCT10_CH = 204, /* Address 0x40298280, size 0x00000040 */ 4977 PROT_DW1_CH_STRUCT11_CH = 205, /* Address 0x402982c0, size 0x00000040 */ 4978 PROT_DW1_CH_STRUCT12_CH = 206, /* Address 0x40298300, size 0x00000040 */ 4979 PROT_DW1_CH_STRUCT13_CH = 207, /* Address 0x40298340, size 0x00000040 */ 4980 PROT_DW1_CH_STRUCT14_CH = 208, /* Address 0x40298380, size 0x00000040 */ 4981 PROT_DW1_CH_STRUCT15_CH = 209, /* Address 0x402983c0, size 0x00000040 */ 4982 PROT_DW1_CH_STRUCT16_CH = 210, /* Address 0x40298400, size 0x00000040 */ 4983 PROT_DW1_CH_STRUCT17_CH = 211, /* Address 0x40298440, size 0x00000040 */ 4984 PROT_DW1_CH_STRUCT18_CH = 212, /* Address 0x40298480, size 0x00000040 */ 4985 PROT_DW1_CH_STRUCT19_CH = 213, /* Address 0x402984c0, size 0x00000040 */ 4986 PROT_DW1_CH_STRUCT20_CH = 214, /* Address 0x40298500, size 0x00000040 */ 4987 PROT_DW1_CH_STRUCT21_CH = 215, /* Address 0x40298540, size 0x00000040 */ 4988 PROT_DW1_CH_STRUCT22_CH = 216, /* Address 0x40298580, size 0x00000040 */ 4989 PROT_DW1_CH_STRUCT23_CH = 217, /* Address 0x402985c0, size 0x00000040 */ 4990 PROT_DW1_CH_STRUCT24_CH = 218, /* Address 0x40298600, size 0x00000040 */ 4991 PROT_DW1_CH_STRUCT25_CH = 219, /* Address 0x40298640, size 0x00000040 */ 4992 PROT_DW1_CH_STRUCT26_CH = 220, /* Address 0x40298680, size 0x00000040 */ 4993 PROT_DW1_CH_STRUCT27_CH = 221, /* Address 0x402986c0, size 0x00000040 */ 4994 PROT_DW1_CH_STRUCT28_CH = 222, /* Address 0x40298700, size 0x00000040 */ 4995 PROT_DW1_CH_STRUCT29_CH = 223, /* Address 0x40298740, size 0x00000040 */ 4996 PROT_DW1_CH_STRUCT30_CH = 224, /* Address 0x40298780, size 0x00000040 */ 4997 PROT_DW1_CH_STRUCT31_CH = 225, /* Address 0x402987c0, size 0x00000040 */ 4998 PROT_DW1_CH_STRUCT32_CH = 226, /* Address 0x40298800, size 0x00000040 */ 4999 PROT_DW1_CH_STRUCT33_CH = 227, /* Address 0x40298840, size 0x00000040 */ 5000 PROT_DW1_CH_STRUCT34_CH = 228, /* Address 0x40298880, size 0x00000040 */ 5001 PROT_DW1_CH_STRUCT35_CH = 229, /* Address 0x402988c0, size 0x00000040 */ 5002 PROT_DW1_CH_STRUCT36_CH = 230, /* Address 0x40298900, size 0x00000040 */ 5003 PROT_DW1_CH_STRUCT37_CH = 231, /* Address 0x40298940, size 0x00000040 */ 5004 PROT_DW1_CH_STRUCT38_CH = 232, /* Address 0x40298980, size 0x00000040 */ 5005 PROT_DW1_CH_STRUCT39_CH = 233, /* Address 0x402989c0, size 0x00000040 */ 5006 PROT_DW1_CH_STRUCT40_CH = 234, /* Address 0x40298a00, size 0x00000040 */ 5007 PROT_DW1_CH_STRUCT41_CH = 235, /* Address 0x40298a40, size 0x00000040 */ 5008 PROT_DW1_CH_STRUCT42_CH = 236, /* Address 0x40298a80, size 0x00000040 */ 5009 PROT_DW1_CH_STRUCT43_CH = 237, /* Address 0x40298ac0, size 0x00000040 */ 5010 PROT_DW1_CH_STRUCT44_CH = 238, /* Address 0x40298b00, size 0x00000040 */ 5011 PROT_DW1_CH_STRUCT45_CH = 239, /* Address 0x40298b40, size 0x00000040 */ 5012 PROT_DW1_CH_STRUCT46_CH = 240, /* Address 0x40298b80, size 0x00000040 */ 5013 PROT_DW1_CH_STRUCT47_CH = 241, /* Address 0x40298bc0, size 0x00000040 */ 5014 PROT_DW1_CH_STRUCT48_CH = 242, /* Address 0x40298c00, size 0x00000040 */ 5015 PROT_DW1_CH_STRUCT49_CH = 243, /* Address 0x40298c40, size 0x00000040 */ 5016 PROT_DW1_CH_STRUCT50_CH = 244, /* Address 0x40298c80, size 0x00000040 */ 5017 PROT_DW1_CH_STRUCT51_CH = 245, /* Address 0x40298cc0, size 0x00000040 */ 5018 PROT_DW1_CH_STRUCT52_CH = 246, /* Address 0x40298d00, size 0x00000040 */ 5019 PROT_DW1_CH_STRUCT53_CH = 247, /* Address 0x40298d40, size 0x00000040 */ 5020 PROT_DW1_CH_STRUCT54_CH = 248, /* Address 0x40298d80, size 0x00000040 */ 5021 PROT_DW1_CH_STRUCT55_CH = 249, /* Address 0x40298dc0, size 0x00000040 */ 5022 PROT_DW1_CH_STRUCT56_CH = 250, /* Address 0x40298e00, size 0x00000040 */ 5023 PROT_DW1_CH_STRUCT57_CH = 251, /* Address 0x40298e40, size 0x00000040 */ 5024 PROT_DMAC_TOP = 252, /* Address 0x402a0000, size 0x00000010 */ 5025 PROT_DMAC_CH0_CH = 253, /* Address 0x402a1000, size 0x00000100 */ 5026 PROT_DMAC_CH1_CH = 254, /* Address 0x402a1100, size 0x00000100 */ 5027 PROT_DMAC_CH2_CH = 255, /* Address 0x402a1200, size 0x00000100 */ 5028 PROT_DMAC_CH3_CH = 256, /* Address 0x402a1300, size 0x00000100 */ 5029 PROT_DMAC_CH4_CH = 257, /* Address 0x402a1400, size 0x00000100 */ 5030 PROT_DMAC_CH5_CH = 258, /* Address 0x402a1500, size 0x00000100 */ 5031 PROT_DMAC_CH6_CH = 259, /* Address 0x402a1600, size 0x00000100 */ 5032 PROT_DMAC_CH7_CH = 260, /* Address 0x402a1700, size 0x00000100 */ 5033 PROT_EFUSE_CTL = 261, /* Address 0x402c0000, size 0x00000200 */ 5034 PROT_EFUSE_DATA = 262, /* Address 0x402c0800, size 0x00000200 */ 5035 PROT_BIST = 263, /* Address 0x402f0000, size 0x00001000 */ 5036 PROT_HSIOM_PRT0_PRT = 264, /* Address 0x40300000, size 0x00000008 */ 5037 PROT_HSIOM_PRT1_PRT = 265, /* Address 0x40300010, size 0x00000008 */ 5038 PROT_HSIOM_PRT2_PRT = 266, /* Address 0x40300020, size 0x00000008 */ 5039 PROT_HSIOM_PRT3_PRT = 267, /* Address 0x40300030, size 0x00000008 */ 5040 PROT_HSIOM_PRT4_PRT = 268, /* Address 0x40300040, size 0x00000008 */ 5041 PROT_HSIOM_PRT5_PRT = 269, /* Address 0x40300050, size 0x00000008 */ 5042 PROT_HSIOM_PRT6_PRT = 270, /* Address 0x40300060, size 0x00000008 */ 5043 PROT_HSIOM_PRT7_PRT = 271, /* Address 0x40300070, size 0x00000008 */ 5044 PROT_HSIOM_PRT8_PRT = 272, /* Address 0x40300080, size 0x00000008 */ 5045 PROT_HSIOM_PRT9_PRT = 273, /* Address 0x40300090, size 0x00000008 */ 5046 PROT_HSIOM_PRT10_PRT = 274, /* Address 0x403000a0, size 0x00000008 */ 5047 PROT_HSIOM_PRT11_PRT = 275, /* Address 0x403000b0, size 0x00000008 */ 5048 PROT_HSIOM_PRT12_PRT = 276, /* Address 0x403000c0, size 0x00000008 */ 5049 PROT_HSIOM_PRT13_PRT = 277, /* Address 0x403000d0, size 0x00000008 */ 5050 PROT_HSIOM_PRT14_PRT = 278, /* Address 0x403000e0, size 0x00000008 */ 5051 PROT_HSIOM_PRT15_PRT = 279, /* Address 0x403000f0, size 0x00000008 */ 5052 PROT_HSIOM_PRT16_PRT = 280, /* Address 0x40300100, size 0x00000008 */ 5053 PROT_HSIOM_PRT17_PRT = 281, /* Address 0x40300110, size 0x00000008 */ 5054 PROT_HSIOM_PRT18_PRT = 282, /* Address 0x40300120, size 0x00000008 */ 5055 PROT_HSIOM_PRT19_PRT = 283, /* Address 0x40300130, size 0x00000008 */ 5056 PROT_HSIOM_PRT20_PRT = 284, /* Address 0x40300140, size 0x00000008 */ 5057 PROT_HSIOM_PRT21_PRT = 285, /* Address 0x40300150, size 0x00000008 */ 5058 PROT_HSIOM_PRT22_PRT = 286, /* Address 0x40300160, size 0x00000008 */ 5059 PROT_HSIOM_PRT23_PRT = 287, /* Address 0x40300170, size 0x00000008 */ 5060 PROT_HSIOM_PRT24_PRT = 288, /* Address 0x40300180, size 0x00000008 */ 5061 PROT_HSIOM_PRT25_PRT = 289, /* Address 0x40300190, size 0x00000008 */ 5062 PROT_HSIOM_PRT26_PRT = 290, /* Address 0x403001a0, size 0x00000008 */ 5063 PROT_HSIOM_PRT27_PRT = 291, /* Address 0x403001b0, size 0x00000008 */ 5064 PROT_HSIOM_PRT28_PRT = 292, /* Address 0x403001c0, size 0x00000008 */ 5065 PROT_HSIOM_PRT29_PRT = 293, /* Address 0x403001d0, size 0x00000008 */ 5066 PROT_HSIOM_PRT30_PRT = 294, /* Address 0x403001e0, size 0x00000008 */ 5067 PROT_HSIOM_PRT31_PRT = 295, /* Address 0x403001f0, size 0x00000008 */ 5068 PROT_HSIOM_PRT32_PRT = 296, /* Address 0x40300200, size 0x00000008 */ 5069 PROT_HSIOM_AMUX = 297, /* Address 0x40302000, size 0x00000010 */ 5070 PROT_HSIOM_MON = 298, /* Address 0x40302200, size 0x00000010 */ 5071 PROT_HSIOM_ALTJTAG = 299, /* Address 0x40302240, size 0x00000004 */ 5072 PROT_GPIO_PRT0_PRT = 300, /* Address 0x40310000, size 0x00000040 */ 5073 PROT_GPIO_PRT1_PRT = 301, /* Address 0x40310080, size 0x00000040 */ 5074 PROT_GPIO_PRT2_PRT = 302, /* Address 0x40310100, size 0x00000040 */ 5075 PROT_GPIO_PRT3_PRT = 303, /* Address 0x40310180, size 0x00000040 */ 5076 PROT_GPIO_PRT4_PRT = 304, /* Address 0x40310200, size 0x00000040 */ 5077 PROT_GPIO_PRT5_PRT = 305, /* Address 0x40310280, size 0x00000040 */ 5078 PROT_GPIO_PRT6_PRT = 306, /* Address 0x40310300, size 0x00000040 */ 5079 PROT_GPIO_PRT7_PRT = 307, /* Address 0x40310380, size 0x00000040 */ 5080 PROT_GPIO_PRT8_PRT = 308, /* Address 0x40310400, size 0x00000040 */ 5081 PROT_GPIO_PRT9_PRT = 309, /* Address 0x40310480, size 0x00000040 */ 5082 PROT_GPIO_PRT10_PRT = 310, /* Address 0x40310500, size 0x00000040 */ 5083 PROT_GPIO_PRT11_PRT = 311, /* Address 0x40310580, size 0x00000040 */ 5084 PROT_GPIO_PRT12_PRT = 312, /* Address 0x40310600, size 0x00000040 */ 5085 PROT_GPIO_PRT13_PRT = 313, /* Address 0x40310680, size 0x00000040 */ 5086 PROT_GPIO_PRT14_PRT = 314, /* Address 0x40310700, size 0x00000040 */ 5087 PROT_GPIO_PRT15_PRT = 315, /* Address 0x40310780, size 0x00000040 */ 5088 PROT_GPIO_PRT16_PRT = 316, /* Address 0x40310800, size 0x00000040 */ 5089 PROT_GPIO_PRT17_PRT = 317, /* Address 0x40310880, size 0x00000040 */ 5090 PROT_GPIO_PRT18_PRT = 318, /* Address 0x40310900, size 0x00000040 */ 5091 PROT_GPIO_PRT19_PRT = 319, /* Address 0x40310980, size 0x00000040 */ 5092 PROT_GPIO_PRT20_PRT = 320, /* Address 0x40310a00, size 0x00000040 */ 5093 PROT_GPIO_PRT21_PRT = 321, /* Address 0x40310a80, size 0x00000040 */ 5094 PROT_GPIO_PRT22_PRT = 322, /* Address 0x40310b00, size 0x00000040 */ 5095 PROT_GPIO_PRT23_PRT = 323, /* Address 0x40310b80, size 0x00000040 */ 5096 PROT_GPIO_PRT24_PRT = 324, /* Address 0x40310c00, size 0x00000040 */ 5097 PROT_GPIO_PRT25_PRT = 325, /* Address 0x40310c80, size 0x00000040 */ 5098 PROT_GPIO_PRT26_PRT = 326, /* Address 0x40310d00, size 0x00000040 */ 5099 PROT_GPIO_PRT27_PRT = 327, /* Address 0x40310d80, size 0x00000040 */ 5100 PROT_GPIO_PRT28_PRT = 328, /* Address 0x40310e00, size 0x00000040 */ 5101 PROT_GPIO_PRT29_PRT = 329, /* Address 0x40310e80, size 0x00000040 */ 5102 PROT_GPIO_PRT30_PRT = 330, /* Address 0x40310f00, size 0x00000040 */ 5103 PROT_GPIO_PRT31_PRT = 331, /* Address 0x40310f80, size 0x00000040 */ 5104 PROT_GPIO_PRT32_PRT = 332, /* Address 0x40311000, size 0x00000040 */ 5105 PROT_GPIO_PRT0_CFG = 333, /* Address 0x40310040, size 0x00000020 */ 5106 PROT_GPIO_PRT1_CFG = 334, /* Address 0x403100c0, size 0x00000020 */ 5107 PROT_GPIO_PRT2_CFG = 335, /* Address 0x40310140, size 0x00000020 */ 5108 PROT_GPIO_PRT3_CFG = 336, /* Address 0x403101c0, size 0x00000020 */ 5109 PROT_GPIO_PRT4_CFG = 337, /* Address 0x40310240, size 0x00000020 */ 5110 PROT_GPIO_PRT5_CFG = 338, /* Address 0x403102c0, size 0x00000020 */ 5111 PROT_GPIO_PRT6_CFG = 339, /* Address 0x40310340, size 0x00000020 */ 5112 PROT_GPIO_PRT7_CFG = 340, /* Address 0x403103c0, size 0x00000020 */ 5113 PROT_GPIO_PRT8_CFG = 341, /* Address 0x40310440, size 0x00000020 */ 5114 PROT_GPIO_PRT9_CFG = 342, /* Address 0x403104c0, size 0x00000020 */ 5115 PROT_GPIO_PRT10_CFG = 343, /* Address 0x40310540, size 0x00000020 */ 5116 PROT_GPIO_PRT11_CFG = 344, /* Address 0x403105c0, size 0x00000020 */ 5117 PROT_GPIO_PRT12_CFG = 345, /* Address 0x40310640, size 0x00000020 */ 5118 PROT_GPIO_PRT13_CFG = 346, /* Address 0x403106c0, size 0x00000020 */ 5119 PROT_GPIO_PRT14_CFG = 347, /* Address 0x40310740, size 0x00000020 */ 5120 PROT_GPIO_PRT15_CFG = 348, /* Address 0x403107c0, size 0x00000020 */ 5121 PROT_GPIO_PRT16_CFG = 349, /* Address 0x40310840, size 0x00000020 */ 5122 PROT_GPIO_PRT17_CFG = 350, /* Address 0x403108c0, size 0x00000020 */ 5123 PROT_GPIO_PRT18_CFG = 351, /* Address 0x40310940, size 0x00000020 */ 5124 PROT_GPIO_PRT19_CFG = 352, /* Address 0x403109c0, size 0x00000020 */ 5125 PROT_GPIO_PRT20_CFG = 353, /* Address 0x40310a40, size 0x00000020 */ 5126 PROT_GPIO_PRT21_CFG = 354, /* Address 0x40310ac0, size 0x00000020 */ 5127 PROT_GPIO_PRT22_CFG = 355, /* Address 0x40310b40, size 0x00000020 */ 5128 PROT_GPIO_PRT23_CFG = 356, /* Address 0x40310bc0, size 0x00000020 */ 5129 PROT_GPIO_PRT24_CFG = 357, /* Address 0x40310c40, size 0x00000020 */ 5130 PROT_GPIO_PRT25_CFG = 358, /* Address 0x40310cc0, size 0x00000020 */ 5131 PROT_GPIO_PRT26_CFG = 359, /* Address 0x40310d40, size 0x00000020 */ 5132 PROT_GPIO_PRT27_CFG = 360, /* Address 0x40310dc0, size 0x00000020 */ 5133 PROT_GPIO_PRT28_CFG = 361, /* Address 0x40310e40, size 0x00000020 */ 5134 PROT_GPIO_PRT29_CFG = 362, /* Address 0x40310ec0, size 0x00000020 */ 5135 PROT_GPIO_PRT30_CFG = 363, /* Address 0x40310f40, size 0x00000020 */ 5136 PROT_GPIO_PRT31_CFG = 364, /* Address 0x40310fc0, size 0x00000020 */ 5137 PROT_GPIO_PRT32_CFG = 365, /* Address 0x40311040, size 0x00000020 */ 5138 PROT_GPIO_GPIO = 366, /* Address 0x40314000, size 0x00000040 */ 5139 PROT_GPIO_TEST = 367, /* Address 0x40315000, size 0x00000008 */ 5140 PROT_SMARTIO_PRT12_PRT = 368, /* Address 0x40320c00, size 0x00000100 */ 5141 PROT_SMARTIO_PRT13_PRT = 369, /* Address 0x40320d00, size 0x00000100 */ 5142 PROT_SMARTIO_PRT14_PRT = 370, /* Address 0x40320e00, size 0x00000100 */ 5143 PROT_SMARTIO_PRT15_PRT = 371, /* Address 0x40320f00, size 0x00000100 */ 5144 PROT_SMARTIO_PRT17_PRT = 372, /* Address 0x40321100, size 0x00000100 */ 5145 PROT_EVTGEN0 = 373, /* Address 0x403f0000, size 0x00001000 */ 5146 PROT_SMIF0 = 374, /* Address 0x40420000, size 0x00010000 */ 5147 PROT_SDHC0 = 375, /* Address 0x40460000, size 0x00010000 */ 5148 PROT_ETH0 = 376, /* Address 0x40480000, size 0x00010000 */ 5149 PROT_LIN0_MAIN = 377, /* Address 0x40500000, size 0x00000008 */ 5150 PROT_LIN0_CH0_CH = 378, /* Address 0x40508000, size 0x00000100 */ 5151 PROT_LIN0_CH1_CH = 379, /* Address 0x40508100, size 0x00000100 */ 5152 PROT_LIN0_CH2_CH = 380, /* Address 0x40508200, size 0x00000100 */ 5153 PROT_LIN0_CH3_CH = 381, /* Address 0x40508300, size 0x00000100 */ 5154 PROT_LIN0_CH4_CH = 382, /* Address 0x40508400, size 0x00000100 */ 5155 PROT_LIN0_CH5_CH = 383, /* Address 0x40508500, size 0x00000100 */ 5156 PROT_LIN0_CH6_CH = 384, /* Address 0x40508600, size 0x00000100 */ 5157 PROT_LIN0_CH7_CH = 385, /* Address 0x40508700, size 0x00000100 */ 5158 PROT_LIN0_CH8_CH = 386, /* Address 0x40508800, size 0x00000100 */ 5159 PROT_LIN0_CH9_CH = 387, /* Address 0x40508900, size 0x00000100 */ 5160 PROT_LIN0_CH10_CH = 388, /* Address 0x40508a00, size 0x00000100 */ 5161 PROT_LIN0_CH11_CH = 389, /* Address 0x40508b00, size 0x00000100 */ 5162 PROT_LIN0_CH12_CH = 390, /* Address 0x40508c00, size 0x00000100 */ 5163 PROT_LIN0_CH13_CH = 391, /* Address 0x40508d00, size 0x00000100 */ 5164 PROT_LIN0_CH14_CH = 392, /* Address 0x40508e00, size 0x00000100 */ 5165 PROT_LIN0_CH15_CH = 393, /* Address 0x40508f00, size 0x00000100 */ 5166 PROT_CANFD0_CH0_CH = 394, /* Address 0x40520000, size 0x00000200 */ 5167 PROT_CANFD0_CH1_CH = 395, /* Address 0x40520200, size 0x00000200 */ 5168 PROT_CANFD0_CH2_CH = 396, /* Address 0x40520400, size 0x00000200 */ 5169 PROT_CANFD0_CH3_CH = 397, /* Address 0x40520600, size 0x00000200 */ 5170 PROT_CANFD1_CH0_CH = 398, /* Address 0x40540000, size 0x00000200 */ 5171 PROT_CANFD1_CH1_CH = 399, /* Address 0x40540200, size 0x00000200 */ 5172 PROT_CANFD1_CH2_CH = 400, /* Address 0x40540400, size 0x00000200 */ 5173 PROT_CANFD1_CH3_CH = 401, /* Address 0x40540600, size 0x00000200 */ 5174 PROT_CANFD0_MAIN = 402, /* Address 0x40521000, size 0x00000100 */ 5175 PROT_CANFD1_MAIN = 403, /* Address 0x40541000, size 0x00000100 */ 5176 PROT_CANFD0_BUF = 404, /* Address 0x40530000, size 0x00010000 */ 5177 PROT_CANFD1_BUF = 405, /* Address 0x40550000, size 0x00010000 */ 5178 PROT_TCPWM0_GRP0_CNT0_CNT = 406, /* Address 0x40580000, size 0x00000080 */ 5179 PROT_TCPWM0_GRP0_CNT1_CNT = 407, /* Address 0x40580080, size 0x00000080 */ 5180 PROT_TCPWM0_GRP0_CNT2_CNT = 408, /* Address 0x40580100, size 0x00000080 */ 5181 PROT_TCPWM0_GRP0_CNT3_CNT = 409, /* Address 0x40580180, size 0x00000080 */ 5182 PROT_TCPWM0_GRP0_CNT4_CNT = 410, /* Address 0x40580200, size 0x00000080 */ 5183 PROT_TCPWM0_GRP0_CNT5_CNT = 411, /* Address 0x40580280, size 0x00000080 */ 5184 PROT_TCPWM0_GRP0_CNT6_CNT = 412, /* Address 0x40580300, size 0x00000080 */ 5185 PROT_TCPWM0_GRP0_CNT7_CNT = 413, /* Address 0x40580380, size 0x00000080 */ 5186 PROT_TCPWM0_GRP0_CNT8_CNT = 414, /* Address 0x40580400, size 0x00000080 */ 5187 PROT_TCPWM0_GRP0_CNT9_CNT = 415, /* Address 0x40580480, size 0x00000080 */ 5188 PROT_TCPWM0_GRP0_CNT10_CNT = 416, /* Address 0x40580500, size 0x00000080 */ 5189 PROT_TCPWM0_GRP0_CNT11_CNT = 417, /* Address 0x40580580, size 0x00000080 */ 5190 PROT_TCPWM0_GRP0_CNT12_CNT = 418, /* Address 0x40580600, size 0x00000080 */ 5191 PROT_TCPWM0_GRP0_CNT13_CNT = 419, /* Address 0x40580680, size 0x00000080 */ 5192 PROT_TCPWM0_GRP0_CNT14_CNT = 420, /* Address 0x40580700, size 0x00000080 */ 5193 PROT_TCPWM0_GRP0_CNT15_CNT = 421, /* Address 0x40580780, size 0x00000080 */ 5194 PROT_TCPWM0_GRP0_CNT16_CNT = 422, /* Address 0x40580800, size 0x00000080 */ 5195 PROT_TCPWM0_GRP0_CNT17_CNT = 423, /* Address 0x40580880, size 0x00000080 */ 5196 PROT_TCPWM0_GRP0_CNT18_CNT = 424, /* Address 0x40580900, size 0x00000080 */ 5197 PROT_TCPWM0_GRP0_CNT19_CNT = 425, /* Address 0x40580980, size 0x00000080 */ 5198 PROT_TCPWM0_GRP0_CNT20_CNT = 426, /* Address 0x40580a00, size 0x00000080 */ 5199 PROT_TCPWM0_GRP0_CNT21_CNT = 427, /* Address 0x40580a80, size 0x00000080 */ 5200 PROT_TCPWM0_GRP0_CNT22_CNT = 428, /* Address 0x40580b00, size 0x00000080 */ 5201 PROT_TCPWM0_GRP0_CNT23_CNT = 429, /* Address 0x40580b80, size 0x00000080 */ 5202 PROT_TCPWM0_GRP0_CNT24_CNT = 430, /* Address 0x40580c00, size 0x00000080 */ 5203 PROT_TCPWM0_GRP0_CNT25_CNT = 431, /* Address 0x40580c80, size 0x00000080 */ 5204 PROT_TCPWM0_GRP0_CNT26_CNT = 432, /* Address 0x40580d00, size 0x00000080 */ 5205 PROT_TCPWM0_GRP0_CNT27_CNT = 433, /* Address 0x40580d80, size 0x00000080 */ 5206 PROT_TCPWM0_GRP0_CNT28_CNT = 434, /* Address 0x40580e00, size 0x00000080 */ 5207 PROT_TCPWM0_GRP0_CNT29_CNT = 435, /* Address 0x40580e80, size 0x00000080 */ 5208 PROT_TCPWM0_GRP0_CNT30_CNT = 436, /* Address 0x40580f00, size 0x00000080 */ 5209 PROT_TCPWM0_GRP0_CNT31_CNT = 437, /* Address 0x40580f80, size 0x00000080 */ 5210 PROT_TCPWM0_GRP0_CNT32_CNT = 438, /* Address 0x40581000, size 0x00000080 */ 5211 PROT_TCPWM0_GRP0_CNT33_CNT = 439, /* Address 0x40581080, size 0x00000080 */ 5212 PROT_TCPWM0_GRP0_CNT34_CNT = 440, /* Address 0x40581100, size 0x00000080 */ 5213 PROT_TCPWM0_GRP0_CNT35_CNT = 441, /* Address 0x40581180, size 0x00000080 */ 5214 PROT_TCPWM0_GRP0_CNT36_CNT = 442, /* Address 0x40581200, size 0x00000080 */ 5215 PROT_TCPWM0_GRP0_CNT37_CNT = 443, /* Address 0x40581280, size 0x00000080 */ 5216 PROT_TCPWM0_GRP0_CNT38_CNT = 444, /* Address 0x40581300, size 0x00000080 */ 5217 PROT_TCPWM0_GRP0_CNT39_CNT = 445, /* Address 0x40581380, size 0x00000080 */ 5218 PROT_TCPWM0_GRP0_CNT40_CNT = 446, /* Address 0x40581400, size 0x00000080 */ 5219 PROT_TCPWM0_GRP0_CNT41_CNT = 447, /* Address 0x40581480, size 0x00000080 */ 5220 PROT_TCPWM0_GRP0_CNT42_CNT = 448, /* Address 0x40581500, size 0x00000080 */ 5221 PROT_TCPWM0_GRP0_CNT43_CNT = 449, /* Address 0x40581580, size 0x00000080 */ 5222 PROT_TCPWM0_GRP0_CNT44_CNT = 450, /* Address 0x40581600, size 0x00000080 */ 5223 PROT_TCPWM0_GRP0_CNT45_CNT = 451, /* Address 0x40581680, size 0x00000080 */ 5224 PROT_TCPWM0_GRP0_CNT46_CNT = 452, /* Address 0x40581700, size 0x00000080 */ 5225 PROT_TCPWM0_GRP0_CNT47_CNT = 453, /* Address 0x40581780, size 0x00000080 */ 5226 PROT_TCPWM0_GRP0_CNT48_CNT = 454, /* Address 0x40581800, size 0x00000080 */ 5227 PROT_TCPWM0_GRP0_CNT49_CNT = 455, /* Address 0x40581880, size 0x00000080 */ 5228 PROT_TCPWM0_GRP0_CNT50_CNT = 456, /* Address 0x40581900, size 0x00000080 */ 5229 PROT_TCPWM0_GRP0_CNT51_CNT = 457, /* Address 0x40581980, size 0x00000080 */ 5230 PROT_TCPWM0_GRP0_CNT52_CNT = 458, /* Address 0x40581a00, size 0x00000080 */ 5231 PROT_TCPWM0_GRP0_CNT53_CNT = 459, /* Address 0x40581a80, size 0x00000080 */ 5232 PROT_TCPWM0_GRP0_CNT54_CNT = 460, /* Address 0x40581b00, size 0x00000080 */ 5233 PROT_TCPWM0_GRP0_CNT55_CNT = 461, /* Address 0x40581b80, size 0x00000080 */ 5234 PROT_TCPWM0_GRP0_CNT56_CNT = 462, /* Address 0x40581c00, size 0x00000080 */ 5235 PROT_TCPWM0_GRP0_CNT57_CNT = 463, /* Address 0x40581c80, size 0x00000080 */ 5236 PROT_TCPWM0_GRP0_CNT58_CNT = 464, /* Address 0x40581d00, size 0x00000080 */ 5237 PROT_TCPWM0_GRP0_CNT59_CNT = 465, /* Address 0x40581d80, size 0x00000080 */ 5238 PROT_TCPWM0_GRP0_CNT60_CNT = 466, /* Address 0x40581e00, size 0x00000080 */ 5239 PROT_TCPWM0_GRP0_CNT61_CNT = 467, /* Address 0x40581e80, size 0x00000080 */ 5240 PROT_TCPWM0_GRP0_CNT62_CNT = 468, /* Address 0x40581f00, size 0x00000080 */ 5241 PROT_TCPWM0_GRP1_CNT0_CNT = 469, /* Address 0x40588000, size 0x00000080 */ 5242 PROT_TCPWM0_GRP1_CNT1_CNT = 470, /* Address 0x40588080, size 0x00000080 */ 5243 PROT_TCPWM0_GRP1_CNT2_CNT = 471, /* Address 0x40588100, size 0x00000080 */ 5244 PROT_TCPWM0_GRP1_CNT3_CNT = 472, /* Address 0x40588180, size 0x00000080 */ 5245 PROT_TCPWM0_GRP1_CNT4_CNT = 473, /* Address 0x40588200, size 0x00000080 */ 5246 PROT_TCPWM0_GRP1_CNT5_CNT = 474, /* Address 0x40588280, size 0x00000080 */ 5247 PROT_TCPWM0_GRP1_CNT6_CNT = 475, /* Address 0x40588300, size 0x00000080 */ 5248 PROT_TCPWM0_GRP1_CNT7_CNT = 476, /* Address 0x40588380, size 0x00000080 */ 5249 PROT_TCPWM0_GRP1_CNT8_CNT = 477, /* Address 0x40588400, size 0x00000080 */ 5250 PROT_TCPWM0_GRP1_CNT9_CNT = 478, /* Address 0x40588480, size 0x00000080 */ 5251 PROT_TCPWM0_GRP1_CNT10_CNT = 479, /* Address 0x40588500, size 0x00000080 */ 5252 PROT_TCPWM0_GRP1_CNT11_CNT = 480, /* Address 0x40588580, size 0x00000080 */ 5253 PROT_TCPWM0_GRP2_CNT0_CNT = 481, /* Address 0x40590000, size 0x00000080 */ 5254 PROT_TCPWM0_GRP2_CNT1_CNT = 482, /* Address 0x40590080, size 0x00000080 */ 5255 PROT_TCPWM0_GRP2_CNT2_CNT = 483, /* Address 0x40590100, size 0x00000080 */ 5256 PROT_TCPWM0_GRP2_CNT3_CNT = 484, /* Address 0x40590180, size 0x00000080 */ 5257 PROT_TCPWM0_GRP2_CNT4_CNT = 485, /* Address 0x40590200, size 0x00000080 */ 5258 PROT_TCPWM0_GRP2_CNT5_CNT = 486, /* Address 0x40590280, size 0x00000080 */ 5259 PROT_TCPWM0_GRP2_CNT6_CNT = 487, /* Address 0x40590300, size 0x00000080 */ 5260 PROT_TCPWM0_GRP2_CNT7_CNT = 488, /* Address 0x40590380, size 0x00000080 */ 5261 PROT_SCB0 = 489, /* Address 0x40600000, size 0x00010000 */ 5262 PROT_SCB1 = 490, /* Address 0x40610000, size 0x00010000 */ 5263 PROT_SCB2 = 491, /* Address 0x40620000, size 0x00010000 */ 5264 PROT_SCB3 = 492, /* Address 0x40630000, size 0x00010000 */ 5265 PROT_SCB4 = 493, /* Address 0x40640000, size 0x00010000 */ 5266 PROT_SCB5 = 494, /* Address 0x40650000, size 0x00010000 */ 5267 PROT_SCB6 = 495, /* Address 0x40660000, size 0x00010000 */ 5268 PROT_SCB7 = 496, /* Address 0x40670000, size 0x00010000 */ 5269 PROT_SCB8 = 497, /* Address 0x40680000, size 0x00010000 */ 5270 PROT_SCB9 = 498, /* Address 0x40690000, size 0x00010000 */ 5271 PROT_SCB10 = 499, /* Address 0x406a0000, size 0x00010000 */ 5272 PROT_I2S0 = 500, /* Address 0x40800000, size 0x00001000 */ 5273 PROT_I2S1 = 501, /* Address 0x40801000, size 0x00001000 */ 5274 PROT_I2S2 = 502, /* Address 0x40802000, size 0x00001000 */ 5275 PROT_PASS0_SAR0_SAR = 503, /* Address 0x40900000, size 0x00000400 */ 5276 PROT_PASS0_SAR1_SAR = 504, /* Address 0x40901000, size 0x00000400 */ 5277 PROT_PASS0_SAR2_SAR = 505, /* Address 0x40902000, size 0x00000400 */ 5278 PROT_PASS0_SAR0_CH0_CH = 506, /* Address 0x40900800, size 0x00000040 */ 5279 PROT_PASS0_SAR0_CH1_CH = 507, /* Address 0x40900840, size 0x00000040 */ 5280 PROT_PASS0_SAR0_CH2_CH = 508, /* Address 0x40900880, size 0x00000040 */ 5281 PROT_PASS0_SAR0_CH3_CH = 509, /* Address 0x409008c0, size 0x00000040 */ 5282 PROT_PASS0_SAR0_CH4_CH = 510, /* Address 0x40900900, size 0x00000040 */ 5283 PROT_PASS0_SAR0_CH5_CH = 511, /* Address 0x40900940, size 0x00000040 */ 5284 PROT_PASS0_SAR0_CH6_CH = 512, /* Address 0x40900980, size 0x00000040 */ 5285 PROT_PASS0_SAR0_CH7_CH = 513, /* Address 0x409009c0, size 0x00000040 */ 5286 PROT_PASS0_SAR0_CH8_CH = 514, /* Address 0x40900a00, size 0x00000040 */ 5287 PROT_PASS0_SAR0_CH9_CH = 515, /* Address 0x40900a40, size 0x00000040 */ 5288 PROT_PASS0_SAR0_CH10_CH = 516, /* Address 0x40900a80, size 0x00000040 */ 5289 PROT_PASS0_SAR0_CH11_CH = 517, /* Address 0x40900ac0, size 0x00000040 */ 5290 PROT_PASS0_SAR0_CH12_CH = 518, /* Address 0x40900b00, size 0x00000040 */ 5291 PROT_PASS0_SAR0_CH13_CH = 519, /* Address 0x40900b40, size 0x00000040 */ 5292 PROT_PASS0_SAR0_CH14_CH = 520, /* Address 0x40900b80, size 0x00000040 */ 5293 PROT_PASS0_SAR0_CH15_CH = 521, /* Address 0x40900bc0, size 0x00000040 */ 5294 PROT_PASS0_SAR0_CH16_CH = 522, /* Address 0x40900c00, size 0x00000040 */ 5295 PROT_PASS0_SAR0_CH17_CH = 523, /* Address 0x40900c40, size 0x00000040 */ 5296 PROT_PASS0_SAR0_CH18_CH = 524, /* Address 0x40900c80, size 0x00000040 */ 5297 PROT_PASS0_SAR0_CH19_CH = 525, /* Address 0x40900cc0, size 0x00000040 */ 5298 PROT_PASS0_SAR0_CH20_CH = 526, /* Address 0x40900d00, size 0x00000040 */ 5299 PROT_PASS0_SAR0_CH21_CH = 527, /* Address 0x40900d40, size 0x00000040 */ 5300 PROT_PASS0_SAR0_CH22_CH = 528, /* Address 0x40900d80, size 0x00000040 */ 5301 PROT_PASS0_SAR0_CH23_CH = 529, /* Address 0x40900dc0, size 0x00000040 */ 5302 PROT_PASS0_SAR0_CH24_CH = 530, /* Address 0x40900e00, size 0x00000040 */ 5303 PROT_PASS0_SAR0_CH25_CH = 531, /* Address 0x40900e40, size 0x00000040 */ 5304 PROT_PASS0_SAR0_CH26_CH = 532, /* Address 0x40900e80, size 0x00000040 */ 5305 PROT_PASS0_SAR0_CH27_CH = 533, /* Address 0x40900ec0, size 0x00000040 */ 5306 PROT_PASS0_SAR0_CH28_CH = 534, /* Address 0x40900f00, size 0x00000040 */ 5307 PROT_PASS0_SAR0_CH29_CH = 535, /* Address 0x40900f40, size 0x00000040 */ 5308 PROT_PASS0_SAR0_CH30_CH = 536, /* Address 0x40900f80, size 0x00000040 */ 5309 PROT_PASS0_SAR0_CH31_CH = 537, /* Address 0x40900fc0, size 0x00000040 */ 5310 PROT_PASS0_SAR1_CH0_CH = 538, /* Address 0x40901800, size 0x00000040 */ 5311 PROT_PASS0_SAR1_CH1_CH = 539, /* Address 0x40901840, size 0x00000040 */ 5312 PROT_PASS0_SAR1_CH2_CH = 540, /* Address 0x40901880, size 0x00000040 */ 5313 PROT_PASS0_SAR1_CH3_CH = 541, /* Address 0x409018c0, size 0x00000040 */ 5314 PROT_PASS0_SAR1_CH4_CH = 542, /* Address 0x40901900, size 0x00000040 */ 5315 PROT_PASS0_SAR1_CH5_CH = 543, /* Address 0x40901940, size 0x00000040 */ 5316 PROT_PASS0_SAR1_CH6_CH = 544, /* Address 0x40901980, size 0x00000040 */ 5317 PROT_PASS0_SAR1_CH7_CH = 545, /* Address 0x409019c0, size 0x00000040 */ 5318 PROT_PASS0_SAR1_CH8_CH = 546, /* Address 0x40901a00, size 0x00000040 */ 5319 PROT_PASS0_SAR1_CH9_CH = 547, /* Address 0x40901a40, size 0x00000040 */ 5320 PROT_PASS0_SAR1_CH10_CH = 548, /* Address 0x40901a80, size 0x00000040 */ 5321 PROT_PASS0_SAR1_CH11_CH = 549, /* Address 0x40901ac0, size 0x00000040 */ 5322 PROT_PASS0_SAR1_CH12_CH = 550, /* Address 0x40901b00, size 0x00000040 */ 5323 PROT_PASS0_SAR1_CH13_CH = 551, /* Address 0x40901b40, size 0x00000040 */ 5324 PROT_PASS0_SAR1_CH14_CH = 552, /* Address 0x40901b80, size 0x00000040 */ 5325 PROT_PASS0_SAR1_CH15_CH = 553, /* Address 0x40901bc0, size 0x00000040 */ 5326 PROT_PASS0_SAR1_CH16_CH = 554, /* Address 0x40901c00, size 0x00000040 */ 5327 PROT_PASS0_SAR1_CH17_CH = 555, /* Address 0x40901c40, size 0x00000040 */ 5328 PROT_PASS0_SAR1_CH18_CH = 556, /* Address 0x40901c80, size 0x00000040 */ 5329 PROT_PASS0_SAR1_CH19_CH = 557, /* Address 0x40901cc0, size 0x00000040 */ 5330 PROT_PASS0_SAR1_CH20_CH = 558, /* Address 0x40901d00, size 0x00000040 */ 5331 PROT_PASS0_SAR1_CH21_CH = 559, /* Address 0x40901d40, size 0x00000040 */ 5332 PROT_PASS0_SAR1_CH22_CH = 560, /* Address 0x40901d80, size 0x00000040 */ 5333 PROT_PASS0_SAR1_CH23_CH = 561, /* Address 0x40901dc0, size 0x00000040 */ 5334 PROT_PASS0_SAR1_CH24_CH = 562, /* Address 0x40901e00, size 0x00000040 */ 5335 PROT_PASS0_SAR1_CH25_CH = 563, /* Address 0x40901e40, size 0x00000040 */ 5336 PROT_PASS0_SAR1_CH26_CH = 564, /* Address 0x40901e80, size 0x00000040 */ 5337 PROT_PASS0_SAR1_CH27_CH = 565, /* Address 0x40901ec0, size 0x00000040 */ 5338 PROT_PASS0_SAR1_CH28_CH = 566, /* Address 0x40901f00, size 0x00000040 */ 5339 PROT_PASS0_SAR1_CH29_CH = 567, /* Address 0x40901f40, size 0x00000040 */ 5340 PROT_PASS0_SAR1_CH30_CH = 568, /* Address 0x40901f80, size 0x00000040 */ 5341 PROT_PASS0_SAR1_CH31_CH = 569, /* Address 0x40901fc0, size 0x00000040 */ 5342 PROT_PASS0_SAR2_CH0_CH = 570, /* Address 0x40902800, size 0x00000040 */ 5343 PROT_PASS0_SAR2_CH1_CH = 571, /* Address 0x40902840, size 0x00000040 */ 5344 PROT_PASS0_SAR2_CH2_CH = 572, /* Address 0x40902880, size 0x00000040 */ 5345 PROT_PASS0_SAR2_CH3_CH = 573, /* Address 0x409028c0, size 0x00000040 */ 5346 PROT_PASS0_SAR2_CH4_CH = 574, /* Address 0x40902900, size 0x00000040 */ 5347 PROT_PASS0_SAR2_CH5_CH = 575, /* Address 0x40902940, size 0x00000040 */ 5348 PROT_PASS0_SAR2_CH6_CH = 576, /* Address 0x40902980, size 0x00000040 */ 5349 PROT_PASS0_SAR2_CH7_CH = 577, /* Address 0x409029c0, size 0x00000040 */ 5350 PROT_PASS0_TOP = 578 /* Address 0x409f0000, size 0x00001000 */ 5351 } cy_en_prot_region_t; 5352 5353 #endif /* _XMC7100_CONFIG_H_ */ 5354 5355 5356 /* [] END OF FILE */ 5357
