1 /***************************************************************************//** 2 * \file cyw20829B0_config.h 3 * 4 * \brief 5 * CYW20829 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYW20829B0_CONFIG_H_ 28 #define _CYW20829B0_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN_POS_EN = 0x0000u, /* cpuss.clock_trace_in_pos_en */ 34 PCLK_SCB0_CLOCK_SCB_EN = 0x0100u, /* scb[0].clock_scb_en */ 35 PCLK_SCB1_CLOCK_SCB_EN = 0x0101u, /* scb[1].clock_scb_en */ 36 PCLK_SCB2_CLOCK_SCB_EN = 0x0102u, /* scb[2].clock_scb_en */ 37 PCLK_TCPWM0_CLOCK_COUNTER_EN0 = 0x0103u, /* tcpwm[0].clock_counter_en[0] */ 38 PCLK_TCPWM0_CLOCK_COUNTER_EN1 = 0x0104u, /* tcpwm[0].clock_counter_en[1] */ 39 PCLK_TCPWM0_CLOCK_COUNTER_EN256 = 0x0105u, /* tcpwm[0].clock_counter_en[256] */ 40 PCLK_TCPWM0_CLOCK_COUNTER_EN257 = 0x0106u, /* tcpwm[0].clock_counter_en[257] */ 41 PCLK_TCPWM0_CLOCK_COUNTER_EN258 = 0x0107u, /* tcpwm[0].clock_counter_en[258] */ 42 PCLK_TCPWM0_CLOCK_COUNTER_EN259 = 0x0108u, /* tcpwm[0].clock_counter_en[259] */ 43 PCLK_TCPWM0_CLOCK_COUNTER_EN260 = 0x0109u, /* tcpwm[0].clock_counter_en[260] */ 44 PCLK_TCPWM0_CLOCK_COUNTER_EN261 = 0x010Au, /* tcpwm[0].clock_counter_en[261] */ 45 PCLK_TCPWM0_CLOCK_COUNTER_EN262 = 0x010Bu, /* tcpwm[0].clock_counter_en[262] */ 46 PCLK_LIN0_CLOCK_CH_EN0 = 0x010Cu, /* lin[0].clock_ch_en[0] */ 47 PCLK_LIN0_CLOCK_CH_EN1 = 0x010Du, /* lin[0].clock_ch_en[1] */ 48 PCLK_CANFD0_CLOCK_CAN_EN0 = 0x010Eu, /* canfd[0].clock_can_en[0] */ 49 PCLK_IOSS_CLOCK_SMARTIO_PCLK_POS_EN3 = 0x010Fu, /* ioss.clock_smartio_pclk_pos_en[3] */ 50 PCLK_SMIF_CLK_MEM = 0x0200u, /* smif.clk_mem */ 51 PCLK_SMIF_CLK_FAST = 0x0201u, /* smif.clk_fast */ 52 PCLK_SMIF_CLK_SLOW = 0x0202u, /* smif.clk_slow */ 53 PCLK_BTSS_CLK_CPUSS_EXP = 0x0203u, /* btss.clk_cpuss_exp */ 54 PCLK_BTSS_CLK_PERI = 0x0204u, /* btss.clk_peri */ 55 PCLK_CRYPTO_CLK_HF = 0x0205u, /* crypto.clk_hf */ 56 PCLK_PDM0_CLK_IF_SRSS = 0x0300u, /* pdm[0].clk_if_srss */ 57 PCLK_TDM0_CLK_IF_SRSS0 = 0x0301u, /* tdm[0].clk_if_srss[0] */ 58 PCLK_ADCMIC_CLK_HF = 0x0500u, /* adcmic.clk_hf */ 59 PCLK_SMIF_CLK_IF = 0x0600u, /* smif.clk_if */ 60 PCLK_IOSS_CLK_HF = 0x0601u /* ioss.clk_hf */ 61 } en_clk_dst_t; 62 63 /* Trigger Group */ 64 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 65 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 66 */ 67 /* Trigger Group Inputs */ 68 /* Trigger Input Group 0 - P-DMA0 Request Assignments */ 69 typedef enum 70 { 71 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 72 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 73 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 74 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 75 TRIG_IN_MUX_0_TCPWM0_TR_OUT00 = 0x00000005u, /* tcpwm[0].tr_out0[0] */ 76 TRIG_IN_MUX_0_TCPWM0_TR_OUT10 = 0x00000006u, /* tcpwm[0].tr_out1[0] */ 77 TRIG_IN_MUX_0_TCPWM0_TR_OUT01 = 0x00000007u, /* tcpwm[0].tr_out0[1] */ 78 TRIG_IN_MUX_0_TCPWM0_TR_OUT11 = 0x00000008u, /* tcpwm[0].tr_out1[1] */ 79 TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000009u, /* ioss.peri_tr_io_input_in[0] */ 80 TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x0000000Au, /* ioss.peri_tr_io_input_in[1] */ 81 TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x0000000Bu, /* ioss.peri_tr_io_input_in[2] */ 82 TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x0000000Cu, /* ioss.peri_tr_io_input_in[3] */ 83 TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x0000000Du, /* ioss.peri_tr_io_input_in[4] */ 84 TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000000Eu, /* ioss.peri_tr_io_input_in[5] */ 85 TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000000Fu, /* ioss.peri_tr_io_input_in[6] */ 86 TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x00000010u, /* ioss.peri_tr_io_input_in[7] */ 87 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000011u, /* cpuss.cti_tr_out[0] */ 88 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000012u, /* cpuss.cti_tr_out[1] */ 89 TRIG_IN_MUX_0_ADCMIC_DC_DONE = 0x00000013u, /* adcmic.tr_adcmic_dc */ 90 TRIG_IN_MUX_0_ADCMIC_DATA_AVAIL = 0x00000014u, /* adcmic.tr_adcmic_data */ 91 TRIG_IN_MUX_0_I2S_TDM_TX0 = 0x00000015u, /* tdm.tr_tx_req[0] */ 92 TRIG_IN_MUX_0_I2S_TDM_RX0 = 0x00000016u, /* tdm.tr_rx_req[0] */ 93 TRIG_IN_MUX_0_PDM_RX0 = 0x00000017u, /* pdm.tr_rx_req[0] */ 94 TRIG_IN_MUX_0_PDM_RX1 = 0x00000018u, /* pdm.tr_rx_req[1] */ 95 TRIG_IN_MUX_0_CRYPTO_TR_TRNG = 0x00000019u /* crypto.tr_trng_bitstream */ 96 } en_trig_input_pdma0_tr_t; 97 98 /* Trigger Input Group 1 - TCPWM0 trigger multiplexer */ 99 typedef enum 100 { 101 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 102 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 103 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 104 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 105 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 106 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 107 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 108 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 109 TRIG_IN_MUX_1_TCPWM0_TR_OUT00 = 0x00000109u, /* tcpwm[0].tr_out0[0] */ 110 TRIG_IN_MUX_1_TCPWM0_TR_OUT10 = 0x0000010Au, /* tcpwm[0].tr_out1[0] */ 111 TRIG_IN_MUX_1_TCPWM0_TR_OUT01 = 0x0000010Bu, /* tcpwm[0].tr_out0[1] */ 112 TRIG_IN_MUX_1_TCPWM0_TR_OUT11 = 0x0000010Cu, /* tcpwm[0].tr_out1[1] */ 113 TRIG_IN_MUX_1_TCPWM0_TR_OUT0256 = 0x0000010Du, /* tcpwm[0].tr_out0[256] */ 114 TRIG_IN_MUX_1_TCPWM0_TR_OUT1256 = 0x0000010Eu, /* tcpwm[0].tr_out1[256] */ 115 TRIG_IN_MUX_1_TCPWM0_TR_OUT0257 = 0x0000010Fu, /* tcpwm[0].tr_out0[257] */ 116 TRIG_IN_MUX_1_TCPWM0_TR_OUT1257 = 0x00000110u, /* tcpwm[0].tr_out1[257] */ 117 TRIG_IN_MUX_1_TCPWM0_TR_OUT0258 = 0x00000111u, /* tcpwm[0].tr_out0[258] */ 118 TRIG_IN_MUX_1_TCPWM0_TR_OUT1258 = 0x00000112u, /* tcpwm[0].tr_out1[258] */ 119 TRIG_IN_MUX_1_TCPWM0_TR_OUT0259 = 0x00000113u, /* tcpwm[0].tr_out0[259] */ 120 TRIG_IN_MUX_1_TCPWM0_TR_OUT1259 = 0x00000114u, /* tcpwm[0].tr_out1[259] */ 121 TRIG_IN_MUX_1_TCPWM0_TR_OUT0260 = 0x00000115u, /* tcpwm[0].tr_out0[260] */ 122 TRIG_IN_MUX_1_TCPWM0_TR_OUT1260 = 0x00000116u, /* tcpwm[0].tr_out1[260] */ 123 TRIG_IN_MUX_1_TCPWM0_TR_OUT0261 = 0x00000117u, /* tcpwm[0].tr_out0[261] */ 124 TRIG_IN_MUX_1_TCPWM0_TR_OUT1261 = 0x00000118u, /* tcpwm[0].tr_out1[261] */ 125 TRIG_IN_MUX_1_TCPWM0_TR_OUT0262 = 0x00000119u, /* tcpwm[0].tr_out0[262] */ 126 TRIG_IN_MUX_1_TCPWM0_TR_OUT1262 = 0x0000011Au, /* tcpwm[0].tr_out1[262] */ 127 TRIG_IN_MUX_1_SCB_I2C_SCL0 = 0x0000011Bu, /* scb[0].tr_i2c_scl_filtered */ 128 TRIG_IN_MUX_1_SCB_TX0 = 0x0000011Cu, /* scb[0].tr_tx_req */ 129 TRIG_IN_MUX_1_SCB_RX0 = 0x0000011Du, /* scb[0].tr_rx_req */ 130 TRIG_IN_MUX_1_CRYPTO_TR_TRNG = 0x0000011Eu, /* crypto.tr_trng_bitstream */ 131 TRIG_IN_MUX_1_SCB_TX1 = 0x0000011Fu, /* scb[1].tr_tx_req */ 132 TRIG_IN_MUX_1_SCB_RX1 = 0x00000120u, /* scb[1].tr_rx_req */ 133 TRIG_IN_MUX_1_SCB_I2C_SCL2 = 0x00000121u, /* scb[2].tr_i2c_scl_filtered */ 134 TRIG_IN_MUX_1_SCB_TX2 = 0x00000122u, /* scb[2].tr_tx_req */ 135 TRIG_IN_MUX_1_SCB_RX2 = 0x00000123u, /* scb[2].tr_rx_req */ 136 TRIG_IN_MUX_1_SMIF_TX = 0x00000124u, /* smif.tr_tx_req */ 137 TRIG_IN_MUX_1_SMIF_RX = 0x00000125u, /* smif.tr_rx_req */ 138 TRIG_IN_MUX_1_I2S_TDM_TX0 = 0x00000126u, /* tdm.tr_tx_req[0] */ 139 TRIG_IN_MUX_1_I2S_TDM_RX0 = 0x00000127u, /* tdm.tr_rx_req[0] */ 140 TRIG_IN_MUX_1_PDM_RX0 = 0x00000128u, /* pdm.tr_rx_req[0] */ 141 TRIG_IN_MUX_1_PDM_RX1 = 0x00000129u, /* pdm.tr_rx_req[1] */ 142 TRIG_IN_MUX_1_PDM_RX_REQ_ALL = 0x0000012Au, /* pdm.tr_rx_req_all */ 143 TRIG_IN_MUX_1_HSIOM_TR_OUT0 = 0x0000012Bu, /* ioss.peri_tr_io_input_in[0] */ 144 TRIG_IN_MUX_1_HSIOM_TR_OUT1 = 0x0000012Cu, /* ioss.peri_tr_io_input_in[1] */ 145 TRIG_IN_MUX_1_HSIOM_TR_OUT2 = 0x0000012Du, /* ioss.peri_tr_io_input_in[2] */ 146 TRIG_IN_MUX_1_HSIOM_TR_OUT3 = 0x0000012Eu, /* ioss.peri_tr_io_input_in[3] */ 147 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x0000012Fu, /* cpuss.cti_tr_out[0] */ 148 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x00000130u, /* cpuss.cti_tr_out[1] */ 149 TRIG_IN_MUX_1_ADCMIC_DC_DONE = 0x00000131u, /* adcmic.tr_adcmic_dc */ 150 TRIG_IN_MUX_1_ADCMIC_DATA_AVAIL = 0x00000132u, /* adcmic.tr_adcmic_data */ 151 TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000133u, /* canfd[0].tr_tmp_rtp_out[0] */ 152 TRIG_IN_MUX_1_BTSS_TR_TX = 0x00000134u, /* btss.tr_tx_start */ 153 TRIG_IN_MUX_1_BTSS_TR_RX = 0x00000135u /* btss.tr_rx_packet_sync */ 154 } en_trig_input_tcpwm0_t; 155 156 /* Trigger Input Group 2 - TCPWM1 trigger multiplexer */ 157 typedef enum 158 { 159 TRIG_IN_MUX_2_PDMA0_TR_OUT8 = 0x00000201u, /* cpuss.dw0_tr_out[8] */ 160 TRIG_IN_MUX_2_PDMA0_TR_OUT9 = 0x00000202u, /* cpuss.dw0_tr_out[9] */ 161 TRIG_IN_MUX_2_PDMA0_TR_OUT10 = 0x00000203u, /* cpuss.dw0_tr_out[10] */ 162 TRIG_IN_MUX_2_PDMA0_TR_OUT11 = 0x00000204u, /* cpuss.dw0_tr_out[11] */ 163 TRIG_IN_MUX_2_PDMA0_TR_OUT12 = 0x00000205u, /* cpuss.dw0_tr_out[12] */ 164 TRIG_IN_MUX_2_PDMA0_TR_OUT13 = 0x00000206u, /* cpuss.dw0_tr_out[13] */ 165 TRIG_IN_MUX_2_PDMA0_TR_OUT14 = 0x00000207u, /* cpuss.dw0_tr_out[14] */ 166 TRIG_IN_MUX_2_PDMA0_TR_OUT15 = 0x00000208u, /* cpuss.dw0_tr_out[15] */ 167 TRIG_IN_MUX_2_TCPWM0_TR_OUT00 = 0x00000209u, /* tcpwm[0].tr_out0[0] */ 168 TRIG_IN_MUX_2_TCPWM0_TR_OUT10 = 0x0000020Au, /* tcpwm[0].tr_out1[0] */ 169 TRIG_IN_MUX_2_TCPWM0_TR_OUT01 = 0x0000020Bu, /* tcpwm[0].tr_out0[1] */ 170 TRIG_IN_MUX_2_TCPWM0_TR_OUT11 = 0x0000020Cu, /* tcpwm[0].tr_out1[1] */ 171 TRIG_IN_MUX_2_TCPWM0_TR_OUT0256 = 0x0000020Du, /* tcpwm[0].tr_out0[256] */ 172 TRIG_IN_MUX_2_TCPWM0_TR_OUT1256 = 0x0000020Eu, /* tcpwm[0].tr_out1[256] */ 173 TRIG_IN_MUX_2_TCPWM0_TR_OUT0257 = 0x0000020Fu, /* tcpwm[0].tr_out0[257] */ 174 TRIG_IN_MUX_2_TCPWM0_TR_OUT1257 = 0x00000210u, /* tcpwm[0].tr_out1[257] */ 175 TRIG_IN_MUX_2_TCPWM0_TR_OUT0258 = 0x00000211u, /* tcpwm[0].tr_out0[258] */ 176 TRIG_IN_MUX_2_TCPWM0_TR_OUT1258 = 0x00000212u, /* tcpwm[0].tr_out1[258] */ 177 TRIG_IN_MUX_2_TCPWM0_TR_OUT0259 = 0x00000213u, /* tcpwm[0].tr_out0[259] */ 178 TRIG_IN_MUX_2_TCPWM0_TR_OUT1259 = 0x00000214u, /* tcpwm[0].tr_out1[259] */ 179 TRIG_IN_MUX_2_TCPWM0_TR_OUT0260 = 0x00000215u, /* tcpwm[0].tr_out0[260] */ 180 TRIG_IN_MUX_2_TCPWM0_TR_OUT1260 = 0x00000216u, /* tcpwm[0].tr_out1[260] */ 181 TRIG_IN_MUX_2_TCPWM0_TR_OUT0261 = 0x00000217u, /* tcpwm[0].tr_out0[261] */ 182 TRIG_IN_MUX_2_TCPWM0_TR_OUT1261 = 0x00000218u, /* tcpwm[0].tr_out1[261] */ 183 TRIG_IN_MUX_2_TCPWM0_TR_OUT0262 = 0x00000219u, /* tcpwm[0].tr_out0[262] */ 184 TRIG_IN_MUX_2_TCPWM0_TR_OUT1262 = 0x0000021Au, /* tcpwm[0].tr_out1[262] */ 185 TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000021Bu, /* scb[0].tr_i2c_scl_filtered */ 186 TRIG_IN_MUX_2_SCB_TX0 = 0x0000021Cu, /* scb[0].tr_tx_req */ 187 TRIG_IN_MUX_2_SCB_RX0 = 0x0000021Du, /* scb[0].tr_rx_req */ 188 TRIG_IN_MUX_2_CRYPTO_TR_TRNG = 0x0000021Eu, /* crypto.tr_trng_bitstream */ 189 TRIG_IN_MUX_2_SCB_TX1 = 0x0000021Fu, /* scb[1].tr_tx_req */ 190 TRIG_IN_MUX_2_SCB_RX1 = 0x00000220u, /* scb[1].tr_rx_req */ 191 TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000221u, /* scb[2].tr_i2c_scl_filtered */ 192 TRIG_IN_MUX_2_SCB_TX2 = 0x00000222u, /* scb[2].tr_tx_req */ 193 TRIG_IN_MUX_2_SCB_RX2 = 0x00000223u, /* scb[2].tr_rx_req */ 194 TRIG_IN_MUX_2_SMIF_TX = 0x00000224u, /* smif.tr_tx_req */ 195 TRIG_IN_MUX_2_SMIF_RX = 0x00000225u, /* smif.tr_rx_req */ 196 TRIG_IN_MUX_2_I2S_TDM_TX0 = 0x00000226u, /* tdm.tr_tx_req[0] */ 197 TRIG_IN_MUX_2_I2S_TDM_RX0 = 0x00000227u, /* tdm.tr_rx_req[0] */ 198 TRIG_IN_MUX_2_PDM_RX0 = 0x00000228u, /* pdm.tr_rx_req[0] */ 199 TRIG_IN_MUX_2_PDM_RX1 = 0x00000229u, /* pdm.tr_rx_req[1] */ 200 TRIG_IN_MUX_2_PDM_RX_REQ_ALL = 0x0000022Au, /* pdm.tr_rx_req_all */ 201 TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x0000022Bu, /* ioss.peri_tr_io_input_in[4] */ 202 TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000022Cu, /* ioss.peri_tr_io_input_in[5] */ 203 TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000022Du, /* ioss.peri_tr_io_input_in[6] */ 204 TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000022Eu, /* ioss.peri_tr_io_input_in[7] */ 205 TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x0000022Fu, /* cpuss.cti_tr_out[0] */ 206 TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000230u, /* cpuss.cti_tr_out[1] */ 207 TRIG_IN_MUX_2_ADCMIC_DC_DONE = 0x00000231u, /* adcmic.tr_adcmic_dc */ 208 TRIG_IN_MUX_2_ADCMIC_DATA_AVAIL = 0x00000232u, /* adcmic.tr_adcmic_data */ 209 TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000233u, /* canfd[0].tr_tmp_rtp_out[0] */ 210 TRIG_IN_MUX_2_BTSS_TR_TX = 0x00000234u, /* btss.tr_tx_start */ 211 TRIG_IN_MUX_2_BTSS_TR_RX = 0x00000235u /* btss.tr_rx_packet_sync */ 212 } en_trig_input_tcpwm1_t; 213 214 /* Trigger Input Group 3 - HSIOM trigger multiplexer */ 215 typedef enum 216 { 217 TRIG_IN_MUX_3_PDMA0_TR_OUT0 = 0x00000301u, /* cpuss.dw0_tr_out[0] */ 218 TRIG_IN_MUX_3_PDMA0_TR_OUT1 = 0x00000302u, /* cpuss.dw0_tr_out[1] */ 219 TRIG_IN_MUX_3_PDMA0_TR_OUT2 = 0x00000303u, /* cpuss.dw0_tr_out[2] */ 220 TRIG_IN_MUX_3_PDMA0_TR_OUT3 = 0x00000304u, /* cpuss.dw0_tr_out[3] */ 221 TRIG_IN_MUX_3_PDMA0_TR_OUT4 = 0x00000305u, /* cpuss.dw0_tr_out[4] */ 222 TRIG_IN_MUX_3_PDMA0_TR_OUT5 = 0x00000306u, /* cpuss.dw0_tr_out[5] */ 223 TRIG_IN_MUX_3_PDMA0_TR_OUT6 = 0x00000307u, /* cpuss.dw0_tr_out[6] */ 224 TRIG_IN_MUX_3_PDMA0_TR_OUT7 = 0x00000308u, /* cpuss.dw0_tr_out[7] */ 225 TRIG_IN_MUX_3_TCPWM0_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[0] */ 226 TRIG_IN_MUX_3_TCPWM0_TR_OUT10 = 0x0000030Au, /* tcpwm[0].tr_out1[0] */ 227 TRIG_IN_MUX_3_TCPWM0_TR_OUT01 = 0x0000030Bu, /* tcpwm[0].tr_out0[1] */ 228 TRIG_IN_MUX_3_TCPWM0_TR_OUT11 = 0x0000030Cu, /* tcpwm[0].tr_out1[1] */ 229 TRIG_IN_MUX_3_TCPWM0_TR_OUT0256 = 0x0000030Du, /* tcpwm[0].tr_out0[256] */ 230 TRIG_IN_MUX_3_TCPWM0_TR_OUT1256 = 0x0000030Eu, /* tcpwm[0].tr_out1[256] */ 231 TRIG_IN_MUX_3_TCPWM0_TR_OUT0257 = 0x0000030Fu, /* tcpwm[0].tr_out0[257] */ 232 TRIG_IN_MUX_3_TCPWM0_TR_OUT1257 = 0x00000310u, /* tcpwm[0].tr_out1[257] */ 233 TRIG_IN_MUX_3_TCPWM0_TR_OUT0258 = 0x00000311u, /* tcpwm[0].tr_out0[258] */ 234 TRIG_IN_MUX_3_TCPWM0_TR_OUT1258 = 0x00000312u, /* tcpwm[0].tr_out1[258] */ 235 TRIG_IN_MUX_3_TCPWM0_TR_OUT0259 = 0x00000313u, /* tcpwm[0].tr_out0[259] */ 236 TRIG_IN_MUX_3_TCPWM0_TR_OUT1259 = 0x00000314u, /* tcpwm[0].tr_out1[259] */ 237 TRIG_IN_MUX_3_TCPWM0_TR_OUT0260 = 0x00000315u, /* tcpwm[0].tr_out0[260] */ 238 TRIG_IN_MUX_3_TCPWM0_TR_OUT1260 = 0x00000316u, /* tcpwm[0].tr_out1[260] */ 239 TRIG_IN_MUX_3_TCPWM0_TR_OUT0261 = 0x00000317u, /* tcpwm[0].tr_out0[261] */ 240 TRIG_IN_MUX_3_TCPWM0_TR_OUT1261 = 0x00000318u, /* tcpwm[0].tr_out1[261] */ 241 TRIG_IN_MUX_3_TCPWM0_TR_OUT0262 = 0x00000319u, /* tcpwm[0].tr_out0[262] */ 242 TRIG_IN_MUX_3_TCPWM0_TR_OUT1262 = 0x0000031Au, /* tcpwm[0].tr_out1[262] */ 243 TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000031Bu, /* scb[0].tr_i2c_scl_filtered */ 244 TRIG_IN_MUX_3_SCB_TX0 = 0x0000031Cu, /* scb[0].tr_tx_req */ 245 TRIG_IN_MUX_3_SCB_RX0 = 0x0000031Du, /* scb[0].tr_rx_req */ 246 TRIG_IN_MUX_3_CRYPTO_TR_TRNG = 0x0000031Eu, /* crypto.tr_trng_bitstream */ 247 TRIG_IN_MUX_3_SCB_TX1 = 0x0000031Fu, /* scb[1].tr_tx_req */ 248 TRIG_IN_MUX_3_SCB_RX1 = 0x00000320u, /* scb[1].tr_rx_req */ 249 TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000321u, /* scb[2].tr_i2c_scl_filtered */ 250 TRIG_IN_MUX_3_SCB_TX2 = 0x00000322u, /* scb[2].tr_tx_req */ 251 TRIG_IN_MUX_3_SCB_RX2 = 0x00000323u, /* scb[2].tr_rx_req */ 252 TRIG_IN_MUX_3_I2S_TDM_TX0 = 0x00000324u, /* tdm.tr_tx_req[0] */ 253 TRIG_IN_MUX_3_I2S_TDM_RX0 = 0x00000325u, /* tdm.tr_rx_req[0] */ 254 TRIG_IN_MUX_3_PDM_RX0 = 0x00000326u, /* pdm.tr_rx_req[0] */ 255 TRIG_IN_MUX_3_PDM_RX1 = 0x00000327u, /* pdm.tr_rx_req[1] */ 256 TRIG_IN_MUX_3_PDM_RX_REQ_ALL = 0x00000328u, /* pdm.tr_rx_req_all */ 257 TRIG_IN_MUX_3_CTI_TR_OUT0 = 0x00000329u, /* cpuss.cti_tr_out[0] */ 258 TRIG_IN_MUX_3_CTI_TR_OUT1 = 0x0000032Au, /* cpuss.cti_tr_out[1] */ 259 TRIG_IN_MUX_3_ADCMIC_DC_DONE = 0x0000032Bu, /* adcmic.tr_adcmic_dc */ 260 TRIG_IN_MUX_3_ADCMIC_DATA_AVAIL = 0x0000032Cu, /* adcmic.tr_adcmic_data */ 261 TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x0000032Du /* canfd[0].tr_tmp_rtp_out[0] */ 262 } en_trig_input_hsiom_t; 263 264 /* Trigger Input Group 4 - CPUSS Debug multiplexer */ 265 typedef enum 266 { 267 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 268 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 269 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 270 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 271 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 272 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 273 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 274 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 275 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 276 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 277 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 278 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 279 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 280 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 281 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 282 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 283 TRIG_IN_MUX_4_TCPWM0_TR_OUT00 = 0x00000411u, /* tcpwm[0].tr_out0[0] */ 284 TRIG_IN_MUX_4_TCPWM0_TR_OUT10 = 0x00000412u, /* tcpwm[0].tr_out1[0] */ 285 TRIG_IN_MUX_4_TCPWM0_TR_OUT01 = 0x00000413u, /* tcpwm[0].tr_out0[1] */ 286 TRIG_IN_MUX_4_TCPWM0_TR_OUT11 = 0x00000414u, /* tcpwm[0].tr_out1[1] */ 287 TRIG_IN_MUX_4_TCPWM0_TR_OUT0256 = 0x00000415u, /* tcpwm[0].tr_out0[256] */ 288 TRIG_IN_MUX_4_TCPWM0_TR_OUT1256 = 0x00000416u, /* tcpwm[0].tr_out1[256] */ 289 TRIG_IN_MUX_4_TCPWM0_TR_OUT0257 = 0x00000417u, /* tcpwm[0].tr_out0[257] */ 290 TRIG_IN_MUX_4_TCPWM0_TR_OUT1257 = 0x00000418u, /* tcpwm[0].tr_out1[257] */ 291 TRIG_IN_MUX_4_TCPWM0_TR_OUT0258 = 0x00000419u, /* tcpwm[0].tr_out0[258] */ 292 TRIG_IN_MUX_4_TCPWM0_TR_OUT1258 = 0x0000041Au, /* tcpwm[0].tr_out1[258] */ 293 TRIG_IN_MUX_4_TCPWM0_TR_OUT0259 = 0x0000041Bu, /* tcpwm[0].tr_out0[259] */ 294 TRIG_IN_MUX_4_TCPWM0_TR_OUT1259 = 0x0000041Cu, /* tcpwm[0].tr_out1[259] */ 295 TRIG_IN_MUX_4_TCPWM0_TR_OUT0260 = 0x0000041Du, /* tcpwm[0].tr_out0[260] */ 296 TRIG_IN_MUX_4_TCPWM0_TR_OUT1260 = 0x0000041Eu, /* tcpwm[0].tr_out1[260] */ 297 TRIG_IN_MUX_4_TCPWM0_TR_OUT0261 = 0x0000041Fu, /* tcpwm[0].tr_out0[261] */ 298 TRIG_IN_MUX_4_TCPWM0_TR_OUT1261 = 0x00000420u, /* tcpwm[0].tr_out1[261] */ 299 TRIG_IN_MUX_4_TCPWM0_TR_OUT0262 = 0x00000421u, /* tcpwm[0].tr_out0[262] */ 300 TRIG_IN_MUX_4_TCPWM0_TR_OUT1262 = 0x00000422u, /* tcpwm[0].tr_out1[262] */ 301 TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x00000423u, /* scb[0].tr_i2c_scl_filtered */ 302 TRIG_IN_MUX_4_SCB_TX0 = 0x00000424u, /* scb[0].tr_tx_req */ 303 TRIG_IN_MUX_4_SCB_RX0 = 0x00000425u, /* scb[0].tr_rx_req */ 304 TRIG_IN_MUX_4_CRYPTO_TR_TRNG = 0x00000426u, /* crypto.tr_trng_bitstream */ 305 TRIG_IN_MUX_4_SCB_TX1 = 0x00000427u, /* scb[1].tr_tx_req */ 306 TRIG_IN_MUX_4_SCB_RX1 = 0x00000428u, /* scb[1].tr_rx_req */ 307 TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x00000429u, /* scb[2].tr_i2c_scl_filtered */ 308 TRIG_IN_MUX_4_SCB_TX2 = 0x0000042Au, /* scb[2].tr_tx_req */ 309 TRIG_IN_MUX_4_SCB_RX2 = 0x0000042Bu, /* scb[2].tr_rx_req */ 310 TRIG_IN_MUX_4_SMIF_TX = 0x0000042Cu, /* smif.tr_tx_req */ 311 TRIG_IN_MUX_4_SMIF_RX = 0x0000042Du, /* smif.tr_rx_req */ 312 TRIG_IN_MUX_4_I2S_TDM_TX0 = 0x0000042Eu, /* tdm.tr_tx_req[0] */ 313 TRIG_IN_MUX_4_I2S_TDM_RX0 = 0x0000042Fu, /* tdm.tr_rx_req[0] */ 314 TRIG_IN_MUX_4_PDM_RX0 = 0x00000430u, /* pdm.tr_rx_req[0] */ 315 TRIG_IN_MUX_4_PDM_RX1 = 0x00000431u, /* pdm.tr_rx_req[1] */ 316 TRIG_IN_MUX_4_PDM_RX_REQ_ALL = 0x00000432u, /* pdm.tr_rx_req_all */ 317 TRIG_IN_MUX_4_HSIOM_TR_OUT0 = 0x00000433u, /* ioss.peri_tr_io_input_in[0] */ 318 TRIG_IN_MUX_4_HSIOM_TR_OUT1 = 0x00000434u, /* ioss.peri_tr_io_input_in[1] */ 319 TRIG_IN_MUX_4_HSIOM_TR_OUT2 = 0x00000435u, /* ioss.peri_tr_io_input_in[2] */ 320 TRIG_IN_MUX_4_HSIOM_TR_OUT3 = 0x00000436u, /* ioss.peri_tr_io_input_in[3] */ 321 TRIG_IN_MUX_4_HSIOM_TR_OUT4 = 0x00000437u, /* ioss.peri_tr_io_input_in[4] */ 322 TRIG_IN_MUX_4_HSIOM_TR_OUT5 = 0x00000438u, /* ioss.peri_tr_io_input_in[5] */ 323 TRIG_IN_MUX_4_HSIOM_TR_OUT6 = 0x00000439u, /* ioss.peri_tr_io_input_in[6] */ 324 TRIG_IN_MUX_4_HSIOM_TR_OUT7 = 0x0000043Au, /* ioss.peri_tr_io_input_in[7] */ 325 TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x0000043Bu, /* cpuss.cti_tr_out[0] */ 326 TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x0000043Cu, /* cpuss.cti_tr_out[1] */ 327 TRIG_IN_MUX_4_ADCMIC_DC_DONE = 0x0000043Du, /* adcmic.tr_adcmic_dc */ 328 TRIG_IN_MUX_4_ADCMIC_DATA_AVAIL = 0x0000043Eu, /* adcmic.tr_adcmic_data */ 329 TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x0000043Fu /* canfd[0].tr_tmp_rtp_out[0] */ 330 } en_trig_input_cpuss_cti_t; 331 332 /* Trigger Input Group 5 - PERI Freeze trigger multiplexer */ 333 typedef enum 334 { 335 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x00000501u, /* cpuss.cti_tr_out[0] */ 336 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x00000502u /* cpuss.cti_tr_out[1] */ 337 } en_trig_input_peri_freeze_t; 338 339 /* Trigger Input Group 6 - TCPWM and PDM trigger multiplexer */ 340 typedef enum 341 { 342 TRIG_IN_MUX_6_TCPWM0_TR_OUT00 = 0x00000601u, /* tcpwm[0].tr_out0[0] */ 343 TRIG_IN_MUX_6_TCPWM0_TR_OUT10 = 0x00000602u, /* tcpwm[0].tr_out1[0] */ 344 TRIG_IN_MUX_6_TCPWM0_TR_OUT01 = 0x00000603u, /* tcpwm[0].tr_out0[1] */ 345 TRIG_IN_MUX_6_TCPWM0_TR_OUT11 = 0x00000604u, /* tcpwm[0].tr_out1[1] */ 346 TRIG_IN_MUX_6_TCPWM0_TR_OUT0256 = 0x00000605u, /* tcpwm[0].tr_out0[256] */ 347 TRIG_IN_MUX_6_TCPWM0_TR_OUT1256 = 0x00000606u, /* tcpwm[0].tr_out1[256] */ 348 TRIG_IN_MUX_6_TCPWM0_TR_OUT0257 = 0x00000607u, /* tcpwm[0].tr_out0[257] */ 349 TRIG_IN_MUX_6_TCPWM0_TR_OUT1257 = 0x00000608u, /* tcpwm[0].tr_out1[257] */ 350 TRIG_IN_MUX_6_TCPWM0_TR_OUT0258 = 0x00000609u, /* tcpwm[0].tr_out0[258] */ 351 TRIG_IN_MUX_6_TCPWM0_TR_OUT1258 = 0x0000060Au, /* tcpwm[0].tr_out1[258] */ 352 TRIG_IN_MUX_6_TCPWM0_TR_OUT0259 = 0x0000060Bu, /* tcpwm[0].tr_out0[259] */ 353 TRIG_IN_MUX_6_TCPWM0_TR_OUT1259 = 0x0000060Cu, /* tcpwm[0].tr_out1[259] */ 354 TRIG_IN_MUX_6_TCPWM0_TR_OUT0260 = 0x0000060Du, /* tcpwm[0].tr_out0[260] */ 355 TRIG_IN_MUX_6_TCPWM0_TR_OUT1260 = 0x0000060Eu, /* tcpwm[0].tr_out1[260] */ 356 TRIG_IN_MUX_6_TCPWM0_TR_OUT0261 = 0x0000060Fu, /* tcpwm[0].tr_out0[261] */ 357 TRIG_IN_MUX_6_TCPWM0_TR_OUT1261 = 0x00000610u, /* tcpwm[0].tr_out1[261] */ 358 TRIG_IN_MUX_6_TCPWM0_TR_OUT0262 = 0x00000611u, /* tcpwm[0].tr_out0[262] */ 359 TRIG_IN_MUX_6_TCPWM0_TR_OUT1262 = 0x00000612u /* tcpwm[0].tr_out1[262] */ 360 } en_trig_input_tcpwm_pdm_t; 361 362 /* Trigger Input Group 7 - CAN TT Synchronization triggers */ 363 typedef enum 364 { 365 TRIG_IN_MUX_7_CAN_TT_TR_OUT0 = 0x00000701u /* canfd[0].tr_tmp_rtp_out[0] */ 366 } en_trig_input_cantt_t; 367 368 /* Trigger Input Group 8 - CAN TT Synchronization triggers */ 369 typedef enum 370 { 371 TRIG_IN_MUX_8_SCB_TX0 = 0x00000801u, /* scb[0].tr_tx_req */ 372 TRIG_IN_MUX_8_CAN_DBG0 = 0x00000802u /* canfd[0].tr_dbg_dma_req[0] */ 373 } en_trig_input_scb_can0_t; 374 375 /* Trigger Input Group 9 - CAN TT Synchronization triggers */ 376 typedef enum 377 { 378 TRIG_IN_MUX_9_SCB_RX0 = 0x00000901u, /* scb[0].tr_rx_req */ 379 TRIG_IN_MUX_9_CAN_FIFO0 = 0x00000902u /* canfd[0].tr_fifo0[0] */ 380 } en_trig_input_scb_can1_t; 381 382 /* Trigger Group Outputs */ 383 /* Trigger Output Group 0 - P-DMA0 Request Assignments */ 384 typedef enum 385 { 386 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 387 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 388 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 389 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u /* cpuss.dw0_tr_in[3] */ 390 } en_trig_output_pdma0_tr_t; 391 392 /* Trigger Output Group 1 - TCPWM0 trigger multiplexer */ 393 typedef enum 394 { 395 TRIG_OUT_MUX_1_TCPWM0_TR_IN0 = 0x40000100u, /* tcpwm[0].tr_all_cnt_in[0] */ 396 TRIG_OUT_MUX_1_TCPWM0_TR_IN1 = 0x40000101u, /* tcpwm[0].tr_all_cnt_in[1] */ 397 TRIG_OUT_MUX_1_TCPWM0_TR_IN2 = 0x40000102u, /* tcpwm[0].tr_all_cnt_in[2] */ 398 TRIG_OUT_MUX_1_TCPWM0_TR_IN3 = 0x40000103u, /* tcpwm[0].tr_all_cnt_in[3] */ 399 TRIG_OUT_MUX_1_TCPWM0_TR_IN4 = 0x40000104u, /* tcpwm[0].tr_all_cnt_in[4] */ 400 TRIG_OUT_MUX_1_TCPWM0_TR_IN5 = 0x40000105u, /* tcpwm[0].tr_all_cnt_in[5] */ 401 TRIG_OUT_MUX_1_TCPWM0_TR_IN6 = 0x40000106u, /* tcpwm[0].tr_all_cnt_in[6] */ 402 TRIG_OUT_MUX_1_TCPWM0_TR_IN7 = 0x40000107u, /* tcpwm[0].tr_all_cnt_in[7] */ 403 TRIG_OUT_MUX_1_TCPWM0_TR_IN8 = 0x40000108u, /* tcpwm[0].tr_all_cnt_in[8] */ 404 TRIG_OUT_MUX_1_TCPWM0_TR_IN9 = 0x40000109u, /* tcpwm[0].tr_all_cnt_in[9] */ 405 TRIG_OUT_MUX_1_TCPWM0_TR_IN10 = 0x4000010Au, /* tcpwm[0].tr_all_cnt_in[10] */ 406 TRIG_OUT_MUX_1_TCPWM0_TR_IN11 = 0x4000010Bu, /* tcpwm[0].tr_all_cnt_in[11] */ 407 TRIG_OUT_MUX_1_TCPWM0_TR_IN12 = 0x4000010Cu, /* tcpwm[0].tr_all_cnt_in[12] */ 408 TRIG_OUT_MUX_1_TCPWM0_TR_IN13 = 0x4000010Du /* tcpwm[0].tr_all_cnt_in[13] */ 409 } en_trig_output_tcpwm0_t; 410 411 /* Trigger Output Group 2 - TCPWM1 trigger multiplexer */ 412 typedef enum 413 { 414 TRIG_OUT_MUX_2_TCPWM0_TR_IN14 = 0x40000200u, /* tcpwm[0].tr_all_cnt_in[14] */ 415 TRIG_OUT_MUX_2_TCPWM0_TR_IN15 = 0x40000201u, /* tcpwm[0].tr_all_cnt_in[15] */ 416 TRIG_OUT_MUX_2_TCPWM0_TR_IN16 = 0x40000202u, /* tcpwm[0].tr_all_cnt_in[16] */ 417 TRIG_OUT_MUX_2_TCPWM0_TR_IN17 = 0x40000203u, /* tcpwm[0].tr_all_cnt_in[17] */ 418 TRIG_OUT_MUX_2_TCPWM0_TR_IN18 = 0x40000204u, /* tcpwm[0].tr_all_cnt_in[18] */ 419 TRIG_OUT_MUX_2_TCPWM0_TR_IN19 = 0x40000205u, /* tcpwm[0].tr_all_cnt_in[19] */ 420 TRIG_OUT_MUX_2_TCPWM0_TR_IN20 = 0x40000206u, /* tcpwm[0].tr_all_cnt_in[20] */ 421 TRIG_OUT_MUX_2_TCPWM0_TR_IN21 = 0x40000207u, /* tcpwm[0].tr_all_cnt_in[21] */ 422 TRIG_OUT_MUX_2_TCPWM0_TR_IN22 = 0x40000208u, /* tcpwm[0].tr_all_cnt_in[22] */ 423 TRIG_OUT_MUX_2_TCPWM0_TR_IN23 = 0x40000209u, /* tcpwm[0].tr_all_cnt_in[23] */ 424 TRIG_OUT_MUX_2_TCPWM0_TR_IN24 = 0x4000020Au, /* tcpwm[0].tr_all_cnt_in[24] */ 425 TRIG_OUT_MUX_2_TCPWM0_TR_IN25 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[25] */ 426 TRIG_OUT_MUX_2_TCPWM0_TR_IN26 = 0x4000020Cu, /* tcpwm[0].tr_all_cnt_in[26] */ 427 TRIG_OUT_MUX_2_TCPWM0_TR_IN27 = 0x4000020Du /* tcpwm[0].tr_all_cnt_in[27] */ 428 } en_trig_output_tcpwm1_t; 429 430 /* Trigger Output Group 3 - HSIOM trigger multiplexer */ 431 typedef enum 432 { 433 TRIG_OUT_MUX_3_HSIOM_TR_IO_OUTPUT0 = 0x40000300u, /* ioss.peri_tr_io_output_out[0] */ 434 TRIG_OUT_MUX_3_HSIOM_TR_IO_OUTPUT1 = 0x40000301u /* ioss.peri_tr_io_output_out[1] */ 435 } en_trig_output_hsiom_t; 436 437 /* Trigger Output Group 4 - CPUSS Debug multiplexer */ 438 typedef enum 439 { 440 TRIG_OUT_MUX_4_CPUSS_CTI_TR_IN0 = 0x40000400u, /* cpuss.cti_tr_in[0] */ 441 TRIG_OUT_MUX_4_CPUSS_CTI_TR_IN1 = 0x40000401u, /* cpuss.cti_tr_in[1] */ 442 TRIG_OUT_MUX_4_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000403u /* srss.tr_debug_freeze_mcwdt[0] */ 443 } en_trig_output_cpuss_cti_t; 444 445 /* Trigger Output Group 5 - PERI Freeze trigger multiplexer */ 446 typedef enum 447 { 448 TRIG_OUT_MUX_5_PERI_DEBUG_FREEZE_TR_IN = 0x40000500u, /* peri.tr_dbg_freeze */ 449 TRIG_OUT_MUX_5_PDM_DEBUG_FREEZE_TR_IN = 0x40000501u, /* pdm.tr_dbg_freeze */ 450 TRIG_OUT_MUX_5_TDM_DEBUG_FREEZE_TR_IN = 0x40000502u, /* tdm.tr_dbg_freeze */ 451 TRIG_OUT_MUX_5_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000503u /* tcpwm[0].tr_debug_freeze */ 452 } en_trig_output_peri_freeze_t; 453 454 /* Trigger Output Group 6 - TCPWM and PDM trigger multiplexer */ 455 typedef enum 456 { 457 TRIG_OUT_MUX_6_PDM_TR_ACTIVATE0 = 0x40000600u, /* pdm.tr_activate[0] */ 458 TRIG_OUT_MUX_6_PDM_TR_ACTIVATE1 = 0x40000601u /* pdm.tr_activate[1] */ 459 } en_trig_output_tcpwm_pdm_t; 460 461 /* Trigger Output Group 7 - CAN TT Synchronization triggers */ 462 typedef enum 463 { 464 TRIG_OUT_MUX_7_CAN_TT_TR_IN0 = 0x40000700u /* canfd[0].tr_evt_swt_in[0] */ 465 } en_trig_output_cantt_t; 466 467 /* Trigger Output Group 8 - CAN TT Synchronization triggers */ 468 typedef enum 469 { 470 TRIG_OUT_MUX_8_PDMA0_TR_IN4 = 0x40000800u /* cpuss.dw0_tr_in[4] */ 471 } en_trig_output_scb_can0_t; 472 473 /* Trigger Output Group 9 - CAN TT Synchronization triggers */ 474 typedef enum 475 { 476 TRIG_OUT_MUX_9_PDMA0_TR_IN5 = 0x40000900u /* cpuss.dw0_tr_in[5] */ 477 } en_trig_output_scb_can1_t; 478 479 /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ 480 typedef enum 481 { 482 TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN6 = 0x40001000u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[6] */ 483 TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN7 = 0x40001001u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[7] */ 484 TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA1_TR_IN8 = 0x40001002u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[8] */ 485 TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA1_TR_IN9 = 0x40001003u /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[9] */ 486 } en_trig_output_1to1_scb_pdma0_tr_t; 487 488 /* Trigger Output Group 1 - I2S and PDM PDMA triggers (OneToOne) */ 489 typedef enum 490 { 491 TRIG_OUT_1TO1_1_I2S0_TX_TO_PDMA0_TR_IN10 = 0x40001100u, /* From tdm.tr_tx_req[0] to cpuss.dw0_tr_in[10] */ 492 TRIG_OUT_1TO1_1_I2S0_RX_TO_PDMA0_TR_IN11 = 0x40001101u, /* From tdm.tr_rx_req[0] to cpuss.dw0_tr_in[11] */ 493 TRIG_OUT_1TO1_1_PDM0_RX_TO_PDMA0_TR_IN12 = 0x40001102u, /* From pdm.tr_rx_req[0] to cpuss.dw0_tr_in[12] */ 494 TRIG_OUT_1TO1_1_PDM0_RX_TO_PDMA0_TR_IN13 = 0x40001103u, /* From pdm.tr_rx_req[1] to cpuss.dw0_tr_in[13] */ 495 TRIG_OUT_1TO1_1_PDM0_RX_ALL_TO_PDMA0_TR_IN14 = 0x40001104u /* From pdm.tr_rx_req_all to cpuss.dw0_tr_in[14] */ 496 } en_trig_output_1to1_audioss_pdma1_tr_t; 497 498 /* Trigger Output Group 2 - CAN to PDMA0 direct connect (OneToOne) */ 499 typedef enum 500 { 501 TRIG_OUT_1TO1_2_CAN_FIFO1_TO_PDMA0_TR_IN15 = 0x40001200u /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[15] */ 502 } en_trig_output_1to1_can_to_pdma0_t; 503 504 /* Trigger Output Group 3 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ 505 typedef enum 506 { 507 TRIG_OUT_1TO1_3_PDMA0_TR_OUT0_ACK_TO_CAN_0 = 0x40001300u /* From cpuss.dw0_tr_out[8] to canfd[0].tr_dbg_dma_ack[0] */ 508 } en_trig_output_1to1_can0_dw_ack_t; 509 510 /* Trigger Output Group 4 - Dedicated triggers to LIN[0] (OneToOne) */ 511 typedef enum 512 { 513 TRIG_OUT_1TO1_4_PDMA0_TR_OUT0_ACK_TO_LIN = 0x40001400u, /* From cpuss.dw0_tr_out[9] to lin[0].tr_cmd_tx_header[0] */ 514 TRIG_OUT_1TO1_4_PDMA0_TR_OUT1_ACK_TO_LIN = 0x40001401u /* From cpuss.dw0_tr_out[10] to lin[0].tr_cmd_tx_header[1] */ 515 } en_trig_output_1to1_to_lin0_t; 516 517 /* Level or edge detection setting for a trigger mux */ 518 typedef enum 519 { 520 /* The trigger is a simple level output */ 521 TRIGGER_TYPE_LEVEL = 0u, 522 /* The trigger is synchronized to the consumer blocks clock 523 and a two cycle pulse is generated on this clock */ 524 TRIGGER_TYPE_EDGE = 1u 525 } en_trig_type_t; 526 527 /* Trigger Type Defines */ 528 /* ADCMIC Trigger Types */ 529 #define TRIGGER_TYPE_ADCMIC_TR_ADCMIC_DATA TRIGGER_TYPE_LEVEL 530 #define TRIGGER_TYPE_ADCMIC_TR_ADCMIC_DC TRIGGER_TYPE_LEVEL 531 /* BTSS Trigger Types */ 532 #define TRIGGER_TYPE_BTSS_TR_RX_PACKET_SYNC TRIGGER_TYPE_EDGE 533 #define TRIGGER_TYPE_BTSS_TR_TX_START TRIGGER_TYPE_EDGE 534 /* CANFD Trigger Types */ 535 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 536 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 537 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 538 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 539 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 540 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 541 /* CPUSS Trigger Types */ 542 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 543 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 544 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 545 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 546 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 547 /* CRYPTO Trigger Types */ 548 #define TRIGGER_TYPE_CRYPTO_TR_TRNG_BITSTREAM TRIGGER_TYPE_LEVEL 549 /* LIN Trigger Types */ 550 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 551 /* PDM Trigger Types */ 552 #define TRIGGER_TYPE_PDM_TR_ACTIVATE TRIGGER_TYPE_LEVEL 553 #define TRIGGER_TYPE_PDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 554 #define TRIGGER_TYPE_PDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 555 #define TRIGGER_TYPE_PDM_TR_RX_REQ_ALL TRIGGER_TYPE_LEVEL 556 /* PERI Trigger Types */ 557 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 558 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 559 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 560 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 561 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 562 /* SCB Trigger Types */ 563 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 564 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 565 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 566 /* SMIF Trigger Types */ 567 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 568 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 569 /* SRSS Trigger Types */ 570 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 571 /* TCPWM Trigger Types */ 572 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 573 /* TDM Trigger Types */ 574 #define TRIGGER_TYPE_TDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 575 #define TRIGGER_TYPE_TDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 576 #define TRIGGER_TYPE_TDM_TR_TX_REQ TRIGGER_TYPE_LEVEL 577 578 /* Include IP definitions */ 579 #include "ip/cyip_peri.h" 580 #include "ip/cyip_ppc.h" 581 #include "ip/cyip_peri_pclk.h" 582 #include "ip/cyip_ramc_ppu.h" 583 #include "ip/cyip_icache.h" 584 #include "ip/cyip_cpuss_ppu.h" 585 #include "ip/cyip_ramc.h" 586 #include "ip/cyip_promc.h" 587 #include "ip/cyip_mxcm33.h" 588 #include "ip/cyip_dw.h" 589 #include "ip/cyip_cpuss.h" 590 #include "ip/cyip_ms_ctl_1_2.h" 591 #include "ip/cyip_cpuss_sl_ctl.h" 592 #include "ip/cyip_ipc.h" 593 #include "ip/cyip_srss.h" 594 #include "ip/cyip_pwrmode.h" 595 #include "ip/cyip_backup.h" 596 #include "ip/cyip_cryptolite.h" 597 #include "ip/cyip_hsiom.h" 598 #include "ip/cyip_gpio.h" 599 #include "ip/cyip_smartio.h" 600 #include "ip/cyip_lin.h" 601 #include "ip/cyip_canfd_v3.h" 602 #include "ip/cyip_tcpwm_v2.h" 603 #include "ip/cyip_mxs40adcmic.h" 604 #include "ip/cyip_scb_v4.h" 605 #include "ip/cyip_efuse_v3.h" 606 #include "ip/cyip_efuse_data_v3_cyw20829.h" 607 #include "ip/cyip_smif_v3.h" 608 #include "ip/cyip_tdm.h" 609 #include "ip/cyip_pdm.h" 610 #include "ip/cyip_mxkeyscan.h" 611 #include "ip/cyip_btss.h" 612 613 /* Parameter Defines */ 614 /* Number of TTCAN instances */ 615 #define CANFD_CAN_NR 1u 616 /* ECC logic present or not */ 617 #define CANFD_ECC_PRESENT 0u 618 /* address included in ECC logic or not */ 619 #define CANFD_ECC_ADDR_PRESENT 0u 620 /* Time Stamp counter present or not (required for instance 0, otherwise not 621 allowed) */ 622 #define CANFD_TS_PRESENT 1u 623 /* Message RAM size in KB */ 624 #define CANFD_MRAM_SIZE 4u 625 /* Message RAM address width */ 626 #define CANFD_MRAM_ADDR_WIDTH 10u 627 /* System RAM 0 MPC protection block size in Bytes: 1<< (RAMC0_BLOCK_SIZE+5). 628 Example: 7 = 4KB protection block size. */ 629 #define CPUSS_RAMC0_BLOCK_SIZE 7u 630 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System 631 SRAM0 is implemented with 8 32KB macros. */ 632 #define CPUSS_RAMC0_MACRO_NR 4u 633 /* Number of power partitions in system RAM 0. Each power partition can be 634 independently power controlled using a switch. Example: RAMC0_MACRO_NR = 16 635 and RAMC0_PWR_GROUP_NR = 4 will create 4 power partitions with 4 macros in 636 each power partition. */ 637 #define CPUSS_RAMC0_PWR_GROUP_NR 4u 638 /* System RAM 1 present or not (0=No, 1=Yes) */ 639 #define CPUSS_RAMC1_PRESENT 0u 640 /* System RAM 1 MPC protection block size in Bytes: 1<< (RAMC1_BLOCK_SIZE+5). 641 Example: 7 = 4KB protection block size. */ 642 #define CPUSS_RAMC1_BLOCK_SIZE 7u 643 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 644 RAM 1 is implemented with 8 32KB macros. */ 645 #define CPUSS_RAMC1_MACRO_NR 1u 646 /* Number of power partitions in system RAM 1. Each power partition can be 647 independently power controlled using a switch. Example: RAMC1_MACRO_NR = 16 648 and RAMC1_PWR_GROUP_NR = 4 will create 4 power partitions with 4 macros in 649 each power partition. */ 650 #define CPUSS_RAMC1_PWR_GROUP_NR 1u 651 /* System RAM 2 present or not (0=No, 1=Yes) */ 652 #define CPUSS_RAMC2_PRESENT 0u 653 /* System RAM 2 MPC protection block size in Bytes: 1<< (RAMC2_BLOCK_SIZE+5). 654 Example: 7 = 4KB protection block size. */ 655 #define CPUSS_RAMC2_BLOCK_SIZE 7u 656 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 657 RAM 2 is implemented with 8 32KB macros. */ 658 #define CPUSS_RAMC2_MACRO_NR 1u 659 /* Number of power partitions in system RAM 2. Each power partition can be 660 independently power controlled using a switch. Example: RAMC2_MACRO_NR = 16 661 and RAMC2_PWR_GROUP_NR = 4 will create 4 power partitions with 4 macros in 662 each power partition. */ 663 #define CPUSS_RAMC2_PWR_GROUP_NR 1u 664 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 665 #define CPUSS_RAMC_ECC_PRESENT 0u 666 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 667 #define CPUSS_RAMC_ECC_ADDR_PRESENT 0u 668 /* System Patchable ROM Controller Present or not ('0' : no, '1': yes) */ 669 #define CPUSS_PROMC_PRESENT 1u 670 /* Number of macros used to implement system patchable ROM. Example: 4 if 512 KB 671 system patchable ROM is implemented with 4 128KB macros. */ 672 #define CPUSS_PROMC_MACRO_NR 1u 673 /* PROMC memory block size for protection scheme : 1<< (PROMC_BLOCK_SIZE+5). 674 Example: 7 = 4KB protection block size. */ 675 #define CPUSS_PROMC_BLOCK_SIZE 6u 676 /* Presence of the patch functionality. 0: ROM cannot be patched. 1: ROM can be 677 patched. */ 678 #define CPUSS_PROMC_PATCH_PRESENT 0u 679 /* Number of patchable locations (patch entries). Possible range [32,512] in 680 powers of 2. (BRCM: 512 is only supported) These are implemented using SRAM. 681 (SNPS: 32x128, 64x128, 128x128, 256x128, 512x128 are supported; BRCM: 4 682 instances of 512x32 only supported) */ 683 #define CPUSS_PROMC_PATCH_NR 64u 684 /* Patch size selection of a single structure. 0: 8 Bytes. 1: 16 Bytes. **) 2: 32 685 Bytes. 3: 64 Bytes. **) The patch size should fit to the word size of the 686 ROM. Thus only PATCH_SIZE=1 is supported for this ROM controller. */ 687 #define CPUSS_PROMC_PATCH_SIZE 1u 688 /* Width of compared address bits. The LSB is determined by the PATCH_SIZE, for 16 689 bytes this equals to bit [4]. The MSB is chosen to address the full size of 690 the ROM in bytes. */ 691 #define CPUSS_PROMC_MATCH_ADDR_SIZE 12u 692 /* Initial value of the first patchable address in the ROM. This address and the 693 following higher addresses are patchable if the function is enabled. */ 694 #define CPUSS_PROMC_SROM_BOUNDARY 0x00001000u 695 /* Flash Controller Present or not ('0' : no, '1': yes) */ 696 #define CPUSS_FLASHC_PRESENT 0u 697 /* Flash data output word size (in Bytes) */ 698 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u 699 /* Number of Flash BIST_DATA registers */ 700 #define CPUSS_FLASHC_BIST_DATA_NR 4u 701 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 702 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 703 Flash, and no Work Flash present. */ 704 #define CPUSS_FLASHC_SONOS_RWW 1u 705 /* SONOS Flash, number of main sectors. */ 706 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u 707 /* SONOS Flash, number of rows per main sector. */ 708 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u 709 /* SONOS Flash, number of words per row of main sector. */ 710 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u 711 /* SONOS Flash, number of special sectors. */ 712 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u 713 /* SONOS Flash, number of rows per special sector. */ 714 #define CPUSS_FLASHC_SONOS_SPL_ROWS 64u 715 /* DataWire 0 present or not ('0': no, '1': yes) */ 716 #define CPUSS_DW0_PRESENT 1u 717 /* Number of DataWire 0 channels (8, 16 or 32) */ 718 #define CPUSS_DW0_CH_NR 16u 719 /* DataWire 1 present or not ('0': no, '1': yes) */ 720 #define CPUSS_DW1_PRESENT 0u 721 /* Number of DataWire 1 channels (8, 16 or 32) */ 722 #define CPUSS_DW1_CH_NR 1u 723 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 724 #define CPUSS_DW_ECC_PRESENT 0u 725 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 726 #define CPUSS_DW_ECC_ADDR_PRESENT 0u 727 /* DMA controller-0 present or not ('0': no, '1': yes) */ 728 #define CPUSS_DMAC0_PRESENT 0u 729 /* Number of DMA controller-0 channels ([1, 8]) */ 730 #define CPUSS_DMAC0_CH_NR 1u 731 /* DMA controller-1 present or not ('0': no, '1': yes) */ 732 #define CPUSS_DMAC1_PRESENT 0u 733 /* Number of DMA controller-1 channels ([1, 8]) */ 734 #define CPUSS_DMAC1_CH_NR 1u 735 /* Number of IPC structures. Legal range [1, 16] */ 736 #define CPUSS_IPC_NR 4u 737 /* Number of IPC interrupt structures. Legal range [1, 16] */ 738 #define CPUSS_IPC_IRQ_NR 2u 739 /* Number of protection contexts supported. Legal range [3, 4, 6, 8] (CDT-336698) */ 740 #define CPUSS_PC_NR 4u 741 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 742 CM0+ PCU, which always uses system interrupt functionality. */ 743 #define CPUSS_SYSTEM_IRQ_PRESENT 0u 744 /* Number of total interrupt request inputs to CPUSS */ 745 #define CPUSS_SYSTEM_INT_NR 70u 746 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */ 747 #define CPUSS_SYSTEM_DPSLP_INT_NR 17u 748 /* Number of CPU interrupts used when SYSTEM_IRQ_PRESENT is '1'. Legal values 8, 749 16. */ 750 #define CPUSS_CM33_INT_NR 8u 751 /* Individual CPU interrupts to be disabled when SYSTEM_IRQ_PRESENT is '0'. 0: To 752 enable respective interrupt-bit functionality; 1: To disable respective 753 interrupt-bit functionality; Default value {480{1'b0}} to enable all 480 754 interrupts of CM33; Example: {479{1'b0},1'b1} disables the interrupt IRQ[0] 755 of CM33 and enables all other interrupts. This parameter is NOT applicable 756 when SYSTEM_IRQ_PRESENT is '1'. */ 757 #define CPUSS_CM33_IRQ_DISABLE 0u 758 /* CM33_0 Floating point unit present or not ('0': no, '1': yes) */ 759 #define CPUSS_CM33_0_FPU_PRESENT 0u 760 /* CM33_0 DSP extension present or not ('0': no, '1': yes) */ 761 #define CPUSS_CM33_0_DSP_PRESENT 0u 762 /* CM33_0 Security extension present or not ('0': no, '1': yes) */ 763 #define CPUSS_CM33_0_SECEXT_PRESENT 0u 764 /* CM33_0 non-secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 765 #define CPUSS_CM33_0_MPU_NS_REGION_NR 8u 766 /* CM33_0 secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 767 #define CPUSS_CM33_0_MPU_S_REGION_NR 0u 768 /* CM33_0 SAU regions. Legal values [0, 4, 8] */ 769 #define CPUSS_CM33_0_SAU_REGION_NR 0u 770 /* CM33_1 present or not. */ 771 #define CPUSS_CM33_1_PRESENT 0u 772 /* CM33_1 Floating point unit present or not ('0': no, '1': yes) */ 773 #define CPUSS_CM33_1_FPU_PRESENT 0u 774 /* CM33_1 DSP extension present or not ('0': no, '1': yes) */ 775 #define CPUSS_CM33_1_DSP_PRESENT 0u 776 /* CM33_1 Security extension present or not ('0': no, '1': yes) */ 777 #define CPUSS_CM33_1_SECEXT_PRESENT 0u 778 /* CM33_1 non-secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 779 #define CPUSS_CM33_1_MPU_NS_REGION_NR 16u 780 /* CM33_1 secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 781 #define CPUSS_CM33_1_MPU_S_REGION_NR 16u 782 /* CM33_1 SAU regions. Legal values [0, 4, 8] */ 783 #define CPUSS_CM33_1_SAU_REGION_NR 8u 784 /* Cache RAM size in Kilo Bytes; Supported values are [8, 16, 32]. */ 785 #define CPUSS_CACHE_SIZE 32u 786 /* Cache RAM ECC present or not ('0': no, '1': yes) */ 787 #define CPUSS_CACHE_RAM_ECC_PRESENT 0u 788 /* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 789 breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 790 watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ 791 #define CPUSS_DEBUG_LVL 2u 792 /* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + 793 ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace 794 level is not supported in CPUSS. */ 795 #define CPUSS_TRACE_LVL 1u 796 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */ 797 #define CPUSS_ETB_PRESENT 0u 798 /* PTM interface present (0=No, 1=Yes) */ 799 #define CPUSS_PTM_PRESENT 0u 800 /* Width of the PTM interface in bits ([2,32]) */ 801 #define CPUSS_PTM_WIDTH 1u 802 /* Width of the TPIU interface in bits ([1,4]) */ 803 #define CPUSS_TPIU_WIDTH 4u 804 /* CPUSS external CODE master interface 0 present or not on CODE infrastructure. 805 ('0': no, '1': yes). */ 806 #define CPUSS_CODE_MS_0_PRESENT 0u 807 /* CPUSS external SYS master interface 0 present or not on SYS infrastructure. 808 ('0': no, '1': yes). */ 809 #define CPUSS_SYS_MS_0_PRESENT 1u 810 /* CPUSS external SYS master interface 1 present or not on SYS infrastructure. 811 ('0': no, '1': yes). */ 812 #define CPUSS_SYS_MS_1_PRESENT 0u 813 /* CPUSS external SYS master NVM interface 0 present or not on SYS infrastructure. 814 ('0': no, '1': yes). */ 815 #define CPUSS_SYS_MS_0_NVM_PRESENT 0u 816 /* CPUSS external SYS master NVM interface 1 present or not on SYS infrastructure. 817 ('0': no, '1': yes). */ 818 #define CPUSS_SYS_MS_1_NVM_PRESENT 0u 819 /* Number of external AHB5 slave interfaces connected to SYSTEM infrastructure. 820 Maximum number of slaves supported is 4. Width of this parameter is 4-bits. 821 1-bit mask for each slave indicating present or not. Example: 4'b0001 - slave 822 0 is present. */ 823 #define CPUSS_SYS_SL_PRESENT 1u 824 /* Number of external EXPANSION masters driving the EXP AHB5 infrastructure. 825 Maximum number of masters supported is 8. Width of this parameter is 8-bits. 826 1-bit mask for each master indicating present or not. Example: 8'b0000_0101 - 827 master 0 & master 2 are present. */ 828 #define CPUSS_EXP_MS_PRESENT 1u 829 /* The timing de-coupled AHB brdige is present or not on the output of EXP 830 infrastructure. ('0': no, '1':yes) */ 831 #define CPUSS_EXP_BRIDGE_PRESENT 1u 832 /* Specifies the CODE interconnect is present or not; 0: Not present; 1: Present; */ 833 #define CPUSS_CODE_INFRA_PRESENT 1u 834 /* Specifies the CODE interconnect arbitration type used for generating the RTL. 835 0: ROUND; round insert an extra cycle each time the downstream port selects a 836 new upstream port to service and must be used to avoid timing issues when 837 target frequency is >=100MHz; 1: ROUND_NOLAT; round_nolat have no such 838 latency and can be used when target frequency is <100MHz; Improves the 839 performance by reducing latency; */ 840 #define CPUSS_CODE_INFRA_ARB_TYPE 1u 841 /* Specifies the SYSTEM interconnect arbitration type used for generating the RTL. 842 0: ROUND; round insert an extra cycle each time the downstream port selects a 843 new upstream port to service and must be used to avoid timing issues when 844 target frequency is >=100MHz; 1: ROUND_NOLAT; round_nolat have no such 845 latency and can be used when target frequency is <100MHz; Improves the 846 performance by reducing latency; */ 847 #define CPUSS_SYSTEM_INFRA_ARB_TYPE 1u 848 /* Specifies the EXPANSION interconnect arbitration type used for generating the 849 RTL. 0: ROUND; round insert an extra cycle each time the downstream port 850 selects a new upstream port to service and must be used to avoid timing 851 issues when target frequency is >=100MHz; 1: ROUND_NOLAT; round_nolat have no 852 such latency and can be used when target frequency is <100MHz; Improves the 853 performance by reducing latency; */ 854 #define CPUSS_EXP_INFRA_ARB_TYPE 1u 855 /* CoreSight Part Identification Number */ 856 #define CPUSS_JEPID 52u 857 /* CoreSight Part Identification Number */ 858 #define CPUSS_JEPCONTINUATION 0u 859 /* CoreSight Part Identification Number */ 860 #define CPUSS_FAMILYID 272u 861 /* ROM trim register width (for ARM 3, for Synopsys 5, for BRCM 6) */ 862 #define CPUSS_ROM_TRIM_WIDTH 5u 863 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002; for BRCM 864 0x0000_0000) */ 865 #define CPUSS_ROM_TRIM_DEFAULT 19u 866 /* RAM trim register width (for ARM 8, for SNPS 15, for BRCM 16) For SNPS: SRAM 867 will get its trim value from trim[15:0] and RF from trim [31:16] */ 868 #define CPUSS_RAM_TRIM_WIDTH 32u 869 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012, 870 for BRCM 0x0000_0000) */ 871 #define CPUSS_RAM_TRIM_DEFAULT 0x00004013u 872 /* RAM Trim control-2 register present or not; 1-present; 0-not present; Place 873 holder for S22 SRAM memories. */ 874 #define CPUSS_TRIM_RAM_CTL2_PRESENT 0u 875 /* RAM trim register width Place holder for S22 SRAM memories. */ 876 #define CPUSS_RAM_TRIM_WIDTH2 32u 877 /* RAM trim register default. Place holder for S22 SRAM memories. */ 878 #define CPUSS_RAM_TRIM_DEFAULT2 0x00006012u 879 /* RAM Trim control-3 register present or not; 1-present; 0-not present; Place 880 holder for S22 SRAM memories. */ 881 #define CPUSS_TRIM_RAM_CTL3_PRESENT 0u 882 /* RAM trim register width Place holder for S22 SRAM memories. */ 883 #define CPUSS_RAM_TRIM_WIDTH3 32u 884 /* RAM trim register default. Place holder for S22 SRAM memories. */ 885 #define CPUSS_RAM_TRIM_DEFAULT3 0x00006012u 886 /* RAM Trim control-4 register present or not; 1-present; 0-not present; Place 887 holder for S22 SRAM memories. */ 888 #define CPUSS_TRIM_RAM_CTL4_PRESENT 0u 889 /* RAM trim register width Place holder for S22 SRAM memories. */ 890 #define CPUSS_RAM_TRIM_WIDTH4 32u 891 /* RAM trim register default. Place holder for S22 SRAM memories. */ 892 #define CPUSS_RAM_TRIM_DEFAULT4 0x00006012u 893 /* Specifies the CM33-0 CACHE SRAM POWER SWITCH is present or not; 0: Not present; 894 1: Present; */ 895 #define CPUSS_CM33_0_CACHE_SWITCH_PRESENT 1u 896 /* Specifies the CM33-1 CACHE SRAM POWER SWITCH is present or not; 0: Not present; 897 1: Present; */ 898 #define CPUSS_CM33_1_CACHE_SWITCH_PRESENT 0u 899 /* Specifies the DW-0 SRAM POWER SWITCH is present or not; 0: Not present; 1: 900 Present; */ 901 #define CPUSS_DW0_SWITCH_PRESENT 0u 902 /* Specifies the DW-1 SRAM POWER SWITCH is present or not; 0: Not present; 1: 903 Present; */ 904 #define CPUSS_DW1_SWITCH_PRESENT 0u 905 /* Specifies the MPC SRAM POWER SWITCH is present or not; 0: Not present; 1: 906 Present; */ 907 #define CPUSS_MPC_SWITCH_PRESENT 0u 908 /* Specifies the PROMC Patch-SRAM POWER SWITCH is present or not; 0: Not present; 909 1: Present; */ 910 #define CPUSS_PROMC_SWITCH_PRESENT 0u 911 /* External Crystal Oscillator is present (high frequency) */ 912 #define CPUSS_ECO_PRESENT 0u 913 /* System RAM 0 size in KB */ 914 #define CPUSS_CHIP_TOP_RAMC0_SIZE 256u 915 /* System RAM 1 size in kilobytes */ 916 #define CPUSS_CHIP_TOP_RAMC1_SIZE 1u 917 /* System RAM 2 size in kilobytes */ 918 #define CPUSS_CHIP_TOP_RAMC2_SIZE 1u 919 /* System Patchable ROM size in KB */ 920 #define CPUSS_CHIP_TOP_PROMC_SIZE 64u 921 /* Flash main region size in KB */ 922 #define CPUSS_CHIP_TOP_FLASH_SIZE 2048u 923 /* Flash work region size in KB (EEPROM emulation, data) */ 924 #define CPUSS_CHIP_TOP_WFLASH_SIZE 32u 925 /* Flash supervisory region size in KB */ 926 #define CPUSS_CHIP_TOP_SFLASH_SIZE 32u 927 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 928 #define CPUSS_CHIP_TOP_ETB_SRAM_SIZE 2u 929 /* See MMIO2 instantiation or not */ 930 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 931 /* ETAS Calibration support pin out present (automotive only) */ 932 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u 933 /* TRACE_LVL>0 */ 934 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 935 /* Number of protection contexts supported. Legal range [3, 4, 6, 8] (CDT-336698) */ 936 #define CPUSS_MS_CTL_STRUCT_PC_NR 4u 937 /* IP MMIO registers base address in the system address space (32-bit Byte address 938 at a 64 kB multiple). The IP MMIO registers occupy a 64 kB memory region in 939 the system address space. */ 940 #define CRYPTOLITE_ADDR_BASE 0x40230000u 941 /* ECC present or not ('0': no, '1': yes). */ 942 #define CRYPTOLITE_ECC_PRESENT 0u 943 /* True random number generation component support ('0': no, '1': yes). */ 944 #define CRYPTOLITE_TRNG_PRESENT 1u 945 /* Vector unit component support ('0': no, '1': yes). */ 946 #define CRYPTOLITE_VU_PRESENT 1u 947 /* SHA-256 hash component support ('0': no, '1': yes). */ 948 #define CRYPTOLITE_SHA_PRESENT 1u 949 /* AES-128 block cipher component support ('0': no, '1': yes). */ 950 #define CRYPTOLITE_AES_PRESENT 1u 951 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 952 #define DFT_NUM_HFROOT 4u 953 /* Width of clk_occ_fast output bus (number of external OCCs) */ 954 #define DFT_EXT_OCC 0u 955 /* Number of PLLs usable as struct mode clock source (number of clk_occ_fast 956 clocks). Not expected to be more than 4 */ 957 #define DFT_NUM_FASTCLK 1u 958 /* Number of select signals to control each FASTCLK multiplexer. Not expected to 959 be more than 2 */ 960 #define DFT_NUM_FASTCLK_SEL 1u 961 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 962 signals. Value defined by CIC during Pass 1. */ 963 #define DFT_MBIST_C_NUM 7u 964 /* Number of LBIST controllers. One LBIST controller on top level and one LBIST 965 controller in each optional HDFT block */ 966 #define DFT_LBIST_C_NUM 1u 967 /* Number of MBISR chains. Separate chains are required for power domains that can 968 be enabled independently */ 969 #define DFT_MBISR_CH_NUM 1u 970 /* Defines if (Burn-In) Monitor function is present */ 971 #define DFT_MONITOR_PRESENT 1u 972 /* Defines if Mentor BISR controller is present (controls generation of control 973 and status register) */ 974 #define DFT_MENTOR_BISR_PRESENT 1u 975 /* Defines if Direct MBIST Access function is present (controls generation of 976 control and status registers) */ 977 #define DFT_DIRECT_MBIST_ACCESS_PRESENT 0u 978 /* Defines if DIRECT_MBIST*SEL and DIRECT_MBIST*_RESULT registers are generated 979 (only used for DIRECT_MBIST_ACCESS_PRESENT=1) */ 980 #define DFT_DIRECT_MBIST_CTRL_ACCESS_PRESENT 0u 981 /* Controls generation of BIST_STEP_SEL_EN and BIST_STEP_SEL register fields 982 within DIRECT_MBIST_CTL reg (only used for DIRECT_MBIST_ACCESS_PRESENT=1) */ 983 #define DFT_DIRECT_MBIST_STEP_ACCESS_PRESENT 0u 984 /* Controls generation of BIST_MEM_SEL_EN and BIST_MEM_SEL register fields within 985 DIRECT_MBIST_CTL reg (only used for DIRECT_MBIST_ACCESS_PRESENT=1) */ 986 #define DFT_DIRECT_MBIST_MEM_ACCESS_PRESENT 0u 987 /* Number of HLBs with Direct MBIST Access function (only used for 988 DIRECT_MBIST_ACCESS_PRESENT=1) */ 989 #define DFT_DIRECT_MBIST_BAP_NUM 1u 990 /* Maximum value of MBIST controllers connected to single BAP (only used for 991 DIRECT_MBIST_ACCESS_PRESENT=1) */ 992 #define DFT_DIRECT_MBIST_CTRL_NUM 1u 993 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST0_COMPLETED 994 register */ 995 #define DFT_MBIST0_C_NUM 7u 996 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST1_COMPLETED 997 register */ 998 #define DFT_MBIST1_C_NUM 1u 999 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST2_COMPLETED 1000 register */ 1001 #define DFT_MBIST2_C_NUM 1u 1002 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST3_COMPLETED 1003 register */ 1004 #define DFT_MBIST3_C_NUM 1u 1005 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST0_SEL and 1006 DIRECT_MBIST0_RESULT registers */ 1007 #define DFT_DIRECT_MBIST0_CTRL_NUM 1u 1008 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST1_SEL and 1009 DIRECT_MBIST1_RESULT registers */ 1010 #define DFT_DIRECT_MBIST1_CTRL_NUM 1u 1011 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST2_SEL and 1012 DIRECT_MBIST2_RESULT registers */ 1013 #define DFT_DIRECT_MBIST2_CTRL_NUM 1u 1014 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST3_SEL and 1015 DIRECT_MBIST3_RESULT registers */ 1016 #define DFT_DIRECT_MBIST3_CTRL_NUM 1u 1017 /* Must be set to 1 when using this mxdft version in MXS40Sv2 devices */ 1018 #define DFT_PLATFORM_MXS40SV2 1u 1019 /* Defines if VCCRET supply is generated in UPF. Must be set to 1 in MXS40S* 1020 technologies and to 0 in MXS40E */ 1021 #define DFT_VCCRET_PRESENT 1u 1022 /* Defines if UPF is generated for S28 technology (1) or S40 technolgy (0) */ 1023 #define DFT_TECH_S28 0u 1024 /* Controls the polulation of the "accessed" monitor bits <IOBSC,0,MBIST,LBIST>. 1025 Default = 4'b1011 */ 1026 #define DFT_POP_ACC 10u 1027 /* Controls the polulation of the "started" monitor bits 1028 <0,FLASH_DBI,MBIST,LBIST>. Default = 4'b0111 */ 1029 #define DFT_POP_START 2u 1030 /* Controls the polulation of the "done" (completed) monitor bits 1031 <0,FLASH_DBI,MBIST,LBIST>. Default = 4'b0111 */ 1032 #define DFT_POP_DONE 2u 1033 /* Controls the polulation of the "failed" monitor bits <0,0,MBIST,LBIST>. Default 1034 = 4'b0011 */ 1035 #define DFT_POP_FAIL 2u 1036 /* Used for mxdft_tap: controls generation of logic for "TDR capture&update via 1037 MMIO" (default value is 1) */ 1038 #define DFT_CAP_UP_PRESENT 0u 1039 /* Number of DataWire channels ([1, 512]) */ 1040 #define DW_CH_NR 16u 1041 /* DataWire SRAM ECC present or not ('0': no, '1': yes) */ 1042 #define DW_ECC_PRESENT 0u 1043 /* DataWire SRAM address ECC present or not ('0': no, '1': yes) */ 1044 #define DW_ECC_ADDR_PRESENT 0u 1045 #define DW_CH_NR_WIDTH 1u 1046 #define DW_CH_STRUCT_ECC_PRESENT 0u 1047 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [4,8,12,16] */ 1048 #define EFUSE_EFUSE_NR 4u 1049 /* Enables limiting access to region defined by PROT_MASTER_START/END by 1050 PROT_MASTER */ 1051 #define EFUSE_BLOCK_NVM_CRYPTO 0u 1052 /* Begining of region of EFUSE only accessible by master defined by PROT_MASTER. */ 1053 #define EFUSE_PROT_MASTER_START 4092u 1054 /* End of region of EFUSE (last address) only accessible by master defined by 1055 PROT_MASTER. */ 1056 #define EFUSE_PROT_MASTER_END 4092u 1057 /* The Master with permission to access the region defined by 1058 PROT_MASTER_START/PROT_MASTER_END */ 1059 #define EFUSE_PROT_MASTER 255u 1060 /* Cache SRAM ECC present or not ('0': no, '1': yes) */ 1061 #define ICACHE_ECC_PRESENT 0u 1062 /* Number of GPIO ports in range 0..31 */ 1063 #define IOSS_GPIO_GPIO_PORT_NR_0_31 6u 1064 /* Number of GPIO ports in range 32..63 */ 1065 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 1066 /* Number of GPIO ports in range 64..95 */ 1067 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 1068 /* Number of GPIO ports in range 96..127 */ 1069 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 1070 /* Number of ports in device */ 1071 #define IOSS_GPIO_GPIO_PORT_NR 6u 1072 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1073 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 1074 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1075 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 1076 /* Indicates port is an HSIO port */ 1077 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_HSIO 0u 1078 /* Indicates port is a GPIO_SMC */ 1079 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO_SMC 0u 1080 /* Indicates port is a HSIO_ENH */ 1081 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_HSIO_ENH 0u 1082 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1083 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u 1084 /* Indicates port supports drive select trims */ 1085 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DS_CTRL 0u 1086 /* Indicates port supports slew extension bits */ 1087 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_EXT 1u 1088 /* Indicates port supports drive select extension trims */ 1089 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_EXT 1u 1090 /* Indicates slew bit width */ 1091 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_WIDTH 1u 1092 /* Indicates drive bit width */ 1093 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_WIDTH 3u 1094 /* Indicates that pin #0 exists for this port with slew control feature */ 1095 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 0u 1096 /* Indicates that pin #1 exists for this port with slew control feature */ 1097 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 0u 1098 /* Indicates that pin #2 exists for this port with slew control feature */ 1099 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 0u 1100 /* Indicates that pin #3 exists for this port with slew control feature */ 1101 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 0u 1102 /* Indicates that pin #4 exists for this port with slew control feature */ 1103 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 1104 /* Indicates that pin #5 exists for this port with slew control feature */ 1105 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 1106 /* Indicates that pin #6 exists for this port with slew control feature */ 1107 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 1108 /* Indicates that pin #7 exists for this port with slew control feature */ 1109 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 1110 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1111 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 1112 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1113 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 1114 /* Indicates port is an HSIO port */ 1115 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_HSIO 0u 1116 /* Indicates port is a GPIO_SMC */ 1117 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO_SMC 0u 1118 /* Indicates port is a HSIO_ENH */ 1119 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_HSIO_ENH 0u 1120 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1121 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u 1122 /* Indicates port supports drive select trims */ 1123 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DS_CTRL 0u 1124 /* Indicates port supports slew extension bits */ 1125 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_EXT 1u 1126 /* Indicates port supports drive select extension trims */ 1127 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_EXT 1u 1128 /* Indicates slew bit width */ 1129 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_WIDTH 1u 1130 /* Indicates drive bit width */ 1131 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_WIDTH 3u 1132 /* Indicates that pin #0 exists for this port with slew control feature */ 1133 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 1134 /* Indicates that pin #1 exists for this port with slew control feature */ 1135 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 1136 /* Indicates that pin #2 exists for this port with slew control feature */ 1137 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 1138 /* Indicates that pin #3 exists for this port with slew control feature */ 1139 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 1140 /* Indicates that pin #4 exists for this port with slew control feature */ 1141 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 1142 /* Indicates that pin #5 exists for this port with slew control feature */ 1143 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 1144 /* Indicates that pin #6 exists for this port with slew control feature */ 1145 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 1146 /* Indicates that pin #7 exists for this port with slew control feature */ 1147 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 1148 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1149 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 1150 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1151 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 1152 /* Indicates port is an HSIO port */ 1153 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_HSIO 1u 1154 /* Indicates port is a GPIO_SMC */ 1155 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO_SMC 0u 1156 /* Indicates port is a HSIO_ENH */ 1157 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_HSIO_ENH 0u 1158 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1159 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u 1160 /* Indicates port supports drive select trims */ 1161 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DS_CTRL 0u 1162 /* Indicates port supports slew extension bits */ 1163 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_EXT 1u 1164 /* Indicates port supports drive select extension trims */ 1165 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_EXT 1u 1166 /* Indicates slew bit width */ 1167 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_WIDTH 1u 1168 /* Indicates drive bit width */ 1169 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_WIDTH 3u 1170 /* Indicates that pin #0 exists for this port with slew control feature */ 1171 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 1172 /* Indicates that pin #1 exists for this port with slew control feature */ 1173 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 1174 /* Indicates that pin #2 exists for this port with slew control feature */ 1175 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 1176 /* Indicates that pin #3 exists for this port with slew control feature */ 1177 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 1178 /* Indicates that pin #4 exists for this port with slew control feature */ 1179 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 1180 /* Indicates that pin #5 exists for this port with slew control feature */ 1181 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 1182 /* Indicates that pin #6 exists for this port with slew control feature */ 1183 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 1184 /* Indicates that pin #7 exists for this port with slew control feature */ 1185 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 1186 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1187 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 1188 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1189 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 1190 /* Indicates port is an HSIO port */ 1191 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_HSIO 0u 1192 /* Indicates port is a GPIO_SMC */ 1193 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO_SMC 0u 1194 /* Indicates port is a HSIO_ENH */ 1195 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_HSIO_ENH 0u 1196 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1197 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u 1198 /* Indicates port supports drive select trims */ 1199 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DS_CTRL 0u 1200 /* Indicates port supports slew extension bits */ 1201 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_EXT 1u 1202 /* Indicates port supports drive select extension trims */ 1203 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_EXT 1u 1204 /* Indicates slew bit width */ 1205 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_WIDTH 1u 1206 /* Indicates drive bit width */ 1207 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_WIDTH 3u 1208 /* Indicates that pin #0 exists for this port with slew control feature */ 1209 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 1210 /* Indicates that pin #1 exists for this port with slew control feature */ 1211 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 1212 /* Indicates that pin #2 exists for this port with slew control feature */ 1213 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 1214 /* Indicates that pin #3 exists for this port with slew control feature */ 1215 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 1216 /* Indicates that pin #4 exists for this port with slew control feature */ 1217 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 1218 /* Indicates that pin #5 exists for this port with slew control feature */ 1219 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 1220 /* Indicates that pin #6 exists for this port with slew control feature */ 1221 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 1222 /* Indicates that pin #7 exists for this port with slew control feature */ 1223 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 1224 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1225 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 1226 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1227 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 1228 /* Indicates port is an HSIO port */ 1229 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_HSIO 0u 1230 /* Indicates port is a GPIO_SMC */ 1231 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO_SMC 0u 1232 /* Indicates port is a HSIO_ENH */ 1233 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_HSIO_ENH 0u 1234 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1235 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u 1236 /* Indicates port supports drive select trims */ 1237 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DS_CTRL 0u 1238 /* Indicates port supports slew extension bits */ 1239 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_EXT 1u 1240 /* Indicates port supports drive select extension trims */ 1241 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_EXT 1u 1242 /* Indicates slew bit width */ 1243 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_WIDTH 1u 1244 /* Indicates drive bit width */ 1245 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_WIDTH 3u 1246 /* Indicates that pin #0 exists for this port with slew control feature */ 1247 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 1u 1248 /* Indicates that pin #1 exists for this port with slew control feature */ 1249 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 1u 1250 /* Indicates that pin #2 exists for this port with slew control feature */ 1251 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 1252 /* Indicates that pin #3 exists for this port with slew control feature */ 1253 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 1254 /* Indicates that pin #4 exists for this port with slew control feature */ 1255 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 1256 /* Indicates that pin #5 exists for this port with slew control feature */ 1257 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 1258 /* Indicates that pin #6 exists for this port with slew control feature */ 1259 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 1260 /* Indicates that pin #7 exists for this port with slew control feature */ 1261 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 1262 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1263 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 1264 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1265 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 1266 /* Indicates port is an HSIO port */ 1267 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_HSIO 0u 1268 /* Indicates port is a GPIO_SMC */ 1269 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO_SMC 0u 1270 /* Indicates port is a HSIO_ENH */ 1271 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_HSIO_ENH 0u 1272 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1273 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u 1274 /* Indicates port supports drive select trims */ 1275 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DS_CTRL 0u 1276 /* Indicates port supports slew extension bits */ 1277 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_EXT 1u 1278 /* Indicates port supports drive select extension trims */ 1279 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_EXT 1u 1280 /* Indicates slew bit width */ 1281 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_WIDTH 1u 1282 /* Indicates drive bit width */ 1283 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_WIDTH 3u 1284 /* Indicates that pin #0 exists for this port with slew control feature */ 1285 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 1286 /* Indicates that pin #1 exists for this port with slew control feature */ 1287 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 1288 /* Indicates that pin #2 exists for this port with slew control feature */ 1289 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 1290 /* Indicates that pin #3 exists for this port with slew control feature */ 1291 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 1292 /* Indicates that pin #4 exists for this port with slew control feature */ 1293 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 1294 /* Indicates that pin #5 exists for this port with slew control feature */ 1295 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 1296 /* Indicates that pin #6 exists for this port with slew control feature */ 1297 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 1298 /* Indicates that pin #7 exists for this port with slew control feature */ 1299 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 1300 /* Power Switch exists */ 1301 #define IOSS_GPIO_PWRSW 0u 1302 /* Number of AMUX splitter cells */ 1303 #define IOSS_HSIOM_AMUX_SPLIT_NR 0u 1304 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 1305 #define IOSS_HSIOM_HSIOM_PORT_NR 6u 1306 /* Number of PWR/GND MONITOR CELLs in the device */ 1307 #define IOSS_HSIOM_MONITOR_NR 0u 1308 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 1309 #define IOSS_HSIOM_MONITOR_NR_0_31 0u 1310 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 1311 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 1312 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 1313 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 1314 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 1315 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 1316 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 1317 #define IOSS_HSIOM_HSIOM_SEC_PORT_NR 0u 1318 /* Mask of SMARTIO instances presence */ 1319 #define IOSS_SMARTIO_SMARTIO_MASK 8u 1320 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 1321 #define IPC_PA_SIZE 32u 1322 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 1323 #define IPC_MASTER_WIDTH 6u 1324 #define IPC_IPC_NR 4u 1325 #define IPC_IPC_IRQ_NR 2u 1326 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 1327 connected), the minimal number of LIN channels is 2. */ 1328 #define LIN_CH_NR 2u 1329 /* Number of AHB5 "hmaster[]" bits ([1, 8]). */ 1330 #define LIN_MASTER_WIDTH 6u 1331 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 1332 8=T28HPL, 9=T28HPC */ 1333 #define LIN_CHIP_TOP_PLATFORM_VARIANT 6u 1334 /* CM33[0] should be 0, CM33[1] should have 1 */ 1335 #define MXCM33_CPU_WAIT_DEFAULT 0u 1336 /* Number of CPU interrupts used when SYSTEM_IRQ_PRESENT is '1'. Legal values 8, 1337 16. */ 1338 #define MXCM33_CM33_INT_NR 8u 1339 /* IRQ expander present ('0': no, '1': yes) */ 1340 #define MXCM33_SYSTEM_IRQ_PRESENT 0u 1341 /* CM33[0] should be 1, CM33[1] should have 0 */ 1342 #define MXCM33_PC_MON_PRESENT 1u 1343 /* Number of system interrupt inputs to CPUSS */ 1344 #define MXCM33_SYSTEM_INT_NR 70u 1345 /* TrustZone security extention present or not */ 1346 #define MXCM33_SECEXT 0u 1347 /* FPU extention present or not */ 1348 #define MXCM33_FPU_PRESENT 0u 1349 /* DSP extention present or not */ 1350 #define MXCM33_DSP_PRESENT 0u 1351 /* AHB5 master bus width */ 1352 #define MXKEYSCAN_AHB_MASTER_WIDTH 6u 1353 /* AHB5 data bus width */ 1354 #define MXKEYSCAN_AHB_DATA_WIDTH 32u 1355 /* AHB5 address bus width */ 1356 #define MXKEYSCAN_AHB_ADDR_WIDTH 12u 1357 /* AHB5 user bus width */ 1358 #define MXKEYSCAN_AHB_USER_WIDTH 4u 1359 /* AHB5 prot bus width */ 1360 #define MXKEYSCAN_AHB_PROT_WIDTH 7u 1361 /* Number of keyboard rows as input */ 1362 #define MXKEYSCAN_NUM_ROWS_IN 8u 1363 /* Number of keyboard columns as output */ 1364 #define MXKEYSCAN_NUM_COLS_OUT 18u 1365 /* CELL VT selection for ACTIVE Domain */ 1366 #define MXKEYSCAN_CELL_VT_TYPE_ACTIVE 1u 1367 /* CELL VT selection DEEEPSLEEP Domain */ 1368 #define MXKEYSCAN_CELL_VT_TYPE_DPSLP 0u 1369 /* Number of PDM structures ({2, 4, 6, 8}]). */ 1370 #define PDM_NR 2u 1371 /* Master interface presence mask (4 bits) */ 1372 #define PERI_MS_PRESENT 3u 1373 /* Clock control functionality present ('0': no, '1': yes) */ 1374 #define PERI_GROUP_PRESENT0_PERI_GROUP_CLOCK_PRESENT 0u 1375 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1376 Group-1 to Group-15 it is 32'h000_0000 */ 1377 #define PERI_GROUP_PRESENT0_PERI_GROUP_SL_CTL_DEFAULT 0xFFFFFFFFu 1378 /* Clock control functionality present ('0': no, '1': yes) */ 1379 #define PERI_GROUP_PRESENT1_PERI_GROUP_CLOCK_PRESENT 1u 1380 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1381 Group-1 to Group-15 it is 32'h000_0000 */ 1382 #define PERI_GROUP_PRESENT1_PERI_GROUP_SL_CTL_DEFAULT 0u 1383 /* Clock control functionality present ('0': no, '1': yes) */ 1384 #define PERI_GROUP_PRESENT2_PERI_GROUP_CLOCK_PRESENT 1u 1385 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1386 Group-1 to Group-15 it is 32'h000_0000 */ 1387 #define PERI_GROUP_PRESENT2_PERI_GROUP_SL_CTL_DEFAULT 0u 1388 /* Clock control functionality present ('0': no, '1': yes) */ 1389 #define PERI_GROUP_PRESENT3_PERI_GROUP_CLOCK_PRESENT 0u 1390 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1391 Group-1 to Group-15 it is 32'h000_0000 */ 1392 #define PERI_GROUP_PRESENT3_PERI_GROUP_SL_CTL_DEFAULT 0u 1393 /* Number of asynchronous PCLK groups */ 1394 #define PERI_PCLK_GROUP_NR 7u 1395 /* Defines the width of INTR_AHB_ERROR.AHB_ERROR_VIO register width based on 1396 number of peripheral groups enabled and AHB error reporting is enabled 1397 (AHB_ERROR_PRESENT==1) */ 1398 #define PERI_GROUP_AHB_ERROR_WIDTH 4u 1399 /* Defines the width of INTR_AHB_ERROR.TIMEOUT_VIO register width based on number 1400 of peripheral groups present and timeout error reporting logic is present 1401 (TIMEOUT_PRESENT==1). Note that group-0 is excluded from timeout reporting, 1402 so max width is 15 (group-1 to group-15). */ 1403 #define PERI_GROUP_TIMEOUT_WIDTH 3u 1404 /* Timeout functionality present ('0': no, '1': yes) */ 1405 #define PERI_TIMEOUT_PRESENT 1u 1406 /* AHB ERROR response reporting present ('0': no, '1':yes) */ 1407 #define PERI_AHB_ERROR_PRESENT 1u 1408 /* Trigger module present ('0': no, '1': yes) */ 1409 #define PERI_TR 1u 1410 /* Number of trigger groups */ 1411 #define PERI_TR_GROUP_NR 10u 1412 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1413 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1414 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1415 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1416 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1417 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1418 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1419 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1420 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1421 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1422 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1423 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1424 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1425 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1426 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1427 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1428 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1429 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1430 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1431 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1432 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1433 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1434 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1435 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1436 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1437 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1438 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1439 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1440 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1441 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1442 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 1443 #define PERI_GR_DIV_ADDR_WIDTH 4u 1444 /* Number of asynchronous PCLK groups */ 1445 #define PERI_PERI_PCLK_PCLK_GROUP_NR 7u 1446 /* Number of 8.0 dividers */ 1447 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 0u 1448 /* Number of 16.0 dividers */ 1449 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 0u 1450 /* Number of 16.5 (fractional) dividers */ 1451 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0u 1452 /* Number of 24.5 (fractional) dividers */ 1453 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 1u 1454 /* Number of programmable clocks [1, 256] */ 1455 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT 1u 1456 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1457 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_PCLK_DIV_PRESENT 1u 1458 /* Number of 8.0 dividers */ 1459 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 5u 1460 /* Number of 16.0 dividers */ 1461 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 4u 1462 /* Number of 16.5 (fractional) dividers */ 1463 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 2u 1464 /* Number of 24.5 (fractional) dividers */ 1465 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 1u 1466 /* Number of programmable clocks [1, 256] */ 1467 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT 16u 1468 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1469 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_PCLK_DIV_PRESENT 1u 1470 /* Number of 8.0 dividers */ 1471 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0u 1472 /* Number of 16.0 dividers */ 1473 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0u 1474 /* Number of 16.5 (fractional) dividers */ 1475 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0u 1476 /* Number of 24.5 (fractional) dividers */ 1477 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0u 1478 /* Number of programmable clocks [1, 256] */ 1479 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_CLOCK_VECT 0u 1480 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1481 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_PCLK_DIV_PRESENT 0u 1482 /* Number of 8.0 dividers */ 1483 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0u 1484 /* Number of 16.0 dividers */ 1485 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0u 1486 /* Number of 16.5 (fractional) dividers */ 1487 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 2u 1488 /* Number of 24.5 (fractional) dividers */ 1489 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0u 1490 /* Number of programmable clocks [1, 256] */ 1491 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_CLOCK_VECT 2u 1492 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1493 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_PCLK_DIV_PRESENT 1u 1494 /* Number of 8.0 dividers */ 1495 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0u 1496 /* Number of 16.0 dividers */ 1497 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0u 1498 /* Number of 16.5 (fractional) dividers */ 1499 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0u 1500 /* Number of 24.5 (fractional) dividers */ 1501 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0u 1502 /* Number of programmable clocks [1, 256] */ 1503 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_CLOCK_VECT 0u 1504 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1505 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_PCLK_DIV_PRESENT 0u 1506 /* Number of 8.0 dividers */ 1507 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0u 1508 /* Number of 16.0 dividers */ 1509 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0u 1510 /* Number of 16.5 (fractional) dividers */ 1511 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0u 1512 /* Number of 24.5 (fractional) dividers */ 1513 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0u 1514 /* Number of programmable clocks [1, 256] */ 1515 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_CLOCK_VECT 0u 1516 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1517 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_PCLK_DIV_PRESENT 0u 1518 /* Number of 8.0 dividers */ 1519 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0u 1520 /* Number of 16.0 dividers */ 1521 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0u 1522 /* Number of 16.5 (fractional) dividers */ 1523 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0u 1524 /* Number of 24.5 (fractional) dividers */ 1525 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0u 1526 /* Number of programmable clocks [1, 256] */ 1527 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_CLOCK_VECT 0u 1528 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1529 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_PCLK_DIV_PRESENT 0u 1530 /* Number of protection contexts supported. Legal range [3, 4, 6, 8] (CDT-336698) */ 1531 #define PERI_PPC_PC_NR 4u 1532 /* Security extension present ('0': no, '1': yes) */ 1533 #define PERI_PPC_SECEXT 0u 1534 /* Security Aware */ 1535 #define PERI_PPC_PPC_NR0_SECURITY_AWARE 0u 1536 /* Security Aware */ 1537 #define PERI_PPC_PPC_NR1_SECURITY_AWARE 0u 1538 /* Security Aware */ 1539 #define PERI_PPC_PPC_NR2_SECURITY_AWARE 0u 1540 /* Security Aware */ 1541 #define PERI_PPC_PPC_NR3_SECURITY_AWARE 0u 1542 /* Security Aware */ 1543 #define PERI_PPC_PPC_NR4_SECURITY_AWARE 0u 1544 /* Security Aware */ 1545 #define PERI_PPC_PPC_NR5_SECURITY_AWARE 0u 1546 /* Security Aware */ 1547 #define PERI_PPC_PPC_NR6_SECURITY_AWARE 0u 1548 /* Security Aware */ 1549 #define PERI_PPC_PPC_NR7_SECURITY_AWARE 0u 1550 /* Security Aware */ 1551 #define PERI_PPC_PPC_NR8_SECURITY_AWARE 0u 1552 /* Security Aware */ 1553 #define PERI_PPC_PPC_NR9_SECURITY_AWARE 0u 1554 /* Security Aware */ 1555 #define PERI_PPC_PPC_NR10_SECURITY_AWARE 0u 1556 /* Security Aware */ 1557 #define PERI_PPC_PPC_NR11_SECURITY_AWARE 0u 1558 /* Security Aware */ 1559 #define PERI_PPC_PPC_NR12_SECURITY_AWARE 0u 1560 /* Security Aware */ 1561 #define PERI_PPC_PPC_NR13_SECURITY_AWARE 0u 1562 /* Security Aware */ 1563 #define PERI_PPC_PPC_NR14_SECURITY_AWARE 0u 1564 /* Security Aware */ 1565 #define PERI_PPC_PPC_NR15_SECURITY_AWARE 0u 1566 /* Security Aware */ 1567 #define PERI_PPC_PPC_NR16_SECURITY_AWARE 0u 1568 /* Security Aware */ 1569 #define PERI_PPC_PPC_NR17_SECURITY_AWARE 0u 1570 /* Security Aware */ 1571 #define PERI_PPC_PPC_NR18_SECURITY_AWARE 0u 1572 /* Security Aware */ 1573 #define PERI_PPC_PPC_NR19_SECURITY_AWARE 0u 1574 /* Security Aware */ 1575 #define PERI_PPC_PPC_NR20_SECURITY_AWARE 0u 1576 /* Security Aware */ 1577 #define PERI_PPC_PPC_NR21_SECURITY_AWARE 0u 1578 /* Security Aware */ 1579 #define PERI_PPC_PPC_NR22_SECURITY_AWARE 0u 1580 /* Security Aware */ 1581 #define PERI_PPC_PPC_NR23_SECURITY_AWARE 0u 1582 /* Security Aware */ 1583 #define PERI_PPC_PPC_NR24_SECURITY_AWARE 0u 1584 /* Security Aware */ 1585 #define PERI_PPC_PPC_NR25_SECURITY_AWARE 0u 1586 /* Security Aware */ 1587 #define PERI_PPC_PPC_NR26_SECURITY_AWARE 0u 1588 /* Security Aware */ 1589 #define PERI_PPC_PPC_NR27_SECURITY_AWARE 0u 1590 /* Security Aware */ 1591 #define PERI_PPC_PPC_NR28_SECURITY_AWARE 0u 1592 /* Security Aware */ 1593 #define PERI_PPC_PPC_NR29_SECURITY_AWARE 0u 1594 /* Security Aware */ 1595 #define PERI_PPC_PPC_NR30_SECURITY_AWARE 0u 1596 /* Security Aware */ 1597 #define PERI_PPC_PPC_NR31_SECURITY_AWARE 0u 1598 /* Security Aware */ 1599 #define PERI_PPC_PPC_NR32_SECURITY_AWARE 0u 1600 /* Security Aware */ 1601 #define PERI_PPC_PPC_NR33_SECURITY_AWARE 0u 1602 /* Security Aware */ 1603 #define PERI_PPC_PPC_NR34_SECURITY_AWARE 0u 1604 /* Security Aware */ 1605 #define PERI_PPC_PPC_NR35_SECURITY_AWARE 0u 1606 /* Security Aware */ 1607 #define PERI_PPC_PPC_NR36_SECURITY_AWARE 0u 1608 /* Security Aware */ 1609 #define PERI_PPC_PPC_NR37_SECURITY_AWARE 0u 1610 /* Security Aware */ 1611 #define PERI_PPC_PPC_NR38_SECURITY_AWARE 0u 1612 /* Security Aware */ 1613 #define PERI_PPC_PPC_NR39_SECURITY_AWARE 0u 1614 /* Security Aware */ 1615 #define PERI_PPC_PPC_NR40_SECURITY_AWARE 0u 1616 /* Security Aware */ 1617 #define PERI_PPC_PPC_NR41_SECURITY_AWARE 0u 1618 /* Security Aware */ 1619 #define PERI_PPC_PPC_NR42_SECURITY_AWARE 0u 1620 /* Security Aware */ 1621 #define PERI_PPC_PPC_NR43_SECURITY_AWARE 0u 1622 /* Security Aware */ 1623 #define PERI_PPC_PPC_NR44_SECURITY_AWARE 0u 1624 /* Security Aware */ 1625 #define PERI_PPC_PPC_NR45_SECURITY_AWARE 0u 1626 /* Security Aware */ 1627 #define PERI_PPC_PPC_NR46_SECURITY_AWARE 0u 1628 /* Security Aware */ 1629 #define PERI_PPC_PPC_NR47_SECURITY_AWARE 0u 1630 /* Security Aware */ 1631 #define PERI_PPC_PPC_NR48_SECURITY_AWARE 0u 1632 /* Security Aware */ 1633 #define PERI_PPC_PPC_NR49_SECURITY_AWARE 0u 1634 /* Security Aware */ 1635 #define PERI_PPC_PPC_NR50_SECURITY_AWARE 0u 1636 /* Security Aware */ 1637 #define PERI_PPC_PPC_NR51_SECURITY_AWARE 0u 1638 /* Security Aware */ 1639 #define PERI_PPC_PPC_NR52_SECURITY_AWARE 0u 1640 /* Security Aware */ 1641 #define PERI_PPC_PPC_NR53_SECURITY_AWARE 0u 1642 /* Security Aware */ 1643 #define PERI_PPC_PPC_NR54_SECURITY_AWARE 0u 1644 /* Security Aware */ 1645 #define PERI_PPC_PPC_NR55_SECURITY_AWARE 0u 1646 /* Security Aware */ 1647 #define PERI_PPC_PPC_NR56_SECURITY_AWARE 0u 1648 /* Security Aware */ 1649 #define PERI_PPC_PPC_NR57_SECURITY_AWARE 0u 1650 /* Security Aware */ 1651 #define PERI_PPC_PPC_NR58_SECURITY_AWARE 0u 1652 /* Security Aware */ 1653 #define PERI_PPC_PPC_NR59_SECURITY_AWARE 0u 1654 /* Security Aware */ 1655 #define PERI_PPC_PPC_NR60_SECURITY_AWARE 0u 1656 /* Security Aware */ 1657 #define PERI_PPC_PPC_NR61_SECURITY_AWARE 0u 1658 /* Security Aware */ 1659 #define PERI_PPC_PPC_NR62_SECURITY_AWARE 0u 1660 /* Security Aware */ 1661 #define PERI_PPC_PPC_NR63_SECURITY_AWARE 0u 1662 /* Security Aware */ 1663 #define PERI_PPC_PPC_NR64_SECURITY_AWARE 0u 1664 /* Security Aware */ 1665 #define PERI_PPC_PPC_NR65_SECURITY_AWARE 1u 1666 /* Security Aware */ 1667 #define PERI_PPC_PPC_NR66_SECURITY_AWARE 1u 1668 /* Security Aware */ 1669 #define PERI_PPC_PPC_NR67_SECURITY_AWARE 1u 1670 /* Security Aware */ 1671 #define PERI_PPC_PPC_NR68_SECURITY_AWARE 1u 1672 /* Security Aware */ 1673 #define PERI_PPC_PPC_NR69_SECURITY_AWARE 1u 1674 /* Security Aware */ 1675 #define PERI_PPC_PPC_NR70_SECURITY_AWARE 1u 1676 /* Security Aware */ 1677 #define PERI_PPC_PPC_NR71_SECURITY_AWARE 0u 1678 /* Security Aware */ 1679 #define PERI_PPC_PPC_NR72_SECURITY_AWARE 0u 1680 /* Security Aware */ 1681 #define PERI_PPC_PPC_NR73_SECURITY_AWARE 0u 1682 /* Security Aware */ 1683 #define PERI_PPC_PPC_NR74_SECURITY_AWARE 0u 1684 /* Security Aware */ 1685 #define PERI_PPC_PPC_NR75_SECURITY_AWARE 0u 1686 /* Security Aware */ 1687 #define PERI_PPC_PPC_NR76_SECURITY_AWARE 0u 1688 /* Security Aware */ 1689 #define PERI_PPC_PPC_NR77_SECURITY_AWARE 0u 1690 /* Security Aware */ 1691 #define PERI_PPC_PPC_NR78_SECURITY_AWARE 0u 1692 /* Security Aware */ 1693 #define PERI_PPC_PPC_NR79_SECURITY_AWARE 0u 1694 /* Security Aware */ 1695 #define PERI_PPC_PPC_NR80_SECURITY_AWARE 0u 1696 /* Security Aware */ 1697 #define PERI_PPC_PPC_NR81_SECURITY_AWARE 0u 1698 /* Security Aware */ 1699 #define PERI_PPC_PPC_NR82_SECURITY_AWARE 0u 1700 /* Security Aware */ 1701 #define PERI_PPC_PPC_NR83_SECURITY_AWARE 0u 1702 /* Security Aware */ 1703 #define PERI_PPC_PPC_NR84_SECURITY_AWARE 0u 1704 /* Security Aware */ 1705 #define PERI_PPC_PPC_NR85_SECURITY_AWARE 0u 1706 /* Security Aware */ 1707 #define PERI_PPC_PPC_NR86_SECURITY_AWARE 1u 1708 /* Security Aware */ 1709 #define PERI_PPC_PPC_NR87_SECURITY_AWARE 1u 1710 /* Security Aware */ 1711 #define PERI_PPC_PPC_NR88_SECURITY_AWARE 1u 1712 /* Security Aware */ 1713 #define PERI_PPC_PPC_NR89_SECURITY_AWARE 1u 1714 /* Security Aware */ 1715 #define PERI_PPC_PPC_NR90_SECURITY_AWARE 1u 1716 /* Security Aware */ 1717 #define PERI_PPC_PPC_NR91_SECURITY_AWARE 1u 1718 /* Security Aware */ 1719 #define PERI_PPC_PPC_NR92_SECURITY_AWARE 1u 1720 /* Security Aware */ 1721 #define PERI_PPC_PPC_NR93_SECURITY_AWARE 1u 1722 /* Security Aware */ 1723 #define PERI_PPC_PPC_NR94_SECURITY_AWARE 1u 1724 /* Security Aware */ 1725 #define PERI_PPC_PPC_NR95_SECURITY_AWARE 1u 1726 /* Security Aware */ 1727 #define PERI_PPC_PPC_NR96_SECURITY_AWARE 1u 1728 /* Security Aware */ 1729 #define PERI_PPC_PPC_NR97_SECURITY_AWARE 1u 1730 /* Security Aware */ 1731 #define PERI_PPC_PPC_NR98_SECURITY_AWARE 1u 1732 /* Security Aware */ 1733 #define PERI_PPC_PPC_NR99_SECURITY_AWARE 1u 1734 /* Security Aware */ 1735 #define PERI_PPC_PPC_NR100_SECURITY_AWARE 1u 1736 /* Security Aware */ 1737 #define PERI_PPC_PPC_NR101_SECURITY_AWARE 1u 1738 /* Security Aware */ 1739 #define PERI_PPC_PPC_NR102_SECURITY_AWARE 1u 1740 /* Security Aware */ 1741 #define PERI_PPC_PPC_NR103_SECURITY_AWARE 1u 1742 /* Security Aware */ 1743 #define PERI_PPC_PPC_NR104_SECURITY_AWARE 1u 1744 /* Security Aware */ 1745 #define PERI_PPC_PPC_NR105_SECURITY_AWARE 1u 1746 /* Security Aware */ 1747 #define PERI_PPC_PPC_NR106_SECURITY_AWARE 1u 1748 /* Security Aware */ 1749 #define PERI_PPC_PPC_NR107_SECURITY_AWARE 0u 1750 /* Security Aware */ 1751 #define PERI_PPC_PPC_NR108_SECURITY_AWARE 0u 1752 /* Security Aware */ 1753 #define PERI_PPC_PPC_NR109_SECURITY_AWARE 0u 1754 /* Security Aware */ 1755 #define PERI_PPC_PPC_NR110_SECURITY_AWARE 0u 1756 /* Security Aware */ 1757 #define PERI_PPC_PPC_NR111_SECURITY_AWARE 0u 1758 /* Security Aware */ 1759 #define PERI_PPC_PPC_NR112_SECURITY_AWARE 0u 1760 /* Security Aware */ 1761 #define PERI_PPC_PPC_NR113_SECURITY_AWARE 0u 1762 /* Security Aware */ 1763 #define PERI_PPC_PPC_NR114_SECURITY_AWARE 0u 1764 /* Security Aware */ 1765 #define PERI_PPC_PPC_NR115_SECURITY_AWARE 0u 1766 /* Security Aware */ 1767 #define PERI_PPC_PPC_NR116_SECURITY_AWARE 0u 1768 /* Security Aware */ 1769 #define PERI_PPC_PPC_NR117_SECURITY_AWARE 0u 1770 /* Security Aware */ 1771 #define PERI_PPC_PPC_NR118_SECURITY_AWARE 0u 1772 /* Security Aware */ 1773 #define PERI_PPC_PPC_NR119_SECURITY_AWARE 0u 1774 /* Security Aware */ 1775 #define PERI_PPC_PPC_NR120_SECURITY_AWARE 0u 1776 /* Security Aware */ 1777 #define PERI_PPC_PPC_NR121_SECURITY_AWARE 0u 1778 /* Security Aware */ 1779 #define PERI_PPC_PPC_NR122_SECURITY_AWARE 0u 1780 /* Security Aware */ 1781 #define PERI_PPC_PPC_NR123_SECURITY_AWARE 0u 1782 /* Security Aware */ 1783 #define PERI_PPC_PPC_NR124_SECURITY_AWARE 0u 1784 /* Security Aware */ 1785 #define PERI_PPC_PPC_NR125_SECURITY_AWARE 0u 1786 /* Security Aware */ 1787 #define PERI_PPC_PPC_NR126_SECURITY_AWARE 0u 1788 /* Security Aware */ 1789 #define PERI_PPC_PPC_NR127_SECURITY_AWARE 0u 1790 /* Security Aware */ 1791 #define PERI_PPC_PPC_NR128_SECURITY_AWARE 0u 1792 /* Security Aware */ 1793 #define PERI_PPC_PPC_NR129_SECURITY_AWARE 0u 1794 /* Security Aware */ 1795 #define PERI_PPC_PPC_NR130_SECURITY_AWARE 0u 1796 /* Security Aware */ 1797 #define PERI_PPC_PPC_NR131_SECURITY_AWARE 0u 1798 /* Security Aware */ 1799 #define PERI_PPC_PPC_NR132_SECURITY_AWARE 0u 1800 /* Security Aware */ 1801 #define PERI_PPC_PPC_NR133_SECURITY_AWARE 0u 1802 /* Security Aware */ 1803 #define PERI_PPC_PPC_NR134_SECURITY_AWARE 0u 1804 /* Security Aware */ 1805 #define PERI_PPC_PPC_NR135_SECURITY_AWARE 0u 1806 /* Security Aware */ 1807 #define PERI_PPC_PPC_NR136_SECURITY_AWARE 0u 1808 /* Security Aware */ 1809 #define PERI_PPC_PPC_NR137_SECURITY_AWARE 0u 1810 /* Security Aware */ 1811 #define PERI_PPC_PPC_NR138_SECURITY_AWARE 0u 1812 /* Security Aware */ 1813 #define PERI_PPC_PPC_NR139_SECURITY_AWARE 0u 1814 /* Security Aware */ 1815 #define PERI_PPC_PPC_NR140_SECURITY_AWARE 0u 1816 /* Security Aware */ 1817 #define PERI_PPC_PPC_NR141_SECURITY_AWARE 0u 1818 /* Security Aware */ 1819 #define PERI_PPC_PPC_NR142_SECURITY_AWARE 0u 1820 /* Security Aware */ 1821 #define PERI_PPC_PPC_NR143_SECURITY_AWARE 0u 1822 /* Security Aware */ 1823 #define PERI_PPC_PPC_NR144_SECURITY_AWARE 0u 1824 /* Security Aware */ 1825 #define PERI_PPC_PPC_NR145_SECURITY_AWARE 0u 1826 /* Security Aware */ 1827 #define PERI_PPC_PPC_NR146_SECURITY_AWARE 0u 1828 /* Security Aware */ 1829 #define PERI_PPC_PPC_NR147_SECURITY_AWARE 0u 1830 /* Security Aware */ 1831 #define PERI_PPC_PPC_NR148_SECURITY_AWARE 0u 1832 /* Security Aware */ 1833 #define PERI_PPC_PPC_NR149_SECURITY_AWARE 0u 1834 /* Security Aware */ 1835 #define PERI_PPC_PPC_NR150_SECURITY_AWARE 0u 1836 /* Security Aware */ 1837 #define PERI_PPC_PPC_NR151_SECURITY_AWARE 0u 1838 /* Security Aware */ 1839 #define PERI_PPC_PPC_NR152_SECURITY_AWARE 0u 1840 /* Security Aware */ 1841 #define PERI_PPC_PPC_NR153_SECURITY_AWARE 0u 1842 /* Security Aware */ 1843 #define PERI_PPC_PPC_NR154_SECURITY_AWARE 0u 1844 /* Security Aware */ 1845 #define PERI_PPC_PPC_NR155_SECURITY_AWARE 0u 1846 /* Security Aware */ 1847 #define PERI_PPC_PPC_NR156_SECURITY_AWARE 0u 1848 /* Presence of the patch functionality. 0: ROM cannot be patched. 1: ROM can be 1849 patched. */ 1850 #define PROMC_PATCH_PRESENT 0u 1851 /* Number of patchable locations (patch entries). Possible range [0,512]. */ 1852 #define PROMC_PATCH_NR 64u 1853 /* Number of patchable locations, qualified by PATCH_PRESENT. Local param to mimic 1854 by product XLS. */ 1855 #define PROMC_PATCH_NR_QUAL 0u 1856 /* Patch size selection of a single structure. 0: 8 Bytes. 1: 16 Bytes. **) 2: 32 1857 Bytes. 3: 64 Bytes. **) The patch size should fit to the word size of the 1858 ROM. Thus only PATCH_SIZE=1 is supported for this ROM controller. */ 1859 #define PROMC_PATCH_SIZE 1u 1860 /* Width of compared address bits. The LSB is determined by the PATCH_SIZE, for 16 1861 bytes this equals to bit [4]. The MSB is chosen to address the full size of 1862 the ROM in bytes. */ 1863 #define PROMC_MATCH_ADDR_SIZE 12u 1864 /* Initial value of the first patchable address in the ROM. This address and the 1865 following higher addresses are patchable if the function is enabled. */ 1866 #define PROMC_SROM_BOUNDARY 303u 1867 /* Width of the byte address (2^ROMC_ADDR_WIDTH byte of total SROM region). */ 1868 #define PROMC_ROMC_ADDR_WIDTH 16u 1869 /* Number of physical SROM macros used. */ 1870 #define PROMC_ROMC_MACRO_NR 1u 1871 /* Width of the byte address per each physical macro. */ 1872 #define PROMC_ROMC_MACRO_ADDR_WIDTH 16u 1873 /* Bit width of hrdata and hwdata (AHB5 slave for ROM access). */ 1874 #define PROMC_DATA_PATH_WIDTH 128u 1875 /* Number of RAM words for patch data. Local param to mimic by product XLS. */ 1876 #define PROMC_PATCH_RAM_WORDS 0u 1877 /* VT type of instantiated tech cells through mxtk. */ 1878 #define PROMC_CELL_VT_TYPE 1u 1879 /* Bit width of mmio_trim_ram_ctl_trim. */ 1880 #define PROMC_TRIM_WIDTH 32u 1881 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 1882 8=T28HPL, 9=T28HPC */ 1883 #define PROMC_PLATFORM_VARIANT 6u 1884 /* RAM vendor (0=Cypress, 1=Synopsys, 2=ARM, 3=Broadcom,4=TSMC) */ 1885 #define PROMC_RAM_VEND 1u 1886 /* Security based access checks are valid (1: NS bit is checked, 0: NS bit is 1887 ignored). */ 1888 #define PROMC_MPC_SECEXT 0u 1889 /* Bit width of hmaster signal. */ 1890 #define PROMC_MPC_MASTER_WIDTH 6u 1891 #define PROMC_MPC_PC_WIDTH 3u 1892 /* Number of supported protection contexts. */ 1893 #define PROMC_MPC_PC_NR 4u 1894 #define PROMC_MPC_BLK_IDX_MAX 0u 1895 #define PROMC_MPC_BLK_IDX_WIDTH 0u 1896 #define PROMC_MPC_EXT_PRESENT 0u 1897 #define PROMC_MPC_BLK_IDX_MAX_TIMES_FOUR_PLUS_THREE 3u 1898 #define PROMC_MPC_BLK_IDX_WIDTH_PLUS_TWO 2u 1899 /* Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1MB) */ 1900 #define PROMC_MPC_BLOCK_SIZE 6u 1901 /* Number of AHB5 "huser[]" bits ([1, 8]). */ 1902 #define PROMC_MPC_USER_WIDTH 4u 1903 /* Number of System SRAM power partions */ 1904 #define RAMC_PWR_GROUP_NR 4u 1905 /* SRAM ECC present or not ('0': no, '1': yes) */ 1906 #define RAMC_ECC_PRESENT 0u 1907 #define RAMC_MPC_MASTER_WIDTH 6u 1908 #define RAMC_MPC_PC_WIDTH 3u 1909 #define RAMC_MPC_PC_NR 4u 1910 #define RAMC_MPC_BLK_IDX_MAX 1u 1911 #define RAMC_MPC_BLK_IDX_WIDTH 1u 1912 #define RAMC_MPC_EXT_PRESENT 0u 1913 #define RAMC_MPC_BLK_IDX_MAX_TIMES_FOUR_PLUS_THREE 7u 1914 #define RAMC_MPC_BLK_IDX_WIDTH_PLUS_TWO 3u 1915 #define RAMC_MPC_BLOCK_SIZE 7u 1916 /* DeepSleep support ('0':no, '1': yes) */ 1917 #define SCB0_DEEPSLEEP 1u 1918 /* Externally clocked support? ('0': no, '1': yes) */ 1919 #define SCB0_EC 1u 1920 /* I2C master support? ('0': no, '1': yes) */ 1921 #define SCB0_I2C_M 1u 1922 /* I2C slave support? ('0': no, '1': yes) */ 1923 #define SCB0_I2C_S 1u 1924 /* I2C support? (I2C_M | I2C_S) */ 1925 #define SCB0_I2C 1u 1926 /* I2C glitch filters present? ('0': no, '1': yes) */ 1927 #define SCB0_I2C_GLITCH 1u 1928 /* Support I2C Hs-mode (3.4Mbps) ('0': no, '1': yes) */ 1929 #define SCB0_I2C_HS 0u 1930 /* I2C externally clocked support? ('0': no, '1': yes) */ 1931 #define SCB0_I2C_EC 1u 1932 /* I2C master and slave support? (I2C_M & I2C_S) */ 1933 #define SCB0_I2C_M_S 1u 1934 /* I2C master and slave support? (I2C_M & I2C_HS) */ 1935 #define SCB0_I2C_M_HS 0u 1936 /* I2C master and slave support? (I2C_S & I2C_HS) */ 1937 #define SCB0_I2C_S_HS 0u 1938 /* I2C slave with EC? (I2C_S & I2C_EC) */ 1939 #define SCB0_I2C_S_EC 1u 1940 /* SPI master support? ('0': no, '1': yes) */ 1941 #define SCB0_SPI_M 1u 1942 /* SPI slave support? ('0': no, '1': yes) */ 1943 #define SCB0_SPI_S 1u 1944 /* SPI support? (SPI_M | SPI_S) */ 1945 #define SCB0_SPI 1u 1946 /* SPI externally clocked support? ('0': no, '1': yes) */ 1947 #define SCB0_SPI_EC 1u 1948 /* SPI slave with EC? (SPI_S & SPI_EC) */ 1949 #define SCB0_SPI_S_EC 1u 1950 /* UART support? ('0': no, '1': yes) */ 1951 #define SCB0_UART 0u 1952 /* SPI or UART (SPI | UART) */ 1953 #define SCB0_SPI_UART 1u 1954 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 1955 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 1956 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 1957 #define SCB0_EZ_DATA_NR 256u 1958 /* Command/response mode support? ('0': no, '1': yes) */ 1959 #define SCB0_CMD_RESP 1u 1960 /* EZ mode support? ('0': no, '1': yes) */ 1961 #define SCB0_EZ 1u 1962 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 1963 #define SCB0_EZ_CMD_RESP 1u 1964 /* I2C slave with EZ mode (I2C_S & EZ) */ 1965 #define SCB0_I2C_S_EZ 1u 1966 /* SPI slave with EZ mode (SPI_S & EZ) */ 1967 #define SCB0_SPI_S_EZ 1u 1968 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 1969 #define SCB0_MASTER_WIDTH 8u 1970 /* Number of used spi_select signals (max 4) */ 1971 #define SCB0_CHIP_TOP_SPI_SEL_NR 3u 1972 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 1973 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 1974 /* ddft_in[1:0] and ddft_out[1:0] are used (not used on M0S8 platform) */ 1975 #define SCB0_CHIP_TOP_DDFT_USED 4u 1976 /* DeepSleep support ('0':no, '1': yes) */ 1977 #define SCB1_DEEPSLEEP 0u 1978 /* Externally clocked support? ('0': no, '1': yes) */ 1979 #define SCB1_EC 0u 1980 /* I2C master support? ('0': no, '1': yes) */ 1981 #define SCB1_I2C_M 0u 1982 /* I2C slave support? ('0': no, '1': yes) */ 1983 #define SCB1_I2C_S 0u 1984 /* I2C support? (I2C_M | I2C_S) */ 1985 #define SCB1_I2C 0u 1986 /* I2C glitch filters present? ('0': no, '1': yes) */ 1987 #define SCB1_I2C_GLITCH 0u 1988 /* Support I2C Hs-mode (3.4Mbps) ('0': no, '1': yes) */ 1989 #define SCB1_I2C_HS 0u 1990 /* I2C externally clocked support? ('0': no, '1': yes) */ 1991 #define SCB1_I2C_EC 0u 1992 /* I2C master and slave support? (I2C_M & I2C_S) */ 1993 #define SCB1_I2C_M_S 0u 1994 /* I2C master and slave support? (I2C_M & I2C_HS) */ 1995 #define SCB1_I2C_M_HS 0u 1996 /* I2C master and slave support? (I2C_S & I2C_HS) */ 1997 #define SCB1_I2C_S_HS 0u 1998 /* I2C slave with EC? (I2C_S & I2C_EC) */ 1999 #define SCB1_I2C_S_EC 0u 2000 /* SPI master support? ('0': no, '1': yes) */ 2001 #define SCB1_SPI_M 1u 2002 /* SPI slave support? ('0': no, '1': yes) */ 2003 #define SCB1_SPI_S 1u 2004 /* SPI support? (SPI_M | SPI_S) */ 2005 #define SCB1_SPI 1u 2006 /* SPI externally clocked support? ('0': no, '1': yes) */ 2007 #define SCB1_SPI_EC 0u 2008 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2009 #define SCB1_SPI_S_EC 0u 2010 /* UART support? ('0': no, '1': yes) */ 2011 #define SCB1_UART 1u 2012 /* SPI or UART (SPI | UART) */ 2013 #define SCB1_SPI_UART 1u 2014 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2015 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2016 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2017 #define SCB1_EZ_DATA_NR 256u 2018 /* Command/response mode support? ('0': no, '1': yes) */ 2019 #define SCB1_CMD_RESP 0u 2020 /* EZ mode support? ('0': no, '1': yes) */ 2021 #define SCB1_EZ 0u 2022 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2023 #define SCB1_EZ_CMD_RESP 0u 2024 /* I2C slave with EZ mode (I2C_S & EZ) */ 2025 #define SCB1_I2C_S_EZ 0u 2026 /* SPI slave with EZ mode (SPI_S & EZ) */ 2027 #define SCB1_SPI_S_EZ 0u 2028 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2029 #define SCB1_MASTER_WIDTH 8u 2030 /* Number of used spi_select signals (max 4) */ 2031 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 2032 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2033 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 2034 /* ddft_in[1:0] and ddft_out[1:0] are used (not used on M0S8 platform) */ 2035 #define SCB1_CHIP_TOP_DDFT_USED 4u 2036 /* DeepSleep support ('0':no, '1': yes) */ 2037 #define SCB2_DEEPSLEEP 0u 2038 /* Externally clocked support? ('0': no, '1': yes) */ 2039 #define SCB2_EC 0u 2040 /* I2C master support? ('0': no, '1': yes) */ 2041 #define SCB2_I2C_M 1u 2042 /* I2C slave support? ('0': no, '1': yes) */ 2043 #define SCB2_I2C_S 1u 2044 /* I2C support? (I2C_M | I2C_S) */ 2045 #define SCB2_I2C 1u 2046 /* I2C glitch filters present? ('0': no, '1': yes) */ 2047 #define SCB2_I2C_GLITCH 1u 2048 /* Support I2C Hs-mode (3.4Mbps) ('0': no, '1': yes) */ 2049 #define SCB2_I2C_HS 0u 2050 /* I2C externally clocked support? ('0': no, '1': yes) */ 2051 #define SCB2_I2C_EC 0u 2052 /* I2C master and slave support? (I2C_M & I2C_S) */ 2053 #define SCB2_I2C_M_S 1u 2054 /* I2C master and slave support? (I2C_M & I2C_HS) */ 2055 #define SCB2_I2C_M_HS 0u 2056 /* I2C master and slave support? (I2C_S & I2C_HS) */ 2057 #define SCB2_I2C_S_HS 0u 2058 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2059 #define SCB2_I2C_S_EC 0u 2060 /* SPI master support? ('0': no, '1': yes) */ 2061 #define SCB2_SPI_M 0u 2062 /* SPI slave support? ('0': no, '1': yes) */ 2063 #define SCB2_SPI_S 0u 2064 /* SPI support? (SPI_M | SPI_S) */ 2065 #define SCB2_SPI 0u 2066 /* SPI externally clocked support? ('0': no, '1': yes) */ 2067 #define SCB2_SPI_EC 0u 2068 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2069 #define SCB2_SPI_S_EC 0u 2070 /* UART support? ('0': no, '1': yes) */ 2071 #define SCB2_UART 1u 2072 /* SPI or UART (SPI | UART) */ 2073 #define SCB2_SPI_UART 1u 2074 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2075 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2076 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2077 #define SCB2_EZ_DATA_NR 256u 2078 /* Command/response mode support? ('0': no, '1': yes) */ 2079 #define SCB2_CMD_RESP 0u 2080 /* EZ mode support? ('0': no, '1': yes) */ 2081 #define SCB2_EZ 0u 2082 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2083 #define SCB2_EZ_CMD_RESP 0u 2084 /* I2C slave with EZ mode (I2C_S & EZ) */ 2085 #define SCB2_I2C_S_EZ 0u 2086 /* SPI slave with EZ mode (SPI_S & EZ) */ 2087 #define SCB2_SPI_S_EZ 0u 2088 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2089 #define SCB2_MASTER_WIDTH 8u 2090 /* Number of used spi_select signals (max 4) */ 2091 #define SCB2_CHIP_TOP_SPI_SEL_NR 0u 2092 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2093 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 2094 /* ddft_in[1:0] and ddft_out[1:0] are used (not used on M0S8 platform) */ 2095 #define SCB2_CHIP_TOP_DDFT_USED 4u 2096 /* Slow AHB XIP cache is present ([0,1]). If SLOW_AHB_XIP_IF_PRESENT=0 then set 2097 this to 0 as well. */ 2098 #define SMIF_SLOW_CACHE_PRESENT 0u 2099 /* Fast AHB XIP cache is present ([0,1]). If FAST_AHB_XIP_IF_PRESENT=0 then set 2100 this to 0 as well. */ 2101 #define SMIF_FAST_CACHE_PRESENT 0u 2102 /* Number of Protection Contexts [1..8] for MPC; only valid when SLOW or 2103 FAST_AHB_XIP_IF_IS_AHB5 */ 2104 #define SMIF_PC_NR 4u 2105 /* Granularity of the MPC block size; 0: 32B, 1: 64B, ... 15: 1MB; only valid when 2106 SLOW or FAST_AHB_XIP_IF_IS_AHB5 */ 2107 #define SMIF_BLOCK_SIZE 12u 2108 /* Base address of the SMIF XIP memory region. This address must be a multiple of 2109 the SMIF XIP memory capacity. This address must be a multiple of the SMIF XIP 2110 memory region capacity (see SMIP_XIP_MASK below). The SMIF XIP memory region 2111 should NOT overlap with other memory regions. This adress must be in the 2112 [0x0000:0000, 0xffff:0000] memory region. However, for MXS40 CM4 based 2113 platform variant, this address must be in the [0x0000:0000, 0x1fff:0000] 2114 memory region (to ensure a connection to the ARM CM4 CPU ICode/DCode memory 2115 region [0x0000:0000, 0x1fff:ffff]). The external memory devices are located 2116 within the SMIF XIP memory region. */ 2117 #define SMIF_SMIF_XIP_ADDR 0x60000000u 2118 /* Capacity of the SMIF XIP memory region. The capacity must be a power of 2 and 2119 greater or equal than 64 KB). The more significant bits of this parameter are 2120 '1' and the lesser significant bits of this parameter are '0'. E.g., 2121 0xfff0:0000 specifies a 1 MB memory region. Legal values are {0xffff:0000, 2122 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 0xffe0:0000, ..., 2123 0x8000:0000, 0x0000:0000}. */ 2124 #define SMIF_SMIF_XIP_MASK 0xF8000000u 2125 /* Cryptography (AES) support. This is a 1-bit parameter: '0' = no support, '1' = 2126 support. */ 2127 #define SMIF_CRYPTO 1u 2128 /* Number of cryptography keys [0,1,2,4,8]; set to 0 if CRYPTO=0 */ 2129 #define SMIF_CRYPTO_KEY_NR 1u 2130 /* Hardcoded 8-bit parameter (do NOT override) that allows crypto key 0 to take on 2131 additional registers to support MMIO encryption */ 2132 #define SMIF_CRYPTO_KEY_MMIO_CAPABLE 1u 2133 /* Bus CRC support is present ([0,1]) Note: In MXS40 SMIF version 2 this option is 2134 currently not available (BUS_CRC_PRESENT=0). Based on project schedules this 2135 feature may be added already to MXS40 SMIF version 2 or to a later SMIF 2136 version. */ 2137 #define SMIF_BUS_CRC_PRESENT 0u 2138 /* Number of external memory devices supported. This parameter is in the range 2139 [1,4]. */ 2140 #define SMIF_DEVICE_NR 2u 2141 /* External memory devices write support. This is a 4-bit field. Each external 2142 memory device has a dedicated bit. E.g., if bit 2 is '1', external device 2 2143 has write support. */ 2144 #define SMIF_DEVICE_WR_EN 3u 2145 /* Number of delay lines ([1..8]). */ 2146 #define SMIF_DELAY_LINES_NR 4u 2147 /* Number of delay taps in clock delay line. */ 2148 #define SMIF_DELAY_TAPS_NR 32u 2149 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2150 #define SMIF_MASTER_WIDTH 6u 2151 /* AXI ID width. Legal range [11,16] */ 2152 #define SMIF_AXIS_ID_WIDTH 16u 2153 /* MPC SECEXT Present */ 2154 #define SMIF_MPC_SECEXT 0u 2155 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 2156 pins) */ 2157 #define SMIF_CHIP_TOP_DATA8_PRESENT 0u 2158 /* Number of used spi_select signals (max 4) */ 2159 #define SMIF_CHIP_TOP_SPI_SEL_NR 2u 2160 /* S40S variant. Must be 1 when targeting S40S and 0 otherwise. */ 2161 #define SRSS_S40S_VARIANT 1u 2162 /* S40E variant. Must be 1 when targeting S40E and 0 otherwise. */ 2163 #define SRSS_S40E_VARIANT 0u 2164 /* Number of regulator modules instantiated within SRSS. Must be > 0. */ 2165 #define SRSS_NUM_ACTREG_PWRMOD 0u 2166 /* Number of shorting switches between vccd and vccact. Must be > 0. */ 2167 #define SRSS_NUM_ACTIVE_SWITCH 2u 2168 /* S40S variant. Number of shorting switches between vccd and vccdplsp for S40S 2169 REGSETB. Must be > 0. Has no affect when S40S_REGSETB_PRESENT=0 */ 2170 #define SRSS_NUM_DPSLP_SWITCH 6u 2171 /* S40S Regulator Set A system is present */ 2172 #define SRSS_S40S_REGSETA_PRESENT 0u 2173 /* S40E Regulator Set A system is present */ 2174 #define SRSS_S40E_REGSETA_PRESENT 0u 2175 /* SIMO buck core regulator is present. Only compatible with S40S linear regulator 2176 system (S40S_LINREG_PRESENT==1). */ 2177 #define SRSS_S40S_SIMOBUCK_PRESENT 0u 2178 /* Precision ILO (PILO) is present */ 2179 #define SRSS_S40S_PILO_PRESENT 1u 2180 /* External Crystal Oscillator is present (high frequency) */ 2181 #define SRSS_ECO_PRESENT 0u 2182 /* Number of clock paths. Must be > 0 */ 2183 #define SRSS_NUM_CLKPATH 4u 2184 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 2185 #define SRSS_NUM_PLL200M 0u 2186 /* Number of HFCLK roots present. Must be > 0 */ 2187 #define SRSS_NUM_HFROOT 4u 2188 /* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ 2189 #define SRSS_NUM_HIBDATA 1u 2190 /* Backup domain is present (includes RTC and WCO) */ 2191 #define SRSS_BACKUP_PRESENT 1u 2192 /* CSV present. User must add one NUM_CLKPATH and one NUM_HFROOT to monitor ILO0 2193 with CSV_HF_REF clock. */ 2194 #define SRSS_CSV_PRESENT 0u 2195 /* Number of software watchdog timers. */ 2196 #define SRSS_NUM_MCWDT 1u 2197 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 2198 #define SRSS_NUM_DSI 0u 2199 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 2200 #define SRSS_ALTHF_PRESENT 1u 2201 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 2202 #define SRSS_ALTLF_PRESENT 0u 2203 /* Use the hardened clkactfllmux block */ 2204 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 2205 /* Number of clock paths, including direct paths in hardened clkactfllmux block 2206 (Must be >= NUM_CLKPATH) */ 2207 #define SRSS_HARD_CLKPATH 8u 2208 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= 2209 NUM_PLL+1) */ 2210 #define SRSS_HARD_CLKPATHMUX 8u 2211 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ 2212 #define SRSS_HARD_HFROOT 8u 2213 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ 2214 #define SRSS_HARD_ECOMUX_PRESENT 1u 2215 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ 2216 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 2217 /* POR present. */ 2218 #define SRSS_POR_PRESENT 0u 2219 /* Low-current buck regulator present. Can be derived from 2220 S40S_SISOBUCKLC_PRESENT, S40S_SISOBUCKMC_PRESENT or S40S_SIMOBUCK_PRESENT. */ 2221 #define SRSS_BUCKCTL_PRESENT 0u 2222 /* Low-current SISO buck core regulator is present. Only compatible with S40S 2223 linear regulator system (S40S_LINREG_PRESENT==1). */ 2224 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 2225 /* S40E linear regulator system is present */ 2226 #define SRSS_S40E_REGHC_PRESENT 0u 2227 /* LPECO mux is present in hardened clkactfllmux block */ 2228 #define SRSS_HARD_LPECOMUX_PRESENT 1u 2229 /* Number of 400MHz PLLs present. */ 2230 #define SRSS_NUM_PLL400M 0u 2231 /* Mask of DIRECT_MUX defaults. For each clock root i, if bit[i] is low the 2232 DIRECT_MUX defaults to IMO. If bit[0] is high, the DIRECT_MUX selects the 2233 output of ROOT_MUX. For backward compatibility, M33-only systems can have all 2234 mask bits high. In all cases, must have bit[0]==1 to start the chip. */ 2235 #define SRSS_MASK_DIRECTMUX_DEF 0x0000FFFFu 2236 /* Mask of which HFCLK roots are enabled when the debugger requests power up 2237 (CDBGPWRUPREQ). For each clock root i, SRSS enables the clock in response to 2238 CDBGPWRUPREQ, if bit[i] of mask is high. SRSS automatically enables clk_hf0, 2239 regardless of setting of mask bit0. */ 2240 #define SRSS_MASK_DEBUG_CLK 1u 2241 /* Total number of PLLs present. */ 2242 #define SRSS_NUM_TOTAL_PLL 0u 2243 /* PMIC control of vccd is present (without REGHC). */ 2244 #define SRSS_S40E_PMIC_PRESENT 0u 2245 /* Number of multi-counter watchdog timers (type B). Software incompatibility with 2246 type A. */ 2247 #define SRSS_NUM_MCWDT_B 0u 2248 /* WDT type A is present (backward compatible version) */ 2249 #define SRSS_WDT_A_PRESENT 1u 2250 /* WDT type B is present. Software incompatibility with type A. */ 2251 #define SRSS_WDT_B_PRESENT 0u 2252 /* Medium-current SISO buck core regulator is present. Only compatible with S40S 2253 linear regulator system (S40S_LINREG_PRESENT==1). */ 2254 #define SRSS_S40S_SISOBUCKMC_PRESENT 0u 2255 /* Mask for whether a PD is present in the PDCM. The zeroth bit is the PD 2256 controlled by the main PPU and must always be set. */ 2257 #define SRSS_PDCM_PD_PRESENT 15u 2258 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2259 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2260 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2261 on. For configurable sense bits, this indicates the reset value of the 2262 configuration register. */ 2263 #define SRSS_PDCM_PD_PRESENT0_PDCM_PD_DEFAULT_ON 6u 2264 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2265 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2266 PD<k/16> can be configured on when PD<k%16> is on. */ 2267 #define SRSS_PDCM_PD_PRESENT0_PDCM_PD_CONFIG_ON 9u 2268 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2269 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2270 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2271 on. For configurable sense bits, this indicates the reset value of the 2272 configuration register. */ 2273 #define SRSS_PDCM_PD_PRESENT1_PDCM_PD_DEFAULT_ON 0u 2274 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2275 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2276 PD<k/16> can be configured on when PD<k%16> is on. */ 2277 #define SRSS_PDCM_PD_PRESENT1_PDCM_PD_CONFIG_ON 10u 2278 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2279 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2280 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2281 on. For configurable sense bits, this indicates the reset value of the 2282 configuration register. */ 2283 #define SRSS_PDCM_PD_PRESENT2_PDCM_PD_DEFAULT_ON 2u 2284 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2285 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2286 PD<k/16> can be configured on when PD<k%16> is on. */ 2287 #define SRSS_PDCM_PD_PRESENT2_PDCM_PD_CONFIG_ON 14u 2288 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2289 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2290 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2291 on. For configurable sense bits, this indicates the reset value of the 2292 configuration register. */ 2293 #define SRSS_PDCM_PD_PRESENT3_PDCM_PD_DEFAULT_ON 0u 2294 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2295 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2296 PD<k/16> can be configured on when PD<k%16> is on. */ 2297 #define SRSS_PDCM_PD_PRESENT3_PDCM_PD_CONFIG_ON 10u 2298 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2299 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2300 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2301 on. For configurable sense bits, this indicates the reset value of the 2302 configuration register. */ 2303 #define SRSS_PDCM_PD_PRESENT4_PDCM_PD_DEFAULT_ON 0u 2304 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2305 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2306 PD<k/16> can be configured on when PD<k%16> is on. */ 2307 #define SRSS_PDCM_PD_PRESENT4_PDCM_PD_CONFIG_ON 0u 2308 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2309 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2310 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2311 on. For configurable sense bits, this indicates the reset value of the 2312 configuration register. */ 2313 #define SRSS_PDCM_PD_PRESENT5_PDCM_PD_DEFAULT_ON 0u 2314 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2315 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2316 PD<k/16> can be configured on when PD<k%16> is on. */ 2317 #define SRSS_PDCM_PD_PRESENT5_PDCM_PD_CONFIG_ON 0u 2318 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2319 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2320 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2321 on. For configurable sense bits, this indicates the reset value of the 2322 configuration register. */ 2323 #define SRSS_PDCM_PD_PRESENT6_PDCM_PD_DEFAULT_ON 0u 2324 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2325 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2326 PD<k/16> can be configured on when PD<k%16> is on. */ 2327 #define SRSS_PDCM_PD_PRESENT6_PDCM_PD_CONFIG_ON 0u 2328 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2329 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2330 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2331 on. For configurable sense bits, this indicates the reset value of the 2332 configuration register. */ 2333 #define SRSS_PDCM_PD_PRESENT7_PDCM_PD_DEFAULT_ON 0u 2334 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2335 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2336 PD<k/16> can be configured on when PD<k%16> is on. */ 2337 #define SRSS_PDCM_PD_PRESENT7_PDCM_PD_CONFIG_ON 0u 2338 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2339 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2340 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2341 on. For configurable sense bits, this indicates the reset value of the 2342 configuration register. */ 2343 #define SRSS_PDCM_PD_PRESENT8_PDCM_PD_DEFAULT_ON 0u 2344 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2345 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2346 PD<k/16> can be configured on when PD<k%16> is on. */ 2347 #define SRSS_PDCM_PD_PRESENT8_PDCM_PD_CONFIG_ON 0u 2348 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2349 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2350 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2351 on. For configurable sense bits, this indicates the reset value of the 2352 configuration register. */ 2353 #define SRSS_PDCM_PD_PRESENT9_PDCM_PD_DEFAULT_ON 0u 2354 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2355 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2356 PD<k/16> can be configured on when PD<k%16> is on. */ 2357 #define SRSS_PDCM_PD_PRESENT9_PDCM_PD_CONFIG_ON 0u 2358 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2359 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2360 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2361 on. For configurable sense bits, this indicates the reset value of the 2362 configuration register. */ 2363 #define SRSS_PDCM_PD_PRESENT10_PDCM_PD_DEFAULT_ON 0u 2364 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2365 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2366 PD<k/16> can be configured on when PD<k%16> is on. */ 2367 #define SRSS_PDCM_PD_PRESENT10_PDCM_PD_CONFIG_ON 0u 2368 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2369 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2370 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2371 on. For configurable sense bits, this indicates the reset value of the 2372 configuration register. */ 2373 #define SRSS_PDCM_PD_PRESENT11_PDCM_PD_DEFAULT_ON 0u 2374 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2375 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2376 PD<k/16> can be configured on when PD<k%16> is on. */ 2377 #define SRSS_PDCM_PD_PRESENT11_PDCM_PD_CONFIG_ON 0u 2378 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2379 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2380 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2381 on. For configurable sense bits, this indicates the reset value of the 2382 configuration register. */ 2383 #define SRSS_PDCM_PD_PRESENT12_PDCM_PD_DEFAULT_ON 0u 2384 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2385 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2386 PD<k/16> can be configured on when PD<k%16> is on. */ 2387 #define SRSS_PDCM_PD_PRESENT12_PDCM_PD_CONFIG_ON 0u 2388 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2389 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2390 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2391 on. For configurable sense bits, this indicates the reset value of the 2392 configuration register. */ 2393 #define SRSS_PDCM_PD_PRESENT13_PDCM_PD_DEFAULT_ON 0u 2394 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2395 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2396 PD<k/16> can be configured on when PD<k%16> is on. */ 2397 #define SRSS_PDCM_PD_PRESENT13_PDCM_PD_CONFIG_ON 0u 2398 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2399 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2400 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2401 on. For configurable sense bits, this indicates the reset value of the 2402 configuration register. */ 2403 #define SRSS_PDCM_PD_PRESENT14_PDCM_PD_DEFAULT_ON 0u 2404 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2405 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2406 PD<k/16> can be configured on when PD<k%16> is on. */ 2407 #define SRSS_PDCM_PD_PRESENT14_PDCM_PD_CONFIG_ON 0u 2408 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2409 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2410 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2411 on. For configurable sense bits, this indicates the reset value of the 2412 configuration register. */ 2413 #define SRSS_PDCM_PD_PRESENT15_PDCM_PD_DEFAULT_ON 0u 2414 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2415 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2416 PD<k/16> can be configured on when PD<k%16> is on. */ 2417 #define SRSS_PDCM_PD_PRESENT15_PDCM_PD_CONFIG_ON 0u 2418 /* FLL present */ 2419 #define SRSS_FLL_PRESENT 1u 2420 /* S40S Regulator Set B system is present */ 2421 #define SRSS_S40S_REGSETB_PRESENT 1u 2422 /* S40S Regulator Set B Nwell regulator is present */ 2423 #define SRSS_S40S_REGSETB_NW_PRESENT 0u 2424 /* Number of additional HIBERNATE wakeup sources */ 2425 #define SRSS_NUM_HIB_WAKE 4u 2426 /* CSV_BAK is present. Monitors clk_bak_hv using clk_ilo0_hv. */ 2427 #define SRSS_CSV_BAK_PRESENT 0u 2428 /* HVLDO0 present */ 2429 #define SRSS_S40S_REGSETB_HVLDO0_PRESENT 1u 2430 /* Width of the WDT (Type A) counter. For backward compatibility, the minimum 2431 allowed is 16b. */ 2432 #define SRSS_NUM_WDT_A_BITS 22u 2433 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 2434 #define SRSS_BACKUP_VBCK_PRESENT 0u 2435 /* Alarm1 present in RTC */ 2436 #define SRSS_BACKUP_ALM1_PRESENT 1u 2437 /* Alarm2 present in RTC */ 2438 #define SRSS_BACKUP_ALM2_PRESENT 1u 2439 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 2440 #define SRSS_BACKUP_BMEM_PRESENT 0u 2441 /* Number of Backup registers to include (each is 32b). Only used when 2442 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2443 #define SRSS_BACKUP_NUM_BREG0 4u 2444 /* Number of Backup registers to include (each is 32b). Only used when 2445 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2446 #define SRSS_BACKUP_NUM_BREG1 4u 2447 /* Number of Backup registers to include (each is 32b). Only used when 2448 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2449 #define SRSS_BACKUP_NUM_BREG2 8u 2450 /* Number of Backup registers to include (each is 32b). Only used when 2451 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2452 #define SRSS_BACKUP_NUM_BREG3 0u 2453 /* Low power external crystal oscillator (LPECO) is present. */ 2454 #define SRSS_BACKUP_S40E_LPECO_PRESENT 0u 2455 /* CSV_BAK is present. Monitors clk_bak_hv using clk_ilo0_hv. */ 2456 #define SRSS_BACKUP_CSV_BAK_PRESENT 0u 2457 /* S40S variant. Must be 1 when targeting S40S and 0 otherwise. */ 2458 #define SRSS_CLK_TRIM_PLL400M_S40S_VARIANT 1u 2459 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 2460 mask indicates presence of a CSV. */ 2461 #define SRSS_CSV_HF_MASK_HFCSV 0u 2462 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2463 #define TCPWM_MASTER_WIDTH 8u 2464 /* Number of input triggers per counter only routed to one counter (0..8) */ 2465 #define TCPWM_TR_ONE_CNT_NR 1u 2466 /* Number of input triggers routed to all counters (0..254), 2467 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 2468 #define TCPWM_TR_ALL_CNT_NR 28u 2469 /* Number of TCPWM counter groups (1..4) */ 2470 #define TCPWM_GRP_NR 2u 2471 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 2472 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 32u 2473 /* Second Capture / Compare Unit is present (0, 1) */ 2474 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 0u 2475 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 2476 GRP_CC1_PRESENT = 1 */ 2477 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 2478 /* Stepper Motor Control features are present (0, 1). */ 2479 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 2480 /* Number of counters per TCPWM group (1..256) */ 2481 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 2u 2482 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 2483 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 2484 /* Second Capture / Compare Unit is present (0, 1) */ 2485 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 2486 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 2487 GRP_CC1_PRESENT = 1 */ 2488 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 2489 /* Stepper Motor Control features are present (0, 1). */ 2490 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 0u 2491 /* Number of counters per TCPWM group (1..256) */ 2492 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 7u 2493 /* Number of AHB-Lite "hmaster[]" bits ([4, 8]). */ 2494 #define TDM_MASTER_WIDTH 8u 2495 /* Number of TDM structures ({1, 2, 3, 4}]). */ 2496 #define TDM_NR 1u 2497 /* Number of channels per TDM structure. */ 2498 #define TDM_NR_CH_NR 2u 2499 /* Number of channels per TDM structure. */ 2500 #define TDM_NR_TDM_RX_STRUCT_CH_NR 2u 2501 /* Number of channels per TDM structure. */ 2502 #define TDM_NR_TDM_TX_STRUCT_CH_NR 2u 2503 /* Spare Enable 0=no spare, 1=max, 2=min */ 2504 #define TDM_SPARE_EN 1u 2505 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 2506 8=T28HPL, 9=T28HPC */ 2507 #define TDM_PLATFORM_VARIANT 6u 2508 /* SRAM vendor ({0=Cypress, 1=Synopsys, 2=ARM, 3=BRCM}) */ 2509 #define TDM_RAM_VEND 1u 2510 /* Use mxsramwrap IP */ 2511 #define TDM_MXSRAMWRAP_EN 1u 2512 /* Number of connected clocks at the IP's top level ([1, 4]). */ 2513 #define TDM_CHIP_TOP_CLK_NR 1u 2514 /* Replay functionality for transmitter. This functionality adds significant 2515 silicon area. */ 2516 #define TDM_TDM_TX_STRUCT_REPLAY_PRESENT 0u 2517 2518 /* MMIO Targets Defines */ 2519 /* MMIO0.SRSS */ 2520 #define CY_MMIO_SRSS_GROUP_NR 0u 2521 #define CY_MMIO_SRSS_SLAVE_NR 4u 2522 /* MMIO0.PWRMODE */ 2523 #define CY_MMIO_PWRMODE_GROUP_NR 0u 2524 #define CY_MMIO_PWRMODE_SLAVE_NR 5u 2525 /* MMIO0.BACKUP */ 2526 #define CY_MMIO_BACKUP_GROUP_NR 0u 2527 #define CY_MMIO_BACKUP_SLAVE_NR 6u 2528 /* MMIO0.CRYPTO */ 2529 #define CY_MMIO_CRYPTO_GROUP_NR 0u 2530 #define CY_MMIO_CRYPTO_SLAVE_NR 7u 2531 /* MMIO1.HSIOM */ 2532 #define CY_MMIO_HSIOM_GROUP_NR 1u 2533 #define CY_MMIO_HSIOM_SLAVE_NR 0u 2534 /* MMIO1.GPIO */ 2535 #define CY_MMIO_GPIO_GROUP_NR 1u 2536 #define CY_MMIO_GPIO_SLAVE_NR 1u 2537 /* MMIO1.SMARTIO */ 2538 #define CY_MMIO_SMARTIO_GROUP_NR 1u 2539 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 2540 /* MMIO1.LIN0 */ 2541 #define CY_MMIO_LIN0_GROUP_NR 1u 2542 #define CY_MMIO_LIN0_SLAVE_NR 3u 2543 /* MMIO1.CANFD0 */ 2544 #define CY_MMIO_CANFD0_GROUP_NR 1u 2545 #define CY_MMIO_CANFD0_SLAVE_NR 4u 2546 /* MMIO1.TCPWM0 */ 2547 #define CY_MMIO_TCPWM0_GROUP_NR 1u 2548 #define CY_MMIO_TCPWM0_SLAVE_NR 5u 2549 /* MMIO1.MXS40ADCMIC0 */ 2550 #define CY_MMIO_MXS40ADCMIC0_GROUP_NR 1u 2551 #define CY_MMIO_MXS40ADCMIC0_SLAVE_NR 6u 2552 /* MMIO1.SCB0 */ 2553 #define CY_MMIO_SCB0_GROUP_NR 1u 2554 #define CY_MMIO_SCB0_SLAVE_NR 7u 2555 /* MMIO1.SCB1 */ 2556 #define CY_MMIO_SCB1_GROUP_NR 1u 2557 #define CY_MMIO_SCB1_SLAVE_NR 8u 2558 /* MMIO1.SCB2 */ 2559 #define CY_MMIO_SCB2_GROUP_NR 1u 2560 #define CY_MMIO_SCB2_SLAVE_NR 9u 2561 /* MMIO2.DFT */ 2562 #define CY_MMIO_DFT_GROUP_NR 2u 2563 #define CY_MMIO_DFT_SLAVE_NR 0u 2564 /* MMIO2.EFUSE */ 2565 #define CY_MMIO_EFUSE_GROUP_NR 2u 2566 #define CY_MMIO_EFUSE_SLAVE_NR 1u 2567 /* MMIO2.SMIF0 */ 2568 #define CY_MMIO_SMIF0_GROUP_NR 2u 2569 #define CY_MMIO_SMIF0_SLAVE_NR 2u 2570 /* MMIO2.TDM0 */ 2571 #define CY_MMIO_TDM0_GROUP_NR 2u 2572 #define CY_MMIO_TDM0_SLAVE_NR 3u 2573 /* MMIO2.PDM0 */ 2574 #define CY_MMIO_PDM0_GROUP_NR 2u 2575 #define CY_MMIO_PDM0_SLAVE_NR 4u 2576 /* MMIO2.KEYSCAN */ 2577 #define CY_MMIO_KEYSCAN_GROUP_NR 2u 2578 #define CY_MMIO_KEYSCAN_SLAVE_NR 5u 2579 /* MMIO3.BTSS */ 2580 #define CY_MMIO_BTSS_GROUP_NR 3u 2581 #define CY_MMIO_BTSS_SLAVE_NR 0u 2582 2583 /* Protection regions */ 2584 typedef enum 2585 { 2586 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00004000 */ 2587 PROT_PERI_GR0_GROUP = 1, /* Address 0x40004010, size 0x00000008 */ 2588 PROT_PERI_GR1_GROUP = 2, /* Address 0x40004040, size 0x00000020 */ 2589 PROT_PERI_GR2_GROUP = 3, /* Address 0x40004080, size 0x00000020 */ 2590 PROT_PERI_GR3_GROUP = 4, /* Address 0x400040d0, size 0x00000010 */ 2591 PROT_PERI_GR0_BOOT = 5, /* Address 0x40004020, size 0x00000004 */ 2592 PROT_PERI_GR1_BOOT = 6, /* Address 0x40004060, size 0x00000004 */ 2593 PROT_PERI_GR2_BOOT = 7, /* Address 0x400040a0, size 0x00000004 */ 2594 PROT_PERI_GR3_BOOT = 8, /* Address 0x400040e0, size 0x00000004 */ 2595 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 2596 PROT_PPC_PPC_SECURE = 10, /* Address 0x40020000, size 0x00004000 */ 2597 PROT_PPC_PPC_NONSECURE = 11, /* Address 0x40024000, size 0x00004000 */ 2598 PROT_PERI_PCLK_MAIN = 12, /* Address 0x40040000, size 0x00010000 */ 2599 PROT_CPUSS = 13, /* Address 0x40100000, size 0x00010000 */ 2600 PROT_RAMC0_CM33 = 14, /* Address 0x40110000, size 0x00000010 */ 2601 PROT_RAMC0_BOOT = 15, /* Address 0x40110100, size 0x00000004 */ 2602 PROT_RAMC0_RAM_PWR = 16, /* Address 0x40110200, size 0x00000100 */ 2603 PROT_RAMC0_MPC0_PPC_MPC_MAIN = 17, /* Address 0x40114000, size 0x00000040 */ 2604 PROT_RAMC0_MPC0_PPC_MPC_PC = 18, /* Address 0x40114100, size 0x00000020 */ 2605 PROT_RAMC0_MPC0_PPC_MPC_ROT = 19, /* Address 0x40114200, size 0x00000020 */ 2606 PROT_PROMC_CM33 = 20, /* Address 0x40140000, size 0x00000004 */ 2607 PROT_PROMC_MPC0_PPC_MPC_MAIN = 21, /* Address 0x40141000, size 0x00000040 */ 2608 PROT_PROMC_MPC0_PPC_MPC_PC = 22, /* Address 0x40141100, size 0x00000020 */ 2609 PROT_PROMC_MPC0_PPC_MPC_ROT = 23, /* Address 0x40141200, size 0x00000020 */ 2610 PROT_MXCM33_CM33 = 24, /* Address 0x40160000, size 0x00000100 */ 2611 PROT_MXCM33_CM33_NS = 25, /* Address 0x40161004, size 0x00000004 */ 2612 PROT_MXCM33_BOOT = 26, /* Address 0x40162000, size 0x00000100 */ 2613 PROT_MXCM33_CM33_INT = 27, /* Address 0x40168000, size 0x00000200 */ 2614 PROT_DW0_DW = 28, /* Address 0x40180000, size 0x00000080 */ 2615 PROT_DW0_DW_CRC = 29, /* Address 0x40180100, size 0x00000080 */ 2616 PROT_DW0_CH_STRUCT0_CH = 30, /* Address 0x40188000, size 0x00000040 */ 2617 PROT_DW0_CH_STRUCT1_CH = 31, /* Address 0x40188040, size 0x00000040 */ 2618 PROT_DW0_CH_STRUCT2_CH = 32, /* Address 0x40188080, size 0x00000040 */ 2619 PROT_DW0_CH_STRUCT3_CH = 33, /* Address 0x401880c0, size 0x00000040 */ 2620 PROT_DW0_CH_STRUCT4_CH = 34, /* Address 0x40188100, size 0x00000040 */ 2621 PROT_DW0_CH_STRUCT5_CH = 35, /* Address 0x40188140, size 0x00000040 */ 2622 PROT_DW0_CH_STRUCT6_CH = 36, /* Address 0x40188180, size 0x00000040 */ 2623 PROT_DW0_CH_STRUCT7_CH = 37, /* Address 0x401881c0, size 0x00000040 */ 2624 PROT_DW0_CH_STRUCT8_CH = 38, /* Address 0x40188200, size 0x00000040 */ 2625 PROT_DW0_CH_STRUCT9_CH = 39, /* Address 0x40188240, size 0x00000040 */ 2626 PROT_DW0_CH_STRUCT10_CH = 40, /* Address 0x40188280, size 0x00000040 */ 2627 PROT_DW0_CH_STRUCT11_CH = 41, /* Address 0x401882c0, size 0x00000040 */ 2628 PROT_DW0_CH_STRUCT12_CH = 42, /* Address 0x40188300, size 0x00000040 */ 2629 PROT_DW0_CH_STRUCT13_CH = 43, /* Address 0x40188340, size 0x00000040 */ 2630 PROT_DW0_CH_STRUCT14_CH = 44, /* Address 0x40188380, size 0x00000040 */ 2631 PROT_DW0_CH_STRUCT15_CH = 45, /* Address 0x401883c0, size 0x00000040 */ 2632 PROT_CPUSS_ALL_PC = 46, /* Address 0x401c0000, size 0x00000080 */ 2633 PROT_CPUSS_DDFT = 47, /* Address 0x401c0080, size 0x00000004 */ 2634 PROT_CPUSS_CM33_NS = 48, /* Address 0x401c0120, size 0x00000004 */ 2635 PROT_CPUSS_AHB_ERR_INT = 49, /* Address 0x401c0200, size 0x00000040 */ 2636 PROT_CPUSS_AP = 50, /* Address 0x401c1000, size 0x00000004 */ 2637 PROT_CPUSS_BOOT = 51, /* Address 0x401c2000, size 0x00000200 */ 2638 PROT_MS0_MAIN = 52, /* Address 0x401c4000, size 0x00000004 */ 2639 PROT_MS4_MAIN = 53, /* Address 0x401c4040, size 0x00000004 */ 2640 PROT_MS7_MAIN = 54, /* Address 0x401c4070, size 0x00000004 */ 2641 PROT_MS9_MAIN = 55, /* Address 0x401c4090, size 0x00000004 */ 2642 PROT_MS31_MAIN = 56, /* Address 0x401c41f0, size 0x00000004 */ 2643 PROT_MS_PC0_PRIV = 57, /* Address 0x401c5000, size 0x00000004 */ 2644 PROT_MS_PC9_PRIV = 58, /* Address 0x401c5090, size 0x00000004 */ 2645 PROT_MS_PC31_PRIV = 59, /* Address 0x401c51f0, size 0x00000004 */ 2646 PROT_MS_PC0_PRIV_MIR = 60, /* Address 0x401c5004, size 0x00000004 */ 2647 PROT_MS_PC9_PRIV_MIR = 61, /* Address 0x401c5094, size 0x00000004 */ 2648 PROT_MS_PC31_PRIV_MIR = 62, /* Address 0x401c51f4, size 0x00000004 */ 2649 PROT_MSC_ACG = 63, /* Address 0x401c6000, size 0x00000040 */ 2650 PROT_CPUSS_SL_CTL_GROUP = 64, /* Address 0x401c8000, size 0x00000008 */ 2651 PROT_IPC_STRUCT0_IPC = 65, /* Address 0x401d0000, size 0x00000020 */ 2652 PROT_IPC_STRUCT1_IPC = 66, /* Address 0x401d0020, size 0x00000020 */ 2653 PROT_IPC_STRUCT2_IPC = 67, /* Address 0x401d0040, size 0x00000020 */ 2654 PROT_IPC_STRUCT3_IPC = 68, /* Address 0x401d0060, size 0x00000020 */ 2655 PROT_IPC_INTR_STRUCT0_INTR = 69, /* Address 0x401d1000, size 0x00000010 */ 2656 PROT_IPC_INTR_STRUCT1_INTR = 70, /* Address 0x401d1020, size 0x00000010 */ 2657 PROT_SRSS_GENERAL = 71, /* Address 0x40200000, size 0x00000400 */ 2658 PROT_SRSS_GENERAL2 = 72, /* Address 0x40200400, size 0x00000020 */ 2659 PROT_SRSS_HIB_DATA = 73, /* Address 0x40200800, size 0x00000100 */ 2660 PROT_SRSS_MAIN = 74, /* Address 0x40201000, size 0x00001000 */ 2661 PROT_SRSS_SECURE = 75, /* Address 0x40202000, size 0x00002000 */ 2662 PROT_SRSS_WDT = 76, /* Address 0x4020c000, size 0x00000010 */ 2663 PROT_MAIN = 77, /* Address 0x4020d000, size 0x00000040 */ 2664 PROT_PWRMODE_PWRMODE = 78, /* Address 0x40210000, size 0x00004000 */ 2665 PROT_BACKUP_BACKUP = 79, /* Address 0x40220000, size 0x00000100 */ 2666 PROT_BACKUP_B_BREG0 = 80, /* Address 0x40221000, size 0x00000010 */ 2667 PROT_BACKUP_B_BREG1 = 81, /* Address 0x40221010, size 0x00000010 */ 2668 PROT_BACKUP_B_BREG2 = 82, /* Address 0x40221020, size 0x00000020 */ 2669 PROT_BACKUP_BACKUP_SECURE = 83, /* Address 0x4022ff00, size 0x00000004 */ 2670 PROT_CRYPTO_MAIN = 84, /* Address 0x40230000, size 0x00000100 */ 2671 PROT_CRYPTO_TRNG = 85, /* Address 0x40230100, size 0x00000100 */ 2672 PROT_HSIOM_PRT0_PRT = 86, /* Address 0x40400000, size 0x00000008 */ 2673 PROT_HSIOM_PRT1_PRT = 87, /* Address 0x40400010, size 0x00000008 */ 2674 PROT_HSIOM_PRT2_PRT = 88, /* Address 0x40400020, size 0x00000008 */ 2675 PROT_HSIOM_PRT3_PRT = 89, /* Address 0x40400030, size 0x00000008 */ 2676 PROT_HSIOM_PRT4_PRT = 90, /* Address 0x40400040, size 0x00000008 */ 2677 PROT_HSIOM_PRT5_PRT = 91, /* Address 0x40400050, size 0x00000008 */ 2678 PROT_HSIOM_MON = 92, /* Address 0x40402200, size 0x00000010 */ 2679 PROT_GPIO_PRT0_PRT = 93, /* Address 0x40410000, size 0x00000040 */ 2680 PROT_GPIO_PRT1_PRT = 94, /* Address 0x40410080, size 0x00000040 */ 2681 PROT_GPIO_PRT2_PRT = 95, /* Address 0x40410100, size 0x00000040 */ 2682 PROT_GPIO_PRT3_PRT = 96, /* Address 0x40410180, size 0x00000040 */ 2683 PROT_GPIO_PRT4_PRT = 97, /* Address 0x40410200, size 0x00000040 */ 2684 PROT_GPIO_PRT5_PRT = 98, /* Address 0x40410280, size 0x00000040 */ 2685 PROT_GPIO_PRT0_CFG = 99, /* Address 0x40410040, size 0x00000040 */ 2686 PROT_GPIO_PRT1_CFG = 100, /* Address 0x404100c0, size 0x00000040 */ 2687 PROT_GPIO_PRT2_CFG = 101, /* Address 0x40410140, size 0x00000040 */ 2688 PROT_GPIO_PRT3_CFG = 102, /* Address 0x404101c0, size 0x00000040 */ 2689 PROT_GPIO_PRT4_CFG = 103, /* Address 0x40410240, size 0x00000040 */ 2690 PROT_GPIO_PRT5_CFG = 104, /* Address 0x404102c0, size 0x00000040 */ 2691 PROT_GPIO_GPIO = 105, /* Address 0x40418000, size 0x00000040 */ 2692 PROT_GPIO_TEST = 106, /* Address 0x40419000, size 0x00000008 */ 2693 PROT_SMARTIO_PRT3_PRT = 107, /* Address 0x40420300, size 0x00000100 */ 2694 PROT_LIN0_MAIN = 108, /* Address 0x40430000, size 0x00000008 */ 2695 PROT_LIN0_CH0_CH = 109, /* Address 0x40438000, size 0x00000100 */ 2696 PROT_LIN0_CH1_CH = 110, /* Address 0x40438100, size 0x00000100 */ 2697 PROT_CANFD0_CH0_CH = 111, /* Address 0x40440000, size 0x00000200 */ 2698 PROT_CANFD0_MAIN = 112, /* Address 0x40441000, size 0x00000040 */ 2699 PROT_CANFD0_BUF = 113, /* Address 0x40450000, size 0x00010000 */ 2700 PROT_TCPWM0_GRP0_CNT0_CNT = 114, /* Address 0x404a0000, size 0x00000080 */ 2701 PROT_TCPWM0_GRP0_CNT1_CNT = 115, /* Address 0x404a0080, size 0x00000080 */ 2702 PROT_TCPWM0_GRP1_CNT0_CNT = 116, /* Address 0x404a8000, size 0x00000080 */ 2703 PROT_TCPWM0_GRP1_CNT1_CNT = 117, /* Address 0x404a8080, size 0x00000080 */ 2704 PROT_TCPWM0_GRP1_CNT2_CNT = 118, /* Address 0x404a8100, size 0x00000080 */ 2705 PROT_TCPWM0_GRP1_CNT3_CNT = 119, /* Address 0x404a8180, size 0x00000080 */ 2706 PROT_TCPWM0_GRP1_CNT4_CNT = 120, /* Address 0x404a8200, size 0x00000080 */ 2707 PROT_TCPWM0_GRP1_CNT5_CNT = 121, /* Address 0x404a8280, size 0x00000080 */ 2708 PROT_TCPWM0_GRP1_CNT6_CNT = 122, /* Address 0x404a8300, size 0x00000080 */ 2709 PROT_MXS40ADCMIC0_MAIN = 123, /* Address 0x40520000, size 0x00000400 */ 2710 PROT_SCB0 = 124, /* Address 0x40590000, size 0x00010000 */ 2711 PROT_SCB1 = 125, /* Address 0x405a0000, size 0x00010000 */ 2712 PROT_SCB2 = 126, /* Address 0x405b0000, size 0x00010000 */ 2713 PROT_DFT = 127, /* Address 0x40800000, size 0x00001000 */ 2714 PROT_EFUSE_CTL1 = 128, /* Address 0x40810000, size 0x00000004 */ 2715 PROT_EFUSE_CTL2 = 129, /* Address 0x40810100, size 0x00000080 */ 2716 PROT_EFUSE_CTL3 = 130, /* Address 0x40810180, size 0x00000004 */ 2717 PROT_EFUSE_DATA_BOOT1 = 131, /* Address 0x40810800, size 0x00000020 */ 2718 PROT_EFUSE_DATA_BOOT2 = 132, /* Address 0x40810820, size 0x00000010 */ 2719 PROT_EFUSE_DATA_BOOT3 = 133, /* Address 0x40810830, size 0x00000004 */ 2720 PROT_EFUSE_DATA_BLESS1 = 134, /* Address 0x40810834, size 0x00000004 */ 2721 PROT_EFUSE_DATA_BLESS2 = 135, /* Address 0x40810838, size 0x00000004 */ 2722 PROT_EFUSE_DATA_BLESS3 = 136, /* Address 0x4081083c, size 0x00000004 */ 2723 PROT_EFUSE_DATA_APP1 = 137, /* Address 0x40810840, size 0x00000010 */ 2724 PROT_EFUSE_DATA_APP2 = 138, /* Address 0x40810850, size 0x00000010 */ 2725 PROT_EFUSE_DATA_APP3 = 139, /* Address 0x40810860, size 0x00000010 */ 2726 PROT_EFUSE_DATA_ALL = 140, /* Address 0x40810870, size 0x00000010 */ 2727 PROT_SMIF0_MAIN = 141, /* Address 0x40890000, size 0x00001000 */ 2728 PROT_SMIF0_MPC0_PPC_MPC_MAIN = 142, /* Address 0x40891000, size 0x00000040 */ 2729 PROT_SMIF0_MPC0_PPC_MPC_PC = 143, /* Address 0x40891100, size 0x00000020 */ 2730 PROT_SMIF0_MPC0_PPC_MPC_ROT = 144, /* Address 0x40891200, size 0x00000020 */ 2731 PROT_TDM0_TDM_STRUCT0_TDM_TX_STRUCT_TX = 145, /* Address 0x408c8000, size 0x00000100 */ 2732 PROT_TDM0_TDM_STRUCT0_TDM_RX_STRUCT_RX = 146, /* Address 0x408c8100, size 0x00000100 */ 2733 PROT_PDM0_MAIN = 147, /* Address 0x408d0000, size 0x00000200 */ 2734 PROT_PDM0_CH0_RX = 148, /* Address 0x408d8000, size 0x00000100 */ 2735 PROT_PDM0_CH1_RX = 149, /* Address 0x408d8100, size 0x00000100 */ 2736 PROT_MXKEYSCAN_MAIN = 150, /* Address 0x40920000, size 0x00000040 */ 2737 PROT_BTSS_ROM = 151, /* Address 0x42000000, size 0x00400000 */ 2738 PROT_BTSS_SYSRAM = 152, /* Address 0x42400000, size 0x00004000 */ 2739 PROT_BTSS_DATA_RAM_IPC = 153, /* Address 0x42600000, size 0x00100000 */ 2740 PROT_BTSS_DRIVER = 154, /* Address 0x42a00000, size 0x00100000 */ 2741 PROT_BTSS_FWONLY = 155, /* Address 0x42b00000, size 0x00100000 */ 2742 PROT_BTSS_SECURE = 156 /* Address 0x42f00000, size 0x00100000 */ 2743 } cy_en_prot_region_t; 2744 2745 #endif /* _CYW20829B0_CONFIG_H_ */ 2746 2747 2748 /* [] END OF FILE */ 2749
