1 /*******************************************************************************
2 * File Name: cyhal_clock_impl.h
3 *
4 * Description:
5 * CAT1 specific implementation for clocks API.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26
27 #pragma once
28
29 #include "cyhal_hw_resources.h"
30
31 #if (CYHAL_DRIVER_AVAILABLE_CLOCK)
32
33 #if defined(__cplusplus)
34 extern "C"
35 {
36 #endif
37
38 #if !defined(SRSS_NUM_PLL)
39
40 #if defined(COMPONENT_CAT1D)
41 #define SRSS_NUM_PLL SRSS_NUM_TOTAL_DPLL
42 #elif defined(COMPONENT_CAT1B)
43 #define SRSS_NUM_PLL (SRSS_NUM_PLL200M + SRSS_NUM_PLL400M)
44 #endif
45
46 #endif /* !defined(SRSS_NUM_PLL) */
47
48 #if defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)
49 #if !defined(SRSS_NUM_PLL400M)
50 #define SRSS_NUM_PLL400M (0)
51 #endif
52 #define _CYHAL_SRSS_NUM_PLL (SRSS_NUM_PLL + SRSS_NUM_PLL400M)
53 #else
54 #define _CYHAL_SRSS_NUM_PLL SRSS_NUM_PLL
55 #endif /* defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0) */
56
57 #if defined(CY_SRSS_ILO_PRESENT)
58 #define _CYHAL_SRSS_ILO_PRESENT (CY_SRSS_ILO_PRESENT)
59 #elif ((CY_SRSS_ILO_COUNT) > 0) || defined(COMPONENT_CAT1A)
60 #define _CYHAL_SRSS_ILO_PRESENT (1)
61 #else
62 #define _CYHAL_SRSS_ILO_PRESENT (0)
63 #endif /* (CY_SRSS_ILO_PRESENT) */
64
65
66 /**
67 * \addtogroup group_hal_impl_clock Clocks
68 * \ingroup group_hal_impl
69 * \{
70 * Implementation specific interface for using the Clock driver. These items, while usable
71 * within the HAL, are <b>not</b> necessarily portable between devices. The diagrams below
72 * show how the clocks relate to each other. This is a superset of what is available. See
73 * the device specific Data Sheet for the exact set of clocks that are available on a
74 * specific device.
75 * \section section_clock_snippets_impl Code snippets
76 * \note Error handling code has been intentionally left out of snippets to highlight API usage.
77 *
78 * \subsection subsection_clock_snippet_5_impl Snippet: System initialization
79 * The following snippet shows the clock driver can be used to initialize all clocks in the system.
80 * \note This example is device specific.
81 * \snippet hal_clock.c snippet_cyhal_clock_system_init_p6
82 * \addtogroup group_hal_impl_clock_psoc6_01 PSoC™ 6S1 Clocks
83 * \{
84 * <b>PSoC™ 6S1 Clock Tree:</b>
85 * \image html psoc6able2_clock_tree.png
86 * \}
87 * \addtogroup group_hal_impl_clock_psoc6_02 PSoC™ 6S2 Clocks
88 * \{
89 * <b>PSoC™ 6S2 Clock Tree:</b>
90 * \image html psoc6a2m_clock_tree.png
91 * \}
92 * \addtogroup group_hal_impl_clock_psoc6_03 PSoC™ 6S3 Clocks
93 * \{
94 * <b>PSoC™ 6S3 Clock Tree:</b>
95 * \image html psoc6a512k_clock_tree.png
96 * \}
97 * \addtogroup group_hal_impl_clock_psoc6_04 PSoC™ 6S4 Clocks
98 * \{
99 * <b>PSoC™ 6S4 Clock Tree:</b>
100 * \image html psoc6a256k_clock_tree.png
101 * \}
102 * \addtogroup group_hal_impl_clock_xmc7100 XMC7100/T2G-B-H-4M Clocks
103 * \{
104 * <b>XMC7100/T2G-B-H-4M Clock Tree:</b>
105 * \image html xmc7100_clock_tree.png
106 * \}
107 * \addtogroup group_hal_impl_clock_xmc7200 XMC7200/T2G-B-H-8M Clocks
108 * \{
109 * <b>XMC7200/T2G-B-H-8M Clock Tree:</b>
110 * \image html xmc7200_clock_tree.png
111 * \}
112 */
113
114 /** \cond INTERNAL */
115 #define SRSS_MFO_PRESENT (SRSS_VER1P3)
116 /** \endcond */
117
118 /** Internal Main Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
119 extern const cyhal_clock_t CYHAL_CLOCK_IMO;
120 /** Internal Main Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
121 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_IMO;
122
123 /** External Clock: This is an off-chip clock (not an oscillator). This clock is stopped in the deep sleep and hibernate power modes. */
124 extern const cyhal_clock_t CYHAL_CLOCK_EXT;
125 /** External Clock: This is an off-chip clock (not an oscillator). This clock is stopped in the deep sleep and hibernate power modes. */
126 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_EXT;
127
128 #if defined(COMPONENT_CAT1C)
129 /*!< CLK MEM */
130 extern const cyhal_clock_t CYHAL_CLOCK_MEM;
131 /*!< CLK MEM */
132 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MEM;
133 #endif
134
135 #if (_CYHAL_SRSS_ILO_PRESENT)
136 /** Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. */
137 extern const cyhal_clock_t CYHAL_CLOCK_ILO[_CYHAL_SRSS_NUM_ILO];
138 /** Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. */
139 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ILO[_CYHAL_SRSS_NUM_ILO];
140 #endif /* (_CYHAL_SRSS_ILO_PRESENT) */
141
142 #if SRSS_ECO_PRESENT
143 /** External Crystal Oscillator: This is an off-chip clock source that is used when specific frequencies and/or very high accuracy is required. This clock is stopped in the deep sleep and hibernate power modes. */
144 extern const cyhal_clock_t CYHAL_CLOCK_ECO;
145 /** External Crystal Oscillator: This is an off-chip clock source that is used when specific frequencies and/or very high accuracy is required. This clock is stopped in the deep sleep and hibernate power modes. */
146 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ECO;
147 /** External Crystal Oscillator Prescaler. */
148 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ECO_PRESCALER;
149 #endif
150 #if SRSS_ALTHF_PRESENT
151 /** Alternate High Frequency Clock: A high speed clock input provided by a subsystem outside the clocking system. This clock is stopped in the deep sleep and hibernate power modes. */
152 extern const cyhal_clock_t CYHAL_CLOCK_ALTHF;
153 /** Alternate High Frequency Clock: A high speed clock input provided by a subsystem outside the clocking system. This clock is stopped in the deep sleep and hibernate power modes. */
154 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALTHF;
155 #endif
156 #if SRSS_ALTLF_PRESENT
157 /** Alternate Low Frequency Clock: A low speed clock input provided by a subsystem outside the clocking system. This clock is the hibernate power mode. */
158 extern const cyhal_clock_t CYHAL_CLOCK_ALTLF;
159 /** Alternate Low Frequency Clock: A low speed clock input provided by a subsystem outside the clocking system. This clock is the hibernate power mode. */
160 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALTLF;
161 #endif
162 #if SRSS_PILO_PRESENT
163 /** Precision ILO: An additional source that can provide a much more accurate 32.768kHz clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. This clock is stopped in the hibernate power mode. */
164 extern const cyhal_clock_t CYHAL_CLOCK_PILO;
165 /** Precision ILO: An additional source that can provide a much more accurate 32.768kHz clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. This clock is stopped in the hibernate power mode. */
166 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PILO;
167 #endif
168 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
169 /** Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
170 extern const cyhal_clock_t CYHAL_CLOCK_WCO;
171 /** Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
172 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_WCO;
173 #endif
174 #if SRSS_S40E_LPECO_PRESENT
175 /** Low Power External Crystal Oscillator: This source is driven from an off-chip external crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
176 extern const cyhal_clock_t CYHAL_CLOCK_LPECO_PRESCALER;
177 /** Low Power External Crystal Oscillator: This source is driven from an off-chip external crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
178 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_LPECO_PRESCALER;
179 #endif
180 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
181 /** Medium Frequency Oscillator: This source produced by dividing the IMO by 4. The MFO works down to DeepSleep, and the IMO does not turn off if this clock requires it. */
182 extern const cyhal_clock_t CYHAL_CLOCK_MFO;
183 #endif
184 /** Medium Frequency Oscillator: This source produced by dividing the IMO by 4. The MFO works down to DeepSleep, and the IMO does not turn off if this clock requires it. */
185 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MFO;
186 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT) || defined(CY_IP_MXS22SRSS)
187 /** Medium Frequency Clock: This clock is a medium frequency, between the Low Frequency Clock (LF) and High Frequency Clock (HF). */
188 extern const cyhal_clock_t CYHAL_CLOCK_MF;
189 /** Medium Frequency Clock: This clock is a medium frequency, between the Low Frequency Clock (LF) and High Frequency Clock (HF). */
190 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MF;
191 #endif
192
193 /** Low Frequency Clock: This clock is the source for the multi-counter watchdog timers (MCWDT), and can also be a source for the RTC. */
194 extern const cyhal_clock_t CYHAL_CLOCK_LF;
195 /** Low Frequency Clock: This clock is the source for the multi-counter watchdog timers (MCWDT), and can also be a source for the RTC. */
196 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_LF;
197
198 /* PUMP clock is only available on CAT1A (SRSS_VERSION 1) and CAT1B devices */
199 #if (defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined(COMPONENT_CAT1B)
200 #define PUMP_PRESENT (1UL)
201 /** Analog Pump Clock: This clock ensures precision analog performance in low voltage applications. */
202 extern const cyhal_clock_t CYHAL_CLOCK_PUMP;
203 /** Analog Pump Clock: This clock ensures precision analog performance in low voltage applications. */
204 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PUMP;
205 #endif /* (defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined(COMPONENT_CAT1B) */
206
207 /** Backup Clock: This clock is available to the backup domain. Typically useful if an external WCO is not available. */
208 extern const cyhal_clock_t CYHAL_CLOCK_BAK;
209 /** Backup Clock: This clock is available to the backup domain. Typically useful if an external WCO is not available. */
210 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_BAK;
211
212 /** AltSysTickClk: Provides an optional external source for the CM4/CM0+ SysTick timers. */
213 extern const cyhal_clock_t CYHAL_CLOCK_ALT_SYS_TICK;
214 /** AltSysTickClk: Provides an optional external source for the CM4/CM0+ SysTick timers. */
215 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALT_SYS_TICK;
216
217 #if (SRSS_NUM_CLKPATH > 0)
218 /** Path mux selection: A clock source for high frequency clocks. */
219 extern const cyhal_clock_t CYHAL_CLOCK_PATHMUX[SRSS_NUM_CLKPATH];
220 /** Path mux selection: A clock source for high frequency clocks. */
221 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PATHMUX[SRSS_NUM_CLKPATH];
222 #endif
223
224 #if defined(COMPONENT_CAT1A)
225 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
226 extern const cyhal_clock_t CYHAL_CLOCK_FAST;
227 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
228 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FAST;
229
230 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
231 extern const cyhal_clock_t CYHAL_CLOCK_PERI;
232 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
233 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PERI;
234 #endif
235
236 #if defined(COMPONENT_CAT1C)
237 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
238 extern const cyhal_clock_t CYHAL_CLOCK_FAST[_CYHAL_SRSS_NUM_FAST];
239 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
240 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FAST[_CYHAL_SRSS_NUM_FAST];
241
242 #endif
243
244 #if defined(COMPONENT_CAT1A) && !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
245 /** Timer Clock: This clock is intended as a source for high-frequency timers, such as the Energy Profiler and CPU SysTick clock. This clock is stopped in the hibernate power mode. */
246 extern const cyhal_clock_t CYHAL_CLOCK_TIMER;
247 /** Timer Clock: This clock is intended as a source for high-frequency timers, such as the Energy Profiler and CPU SysTick clock. This clock is stopped in the hibernate power mode. */
248 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_TIMER;
249 #endif
250
251 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
252 /** Slow Clock: This clock is used for the CM0+ CPU, Datawire and CRYPTO components and the associated CPUSS slow infrastructure. */
253 extern const cyhal_clock_t CYHAL_CLOCK_SLOW;
254 /** Slow Clock: This clock is used for the CM0+ CPU, Datawire and CRYPTO components and the associated CPUSS slow infrastructure. */
255 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_SLOW;
256 #endif
257 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
258 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
259 /** Internal High-Speed Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
260 extern const cyhal_clock_t CYHAL_CLOCK_IHO;
261 /** Internal High-Speed Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
262 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_IHO;
263 #endif
264
265 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
266 extern const cyhal_clock_t CYHAL_CLOCK_PERI[CY_PERI_GROUP_NR];
267 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
268 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PERI[CY_PERI_GROUP_NR];
269 #endif
270
271 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
272 /** Frequency-Locked Loop: This is a high-frequency clock suitable for most on-chip purposes. It is similar to a PLL, but starts up much faster and consumes less current. This clock is stopped in the deep sleep and hibernate power modes. */
273 extern const cyhal_clock_t CYHAL_CLOCK_FLL;
274 /** Frequency-Locked Loop: This is a high-frequency clock suitable for most on-chip purposes. It is similar to a PLL, but starts up much faster and consumes less current. This clock is stopped in the deep sleep and hibernate power modes. */
275 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FLL;
276 #endif
277
278 #if (_CYHAL_SRSS_NUM_PLL > 0) && defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)
279 /** Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
280 extern const cyhal_clock_t CYHAL_CLOCK_PLL[_CYHAL_SRSS_NUM_PLL];
281 /** Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
282 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[_CYHAL_SRSS_NUM_PLL];
283 #endif
284 #if (SRSS_NUM_PLL > 0) && defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)
285 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
286 extern const cyhal_clock_t CYHAL_CLOCK_PLL200[SRSS_NUM_PLL200M];
287 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
288 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL200M[SRSS_NUM_PLL200M];
289 #endif
290 #if defined(SRSS_NUM_PLL400M) && (SRSS_NUM_PLL400M > 0) && defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)
291 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
292 extern const cyhal_clock_t CYHAL_CLOCK_PLL400[SRSS_NUM_PLL400M];
293 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
294 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL400M[SRSS_NUM_PLL400M];
295 #endif
296
297 #if defined(COMPONENT_CAT1B) && (defined(SRSS_NUM_PLL200M) && (SRSS_NUM_PLL200M > 0))
298 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
299 extern const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL200M];
300 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
301 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[SRSS_NUM_PLL200M];
302 #endif
303 #if defined(COMPONENT_CAT1B) && (defined(SRSS_NUM_PLL400M) && (SRSS_NUM_PLL400M > 0))
304 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
305 extern const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL400M];
306 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
307 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[SRSS_NUM_PLL400M];
308 #endif
309
310 #if (SRSS_NUM_DPLL250M > 0) && defined(COMPONENT_CAT1D)
311 /** 250MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
312 extern const cyhal_clock_t CYHAL_CLOCK_DPLL250[SRSS_NUM_DPLL250M];
313 /** 250MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
314 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_DPLL250M[SRSS_NUM_DPLL250M];
315 #endif
316 #if (SRSS_NUM_DPLL500M > 0) && defined(COMPONENT_CAT1D)
317 /** 500MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
318 extern const cyhal_clock_t CYHAL_CLOCK_DPLL500[SRSS_NUM_DPLL500M];
319 /** 500MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
320 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_DPLL500M[SRSS_NUM_DPLL500M];
321 #endif
322
323 /** High Frequency Clock: A high-frequency clock output driving specific peripherals. */
324 extern const cyhal_clock_t CYHAL_CLOCK_HF[SRSS_NUM_HFROOT];
325 /** High Frequency Clock: A high-frequency clock output driving specific peripherals. */
326 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_HF[SRSS_NUM_HFROOT];
327
328 /** \} group_hal_impl_clock */
329
330 cy_rslt_t _cyhal_clock_allocate_channel(cyhal_clock_t *clock, cyhal_clock_block_t block, const void* funcs);
331
332 const void* _cyhal_clock_get_funcs_pathmux(void);
333 #if (_CYHAL_SRSS_NUM_PLL > 0)
334 const void* _cyhal_clock_get_funcs_pll(void);
335 #endif
336 const void* _cyhal_clock_get_funcs_hf(void);
337 const void* _cyhal_clock_get_funcs_peripheral(void);
338
339
_cyhal_clock_get_funcs(cyhal_clock_block_t block)340 static inline const void* _cyhal_clock_get_funcs(cyhal_clock_block_t block)
341 {
342 switch (block)
343 {
344 case CYHAL_CLOCK_BLOCK_PATHMUX:
345 return _cyhal_clock_get_funcs_pathmux();
346 #if (_CYHAL_SRSS_NUM_PLL > 0)
347 #if defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)
348 #if defined(SRSS_NUM_PLL200M) && (SRSS_NUM_PLL200M > 0)
349 case CYHAL_CLOCK_BLOCK_PLL200:
350 #endif
351 #if defined(SRSS_NUM_PLL400M) && (SRSS_NUM_PLL400M > 0)
352 case CYHAL_CLOCK_BLOCK_PLL400:
353 #endif
354 #elif defined(COMPONENT_CAT1D)
355 case CYHAL_CLOCK_BLOCK_DPLL250:
356 case CYHAL_CLOCK_BLOCK_DPLL500:
357 #else
358 case CYHAL_CLOCK_BLOCK_PLL:
359 #endif
360 return _cyhal_clock_get_funcs_pll();
361 #endif
362 case CYHAL_CLOCK_BLOCK_HF:
363 return _cyhal_clock_get_funcs_hf();
364 default:
365 return (block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
366 ? _cyhal_clock_get_funcs_peripheral()
367 : NULL;
368 }
369 }
_cyhal_clock_allocate(cyhal_clock_t * clock,cyhal_clock_block_t block)370 static inline cy_rslt_t _cyhal_clock_allocate(cyhal_clock_t *clock, cyhal_clock_block_t block)
371 {
372 CY_ASSERT(NULL != clock);
373
374 const void* funcs = _cyhal_clock_get_funcs(block);
375 return (NULL == funcs)
376 ? CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED
377 : _cyhal_clock_allocate_channel(clock, block, funcs);
378 }
_cyhal_clock_allocate_peri(cyhal_clock_t * clock,cyhal_clock_block_t block)379 static inline cy_rslt_t _cyhal_clock_allocate_peri(cyhal_clock_t *clock, cyhal_clock_block_t block)
380 {
381 CY_ASSERT(NULL != clock);
382
383 const void* funcs = _cyhal_clock_get_funcs_peripheral();
384 return _cyhal_clock_allocate_channel(clock, block, funcs);
385 }
386
387 #define cyhal_clock_allocate(clock, block) _cyhal_clock_allocate(clock, block)
388
389 #if defined(__cplusplus)
390 }
391 #endif
392
393 #endif // CYHAL_DRIVER_AVAILABLE_CLOCK
394
