1 /***************************************************************************//** 2 * \file fx3g2_config.h 3 * 4 * \brief 5 * FX3G2 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _FX3G2_CONFIG_H_ 28 #define _FX3G2_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ 34 PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ 35 PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ 36 PCLK_SCB3_CLOCK = 0x0003u, /* scb[3].clock */ 37 PCLK_SCB4_CLOCK = 0x0004u, /* scb[4].clock */ 38 PCLK_SCB5_CLOCK = 0x0005u, /* scb[5].clock */ 39 PCLK_SCB6_CLOCK = 0x0006u, /* scb[6].clock */ 40 PCLK_TCPWM0_CLOCKS0 = 0x0007u, /* tcpwm[0].clocks[0] */ 41 PCLK_TCPWM0_CLOCKS1 = 0x0008u, /* tcpwm[0].clocks[1] */ 42 PCLK_TCPWM0_CLOCKS2 = 0x0009u, /* tcpwm[0].clocks[2] */ 43 PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ 44 PCLK_TCPWM0_CLOCKS4 = 0x000Bu, /* tcpwm[0].clocks[4] */ 45 PCLK_TCPWM0_CLOCKS5 = 0x000Cu, /* tcpwm[0].clocks[5] */ 46 PCLK_TCPWM0_CLOCKS6 = 0x000Du, /* tcpwm[0].clocks[6] */ 47 PCLK_TCPWM0_CLOCKS7 = 0x000Eu, /* tcpwm[0].clocks[7] */ 48 PCLK_CPUSS_CLOCK_TRACE_IN = 0x000Fu, /* cpuss.clock_trace_in */ 49 PCLK_USB_CLOCK_DEV_BRS = 0x0010u, /* usb.clock_dev_brs */ 50 PCLK_CANFD0_CLOCK_CAN0 = 0x0011u, /* canfd[0].clock_can[0] */ 51 PCLK_LVDS2USB32SS_CLOCK_SAR = 0x0012u /* lvds2usb32ss.clock_sar */ 52 } en_clk_dst_t; 53 54 /* Trigger Group */ 55 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 56 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 57 */ 58 /* Trigger Group Inputs */ 59 /* Trigger Input Group 0 - PDMA0 Request Assignments */ 60 typedef enum 61 { 62 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 63 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 64 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 65 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 66 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 67 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 68 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 69 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 70 TRIG_IN_MUX_0_PDMA0_TR_OUT8 = 0x00000009u, /* cpuss.dw0_tr_out[8] */ 71 TRIG_IN_MUX_0_PDMA0_TR_OUT9 = 0x0000000Au, /* cpuss.dw0_tr_out[9] */ 72 TRIG_IN_MUX_0_PDMA0_TR_OUT10 = 0x0000000Bu, /* cpuss.dw0_tr_out[10] */ 73 TRIG_IN_MUX_0_PDMA0_TR_OUT11 = 0x0000000Cu, /* cpuss.dw0_tr_out[11] */ 74 TRIG_IN_MUX_0_PDMA0_TR_OUT12 = 0x0000000Du, /* cpuss.dw0_tr_out[12] */ 75 TRIG_IN_MUX_0_PDMA0_TR_OUT13 = 0x0000000Eu, /* cpuss.dw0_tr_out[13] */ 76 TRIG_IN_MUX_0_PDMA0_TR_OUT14 = 0x0000000Fu, /* cpuss.dw0_tr_out[14] */ 77 TRIG_IN_MUX_0_PDMA0_TR_OUT15 = 0x00000010u, /* cpuss.dw0_tr_out[15] */ 78 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000011u, /* cpuss.dw1_tr_out[0] */ 79 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x00000012u, /* cpuss.dw1_tr_out[1] */ 80 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x00000013u, /* cpuss.dw1_tr_out[2] */ 81 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x00000014u, /* cpuss.dw1_tr_out[3] */ 82 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x00000015u, /* cpuss.dw1_tr_out[4] */ 83 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x00000016u, /* cpuss.dw1_tr_out[5] */ 84 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x00000017u, /* cpuss.dw1_tr_out[6] */ 85 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000018u, /* cpuss.dw1_tr_out[7] */ 86 TRIG_IN_MUX_0_PDMA1_TR_OUT8 = 0x00000019u, /* cpuss.dw1_tr_out[8] */ 87 TRIG_IN_MUX_0_PDMA1_TR_OUT9 = 0x0000001Au, /* cpuss.dw1_tr_out[9] */ 88 TRIG_IN_MUX_0_PDMA1_TR_OUT10 = 0x0000001Bu, /* cpuss.dw1_tr_out[10] */ 89 TRIG_IN_MUX_0_PDMA1_TR_OUT11 = 0x0000001Cu, /* cpuss.dw1_tr_out[11] */ 90 TRIG_IN_MUX_0_PDMA1_TR_OUT12 = 0x0000001Du, /* cpuss.dw1_tr_out[12] */ 91 TRIG_IN_MUX_0_PDMA1_TR_OUT13 = 0x0000001Eu, /* cpuss.dw1_tr_out[13] */ 92 TRIG_IN_MUX_0_PDMA1_TR_OUT14 = 0x0000001Fu, /* cpuss.dw1_tr_out[14] */ 93 TRIG_IN_MUX_0_PDMA1_TR_OUT15 = 0x00000020u, /* cpuss.dw1_tr_out[15] */ 94 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000021u, /* cpuss.dmac_tr_out[0] */ 95 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000022u, /* cpuss.dmac_tr_out[1] */ 96 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x00000023u, /* cpuss.dmac_tr_out[2] */ 97 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x00000024u, /* cpuss.dmac_tr_out[3] */ 98 TRIG_IN_MUX_0_MDMA_TR_OUT4 = 0x00000025u, /* cpuss.dmac_tr_out[4] */ 99 TRIG_IN_MUX_0_MDMA_TR_OUT5 = 0x00000026u, /* cpuss.dmac_tr_out[5] */ 100 TRIG_IN_MUX_0_USB_DMA_REQ0 = 0x00000027u, /* usb.dma_req[0] */ 101 TRIG_IN_MUX_0_USB_DMA_REQ1 = 0x00000028u, /* usb.dma_req[1] */ 102 TRIG_IN_MUX_0_USB_DMA_REQ2 = 0x00000029u, /* usb.dma_req[2] */ 103 TRIG_IN_MUX_0_USB_DMA_REQ3 = 0x0000002Au, /* usb.dma_req[3] */ 104 TRIG_IN_MUX_0_USB_DMA_REQ4 = 0x0000002Bu, /* usb.dma_req[4] */ 105 TRIG_IN_MUX_0_USB_DMA_REQ5 = 0x0000002Cu, /* usb.dma_req[5] */ 106 TRIG_IN_MUX_0_USB_DMA_REQ6 = 0x0000002Du, /* usb.dma_req[6] */ 107 TRIG_IN_MUX_0_USB_DMA_REQ7 = 0x0000002Eu, /* usb.dma_req[7] */ 108 TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x0000002Fu, /* peri.tr_io_input[0] */ 109 TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000030u, /* peri.tr_io_input[1] */ 110 TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000031u, /* peri.tr_io_input[2] */ 111 TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000032u, /* peri.tr_io_input[3] */ 112 TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000033u, /* peri.tr_io_input[4] */ 113 TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x00000034u, /* peri.tr_io_input[5] */ 114 TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x00000035u, /* peri.tr_io_input[6] */ 115 TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x00000036u, /* peri.tr_io_input[7] */ 116 TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x00000037u, /* peri.tr_io_input[8] */ 117 TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x00000038u, /* peri.tr_io_input[9] */ 118 TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x00000039u, /* peri.tr_io_input[10] */ 119 TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x0000003Au, /* peri.tr_io_input[11] */ 120 TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x0000003Bu, /* peri.tr_io_input[12] */ 121 TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x0000003Cu, /* peri.tr_io_input[13] */ 122 TRIG_IN_MUX_0_HSIOM_TR_OUT14 = 0x0000003Du, /* peri.tr_io_input[14] */ 123 TRIG_IN_MUX_0_HSIOM_TR_OUT15 = 0x0000003Eu, /* peri.tr_io_input[15] */ 124 TRIG_IN_MUX_0_HSIOM_TR_OUT16 = 0x0000003Fu, /* peri.tr_io_input[16] */ 125 TRIG_IN_MUX_0_HSIOM_TR_OUT17 = 0x00000040u, /* peri.tr_io_input[17] */ 126 TRIG_IN_MUX_0_HSIOM_TR_OUT18 = 0x00000041u, /* peri.tr_io_input[18] */ 127 TRIG_IN_MUX_0_HSIOM_TR_OUT19 = 0x00000042u, /* peri.tr_io_input[19] */ 128 TRIG_IN_MUX_0_HSIOM_TR_OUT20 = 0x00000043u, /* peri.tr_io_input[20] */ 129 TRIG_IN_MUX_0_HSIOM_TR_OUT21 = 0x00000044u, /* peri.tr_io_input[21] */ 130 TRIG_IN_MUX_0_HSIOM_TR_OUT22 = 0x00000045u, /* peri.tr_io_input[22] */ 131 TRIG_IN_MUX_0_HSIOM_TR_OUT23 = 0x00000046u, /* peri.tr_io_input[23] */ 132 TRIG_IN_MUX_0_TCPWM_TR_OVERFLOW0 = 0x00000049u, /* tcpwm[0].tr_overflow[0] */ 133 TRIG_IN_MUX_0_TCPWM_TR_COMPARE_MATCH0 = 0x0000004Au, /* tcpwm[0].tr_compare_match[0] */ 134 TRIG_IN_MUX_0_TCPWM_TR_UNDERFLOW0 = 0x0000004Bu, /* tcpwm[0].tr_underflow[0] */ 135 TRIG_IN_MUX_0_TCPWM_TR_OVERFLOW1 = 0x0000004Cu, /* tcpwm[0].tr_overflow[1] */ 136 TRIG_IN_MUX_0_TCPWM_TR_COMPARE_MATCH1 = 0x0000004Du, /* tcpwm[0].tr_compare_match[1] */ 137 TRIG_IN_MUX_0_TCPWM_TR_UNDERFLOW1 = 0x0000004Eu, /* tcpwm[0].tr_underflow[1] */ 138 TRIG_IN_MUX_0_TCPWM_TR_OVERFLOW2 = 0x0000004Fu, /* tcpwm[0].tr_overflow[2] */ 139 TRIG_IN_MUX_0_TCPWM_TR_COMPARE_MATCH2 = 0x00000050u, /* tcpwm[0].tr_compare_match[2] */ 140 TRIG_IN_MUX_0_TCPWM_TR_UNDERFLOW2 = 0x00000051u, /* tcpwm[0].tr_underflow[2] */ 141 TRIG_IN_MUX_0_TCPWM_TR_OVERFLOW3 = 0x00000052u, /* tcpwm[0].tr_overflow[3] */ 142 TRIG_IN_MUX_0_TCPWM_TR_COMPARE_MATCH3 = 0x00000053u, /* tcpwm[0].tr_compare_match[3] */ 143 TRIG_IN_MUX_0_TCPWM_TR_UNDERFLOW3 = 0x00000054u, /* tcpwm[0].tr_underflow[3] */ 144 TRIG_IN_MUX_0_USBHSDEV_TR_OUT0 = 0x00000055u, /* usbhsdev.u2d_tr_out[0] */ 145 TRIG_IN_MUX_0_USBHSDEV_TR_OUT1 = 0x00000056u, /* usbhsdev.u2d_tr_out[1] */ 146 TRIG_IN_MUX_0_USBHSDEV_TR_OUT2 = 0x00000057u, /* usbhsdev.u2d_tr_out[2] */ 147 TRIG_IN_MUX_0_USBHSDEV_TR_OUT3 = 0x00000058u, /* usbhsdev.u2d_tr_out[3] */ 148 TRIG_IN_MUX_0_USBHSDEV_TR_OUT4 = 0x00000059u, /* usbhsdev.u2d_tr_out[4] */ 149 TRIG_IN_MUX_0_USBHSDEV_TR_OUT5 = 0x0000005Au, /* usbhsdev.u2d_tr_out[5] */ 150 TRIG_IN_MUX_0_USBHSDEV_TR_OUT6 = 0x0000005Bu, /* usbhsdev.u2d_tr_out[6] */ 151 TRIG_IN_MUX_0_USBHSDEV_TR_OUT7 = 0x0000005Cu, /* usbhsdev.u2d_tr_out[7] */ 152 TRIG_IN_MUX_0_USBHSDEV_TR_OUT8 = 0x0000005Du, /* usbhsdev.u2d_tr_out[8] */ 153 TRIG_IN_MUX_0_USBHSDEV_TR_OUT9 = 0x0000005Eu, /* usbhsdev.u2d_tr_out[9] */ 154 TRIG_IN_MUX_0_USBHSDEV_TR_OUT10 = 0x0000005Fu, /* usbhsdev.u2d_tr_out[10] */ 155 TRIG_IN_MUX_0_USBHSDEV_TR_OUT11 = 0x00000060u, /* usbhsdev.u2d_tr_out[11] */ 156 TRIG_IN_MUX_0_USBHSDEV_TR_OUT12 = 0x00000061u, /* usbhsdev.u2d_tr_out[12] */ 157 TRIG_IN_MUX_0_USBHSDEV_TR_OUT13 = 0x00000062u, /* usbhsdev.u2d_tr_out[13] */ 158 TRIG_IN_MUX_0_USBHSDEV_TR_OUT14 = 0x00000063u, /* usbhsdev.u2d_tr_out[14] */ 159 TRIG_IN_MUX_0_USBHSDEV_TR_OUT15 = 0x00000064u, /* usbhsdev.u2d_tr_out[15] */ 160 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT0 = 0x00000065u, /* lvds2usb32ss.hbwss_otrig_o[0] */ 161 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT1 = 0x00000066u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 162 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT2 = 0x00000067u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 163 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT3 = 0x00000068u, /* lvds2usb32ss.hbwss_otrig_o[3] */ 164 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT4 = 0x00000069u, /* lvds2usb32ss.hbwss_otrig_o[4] */ 165 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT5 = 0x0000006Au, /* lvds2usb32ss.hbwss_otrig_o[5] */ 166 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT6 = 0x0000006Bu, /* lvds2usb32ss.hbwss_otrig_o[6] */ 167 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT7 = 0x0000006Cu, /* lvds2usb32ss.hbwss_otrig_o[7] */ 168 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT8 = 0x0000006Du, /* lvds2usb32ss.hbwss_otrig_o[8] */ 169 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT9 = 0x0000006Eu, /* lvds2usb32ss.hbwss_otrig_o[9] */ 170 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT10 = 0x0000006Fu, /* lvds2usb32ss.hbwss_otrig_o[10] */ 171 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT11 = 0x00000070u, /* lvds2usb32ss.hbwss_otrig_o[11] */ 172 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT12 = 0x00000071u, /* lvds2usb32ss.hbwss_otrig_o[12] */ 173 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT13 = 0x00000072u, /* lvds2usb32ss.hbwss_otrig_o[13] */ 174 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT14 = 0x00000073u, /* lvds2usb32ss.hbwss_otrig_o[14] */ 175 TRIG_IN_MUX_0_LVDS2USB32SS_TR_OUT15 = 0x00000074u, /* lvds2usb32ss.hbwss_otrig_o[15] */ 176 TRIG_IN_MUX_0_CAN_DBG_DMA = 0x00000075u, /* canfd[0].tr_dbg_dma_req[0] */ 177 TRIG_IN_MUX_0_LVDS2USB32SS_FRM_CNTR_VLD = 0x00000076u /* lvds2usb32ss.usb32_frm_cntr_vld_o */ 178 } en_trig_input_pdma0_tr_t; 179 180 /* Trigger Input Group 1 - PDMA1 Request Assignments */ 181 typedef enum 182 { 183 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 184 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 185 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 186 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 187 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 188 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 189 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 190 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 191 TRIG_IN_MUX_1_PDMA0_TR_OUT8 = 0x00000109u, /* cpuss.dw0_tr_out[8] */ 192 TRIG_IN_MUX_1_PDMA0_TR_OUT9 = 0x0000010Au, /* cpuss.dw0_tr_out[9] */ 193 TRIG_IN_MUX_1_PDMA0_TR_OUT10 = 0x0000010Bu, /* cpuss.dw0_tr_out[10] */ 194 TRIG_IN_MUX_1_PDMA0_TR_OUT11 = 0x0000010Cu, /* cpuss.dw0_tr_out[11] */ 195 TRIG_IN_MUX_1_PDMA0_TR_OUT12 = 0x0000010Du, /* cpuss.dw0_tr_out[12] */ 196 TRIG_IN_MUX_1_PDMA0_TR_OUT13 = 0x0000010Eu, /* cpuss.dw0_tr_out[13] */ 197 TRIG_IN_MUX_1_PDMA0_TR_OUT14 = 0x0000010Fu, /* cpuss.dw0_tr_out[14] */ 198 TRIG_IN_MUX_1_PDMA0_TR_OUT15 = 0x00000110u, /* cpuss.dw0_tr_out[15] */ 199 TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000111u, /* cpuss.dw1_tr_out[0] */ 200 TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x00000112u, /* cpuss.dw1_tr_out[1] */ 201 TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x00000113u, /* cpuss.dw1_tr_out[2] */ 202 TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x00000114u, /* cpuss.dw1_tr_out[3] */ 203 TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x00000115u, /* cpuss.dw1_tr_out[4] */ 204 TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x00000116u, /* cpuss.dw1_tr_out[5] */ 205 TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x00000117u, /* cpuss.dw1_tr_out[6] */ 206 TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000118u, /* cpuss.dw1_tr_out[7] */ 207 TRIG_IN_MUX_1_PDMA1_TR_OUT8 = 0x00000119u, /* cpuss.dw1_tr_out[8] */ 208 TRIG_IN_MUX_1_PDMA1_TR_OUT9 = 0x0000011Au, /* cpuss.dw1_tr_out[9] */ 209 TRIG_IN_MUX_1_PDMA1_TR_OUT10 = 0x0000011Bu, /* cpuss.dw1_tr_out[10] */ 210 TRIG_IN_MUX_1_PDMA1_TR_OUT11 = 0x0000011Cu, /* cpuss.dw1_tr_out[11] */ 211 TRIG_IN_MUX_1_PDMA1_TR_OUT12 = 0x0000011Du, /* cpuss.dw1_tr_out[12] */ 212 TRIG_IN_MUX_1_PDMA1_TR_OUT13 = 0x0000011Eu, /* cpuss.dw1_tr_out[13] */ 213 TRIG_IN_MUX_1_PDMA1_TR_OUT14 = 0x0000011Fu, /* cpuss.dw1_tr_out[14] */ 214 TRIG_IN_MUX_1_PDMA1_TR_OUT15 = 0x00000120u, /* cpuss.dw1_tr_out[15] */ 215 TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000121u, /* cpuss.dmac_tr_out[0] */ 216 TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000122u, /* cpuss.dmac_tr_out[1] */ 217 TRIG_IN_MUX_1_MDMA_TR_OUT2 = 0x00000123u, /* cpuss.dmac_tr_out[2] */ 218 TRIG_IN_MUX_1_MDMA_TR_OUT3 = 0x00000124u, /* cpuss.dmac_tr_out[3] */ 219 TRIG_IN_MUX_1_MDMA_TR_OUT4 = 0x00000125u, /* cpuss.dmac_tr_out[4] */ 220 TRIG_IN_MUX_1_MDMA_TR_OUT5 = 0x00000126u, /* cpuss.dmac_tr_out[5] */ 221 TRIG_IN_MUX_1_USB_DMA_REQ0 = 0x00000127u, /* usb.dma_req[0] */ 222 TRIG_IN_MUX_1_USB_DMA_REQ1 = 0x00000128u, /* usb.dma_req[1] */ 223 TRIG_IN_MUX_1_USB_DMA_REQ2 = 0x00000129u, /* usb.dma_req[2] */ 224 TRIG_IN_MUX_1_USB_DMA_REQ3 = 0x0000012Au, /* usb.dma_req[3] */ 225 TRIG_IN_MUX_1_USB_DMA_REQ4 = 0x0000012Bu, /* usb.dma_req[4] */ 226 TRIG_IN_MUX_1_USB_DMA_REQ5 = 0x0000012Cu, /* usb.dma_req[5] */ 227 TRIG_IN_MUX_1_USB_DMA_REQ6 = 0x0000012Du, /* usb.dma_req[6] */ 228 TRIG_IN_MUX_1_USB_DMA_REQ7 = 0x0000012Eu, /* usb.dma_req[7] */ 229 TRIG_IN_MUX_1_HSIOM_TR_OUT0 = 0x0000012Fu, /* peri.tr_io_input[0] */ 230 TRIG_IN_MUX_1_HSIOM_TR_OUT1 = 0x00000130u, /* peri.tr_io_input[1] */ 231 TRIG_IN_MUX_1_HSIOM_TR_OUT2 = 0x00000131u, /* peri.tr_io_input[2] */ 232 TRIG_IN_MUX_1_HSIOM_TR_OUT3 = 0x00000132u, /* peri.tr_io_input[3] */ 233 TRIG_IN_MUX_1_HSIOM_TR_OUT4 = 0x00000133u, /* peri.tr_io_input[4] */ 234 TRIG_IN_MUX_1_HSIOM_TR_OUT5 = 0x00000134u, /* peri.tr_io_input[5] */ 235 TRIG_IN_MUX_1_HSIOM_TR_OUT6 = 0x00000135u, /* peri.tr_io_input[6] */ 236 TRIG_IN_MUX_1_HSIOM_TR_OUT7 = 0x00000136u, /* peri.tr_io_input[7] */ 237 TRIG_IN_MUX_1_HSIOM_TR_OUT8 = 0x00000137u, /* peri.tr_io_input[8] */ 238 TRIG_IN_MUX_1_HSIOM_TR_OUT9 = 0x00000138u, /* peri.tr_io_input[9] */ 239 TRIG_IN_MUX_1_HSIOM_TR_OUT10 = 0x00000139u, /* peri.tr_io_input[10] */ 240 TRIG_IN_MUX_1_HSIOM_TR_OUT11 = 0x0000013Au, /* peri.tr_io_input[11] */ 241 TRIG_IN_MUX_1_HSIOM_TR_OUT12 = 0x0000013Bu, /* peri.tr_io_input[12] */ 242 TRIG_IN_MUX_1_HSIOM_TR_OUT13 = 0x0000013Cu, /* peri.tr_io_input[13] */ 243 TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x0000013Du, /* peri.tr_io_input[14] */ 244 TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x0000013Eu, /* peri.tr_io_input[15] */ 245 TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x0000013Fu, /* peri.tr_io_input[16] */ 246 TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000140u, /* peri.tr_io_input[17] */ 247 TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x00000141u, /* peri.tr_io_input[18] */ 248 TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x00000142u, /* peri.tr_io_input[19] */ 249 TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x00000143u, /* peri.tr_io_input[20] */ 250 TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x00000144u, /* peri.tr_io_input[21] */ 251 TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x00000145u, /* peri.tr_io_input[22] */ 252 TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x00000146u, /* peri.tr_io_input[23] */ 253 TRIG_IN_MUX_1_TCPWM_TR_OVERFLOW4 = 0x00000147u, /* tcpwm[0].tr_overflow[4] */ 254 TRIG_IN_MUX_1_TCPWM_TR_COMPARE_MATCH4 = 0x00000148u, /* tcpwm[0].tr_compare_match[4] */ 255 TRIG_IN_MUX_1_TCPWM_TR_UNDERFLOW4 = 0x00000149u, /* tcpwm[0].tr_underflow[4] */ 256 TRIG_IN_MUX_1_TCPWM_TR_OVERFLOW5 = 0x0000014Au, /* tcpwm[0].tr_overflow[5] */ 257 TRIG_IN_MUX_1_TCPWM_TR_COMPARE_MATCH5 = 0x0000014Bu, /* tcpwm[0].tr_compare_match[5] */ 258 TRIG_IN_MUX_1_TCPWM_TR_UNDERFLOW5 = 0x0000014Cu, /* tcpwm[0].tr_underflow[5] */ 259 TRIG_IN_MUX_1_TCPWM_TR_OVERFLOW6 = 0x0000014Du, /* tcpwm[0].tr_overflow[6] */ 260 TRIG_IN_MUX_1_TCPWM_TR_COMPARE_MATCH6 = 0x0000014Eu, /* tcpwm[0].tr_compare_match[6] */ 261 TRIG_IN_MUX_1_TCPWM_TR_UNDERFLOW6 = 0x0000014Fu, /* tcpwm[0].tr_underflow[6] */ 262 TRIG_IN_MUX_1_TCPWM_TR_OVERFLOW7 = 0x00000150u, /* tcpwm[0].tr_overflow[7] */ 263 TRIG_IN_MUX_1_TCPWM_TR_COMPARE_MATCH7 = 0x00000151u, /* tcpwm[0].tr_compare_match[7] */ 264 TRIG_IN_MUX_1_TCPWM_TR_UNDERFLOW7 = 0x00000152u, /* tcpwm[0].tr_underflow[7] */ 265 TRIG_IN_MUX_1_USBHSDEV_TR_OUT16 = 0x00000153u, /* usbhsdev.u2d_tr_out[16] */ 266 TRIG_IN_MUX_1_USBHSDEV_TR_OUT17 = 0x00000154u, /* usbhsdev.u2d_tr_out[17] */ 267 TRIG_IN_MUX_1_USBHSDEV_TR_OUT18 = 0x00000155u, /* usbhsdev.u2d_tr_out[18] */ 268 TRIG_IN_MUX_1_USBHSDEV_TR_OUT19 = 0x00000156u, /* usbhsdev.u2d_tr_out[19] */ 269 TRIG_IN_MUX_1_USBHSDEV_TR_OUT20 = 0x00000157u, /* usbhsdev.u2d_tr_out[20] */ 270 TRIG_IN_MUX_1_USBHSDEV_TR_OUT21 = 0x00000158u, /* usbhsdev.u2d_tr_out[21] */ 271 TRIG_IN_MUX_1_USBHSDEV_TR_OUT22 = 0x00000159u, /* usbhsdev.u2d_tr_out[22] */ 272 TRIG_IN_MUX_1_USBHSDEV_TR_OUT23 = 0x0000015Au, /* usbhsdev.u2d_tr_out[23] */ 273 TRIG_IN_MUX_1_USBHSDEV_TR_OUT24 = 0x0000015Bu, /* usbhsdev.u2d_tr_out[24] */ 274 TRIG_IN_MUX_1_USBHSDEV_TR_OUT25 = 0x0000015Cu, /* usbhsdev.u2d_tr_out[25] */ 275 TRIG_IN_MUX_1_USBHSDEV_TR_OUT26 = 0x0000015Du, /* usbhsdev.u2d_tr_out[26] */ 276 TRIG_IN_MUX_1_USBHSDEV_TR_OUT27 = 0x0000015Eu, /* usbhsdev.u2d_tr_out[27] */ 277 TRIG_IN_MUX_1_USBHSDEV_TR_OUT28 = 0x0000015Fu, /* usbhsdev.u2d_tr_out[28] */ 278 TRIG_IN_MUX_1_USBHSDEV_TR_OUT29 = 0x00000160u, /* usbhsdev.u2d_tr_out[29] */ 279 TRIG_IN_MUX_1_USBHSDEV_TR_OUT30 = 0x00000161u, /* usbhsdev.u2d_tr_out[30] */ 280 TRIG_IN_MUX_1_USBHSDEV_TR_OUT31 = 0x00000162u, /* usbhsdev.u2d_tr_out[31] */ 281 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT0 = 0x00000163u, /* lvds2usb32ss.hbwss_otrig_o[0] */ 282 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT1 = 0x00000164u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 283 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT2 = 0x00000165u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 284 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT3 = 0x00000166u, /* lvds2usb32ss.hbwss_otrig_o[3] */ 285 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT4 = 0x00000167u, /* lvds2usb32ss.hbwss_otrig_o[4] */ 286 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT5 = 0x00000168u, /* lvds2usb32ss.hbwss_otrig_o[5] */ 287 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT6 = 0x00000169u, /* lvds2usb32ss.hbwss_otrig_o[6] */ 288 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT7 = 0x0000016Au, /* lvds2usb32ss.hbwss_otrig_o[7] */ 289 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT8 = 0x0000016Bu, /* lvds2usb32ss.hbwss_otrig_o[8] */ 290 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT9 = 0x0000016Cu, /* lvds2usb32ss.hbwss_otrig_o[9] */ 291 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT10 = 0x0000016Du, /* lvds2usb32ss.hbwss_otrig_o[10] */ 292 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT11 = 0x0000016Eu, /* lvds2usb32ss.hbwss_otrig_o[11] */ 293 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT12 = 0x0000016Fu, /* lvds2usb32ss.hbwss_otrig_o[12] */ 294 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT13 = 0x00000170u, /* lvds2usb32ss.hbwss_otrig_o[13] */ 295 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT14 = 0x00000171u, /* lvds2usb32ss.hbwss_otrig_o[14] */ 296 TRIG_IN_MUX_1_LVDS2USB32SS_TR_OUT15 = 0x00000172u, /* lvds2usb32ss.hbwss_otrig_o[15] */ 297 TRIG_IN_MUX_1_LVDS2USB32SS_FRM_CNTR_VLD = 0x00000173u /* lvds2usb32ss.usb32_frm_cntr_vld_o */ 298 } en_trig_input_pdma1_tr_t; 299 300 /* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ 301 typedef enum 302 { 303 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ 304 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ 305 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ 306 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ 307 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ 308 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ 309 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ 310 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ 311 TRIG_IN_MUX_2_PDMA0_TR_OUT8 = 0x00000209u, /* cpuss.dw0_tr_out[8] */ 312 TRIG_IN_MUX_2_PDMA0_TR_OUT9 = 0x0000020Au, /* cpuss.dw0_tr_out[9] */ 313 TRIG_IN_MUX_2_PDMA0_TR_OUT10 = 0x0000020Bu, /* cpuss.dw0_tr_out[10] */ 314 TRIG_IN_MUX_2_PDMA0_TR_OUT11 = 0x0000020Cu, /* cpuss.dw0_tr_out[11] */ 315 TRIG_IN_MUX_2_PDMA0_TR_OUT12 = 0x0000020Du, /* cpuss.dw0_tr_out[12] */ 316 TRIG_IN_MUX_2_PDMA0_TR_OUT13 = 0x0000020Eu, /* cpuss.dw0_tr_out[13] */ 317 TRIG_IN_MUX_2_PDMA0_TR_OUT14 = 0x0000020Fu, /* cpuss.dw0_tr_out[14] */ 318 TRIG_IN_MUX_2_PDMA0_TR_OUT15 = 0x00000210u, /* cpuss.dw0_tr_out[15] */ 319 TRIG_IN_MUX_2_PDMA0_TR_OUT16 = 0x00000211u, /* cpuss.dw0_tr_out[16] */ 320 TRIG_IN_MUX_2_PDMA0_TR_OUT17 = 0x00000212u, /* cpuss.dw0_tr_out[17] */ 321 TRIG_IN_MUX_2_PDMA0_TR_OUT18 = 0x00000213u, /* cpuss.dw0_tr_out[18] */ 322 TRIG_IN_MUX_2_PDMA0_TR_OUT19 = 0x00000214u, /* cpuss.dw0_tr_out[19] */ 323 TRIG_IN_MUX_2_PDMA0_TR_OUT20 = 0x00000215u, /* cpuss.dw0_tr_out[20] */ 324 TRIG_IN_MUX_2_PDMA0_TR_OUT21 = 0x00000216u, /* cpuss.dw0_tr_out[21] */ 325 TRIG_IN_MUX_2_PDMA0_TR_OUT22 = 0x00000217u, /* cpuss.dw0_tr_out[22] */ 326 TRIG_IN_MUX_2_PDMA0_TR_OUT23 = 0x00000218u, /* cpuss.dw0_tr_out[23] */ 327 TRIG_IN_MUX_2_PDMA1_TR_OUT0 = 0x00000219u, /* cpuss.dw1_tr_out[0] */ 328 TRIG_IN_MUX_2_PDMA1_TR_OUT1 = 0x0000021Au, /* cpuss.dw1_tr_out[1] */ 329 TRIG_IN_MUX_2_PDMA1_TR_OUT2 = 0x0000021Bu, /* cpuss.dw1_tr_out[2] */ 330 TRIG_IN_MUX_2_PDMA1_TR_OUT3 = 0x0000021Cu, /* cpuss.dw1_tr_out[3] */ 331 TRIG_IN_MUX_2_PDMA1_TR_OUT4 = 0x0000021Du, /* cpuss.dw1_tr_out[4] */ 332 TRIG_IN_MUX_2_PDMA1_TR_OUT5 = 0x0000021Eu, /* cpuss.dw1_tr_out[5] */ 333 TRIG_IN_MUX_2_PDMA1_TR_OUT6 = 0x0000021Fu, /* cpuss.dw1_tr_out[6] */ 334 TRIG_IN_MUX_2_PDMA1_TR_OUT7 = 0x00000220u, /* cpuss.dw1_tr_out[7] */ 335 TRIG_IN_MUX_2_PDMA1_TR_OUT8 = 0x00000221u, /* cpuss.dw1_tr_out[8] */ 336 TRIG_IN_MUX_2_PDMA1_TR_OUT9 = 0x00000222u, /* cpuss.dw1_tr_out[9] */ 337 TRIG_IN_MUX_2_PDMA1_TR_OUT10 = 0x00000223u, /* cpuss.dw1_tr_out[10] */ 338 TRIG_IN_MUX_2_PDMA1_TR_OUT11 = 0x00000224u, /* cpuss.dw1_tr_out[11] */ 339 TRIG_IN_MUX_2_PDMA1_TR_OUT12 = 0x00000225u, /* cpuss.dw1_tr_out[12] */ 340 TRIG_IN_MUX_2_PDMA1_TR_OUT13 = 0x00000226u, /* cpuss.dw1_tr_out[13] */ 341 TRIG_IN_MUX_2_PDMA1_TR_OUT14 = 0x00000227u, /* cpuss.dw1_tr_out[14] */ 342 TRIG_IN_MUX_2_PDMA1_TR_OUT15 = 0x00000228u, /* cpuss.dw1_tr_out[15] */ 343 TRIG_IN_MUX_2_PDMA1_TR_OUT16 = 0x00000229u, /* cpuss.dw1_tr_out[16] */ 344 TRIG_IN_MUX_2_PDMA1_TR_OUT17 = 0x0000022Au, /* cpuss.dw1_tr_out[17] */ 345 TRIG_IN_MUX_2_PDMA1_TR_OUT18 = 0x0000022Bu, /* cpuss.dw1_tr_out[18] */ 346 TRIG_IN_MUX_2_PDMA1_TR_OUT19 = 0x0000022Cu, /* cpuss.dw1_tr_out[19] */ 347 TRIG_IN_MUX_2_PDMA1_TR_OUT20 = 0x0000022Du, /* cpuss.dw1_tr_out[20] */ 348 TRIG_IN_MUX_2_PDMA1_TR_OUT21 = 0x0000022Eu, /* cpuss.dw1_tr_out[21] */ 349 TRIG_IN_MUX_2_PDMA1_TR_OUT22 = 0x0000022Fu, /* cpuss.dw1_tr_out[22] */ 350 TRIG_IN_MUX_2_PDMA1_TR_OUT23 = 0x00000230u, /* cpuss.dw1_tr_out[23] */ 351 TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000231u, /* cpuss.dmac_tr_out[0] */ 352 TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x00000232u, /* cpuss.dmac_tr_out[1] */ 353 TRIG_IN_MUX_2_MDMA_TR_OUT2 = 0x00000233u, /* cpuss.dmac_tr_out[2] */ 354 TRIG_IN_MUX_2_MDMA_TR_OUT3 = 0x00000234u, /* cpuss.dmac_tr_out[3] */ 355 TRIG_IN_MUX_2_MDMA_TR_OUT4 = 0x00000235u, /* cpuss.dmac_tr_out[4] */ 356 TRIG_IN_MUX_2_MDMA_TR_OUT5 = 0x00000236u, /* cpuss.dmac_tr_out[5] */ 357 TRIG_IN_MUX_2_USB_DMA_REQ0 = 0x00000237u, /* usb.dma_req[0] */ 358 TRIG_IN_MUX_2_USB_DMA_REQ1 = 0x00000238u, /* usb.dma_req[1] */ 359 TRIG_IN_MUX_2_USB_DMA_REQ2 = 0x00000239u, /* usb.dma_req[2] */ 360 TRIG_IN_MUX_2_USB_DMA_REQ3 = 0x0000023Au, /* usb.dma_req[3] */ 361 TRIG_IN_MUX_2_USB_DMA_REQ4 = 0x0000023Bu, /* usb.dma_req[4] */ 362 TRIG_IN_MUX_2_USB_DMA_REQ5 = 0x0000023Cu, /* usb.dma_req[5] */ 363 TRIG_IN_MUX_2_USB_DMA_REQ6 = 0x0000023Du, /* usb.dma_req[6] */ 364 TRIG_IN_MUX_2_USB_DMA_REQ7 = 0x0000023Eu, /* usb.dma_req[7] */ 365 TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x0000023Fu, /* peri.tr_io_input[0] */ 366 TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000240u, /* peri.tr_io_input[1] */ 367 TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000241u, /* peri.tr_io_input[2] */ 368 TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000242u, /* peri.tr_io_input[3] */ 369 TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000243u, /* peri.tr_io_input[4] */ 370 TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x00000244u, /* peri.tr_io_input[5] */ 371 TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x00000245u, /* peri.tr_io_input[6] */ 372 TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x00000246u, /* peri.tr_io_input[7] */ 373 TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x00000247u, /* peri.tr_io_input[8] */ 374 TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x00000248u, /* peri.tr_io_input[9] */ 375 TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x00000249u, /* peri.tr_io_input[10] */ 376 TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x0000024Au, /* peri.tr_io_input[11] */ 377 TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x0000024Bu, /* peri.tr_io_input[12] */ 378 TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x0000024Cu, /* peri.tr_io_input[13] */ 379 TRIG_IN_MUX_2_HSIOM_TR_OUT14 = 0x0000024Du, /* peri.tr_io_input[14] */ 380 TRIG_IN_MUX_2_HSIOM_TR_OUT15 = 0x0000024Eu, /* peri.tr_io_input[15] */ 381 TRIG_IN_MUX_2_HSIOM_TR_OUT16 = 0x0000024Fu, /* peri.tr_io_input[16] */ 382 TRIG_IN_MUX_2_HSIOM_TR_OUT17 = 0x00000250u, /* peri.tr_io_input[17] */ 383 TRIG_IN_MUX_2_HSIOM_TR_OUT18 = 0x00000251u, /* peri.tr_io_input[18] */ 384 TRIG_IN_MUX_2_HSIOM_TR_OUT19 = 0x00000252u, /* peri.tr_io_input[19] */ 385 TRIG_IN_MUX_2_HSIOM_TR_OUT20 = 0x00000253u, /* peri.tr_io_input[20] */ 386 TRIG_IN_MUX_2_HSIOM_TR_OUT21 = 0x00000254u, /* peri.tr_io_input[21] */ 387 TRIG_IN_MUX_2_HSIOM_TR_OUT22 = 0x00000255u, /* peri.tr_io_input[22] */ 388 TRIG_IN_MUX_2_HSIOM_TR_OUT23 = 0x00000256u, /* peri.tr_io_input[23] */ 389 TRIG_IN_MUX_2_USBHSDEV_TR_OUT0 = 0x00000259u, /* usbhsdev.u2d_tr_out[0] */ 390 TRIG_IN_MUX_2_USBHSDEV_TR_OUT1 = 0x0000025Au, /* usbhsdev.u2d_tr_out[1] */ 391 TRIG_IN_MUX_2_USBHSDEV_TR_OUT2 = 0x0000025Bu, /* usbhsdev.u2d_tr_out[2] */ 392 TRIG_IN_MUX_2_USBHSDEV_TR_OUT3 = 0x0000025Cu, /* usbhsdev.u2d_tr_out[3] */ 393 TRIG_IN_MUX_2_USBHSDEV_TR_OUT4 = 0x0000025Du, /* usbhsdev.u2d_tr_out[4] */ 394 TRIG_IN_MUX_2_USBHSDEV_TR_OUT5 = 0x0000025Eu, /* usbhsdev.u2d_tr_out[5] */ 395 TRIG_IN_MUX_2_USBHSDEV_TR_OUT6 = 0x0000025Fu, /* usbhsdev.u2d_tr_out[6] */ 396 TRIG_IN_MUX_2_USBHSDEV_TR_OUT7 = 0x00000260u, /* usbhsdev.u2d_tr_out[7] */ 397 TRIG_IN_MUX_2_USBHSDEV_TR_OUT8 = 0x00000261u, /* usbhsdev.u2d_tr_out[8] */ 398 TRIG_IN_MUX_2_USBHSDEV_TR_OUT9 = 0x00000262u, /* usbhsdev.u2d_tr_out[9] */ 399 TRIG_IN_MUX_2_USBHSDEV_TR_OUT10 = 0x00000263u, /* usbhsdev.u2d_tr_out[10] */ 400 TRIG_IN_MUX_2_USBHSDEV_TR_OUT11 = 0x00000264u, /* usbhsdev.u2d_tr_out[11] */ 401 TRIG_IN_MUX_2_USBHSDEV_TR_OUT12 = 0x00000265u, /* usbhsdev.u2d_tr_out[12] */ 402 TRIG_IN_MUX_2_USBHSDEV_TR_OUT13 = 0x00000266u, /* usbhsdev.u2d_tr_out[13] */ 403 TRIG_IN_MUX_2_USBHSDEV_TR_OUT14 = 0x00000267u, /* usbhsdev.u2d_tr_out[14] */ 404 TRIG_IN_MUX_2_USBHSDEV_TR_OUT15 = 0x00000268u, /* usbhsdev.u2d_tr_out[15] */ 405 TRIG_IN_MUX_2_USBHSDEV_TR_OUT16 = 0x00000269u, /* usbhsdev.u2d_tr_out[16] */ 406 TRIG_IN_MUX_2_USBHSDEV_TR_OUT17 = 0x0000026Au, /* usbhsdev.u2d_tr_out[17] */ 407 TRIG_IN_MUX_2_USBHSDEV_TR_OUT18 = 0x0000026Bu, /* usbhsdev.u2d_tr_out[18] */ 408 TRIG_IN_MUX_2_USBHSDEV_TR_OUT19 = 0x0000026Cu, /* usbhsdev.u2d_tr_out[19] */ 409 TRIG_IN_MUX_2_USBHSDEV_TR_OUT20 = 0x0000026Du, /* usbhsdev.u2d_tr_out[20] */ 410 TRIG_IN_MUX_2_USBHSDEV_TR_OUT21 = 0x0000026Eu, /* usbhsdev.u2d_tr_out[21] */ 411 TRIG_IN_MUX_2_USBHSDEV_TR_OUT22 = 0x0000026Fu, /* usbhsdev.u2d_tr_out[22] */ 412 TRIG_IN_MUX_2_USBHSDEV_TR_OUT23 = 0x00000270u, /* usbhsdev.u2d_tr_out[23] */ 413 TRIG_IN_MUX_2_USBHSDEV_TR_OUT24 = 0x00000271u, /* usbhsdev.u2d_tr_out[24] */ 414 TRIG_IN_MUX_2_USBHSDEV_TR_OUT25 = 0x00000272u, /* usbhsdev.u2d_tr_out[25] */ 415 TRIG_IN_MUX_2_USBHSDEV_TR_OUT26 = 0x00000273u, /* usbhsdev.u2d_tr_out[26] */ 416 TRIG_IN_MUX_2_USBHSDEV_TR_OUT27 = 0x00000274u, /* usbhsdev.u2d_tr_out[27] */ 417 TRIG_IN_MUX_2_USBHSDEV_TR_OUT28 = 0x00000275u, /* usbhsdev.u2d_tr_out[28] */ 418 TRIG_IN_MUX_2_USBHSDEV_TR_OUT29 = 0x00000276u, /* usbhsdev.u2d_tr_out[29] */ 419 TRIG_IN_MUX_2_USBHSDEV_TR_OUT30 = 0x00000277u, /* usbhsdev.u2d_tr_out[30] */ 420 TRIG_IN_MUX_2_USBHSDEV_TR_OUT31 = 0x00000278u, /* usbhsdev.u2d_tr_out[31] */ 421 TRIG_IN_MUX_2_SMIF_TX_REQ = 0x00000279u, /* smif.tr_tx_req */ 422 TRIG_IN_MUX_2_SMIF_RX_REQ = 0x0000027Au, /* smif.tr_rx_req */ 423 TRIG_IN_MUX_2_PDM_RX_REQ0 = 0x0000027Bu, /* pdm[0].tr_rx_req[0] */ 424 TRIG_IN_MUX_2_PDM_RX_REQ1 = 0x0000027Cu, /* pdm[0].tr_rx_req[1] */ 425 TRIG_IN_MUX_2_TDM_TX_REQ = 0x0000027Du, /* tdm[0].tr_tx_req */ 426 TRIG_IN_MUX_2_TDM_RX_REQ = 0x0000027Eu, /* tdm[0].tr_rx_req */ 427 TRIG_IN_MUX_2_SCB0_TX_REQ = 0x0000027Fu, /* scb[0].tr_tx_req */ 428 TRIG_IN_MUX_2_SCB0_RX_REQ = 0x00000280u, /* scb[0].tr_rx_req */ 429 TRIG_IN_MUX_2_SCB0_SCL_FILTERED = 0x00000281u, /* scb[0].tr_i2c_scl_filtered */ 430 TRIG_IN_MUX_2_SCB1_TX_REQ = 0x00000282u, /* scb[1].tr_tx_req */ 431 TRIG_IN_MUX_2_SCB1_RX_REQ = 0x00000283u, /* scb[1].tr_rx_req */ 432 TRIG_IN_MUX_2_SCB1_SCL_FILTERED = 0x00000284u, /* scb[1].tr_i2c_scl_filtered */ 433 TRIG_IN_MUX_2_SCB2_TX_REQ = 0x00000285u, /* scb[2].tr_tx_req */ 434 TRIG_IN_MUX_2_SCB2_RX_REQ = 0x00000286u, /* scb[2].tr_rx_req */ 435 TRIG_IN_MUX_2_SCB2_SCL_FILTERED = 0x00000287u, /* scb[2].tr_i2c_scl_filtered */ 436 TRIG_IN_MUX_2_SCB3_TX_REQ = 0x00000288u, /* scb[3].tr_tx_req */ 437 TRIG_IN_MUX_2_SCB3_RX_REQ = 0x00000289u, /* scb[3].tr_rx_req */ 438 TRIG_IN_MUX_2_SCB3_SCL_FILTERED = 0x0000028Au, /* scb[3].tr_i2c_scl_filtered */ 439 TRIG_IN_MUX_2_CAN_FIFO0 = 0x0000028Bu, /* canfd[0].tr_fifo0[0] */ 440 TRIG_IN_MUX_2_CAN_FIFO1 = 0x0000028Cu, /* canfd[0].tr_fifo1[0] */ 441 TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x0000028Du, /* cpuss.cti_tr_out[0] */ 442 TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x0000028Eu, /* cpuss.cti_tr_out[1] */ 443 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT0 = 0x0000028Fu, /* lvds2usb32ss.hbwss_otrig_o[0] */ 444 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT1 = 0x00000290u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 445 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT2 = 0x00000291u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 446 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT3 = 0x00000292u, /* lvds2usb32ss.hbwss_otrig_o[3] */ 447 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT4 = 0x00000293u, /* lvds2usb32ss.hbwss_otrig_o[4] */ 448 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT5 = 0x00000294u, /* lvds2usb32ss.hbwss_otrig_o[5] */ 449 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT6 = 0x00000295u, /* lvds2usb32ss.hbwss_otrig_o[6] */ 450 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT7 = 0x00000296u, /* lvds2usb32ss.hbwss_otrig_o[7] */ 451 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT8 = 0x00000297u, /* lvds2usb32ss.hbwss_otrig_o[8] */ 452 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT9 = 0x00000298u, /* lvds2usb32ss.hbwss_otrig_o[9] */ 453 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT10 = 0x00000299u, /* lvds2usb32ss.hbwss_otrig_o[10] */ 454 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT11 = 0x0000029Au, /* lvds2usb32ss.hbwss_otrig_o[11] */ 455 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT12 = 0x0000029Bu, /* lvds2usb32ss.hbwss_otrig_o[12] */ 456 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT13 = 0x0000029Cu, /* lvds2usb32ss.hbwss_otrig_o[13] */ 457 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT14 = 0x0000029Du, /* lvds2usb32ss.hbwss_otrig_o[14] */ 458 TRIG_IN_MUX_2_LVDS2USB32SS_TR_OUT15 = 0x0000029Eu, /* lvds2usb32ss.hbwss_otrig_o[15] */ 459 TRIG_IN_MUX_2_SCB4_TX_REQ = 0x000002AFu, /* scb[4].tr_tx_req */ 460 TRIG_IN_MUX_2_SCB4_RX_REQ = 0x000002B0u, /* scb[4].tr_rx_req */ 461 TRIG_IN_MUX_2_SCB4_SCL_FILTERED = 0x000002B1u, /* scb[4].tr_i2c_scl_filtered */ 462 TRIG_IN_MUX_2_SCB5_TX_REQ = 0x000002B2u, /* scb[5].tr_tx_req */ 463 TRIG_IN_MUX_2_SCB5_RX_REQ = 0x000002B3u, /* scb[5].tr_rx_req */ 464 TRIG_IN_MUX_2_SCB5_SCL_FILTERED = 0x000002B4u, /* scb[5].tr_i2c_scl_filtered */ 465 TRIG_IN_MUX_2_SCB6_TX_REQ = 0x000002B5u, /* scb[6].tr_tx_req */ 466 TRIG_IN_MUX_2_SCB6_RX_REQ = 0x000002B6u, /* scb[6].tr_rx_req */ 467 TRIG_IN_MUX_2_SCB6_SCL_FILTERED = 0x000002B7u, /* scb[6].tr_i2c_scl_filtered */ 468 TRIG_IN_MUX_2_LVDS2USB32SS_FRM_CNTR_VLD = 0x000002B8u /* lvds2usb32ss.usb32_frm_cntr_vld_o */ 469 } en_trig_input_tcpwm0_t; 470 471 /* Trigger Input Group 3 - IO trigger multiplexer */ 472 typedef enum 473 { 474 TRIG_IN_MUX_3_PDMA0_TR_OUT0 = 0x00000301u, /* cpuss.dw0_tr_out[0] */ 475 TRIG_IN_MUX_3_PDMA0_TR_OUT1 = 0x00000302u, /* cpuss.dw0_tr_out[1] */ 476 TRIG_IN_MUX_3_PDMA0_TR_OUT2 = 0x00000303u, /* cpuss.dw0_tr_out[2] */ 477 TRIG_IN_MUX_3_PDMA0_TR_OUT3 = 0x00000304u, /* cpuss.dw0_tr_out[3] */ 478 TRIG_IN_MUX_3_PDMA0_TR_OUT4 = 0x00000305u, /* cpuss.dw0_tr_out[4] */ 479 TRIG_IN_MUX_3_PDMA0_TR_OUT5 = 0x00000306u, /* cpuss.dw0_tr_out[5] */ 480 TRIG_IN_MUX_3_PDMA0_TR_OUT6 = 0x00000307u, /* cpuss.dw0_tr_out[6] */ 481 TRIG_IN_MUX_3_PDMA0_TR_OUT7 = 0x00000308u, /* cpuss.dw0_tr_out[7] */ 482 TRIG_IN_MUX_3_PDMA0_TR_OUT8 = 0x00000309u, /* cpuss.dw0_tr_out[8] */ 483 TRIG_IN_MUX_3_PDMA0_TR_OUT9 = 0x0000030Au, /* cpuss.dw0_tr_out[9] */ 484 TRIG_IN_MUX_3_PDMA0_TR_OUT10 = 0x0000030Bu, /* cpuss.dw0_tr_out[10] */ 485 TRIG_IN_MUX_3_PDMA0_TR_OUT11 = 0x0000030Cu, /* cpuss.dw0_tr_out[11] */ 486 TRIG_IN_MUX_3_PDMA0_TR_OUT12 = 0x0000030Du, /* cpuss.dw0_tr_out[12] */ 487 TRIG_IN_MUX_3_PDMA0_TR_OUT13 = 0x0000030Eu, /* cpuss.dw0_tr_out[13] */ 488 TRIG_IN_MUX_3_PDMA0_TR_OUT14 = 0x0000030Fu, /* cpuss.dw0_tr_out[14] */ 489 TRIG_IN_MUX_3_PDMA0_TR_OUT15 = 0x00000310u, /* cpuss.dw0_tr_out[15] */ 490 TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000311u, /* cpuss.dw1_tr_out[0] */ 491 TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000312u, /* cpuss.dw1_tr_out[1] */ 492 TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000313u, /* cpuss.dw1_tr_out[2] */ 493 TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000314u, /* cpuss.dw1_tr_out[3] */ 494 TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000315u, /* cpuss.dw1_tr_out[4] */ 495 TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000316u, /* cpuss.dw1_tr_out[5] */ 496 TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000317u, /* cpuss.dw1_tr_out[6] */ 497 TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000318u, /* cpuss.dw1_tr_out[7] */ 498 TRIG_IN_MUX_3_PDMA1_TR_OUT8 = 0x00000319u, /* cpuss.dw1_tr_out[8] */ 499 TRIG_IN_MUX_3_PDMA1_TR_OUT9 = 0x0000031Au, /* cpuss.dw1_tr_out[9] */ 500 TRIG_IN_MUX_3_PDMA1_TR_OUT10 = 0x0000031Bu, /* cpuss.dw1_tr_out[10] */ 501 TRIG_IN_MUX_3_PDMA1_TR_OUT11 = 0x0000031Cu, /* cpuss.dw1_tr_out[11] */ 502 TRIG_IN_MUX_3_PDMA1_TR_OUT12 = 0x0000031Du, /* cpuss.dw1_tr_out[12] */ 503 TRIG_IN_MUX_3_PDMA1_TR_OUT13 = 0x0000031Eu, /* cpuss.dw1_tr_out[13] */ 504 TRIG_IN_MUX_3_PDMA1_TR_OUT14 = 0x0000031Fu, /* cpuss.dw1_tr_out[14] */ 505 TRIG_IN_MUX_3_PDMA1_TR_OUT15 = 0x00000320u, /* cpuss.dw1_tr_out[15] */ 506 TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000321u, /* cpuss.dmac_tr_out[0] */ 507 TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x00000322u, /* cpuss.dmac_tr_out[1] */ 508 TRIG_IN_MUX_3_MDMA_TR_OUT2 = 0x00000323u, /* cpuss.dmac_tr_out[2] */ 509 TRIG_IN_MUX_3_MDMA_TR_OUT3 = 0x00000324u, /* cpuss.dmac_tr_out[3] */ 510 TRIG_IN_MUX_3_MDMA_TR_OUT4 = 0x00000325u, /* cpuss.dmac_tr_out[4] */ 511 TRIG_IN_MUX_3_MDMA_TR_OUT5 = 0x00000326u, /* cpuss.dmac_tr_out[5] */ 512 TRIG_IN_MUX_3_USB_DMA_REQ0 = 0x00000327u, /* usb.dma_req[0] */ 513 TRIG_IN_MUX_3_USB_DMA_REQ1 = 0x00000328u, /* usb.dma_req[1] */ 514 TRIG_IN_MUX_3_USB_DMA_REQ2 = 0x00000329u, /* usb.dma_req[2] */ 515 TRIG_IN_MUX_3_USB_DMA_REQ3 = 0x0000032Au, /* usb.dma_req[3] */ 516 TRIG_IN_MUX_3_USB_DMA_REQ4 = 0x0000032Bu, /* usb.dma_req[4] */ 517 TRIG_IN_MUX_3_USB_DMA_REQ5 = 0x0000032Cu, /* usb.dma_req[5] */ 518 TRIG_IN_MUX_3_USB_DMA_REQ6 = 0x0000032Du, /* usb.dma_req[6] */ 519 TRIG_IN_MUX_3_USB_DMA_REQ7 = 0x0000032Eu, /* usb.dma_req[7] */ 520 TRIG_IN_MUX_3_USBHSDEV_TR_OUT0 = 0x00000331u, /* usbhsdev.u2d_tr_out[0] */ 521 TRIG_IN_MUX_3_USBHSDEV_TR_OUT1 = 0x00000332u, /* usbhsdev.u2d_tr_out[1] */ 522 TRIG_IN_MUX_3_USBHSDEV_TR_OUT2 = 0x00000333u, /* usbhsdev.u2d_tr_out[2] */ 523 TRIG_IN_MUX_3_USBHSDEV_TR_OUT3 = 0x00000334u, /* usbhsdev.u2d_tr_out[3] */ 524 TRIG_IN_MUX_3_USBHSDEV_TR_OUT4 = 0x00000335u, /* usbhsdev.u2d_tr_out[4] */ 525 TRIG_IN_MUX_3_USBHSDEV_TR_OUT5 = 0x00000336u, /* usbhsdev.u2d_tr_out[5] */ 526 TRIG_IN_MUX_3_USBHSDEV_TR_OUT6 = 0x00000337u, /* usbhsdev.u2d_tr_out[6] */ 527 TRIG_IN_MUX_3_USBHSDEV_TR_OUT7 = 0x00000338u, /* usbhsdev.u2d_tr_out[7] */ 528 TRIG_IN_MUX_3_USBHSDEV_TR_OUT8 = 0x00000339u, /* usbhsdev.u2d_tr_out[8] */ 529 TRIG_IN_MUX_3_USBHSDEV_TR_OUT9 = 0x0000033Au, /* usbhsdev.u2d_tr_out[9] */ 530 TRIG_IN_MUX_3_USBHSDEV_TR_OUT10 = 0x0000033Bu, /* usbhsdev.u2d_tr_out[10] */ 531 TRIG_IN_MUX_3_USBHSDEV_TR_OUT11 = 0x0000033Cu, /* usbhsdev.u2d_tr_out[11] */ 532 TRIG_IN_MUX_3_USBHSDEV_TR_OUT12 = 0x0000033Du, /* usbhsdev.u2d_tr_out[12] */ 533 TRIG_IN_MUX_3_USBHSDEV_TR_OUT13 = 0x0000033Eu, /* usbhsdev.u2d_tr_out[13] */ 534 TRIG_IN_MUX_3_USBHSDEV_TR_OUT14 = 0x0000033Fu, /* usbhsdev.u2d_tr_out[14] */ 535 TRIG_IN_MUX_3_USBHSDEV_TR_OUT15 = 0x00000340u, /* usbhsdev.u2d_tr_out[15] */ 536 TRIG_IN_MUX_3_USBHSDEV_TR_OUT16 = 0x00000341u, /* usbhsdev.u2d_tr_out[16] */ 537 TRIG_IN_MUX_3_USBHSDEV_TR_OUT17 = 0x00000342u, /* usbhsdev.u2d_tr_out[17] */ 538 TRIG_IN_MUX_3_USBHSDEV_TR_OUT18 = 0x00000343u, /* usbhsdev.u2d_tr_out[18] */ 539 TRIG_IN_MUX_3_USBHSDEV_TR_OUT19 = 0x00000344u, /* usbhsdev.u2d_tr_out[19] */ 540 TRIG_IN_MUX_3_USBHSDEV_TR_OUT20 = 0x00000345u, /* usbhsdev.u2d_tr_out[20] */ 541 TRIG_IN_MUX_3_USBHSDEV_TR_OUT21 = 0x00000346u, /* usbhsdev.u2d_tr_out[21] */ 542 TRIG_IN_MUX_3_USBHSDEV_TR_OUT22 = 0x00000347u, /* usbhsdev.u2d_tr_out[22] */ 543 TRIG_IN_MUX_3_USBHSDEV_TR_OUT23 = 0x00000348u, /* usbhsdev.u2d_tr_out[23] */ 544 TRIG_IN_MUX_3_USBHSDEV_TR_OUT24 = 0x00000349u, /* usbhsdev.u2d_tr_out[24] */ 545 TRIG_IN_MUX_3_USBHSDEV_TR_OUT25 = 0x0000034Au, /* usbhsdev.u2d_tr_out[25] */ 546 TRIG_IN_MUX_3_USBHSDEV_TR_OUT26 = 0x0000034Bu, /* usbhsdev.u2d_tr_out[26] */ 547 TRIG_IN_MUX_3_USBHSDEV_TR_OUT27 = 0x0000034Cu, /* usbhsdev.u2d_tr_out[27] */ 548 TRIG_IN_MUX_3_USBHSDEV_TR_OUT28 = 0x0000034Du, /* usbhsdev.u2d_tr_out[28] */ 549 TRIG_IN_MUX_3_USBHSDEV_TR_OUT29 = 0x0000034Eu, /* usbhsdev.u2d_tr_out[29] */ 550 TRIG_IN_MUX_3_USBHSDEV_TR_OUT30 = 0x0000034Fu, /* usbhsdev.u2d_tr_out[30] */ 551 TRIG_IN_MUX_3_USBHSDEV_TR_OUT31 = 0x00000350u, /* usbhsdev.u2d_tr_out[31] */ 552 TRIG_IN_MUX_3_SMIF_TX_REQ = 0x00000351u, /* smif.tr_tx_req */ 553 TRIG_IN_MUX_3_SMIF_RX_REQ = 0x00000352u, /* smif.tr_rx_req */ 554 TRIG_IN_MUX_3_PDM_RX_REQ0 = 0x00000353u, /* pdm[0].tr_rx_req[0] */ 555 TRIG_IN_MUX_3_PDM_RX_REQ1 = 0x00000354u, /* pdm[0].tr_rx_req[1] */ 556 TRIG_IN_MUX_3_TDM_TX_REQ = 0x00000355u, /* tdm[0].tr_tx_req */ 557 TRIG_IN_MUX_3_TDM_RX_REQ = 0x00000356u, /* tdm[0].tr_rx_req */ 558 TRIG_IN_MUX_3_SCB0_TX_REQ = 0x00000357u, /* scb[0].tr_tx_req */ 559 TRIG_IN_MUX_3_SCB0_RX_REQ = 0x00000358u, /* scb[0].tr_rx_req */ 560 TRIG_IN_MUX_3_SCB0_SCL_FILTERED = 0x00000359u, /* scb[0].tr_i2c_scl_filtered */ 561 TRIG_IN_MUX_3_SCB1_TX_REQ = 0x0000035Au, /* scb[1].tr_tx_req */ 562 TRIG_IN_MUX_3_SCB1_RX_REQ = 0x0000035Bu, /* scb[1].tr_rx_req */ 563 TRIG_IN_MUX_3_SCB1_SCL_FILTERED = 0x0000035Cu, /* scb[1].tr_i2c_scl_filtered */ 564 TRIG_IN_MUX_3_SCB2_TX_REQ = 0x0000035Du, /* scb[2].tr_tx_req */ 565 TRIG_IN_MUX_3_SCB2_RX_REQ = 0x0000035Eu, /* scb[2].tr_rx_req */ 566 TRIG_IN_MUX_3_SCB2_SCL_FILTERED = 0x0000035Fu, /* scb[2].tr_i2c_scl_filtered */ 567 TRIG_IN_MUX_3_SCB3_TX_REQ = 0x00000360u, /* scb[3].tr_tx_req */ 568 TRIG_IN_MUX_3_SCB3_RX_REQ = 0x00000361u, /* scb[3].tr_rx_req */ 569 TRIG_IN_MUX_3_SCB3_SCL_FILTERED = 0x00000362u, /* scb[3].tr_i2c_scl_filtered */ 570 TRIG_IN_MUX_3_CAN_FIFO0 = 0x00000363u, /* canfd[0].tr_fifo0[0] */ 571 TRIG_IN_MUX_3_CAN_FIFO1 = 0x00000364u, /* canfd[0].tr_fifo1[0] */ 572 TRIG_IN_MUX_3_CTI_TR_OUT0 = 0x00000365u, /* cpuss.cti_tr_out[0] */ 573 TRIG_IN_MUX_3_CTI_TR_OUT1 = 0x00000366u, /* cpuss.cti_tr_out[1] */ 574 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW0 = 0x00000367u, /* tcpwm[0].tr_overflow[0] */ 575 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH0 = 0x00000368u, /* tcpwm[0].tr_compare_match[0] */ 576 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW0 = 0x00000369u, /* tcpwm[0].tr_underflow[0] */ 577 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW1 = 0x0000036Au, /* tcpwm[0].tr_overflow[1] */ 578 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH1 = 0x0000036Bu, /* tcpwm[0].tr_compare_match[1] */ 579 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW1 = 0x0000036Cu, /* tcpwm[0].tr_underflow[1] */ 580 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW2 = 0x0000036Du, /* tcpwm[0].tr_overflow[2] */ 581 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH2 = 0x0000036Eu, /* tcpwm[0].tr_compare_match[2] */ 582 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW2 = 0x0000036Fu, /* tcpwm[0].tr_underflow[2] */ 583 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW3 = 0x00000370u, /* tcpwm[0].tr_overflow[3] */ 584 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH3 = 0x00000371u, /* tcpwm[0].tr_compare_match[3] */ 585 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW3 = 0x00000372u, /* tcpwm[0].tr_underflow[3] */ 586 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW4 = 0x00000373u, /* tcpwm[0].tr_overflow[4] */ 587 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH4 = 0x00000374u, /* tcpwm[0].tr_compare_match[4] */ 588 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW4 = 0x00000375u, /* tcpwm[0].tr_underflow[4] */ 589 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW5 = 0x00000376u, /* tcpwm[0].tr_overflow[5] */ 590 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH5 = 0x00000377u, /* tcpwm[0].tr_compare_match[5] */ 591 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW5 = 0x00000378u, /* tcpwm[0].tr_underflow[5] */ 592 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW6 = 0x00000379u, /* tcpwm[0].tr_overflow[6] */ 593 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH6 = 0x0000037Au, /* tcpwm[0].tr_compare_match[6] */ 594 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW6 = 0x0000037Bu, /* tcpwm[0].tr_underflow[6] */ 595 TRIG_IN_MUX_3_TCPWM_TR_OVERFLOW7 = 0x0000037Cu, /* tcpwm[0].tr_overflow[7] */ 596 TRIG_IN_MUX_3_TCPWM_TR_COMPARE_MATCH7 = 0x0000037Du, /* tcpwm[0].tr_compare_match[7] */ 597 TRIG_IN_MUX_3_TCPWM_TR_UNDERFLOW7 = 0x0000037Eu, /* tcpwm[0].tr_underflow[7] */ 598 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT0 = 0x0000037Fu, /* lvds2usb32ss.hbwss_otrig_o[0] */ 599 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT1 = 0x00000380u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 600 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT2 = 0x00000381u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 601 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT3 = 0x00000382u, /* lvds2usb32ss.hbwss_otrig_o[3] */ 602 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT4 = 0x00000383u, /* lvds2usb32ss.hbwss_otrig_o[4] */ 603 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT5 = 0x00000384u, /* lvds2usb32ss.hbwss_otrig_o[5] */ 604 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT6 = 0x00000385u, /* lvds2usb32ss.hbwss_otrig_o[6] */ 605 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT7 = 0x00000386u, /* lvds2usb32ss.hbwss_otrig_o[7] */ 606 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT8 = 0x00000387u, /* lvds2usb32ss.hbwss_otrig_o[8] */ 607 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT9 = 0x00000388u, /* lvds2usb32ss.hbwss_otrig_o[9] */ 608 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT10 = 0x00000389u, /* lvds2usb32ss.hbwss_otrig_o[10] */ 609 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT11 = 0x0000038Au, /* lvds2usb32ss.hbwss_otrig_o[11] */ 610 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT12 = 0x0000038Bu, /* lvds2usb32ss.hbwss_otrig_o[12] */ 611 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT13 = 0x0000038Cu, /* lvds2usb32ss.hbwss_otrig_o[13] */ 612 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT14 = 0x0000038Du, /* lvds2usb32ss.hbwss_otrig_o[14] */ 613 TRIG_IN_MUX_3_LVDS2USB32SS_TR_OUT15 = 0x0000038Eu, /* lvds2usb32ss.hbwss_otrig_o[15] */ 614 TRIG_IN_MUX_3_SCB4_TX_REQ = 0x0000039Fu, /* scb[4].tr_tx_req */ 615 TRIG_IN_MUX_3_SCB4_RX_REQ = 0x000003A0u, /* scb[4].tr_rx_req */ 616 TRIG_IN_MUX_3_SCB4_SCL_FILTERED = 0x000003A1u, /* scb[4].tr_i2c_scl_filtered */ 617 TRIG_IN_MUX_3_SCB5_TX_REQ = 0x000003A2u, /* scb[5].tr_tx_req */ 618 TRIG_IN_MUX_3_SCB5_RX_REQ = 0x000003A3u, /* scb[5].tr_rx_req */ 619 TRIG_IN_MUX_3_SCB5_SCL_FILTERED = 0x000003A4u, /* scb[5].tr_i2c_scl_filtered */ 620 TRIG_IN_MUX_3_SCB6_TX_REQ = 0x000003A5u, /* scb[6].tr_tx_req */ 621 TRIG_IN_MUX_3_SCB6_RX_REQ = 0x000003A6u, /* scb[6].tr_rx_req */ 622 TRIG_IN_MUX_3_SCB6_SCL_FILTERED = 0x000003A7u /* scb[6].tr_i2c_scl_filtered */ 623 } en_trig_input_ioss_t; 624 625 /* Trigger Input Group 4 - IO trigger multiplexer */ 626 typedef enum 627 { 628 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 629 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 630 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 631 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 632 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 633 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 634 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 635 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 636 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 637 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 638 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 639 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 640 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 641 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 642 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 643 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 644 TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ 645 TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ 646 TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ 647 TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ 648 TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ 649 TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ 650 TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ 651 TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ 652 TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x00000419u, /* cpuss.dw1_tr_out[0] */ 653 TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Au, /* cpuss.dw1_tr_out[1] */ 654 TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x0000041Bu, /* cpuss.dw1_tr_out[2] */ 655 TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x0000041Cu, /* cpuss.dw1_tr_out[3] */ 656 TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x0000041Du, /* cpuss.dw1_tr_out[4] */ 657 TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x0000041Eu, /* cpuss.dw1_tr_out[5] */ 658 TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x0000041Fu, /* cpuss.dw1_tr_out[6] */ 659 TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000420u, /* cpuss.dw1_tr_out[7] */ 660 TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000421u, /* cpuss.dw1_tr_out[8] */ 661 TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000422u, /* cpuss.dw1_tr_out[9] */ 662 TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000423u, /* cpuss.dw1_tr_out[10] */ 663 TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000424u, /* cpuss.dw1_tr_out[11] */ 664 TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x00000425u, /* cpuss.dw1_tr_out[12] */ 665 TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x00000426u, /* cpuss.dw1_tr_out[13] */ 666 TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x00000427u, /* cpuss.dw1_tr_out[14] */ 667 TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x00000428u, /* cpuss.dw1_tr_out[15] */ 668 TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x00000429u, /* cpuss.dw1_tr_out[16] */ 669 TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Au, /* cpuss.dw1_tr_out[17] */ 670 TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x0000042Bu, /* cpuss.dw1_tr_out[18] */ 671 TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x0000042Cu, /* cpuss.dw1_tr_out[19] */ 672 TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x0000042Du, /* cpuss.dw1_tr_out[20] */ 673 TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x0000042Eu, /* cpuss.dw1_tr_out[21] */ 674 TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x0000042Fu, /* cpuss.dw1_tr_out[22] */ 675 TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000430u, /* cpuss.dw1_tr_out[23] */ 676 TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x00000431u, /* cpuss.dmac_tr_out[0] */ 677 TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x00000432u, /* cpuss.dmac_tr_out[1] */ 678 TRIG_IN_MUX_4_MDMA_TR_OUT2 = 0x00000433u, /* cpuss.dmac_tr_out[2] */ 679 TRIG_IN_MUX_4_MDMA_TR_OUT3 = 0x00000434u, /* cpuss.dmac_tr_out[3] */ 680 TRIG_IN_MUX_4_MDMA_TR_OUT4 = 0x00000435u, /* cpuss.dmac_tr_out[4] */ 681 TRIG_IN_MUX_4_MDMA_TR_OUT5 = 0x00000436u, /* cpuss.dmac_tr_out[5] */ 682 TRIG_IN_MUX_4_USB_DMA_REQ0 = 0x00000437u, /* usb.dma_req[0] */ 683 TRIG_IN_MUX_4_USB_DMA_REQ1 = 0x00000438u, /* usb.dma_req[1] */ 684 TRIG_IN_MUX_4_USB_DMA_REQ2 = 0x00000439u, /* usb.dma_req[2] */ 685 TRIG_IN_MUX_4_USB_DMA_REQ3 = 0x0000043Au, /* usb.dma_req[3] */ 686 TRIG_IN_MUX_4_USB_DMA_REQ4 = 0x0000043Bu, /* usb.dma_req[4] */ 687 TRIG_IN_MUX_4_USB_DMA_REQ5 = 0x0000043Cu, /* usb.dma_req[5] */ 688 TRIG_IN_MUX_4_USB_DMA_REQ6 = 0x0000043Du, /* usb.dma_req[6] */ 689 TRIG_IN_MUX_4_USB_DMA_REQ7 = 0x0000043Eu, /* usb.dma_req[7] */ 690 TRIG_IN_MUX_4_HSIOM_TR_OUT0 = 0x0000043Fu, /* peri.tr_io_input[0] */ 691 TRIG_IN_MUX_4_HSIOM_TR_OUT1 = 0x00000440u, /* peri.tr_io_input[1] */ 692 TRIG_IN_MUX_4_HSIOM_TR_OUT2 = 0x00000441u, /* peri.tr_io_input[2] */ 693 TRIG_IN_MUX_4_HSIOM_TR_OUT3 = 0x00000442u, /* peri.tr_io_input[3] */ 694 TRIG_IN_MUX_4_HSIOM_TR_OUT4 = 0x00000443u, /* peri.tr_io_input[4] */ 695 TRIG_IN_MUX_4_HSIOM_TR_OUT5 = 0x00000444u, /* peri.tr_io_input[5] */ 696 TRIG_IN_MUX_4_HSIOM_TR_OUT6 = 0x00000445u, /* peri.tr_io_input[6] */ 697 TRIG_IN_MUX_4_HSIOM_TR_OUT7 = 0x00000446u, /* peri.tr_io_input[7] */ 698 TRIG_IN_MUX_4_HSIOM_TR_OUT8 = 0x00000447u, /* peri.tr_io_input[8] */ 699 TRIG_IN_MUX_4_HSIOM_TR_OUT9 = 0x00000448u, /* peri.tr_io_input[9] */ 700 TRIG_IN_MUX_4_HSIOM_TR_OUT10 = 0x00000449u, /* peri.tr_io_input[10] */ 701 TRIG_IN_MUX_4_HSIOM_TR_OUT11 = 0x0000044Au, /* peri.tr_io_input[11] */ 702 TRIG_IN_MUX_4_HSIOM_TR_OUT12 = 0x0000044Bu, /* peri.tr_io_input[12] */ 703 TRIG_IN_MUX_4_HSIOM_TR_OUT13 = 0x0000044Cu, /* peri.tr_io_input[13] */ 704 TRIG_IN_MUX_4_HSIOM_TR_OUT14 = 0x0000044Du, /* peri.tr_io_input[14] */ 705 TRIG_IN_MUX_4_HSIOM_TR_OUT15 = 0x0000044Eu, /* peri.tr_io_input[15] */ 706 TRIG_IN_MUX_4_HSIOM_TR_OUT16 = 0x0000044Fu, /* peri.tr_io_input[16] */ 707 TRIG_IN_MUX_4_HSIOM_TR_OUT17 = 0x00000450u, /* peri.tr_io_input[17] */ 708 TRIG_IN_MUX_4_HSIOM_TR_OUT18 = 0x00000451u, /* peri.tr_io_input[18] */ 709 TRIG_IN_MUX_4_HSIOM_TR_OUT19 = 0x00000452u, /* peri.tr_io_input[19] */ 710 TRIG_IN_MUX_4_HSIOM_TR_OUT20 = 0x00000453u, /* peri.tr_io_input[20] */ 711 TRIG_IN_MUX_4_HSIOM_TR_OUT21 = 0x00000454u, /* peri.tr_io_input[21] */ 712 TRIG_IN_MUX_4_HSIOM_TR_OUT22 = 0x00000455u, /* peri.tr_io_input[22] */ 713 TRIG_IN_MUX_4_HSIOM_TR_OUT23 = 0x00000456u, /* peri.tr_io_input[23] */ 714 TRIG_IN_MUX_4_USBHSDEV_TR_OUT0 = 0x00000459u, /* usbhsdev.u2d_tr_out[0] */ 715 TRIG_IN_MUX_4_USBHSDEV_TR_OUT1 = 0x0000045Au, /* usbhsdev.u2d_tr_out[1] */ 716 TRIG_IN_MUX_4_USBHSDEV_TR_OUT2 = 0x0000045Bu, /* usbhsdev.u2d_tr_out[2] */ 717 TRIG_IN_MUX_4_USBHSDEV_TR_OUT3 = 0x0000045Cu, /* usbhsdev.u2d_tr_out[3] */ 718 TRIG_IN_MUX_4_USBHSDEV_TR_OUT4 = 0x0000045Du, /* usbhsdev.u2d_tr_out[4] */ 719 TRIG_IN_MUX_4_USBHSDEV_TR_OUT5 = 0x0000045Eu, /* usbhsdev.u2d_tr_out[5] */ 720 TRIG_IN_MUX_4_USBHSDEV_TR_OUT6 = 0x0000045Fu, /* usbhsdev.u2d_tr_out[6] */ 721 TRIG_IN_MUX_4_USBHSDEV_TR_OUT7 = 0x00000460u, /* usbhsdev.u2d_tr_out[7] */ 722 TRIG_IN_MUX_4_USBHSDEV_TR_OUT8 = 0x00000461u, /* usbhsdev.u2d_tr_out[8] */ 723 TRIG_IN_MUX_4_USBHSDEV_TR_OUT9 = 0x00000462u, /* usbhsdev.u2d_tr_out[9] */ 724 TRIG_IN_MUX_4_USBHSDEV_TR_OUT10 = 0x00000463u, /* usbhsdev.u2d_tr_out[10] */ 725 TRIG_IN_MUX_4_USBHSDEV_TR_OUT11 = 0x00000464u, /* usbhsdev.u2d_tr_out[11] */ 726 TRIG_IN_MUX_4_USBHSDEV_TR_OUT12 = 0x00000465u, /* usbhsdev.u2d_tr_out[12] */ 727 TRIG_IN_MUX_4_USBHSDEV_TR_OUT13 = 0x00000466u, /* usbhsdev.u2d_tr_out[13] */ 728 TRIG_IN_MUX_4_USBHSDEV_TR_OUT14 = 0x00000467u, /* usbhsdev.u2d_tr_out[14] */ 729 TRIG_IN_MUX_4_USBHSDEV_TR_OUT15 = 0x00000468u, /* usbhsdev.u2d_tr_out[15] */ 730 TRIG_IN_MUX_4_USBHSDEV_TR_OUT16 = 0x00000469u, /* usbhsdev.u2d_tr_out[16] */ 731 TRIG_IN_MUX_4_USBHSDEV_TR_OUT17 = 0x0000046Au, /* usbhsdev.u2d_tr_out[17] */ 732 TRIG_IN_MUX_4_USBHSDEV_TR_OUT18 = 0x0000046Bu, /* usbhsdev.u2d_tr_out[18] */ 733 TRIG_IN_MUX_4_USBHSDEV_TR_OUT19 = 0x0000046Cu, /* usbhsdev.u2d_tr_out[19] */ 734 TRIG_IN_MUX_4_USBHSDEV_TR_OUT20 = 0x0000046Du, /* usbhsdev.u2d_tr_out[20] */ 735 TRIG_IN_MUX_4_USBHSDEV_TR_OUT21 = 0x0000046Eu, /* usbhsdev.u2d_tr_out[21] */ 736 TRIG_IN_MUX_4_USBHSDEV_TR_OUT22 = 0x0000046Fu, /* usbhsdev.u2d_tr_out[22] */ 737 TRIG_IN_MUX_4_USBHSDEV_TR_OUT23 = 0x00000470u, /* usbhsdev.u2d_tr_out[23] */ 738 TRIG_IN_MUX_4_USBHSDEV_TR_OUT24 = 0x00000471u, /* usbhsdev.u2d_tr_out[24] */ 739 TRIG_IN_MUX_4_USBHSDEV_TR_OUT25 = 0x00000472u, /* usbhsdev.u2d_tr_out[25] */ 740 TRIG_IN_MUX_4_USBHSDEV_TR_OUT26 = 0x00000473u, /* usbhsdev.u2d_tr_out[26] */ 741 TRIG_IN_MUX_4_USBHSDEV_TR_OUT27 = 0x00000474u, /* usbhsdev.u2d_tr_out[27] */ 742 TRIG_IN_MUX_4_USBHSDEV_TR_OUT28 = 0x00000475u, /* usbhsdev.u2d_tr_out[28] */ 743 TRIG_IN_MUX_4_USBHSDEV_TR_OUT29 = 0x00000476u, /* usbhsdev.u2d_tr_out[29] */ 744 TRIG_IN_MUX_4_USBHSDEV_TR_OUT30 = 0x00000477u, /* usbhsdev.u2d_tr_out[30] */ 745 TRIG_IN_MUX_4_USBHSDEV_TR_OUT31 = 0x00000478u, /* usbhsdev.u2d_tr_out[31] */ 746 TRIG_IN_MUX_4_SMIF_TX_REQ = 0x00000479u, /* smif.tr_tx_req */ 747 TRIG_IN_MUX_4_SMIF_RX_REQ = 0x0000047Au, /* smif.tr_rx_req */ 748 TRIG_IN_MUX_4_PDM_RX_REQ0 = 0x0000047Bu, /* pdm[0].tr_rx_req[0] */ 749 TRIG_IN_MUX_4_PDM_RX_REQ1 = 0x0000047Cu, /* pdm[0].tr_rx_req[1] */ 750 TRIG_IN_MUX_4_TDM_TX_REQ = 0x0000047Du, /* tdm[0].tr_tx_req */ 751 TRIG_IN_MUX_4_TDM_RX_REQ = 0x0000047Eu, /* tdm[0].tr_rx_req */ 752 TRIG_IN_MUX_4_SCB0_TX_REQ = 0x0000047Fu, /* scb[0].tr_tx_req */ 753 TRIG_IN_MUX_4_SCB0_RX_REQ = 0x00000480u, /* scb[0].tr_rx_req */ 754 TRIG_IN_MUX_4_SCB0_SCL_FILTERED = 0x00000481u, /* scb[0].tr_i2c_scl_filtered */ 755 TRIG_IN_MUX_4_SCB1_TX_REQ = 0x00000482u, /* scb[1].tr_tx_req */ 756 TRIG_IN_MUX_4_SCB1_RX_REQ = 0x00000483u, /* scb[1].tr_rx_req */ 757 TRIG_IN_MUX_4_SCB1_SCL_FILTERED = 0x00000484u, /* scb[1].tr_i2c_scl_filtered */ 758 TRIG_IN_MUX_4_SCB2_TX_REQ = 0x00000485u, /* scb[2].tr_tx_req */ 759 TRIG_IN_MUX_4_SCB2_RX_REQ = 0x00000486u, /* scb[2].tr_rx_req */ 760 TRIG_IN_MUX_4_SCB2_SCL_FILTERED = 0x00000487u, /* scb[2].tr_i2c_scl_filtered */ 761 TRIG_IN_MUX_4_SCB3_TX_REQ = 0x00000488u, /* scb[3].tr_tx_req */ 762 TRIG_IN_MUX_4_SCB3_RX_REQ = 0x00000489u, /* scb[3].tr_rx_req */ 763 TRIG_IN_MUX_4_SCB3_SCL_FILTERED = 0x0000048Au, /* scb[3].tr_i2c_scl_filtered */ 764 TRIG_IN_MUX_4_CAN_FIFO0 = 0x0000048Bu, /* canfd[0].tr_fifo0[0] */ 765 TRIG_IN_MUX_4_CAN_FIFO1 = 0x0000048Cu, /* canfd[0].tr_fifo1[0] */ 766 TRIG_IN_MUX_4_CAN_DBG_DMA = 0x0000048Du, /* canfd[0].tr_dbg_dma_req[0] */ 767 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW0 = 0x0000048Eu, /* tcpwm[0].tr_overflow[0] */ 768 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH0 = 0x0000048Fu, /* tcpwm[0].tr_compare_match[0] */ 769 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW0 = 0x00000490u, /* tcpwm[0].tr_underflow[0] */ 770 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW1 = 0x00000491u, /* tcpwm[0].tr_overflow[1] */ 771 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH1 = 0x00000492u, /* tcpwm[0].tr_compare_match[1] */ 772 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW1 = 0x00000493u, /* tcpwm[0].tr_underflow[1] */ 773 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW2 = 0x00000494u, /* tcpwm[0].tr_overflow[2] */ 774 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH2 = 0x00000495u, /* tcpwm[0].tr_compare_match[2] */ 775 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW2 = 0x00000496u, /* tcpwm[0].tr_underflow[2] */ 776 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW3 = 0x00000497u, /* tcpwm[0].tr_overflow[3] */ 777 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH3 = 0x00000498u, /* tcpwm[0].tr_compare_match[3] */ 778 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW3 = 0x00000499u, /* tcpwm[0].tr_underflow[3] */ 779 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW4 = 0x0000049Au, /* tcpwm[0].tr_overflow[4] */ 780 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH4 = 0x0000049Bu, /* tcpwm[0].tr_compare_match[4] */ 781 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW4 = 0x0000049Cu, /* tcpwm[0].tr_underflow[4] */ 782 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW5 = 0x0000049Du, /* tcpwm[0].tr_overflow[5] */ 783 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH5 = 0x0000049Eu, /* tcpwm[0].tr_compare_match[5] */ 784 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW5 = 0x0000049Fu, /* tcpwm[0].tr_underflow[5] */ 785 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW6 = 0x000004A0u, /* tcpwm[0].tr_overflow[6] */ 786 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH6 = 0x000004A1u, /* tcpwm[0].tr_compare_match[6] */ 787 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW6 = 0x000004A2u, /* tcpwm[0].tr_underflow[6] */ 788 TRIG_IN_MUX_4_TCPWM_TR_OVERFLOW7 = 0x000004A3u, /* tcpwm[0].tr_overflow[7] */ 789 TRIG_IN_MUX_4_TCPWM_TR_COMPARE_MATCH7 = 0x000004A4u, /* tcpwm[0].tr_compare_match[7] */ 790 TRIG_IN_MUX_4_TCPWM_TR_UNDERFLOW7 = 0x000004A5u, /* tcpwm[0].tr_underflow[7] */ 791 TRIG_IN_MUX_4_CAN_TT_TR_OUT0 = 0x000004A6u, /* canfd[0].tr_tmp_rtp_out[0] */ 792 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT0 = 0x000004A7u, /* lvds2usb32ss.hbwss_otrig_o[0] */ 793 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT1 = 0x000004A8u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 794 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT2 = 0x000004A9u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 795 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT3 = 0x000004AAu, /* lvds2usb32ss.hbwss_otrig_o[3] */ 796 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT4 = 0x000004ABu, /* lvds2usb32ss.hbwss_otrig_o[4] */ 797 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT5 = 0x000004ACu, /* lvds2usb32ss.hbwss_otrig_o[5] */ 798 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT6 = 0x000004ADu, /* lvds2usb32ss.hbwss_otrig_o[6] */ 799 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT7 = 0x000004AEu, /* lvds2usb32ss.hbwss_otrig_o[7] */ 800 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT8 = 0x000004AFu, /* lvds2usb32ss.hbwss_otrig_o[8] */ 801 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT9 = 0x000004B0u, /* lvds2usb32ss.hbwss_otrig_o[9] */ 802 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT10 = 0x000004B1u, /* lvds2usb32ss.hbwss_otrig_o[10] */ 803 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT11 = 0x000004B2u, /* lvds2usb32ss.hbwss_otrig_o[11] */ 804 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT12 = 0x000004B3u, /* lvds2usb32ss.hbwss_otrig_o[12] */ 805 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT13 = 0x000004B4u, /* lvds2usb32ss.hbwss_otrig_o[13] */ 806 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT14 = 0x000004B5u, /* lvds2usb32ss.hbwss_otrig_o[14] */ 807 TRIG_IN_MUX_4_LVDS2USB32SS_TR_OUT15 = 0x000004B6u, /* lvds2usb32ss.hbwss_otrig_o[15] */ 808 TRIG_IN_MUX_4_SCB4_TX_REQ = 0x000004C7u, /* scb[4].tr_tx_req */ 809 TRIG_IN_MUX_4_SCB4_RX_REQ = 0x000004C8u, /* scb[4].tr_rx_req */ 810 TRIG_IN_MUX_4_SCB4_SCL_FILTERED = 0x000004C9u, /* scb[4].tr_i2c_scl_filtered */ 811 TRIG_IN_MUX_4_SCB5_TX_REQ = 0x000004CAu, /* scb[5].tr_tx_req */ 812 TRIG_IN_MUX_4_SCB5_RX_REQ = 0x000004CBu, /* scb[5].tr_rx_req */ 813 TRIG_IN_MUX_4_SCB5_SCL_FILTERED = 0x000004CCu, /* scb[5].tr_i2c_scl_filtered */ 814 TRIG_IN_MUX_4_SCB6_TX_REQ = 0x000004CDu, /* scb[6].tr_tx_req */ 815 TRIG_IN_MUX_4_SCB6_RX_REQ = 0x000004CEu, /* scb[6].tr_rx_req */ 816 TRIG_IN_MUX_4_SCB6_SCL_FILTERED = 0x000004CFu /* scb[6].tr_i2c_scl_filtered */ 817 } en_trig_input_cpuss_cti_t; 818 819 /* Trigger Input Group 5 - MDMA trigger multiplexer */ 820 typedef enum 821 { 822 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ 823 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ 824 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ 825 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ 826 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ 827 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ 828 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ 829 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ 830 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ 831 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ 832 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ 833 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ 834 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ 835 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ 836 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ 837 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ 838 TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ 839 TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ 840 TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ 841 TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ 842 TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ 843 TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ 844 TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ 845 TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ 846 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x00000519u, /* cpuss.dw1_tr_out[0] */ 847 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Au, /* cpuss.dw1_tr_out[1] */ 848 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x0000051Bu, /* cpuss.dw1_tr_out[2] */ 849 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x0000051Cu, /* cpuss.dw1_tr_out[3] */ 850 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x0000051Du, /* cpuss.dw1_tr_out[4] */ 851 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x0000051Eu, /* cpuss.dw1_tr_out[5] */ 852 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x0000051Fu, /* cpuss.dw1_tr_out[6] */ 853 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000520u, /* cpuss.dw1_tr_out[7] */ 854 TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000521u, /* cpuss.dw1_tr_out[8] */ 855 TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000522u, /* cpuss.dw1_tr_out[9] */ 856 TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000523u, /* cpuss.dw1_tr_out[10] */ 857 TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000524u, /* cpuss.dw1_tr_out[11] */ 858 TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x00000525u, /* cpuss.dw1_tr_out[12] */ 859 TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x00000526u, /* cpuss.dw1_tr_out[13] */ 860 TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x00000527u, /* cpuss.dw1_tr_out[14] */ 861 TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x00000528u, /* cpuss.dw1_tr_out[15] */ 862 TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x00000529u, /* cpuss.dw1_tr_out[16] */ 863 TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Au, /* cpuss.dw1_tr_out[17] */ 864 TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x0000052Bu, /* cpuss.dw1_tr_out[18] */ 865 TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x0000052Cu, /* cpuss.dw1_tr_out[19] */ 866 TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x0000052Du, /* cpuss.dw1_tr_out[20] */ 867 TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x0000052Eu, /* cpuss.dw1_tr_out[21] */ 868 TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x0000052Fu, /* cpuss.dw1_tr_out[22] */ 869 TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000530u, /* cpuss.dw1_tr_out[23] */ 870 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x00000531u, /* cpuss.dmac_tr_out[0] */ 871 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x00000532u, /* cpuss.dmac_tr_out[1] */ 872 TRIG_IN_MUX_5_MDMA_TR_OUT2 = 0x00000533u, /* cpuss.dmac_tr_out[2] */ 873 TRIG_IN_MUX_5_MDMA_TR_OUT3 = 0x00000534u, /* cpuss.dmac_tr_out[3] */ 874 TRIG_IN_MUX_5_MDMA_TR_OUT4 = 0x00000535u, /* cpuss.dmac_tr_out[4] */ 875 TRIG_IN_MUX_5_MDMA_TR_OUT5 = 0x00000536u, /* cpuss.dmac_tr_out[5] */ 876 TRIG_IN_MUX_5_USB_DMA_REQ0 = 0x00000537u, /* usb.dma_req[0] */ 877 TRIG_IN_MUX_5_USB_DMA_REQ1 = 0x00000538u, /* usb.dma_req[1] */ 878 TRIG_IN_MUX_5_USB_DMA_REQ2 = 0x00000539u, /* usb.dma_req[2] */ 879 TRIG_IN_MUX_5_USB_DMA_REQ3 = 0x0000053Au, /* usb.dma_req[3] */ 880 TRIG_IN_MUX_5_USB_DMA_REQ4 = 0x0000053Bu, /* usb.dma_req[4] */ 881 TRIG_IN_MUX_5_USB_DMA_REQ5 = 0x0000053Cu, /* usb.dma_req[5] */ 882 TRIG_IN_MUX_5_USB_DMA_REQ6 = 0x0000053Du, /* usb.dma_req[6] */ 883 TRIG_IN_MUX_5_USB_DMA_REQ7 = 0x0000053Eu, /* usb.dma_req[7] */ 884 TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x0000053Fu, /* peri.tr_io_input[0] */ 885 TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x00000540u, /* peri.tr_io_input[1] */ 886 TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x00000541u, /* peri.tr_io_input[2] */ 887 TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x00000542u, /* peri.tr_io_input[3] */ 888 TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x00000543u, /* peri.tr_io_input[4] */ 889 TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x00000544u, /* peri.tr_io_input[5] */ 890 TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x00000545u, /* peri.tr_io_input[6] */ 891 TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x00000546u, /* peri.tr_io_input[7] */ 892 TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x00000547u, /* peri.tr_io_input[8] */ 893 TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x00000548u, /* peri.tr_io_input[9] */ 894 TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x00000549u, /* peri.tr_io_input[10] */ 895 TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x0000054Au, /* peri.tr_io_input[11] */ 896 TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x0000054Bu, /* peri.tr_io_input[12] */ 897 TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x0000054Cu, /* peri.tr_io_input[13] */ 898 TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x0000054Du, /* peri.tr_io_input[14] */ 899 TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x0000054Eu, /* peri.tr_io_input[15] */ 900 TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x0000054Fu, /* peri.tr_io_input[16] */ 901 TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x00000550u, /* peri.tr_io_input[17] */ 902 TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x00000551u, /* peri.tr_io_input[18] */ 903 TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x00000552u, /* peri.tr_io_input[19] */ 904 TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x00000553u, /* peri.tr_io_input[20] */ 905 TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x00000554u, /* peri.tr_io_input[21] */ 906 TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x00000555u, /* peri.tr_io_input[22] */ 907 TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x00000556u, /* peri.tr_io_input[23] */ 908 TRIG_IN_MUX_5_USBHSDEV_TR_OUT0 = 0x00000557u, /* usbhsdev.u2d_tr_out[0] */ 909 TRIG_IN_MUX_5_USBHSDEV_TR_OUT1 = 0x00000558u, /* usbhsdev.u2d_tr_out[1] */ 910 TRIG_IN_MUX_5_USBHSDEV_TR_OUT2 = 0x00000559u, /* usbhsdev.u2d_tr_out[2] */ 911 TRIG_IN_MUX_5_USBHSDEV_TR_OUT3 = 0x0000055Au, /* usbhsdev.u2d_tr_out[3] */ 912 TRIG_IN_MUX_5_USBHSDEV_TR_OUT4 = 0x0000055Bu, /* usbhsdev.u2d_tr_out[4] */ 913 TRIG_IN_MUX_5_USBHSDEV_TR_OUT5 = 0x0000055Cu, /* usbhsdev.u2d_tr_out[5] */ 914 TRIG_IN_MUX_5_USBHSDEV_TR_OUT6 = 0x0000055Du, /* usbhsdev.u2d_tr_out[6] */ 915 TRIG_IN_MUX_5_USBHSDEV_TR_OUT7 = 0x0000055Eu, /* usbhsdev.u2d_tr_out[7] */ 916 TRIG_IN_MUX_5_USBHSDEV_TR_OUT8 = 0x0000055Fu, /* usbhsdev.u2d_tr_out[8] */ 917 TRIG_IN_MUX_5_USBHSDEV_TR_OUT9 = 0x00000560u, /* usbhsdev.u2d_tr_out[9] */ 918 TRIG_IN_MUX_5_USBHSDEV_TR_OUT10 = 0x00000561u, /* usbhsdev.u2d_tr_out[10] */ 919 TRIG_IN_MUX_5_USBHSDEV_TR_OUT11 = 0x00000562u, /* usbhsdev.u2d_tr_out[11] */ 920 TRIG_IN_MUX_5_USBHSDEV_TR_OUT12 = 0x00000563u, /* usbhsdev.u2d_tr_out[12] */ 921 TRIG_IN_MUX_5_USBHSDEV_TR_OUT13 = 0x00000564u, /* usbhsdev.u2d_tr_out[13] */ 922 TRIG_IN_MUX_5_USBHSDEV_TR_OUT14 = 0x00000565u, /* usbhsdev.u2d_tr_out[14] */ 923 TRIG_IN_MUX_5_USBHSDEV_TR_OUT15 = 0x00000566u, /* usbhsdev.u2d_tr_out[15] */ 924 TRIG_IN_MUX_5_USBHSDEV_TR_OUT16 = 0x00000567u, /* usbhsdev.u2d_tr_out[16] */ 925 TRIG_IN_MUX_5_USBHSDEV_TR_OUT17 = 0x00000568u, /* usbhsdev.u2d_tr_out[17] */ 926 TRIG_IN_MUX_5_USBHSDEV_TR_OUT18 = 0x00000569u, /* usbhsdev.u2d_tr_out[18] */ 927 TRIG_IN_MUX_5_USBHSDEV_TR_OUT19 = 0x0000056Au, /* usbhsdev.u2d_tr_out[19] */ 928 TRIG_IN_MUX_5_USBHSDEV_TR_OUT20 = 0x0000056Bu, /* usbhsdev.u2d_tr_out[20] */ 929 TRIG_IN_MUX_5_USBHSDEV_TR_OUT21 = 0x0000056Cu, /* usbhsdev.u2d_tr_out[21] */ 930 TRIG_IN_MUX_5_USBHSDEV_TR_OUT22 = 0x0000056Du, /* usbhsdev.u2d_tr_out[22] */ 931 TRIG_IN_MUX_5_USBHSDEV_TR_OUT23 = 0x0000056Eu, /* usbhsdev.u2d_tr_out[23] */ 932 TRIG_IN_MUX_5_USBHSDEV_TR_OUT24 = 0x0000056Fu, /* usbhsdev.u2d_tr_out[24] */ 933 TRIG_IN_MUX_5_USBHSDEV_TR_OUT25 = 0x00000570u, /* usbhsdev.u2d_tr_out[25] */ 934 TRIG_IN_MUX_5_USBHSDEV_TR_OUT26 = 0x00000571u, /* usbhsdev.u2d_tr_out[26] */ 935 TRIG_IN_MUX_5_USBHSDEV_TR_OUT27 = 0x00000572u, /* usbhsdev.u2d_tr_out[27] */ 936 TRIG_IN_MUX_5_USBHSDEV_TR_OUT28 = 0x00000573u, /* usbhsdev.u2d_tr_out[28] */ 937 TRIG_IN_MUX_5_USBHSDEV_TR_OUT29 = 0x00000574u, /* usbhsdev.u2d_tr_out[29] */ 938 TRIG_IN_MUX_5_USBHSDEV_TR_OUT30 = 0x00000575u, /* usbhsdev.u2d_tr_out[30] */ 939 TRIG_IN_MUX_5_USBHSDEV_TR_OUT31 = 0x00000576u, /* usbhsdev.u2d_tr_out[31] */ 940 TRIG_IN_MUX_5_SMIF_TX_REQ = 0x00000577u, /* smif.tr_tx_req */ 941 TRIG_IN_MUX_5_SMIF_RX_REQ = 0x00000578u, /* smif.tr_rx_req */ 942 TRIG_IN_MUX_5_PDM_RX_REQ0 = 0x00000579u, /* pdm[0].tr_rx_req[0] */ 943 TRIG_IN_MUX_5_PDM_RX_REQ1 = 0x0000057Au, /* pdm[0].tr_rx_req[1] */ 944 TRIG_IN_MUX_5_TDM_TX_REQ = 0x0000057Bu, /* tdm[0].tr_tx_req */ 945 TRIG_IN_MUX_5_TDM_RX_REQ = 0x0000057Cu, /* tdm[0].tr_rx_req */ 946 TRIG_IN_MUX_5_SCB0_TX_REQ = 0x0000057Du, /* scb[0].tr_tx_req */ 947 TRIG_IN_MUX_5_SCB0_RX_REQ = 0x0000057Eu, /* scb[0].tr_rx_req */ 948 TRIG_IN_MUX_5_SCB0_SCL_FILTERED = 0x0000057Fu, /* scb[0].tr_i2c_scl_filtered */ 949 TRIG_IN_MUX_5_SCB1_TX_REQ = 0x00000580u, /* scb[1].tr_tx_req */ 950 TRIG_IN_MUX_5_SCB1_RX_REQ = 0x00000581u, /* scb[1].tr_rx_req */ 951 TRIG_IN_MUX_5_SCB1_SCL_FILTERED = 0x00000582u, /* scb[1].tr_i2c_scl_filtered */ 952 TRIG_IN_MUX_5_SCB2_TX_REQ = 0x00000583u, /* scb[2].tr_tx_req */ 953 TRIG_IN_MUX_5_SCB2_RX_REQ = 0x00000584u, /* scb[2].tr_rx_req */ 954 TRIG_IN_MUX_5_SCB2_SCL_FILTERED = 0x00000585u, /* scb[2].tr_i2c_scl_filtered */ 955 TRIG_IN_MUX_5_SCB3_TX_REQ = 0x00000586u, /* scb[3].tr_tx_req */ 956 TRIG_IN_MUX_5_SCB3_RX_REQ = 0x00000587u, /* scb[3].tr_rx_req */ 957 TRIG_IN_MUX_5_SCB3_SCL_FILTERED = 0x00000588u, /* scb[3].tr_i2c_scl_filtered */ 958 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW0 = 0x00000589u, /* tcpwm[0].tr_overflow[0] */ 959 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH0 = 0x0000058Au, /* tcpwm[0].tr_compare_match[0] */ 960 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW0 = 0x0000058Bu, /* tcpwm[0].tr_underflow[0] */ 961 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW1 = 0x0000058Cu, /* tcpwm[0].tr_overflow[1] */ 962 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH1 = 0x0000058Du, /* tcpwm[0].tr_compare_match[1] */ 963 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW1 = 0x0000058Eu, /* tcpwm[0].tr_underflow[1] */ 964 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW2 = 0x0000058Fu, /* tcpwm[0].tr_overflow[2] */ 965 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH2 = 0x00000590u, /* tcpwm[0].tr_compare_match[2] */ 966 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW2 = 0x00000591u, /* tcpwm[0].tr_underflow[2] */ 967 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW3 = 0x00000592u, /* tcpwm[0].tr_overflow[3] */ 968 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH3 = 0x00000593u, /* tcpwm[0].tr_compare_match[3] */ 969 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW3 = 0x00000594u, /* tcpwm[0].tr_underflow[3] */ 970 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW4 = 0x00000595u, /* tcpwm[0].tr_overflow[4] */ 971 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH4 = 0x00000596u, /* tcpwm[0].tr_compare_match[4] */ 972 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW4 = 0x00000597u, /* tcpwm[0].tr_underflow[4] */ 973 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW5 = 0x00000598u, /* tcpwm[0].tr_overflow[5] */ 974 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH5 = 0x00000599u, /* tcpwm[0].tr_compare_match[5] */ 975 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW5 = 0x0000059Au, /* tcpwm[0].tr_underflow[5] */ 976 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW6 = 0x0000059Bu, /* tcpwm[0].tr_overflow[6] */ 977 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH6 = 0x0000059Cu, /* tcpwm[0].tr_compare_match[6] */ 978 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW6 = 0x0000059Du, /* tcpwm[0].tr_underflow[6] */ 979 TRIG_IN_MUX_5_TCPWM_TR_OVERFLOW7 = 0x0000059Eu, /* tcpwm[0].tr_overflow[7] */ 980 TRIG_IN_MUX_5_TCPWM_TR_COMPARE_MATCH7 = 0x0000059Fu, /* tcpwm[0].tr_compare_match[7] */ 981 TRIG_IN_MUX_5_TCPWM_TR_UNDERFLOW7 = 0x000005A0u, /* tcpwm[0].tr_underflow[7] */ 982 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT0 = 0x000005A1u, /* lvds2usb32ss.hbwss_otrig_o[0] */ 983 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT1 = 0x000005A2u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 984 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT2 = 0x000005A3u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 985 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT3 = 0x000005A4u, /* lvds2usb32ss.hbwss_otrig_o[3] */ 986 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT4 = 0x000005A5u, /* lvds2usb32ss.hbwss_otrig_o[4] */ 987 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT5 = 0x000005A6u, /* lvds2usb32ss.hbwss_otrig_o[5] */ 988 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT6 = 0x000005A7u, /* lvds2usb32ss.hbwss_otrig_o[6] */ 989 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT7 = 0x000005A8u, /* lvds2usb32ss.hbwss_otrig_o[7] */ 990 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT8 = 0x000005A9u, /* lvds2usb32ss.hbwss_otrig_o[8] */ 991 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT9 = 0x000005AAu, /* lvds2usb32ss.hbwss_otrig_o[9] */ 992 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT10 = 0x000005ABu, /* lvds2usb32ss.hbwss_otrig_o[10] */ 993 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT11 = 0x000005ACu, /* lvds2usb32ss.hbwss_otrig_o[11] */ 994 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT12 = 0x000005ADu, /* lvds2usb32ss.hbwss_otrig_o[12] */ 995 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT13 = 0x000005AEu, /* lvds2usb32ss.hbwss_otrig_o[13] */ 996 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT14 = 0x000005AFu, /* lvds2usb32ss.hbwss_otrig_o[14] */ 997 TRIG_IN_MUX_5_LVDS2USB32SS_TR_OUT15 = 0x000005B0u, /* lvds2usb32ss.hbwss_otrig_o[15] */ 998 TRIG_IN_MUX_5_SCB4_TX_REQ = 0x000005C1u, /* scb[4].tr_tx_req */ 999 TRIG_IN_MUX_5_SCB4_RX_REQ = 0x000005C2u, /* scb[4].tr_rx_req */ 1000 TRIG_IN_MUX_5_SCB4_SCL_FILTERED = 0x000005C3u, /* scb[4].tr_i2c_scl_filtered */ 1001 TRIG_IN_MUX_5_SCB5_TX_REQ = 0x000005C4u, /* scb[5].tr_tx_req */ 1002 TRIG_IN_MUX_5_SCB5_RX_REQ = 0x000005C5u, /* scb[5].tr_rx_req */ 1003 TRIG_IN_MUX_5_SCB5_SCL_FILTERED = 0x000005C6u, /* scb[5].tr_i2c_scl_filtered */ 1004 TRIG_IN_MUX_5_SCB6_TX_REQ = 0x000005C7u, /* scb[6].tr_tx_req */ 1005 TRIG_IN_MUX_5_SCB6_RX_REQ = 0x000005C8u, /* scb[6].tr_rx_req */ 1006 TRIG_IN_MUX_5_SCB6_SCL_FILTERED = 0x000005C9u, /* scb[6].tr_i2c_scl_filtered */ 1007 TRIG_IN_MUX_5_LVDS2USB32SS_FRM_CNTR_VLD = 0x000005CAu /* lvds2usb32ss.usb32_frm_cntr_vld_o */ 1008 } en_trig_input_mdma_t; 1009 1010 /* Trigger Input Group 6 - PERI Freeze trigger multiplexer */ 1011 typedef enum 1012 { 1013 TRIG_IN_MUX_6_CTI_TR_OUT0 = 0x00000601u, /* cpuss.cti_tr_out[0] */ 1014 TRIG_IN_MUX_6_CTI_TR_OUT1 = 0x00000602u /* cpuss.cti_tr_out[1] */ 1015 } en_trig_input_peri_freeze_t; 1016 1017 /* Trigger Input Group 7 - usb DMA Trigger multiplexer */ 1018 typedef enum 1019 { 1020 TRIG_IN_MUX_7_PDMA0_TR_OUT0 = 0x00000701u, /* cpuss.dw0_tr_out[0] */ 1021 TRIG_IN_MUX_7_PDMA0_TR_OUT1 = 0x00000702u, /* cpuss.dw0_tr_out[1] */ 1022 TRIG_IN_MUX_7_PDMA0_TR_OUT2 = 0x00000703u, /* cpuss.dw0_tr_out[2] */ 1023 TRIG_IN_MUX_7_PDMA0_TR_OUT3 = 0x00000704u, /* cpuss.dw0_tr_out[3] */ 1024 TRIG_IN_MUX_7_PDMA0_TR_OUT4 = 0x00000705u, /* cpuss.dw0_tr_out[4] */ 1025 TRIG_IN_MUX_7_PDMA0_TR_OUT5 = 0x00000706u, /* cpuss.dw0_tr_out[5] */ 1026 TRIG_IN_MUX_7_PDMA0_TR_OUT6 = 0x00000707u, /* cpuss.dw0_tr_out[6] */ 1027 TRIG_IN_MUX_7_PDMA0_TR_OUT7 = 0x00000708u, /* cpuss.dw0_tr_out[7] */ 1028 TRIG_IN_MUX_7_PDMA0_TR_OUT8 = 0x00000709u, /* cpuss.dw0_tr_out[8] */ 1029 TRIG_IN_MUX_7_PDMA0_TR_OUT9 = 0x0000070Au, /* cpuss.dw0_tr_out[9] */ 1030 TRIG_IN_MUX_7_PDMA0_TR_OUT10 = 0x0000070Bu, /* cpuss.dw0_tr_out[10] */ 1031 TRIG_IN_MUX_7_PDMA0_TR_OUT11 = 0x0000070Cu, /* cpuss.dw0_tr_out[11] */ 1032 TRIG_IN_MUX_7_PDMA0_TR_OUT12 = 0x0000070Du, /* cpuss.dw0_tr_out[12] */ 1033 TRIG_IN_MUX_7_PDMA0_TR_OUT13 = 0x0000070Eu, /* cpuss.dw0_tr_out[13] */ 1034 TRIG_IN_MUX_7_PDMA0_TR_OUT14 = 0x0000070Fu, /* cpuss.dw0_tr_out[14] */ 1035 TRIG_IN_MUX_7_PDMA0_TR_OUT15 = 0x00000710u, /* cpuss.dw0_tr_out[15] */ 1036 TRIG_IN_MUX_7_PDMA0_TR_OUT16 = 0x00000711u, /* cpuss.dw0_tr_out[16] */ 1037 TRIG_IN_MUX_7_PDMA0_TR_OUT17 = 0x00000712u, /* cpuss.dw0_tr_out[17] */ 1038 TRIG_IN_MUX_7_PDMA0_TR_OUT18 = 0x00000713u, /* cpuss.dw0_tr_out[18] */ 1039 TRIG_IN_MUX_7_PDMA0_TR_OUT19 = 0x00000714u, /* cpuss.dw0_tr_out[19] */ 1040 TRIG_IN_MUX_7_PDMA0_TR_OUT20 = 0x00000715u, /* cpuss.dw0_tr_out[20] */ 1041 TRIG_IN_MUX_7_PDMA0_TR_OUT21 = 0x00000716u, /* cpuss.dw0_tr_out[21] */ 1042 TRIG_IN_MUX_7_PDMA0_TR_OUT22 = 0x00000717u, /* cpuss.dw0_tr_out[22] */ 1043 TRIG_IN_MUX_7_PDMA0_TR_OUT23 = 0x00000718u, /* cpuss.dw0_tr_out[23] */ 1044 TRIG_IN_MUX_7_PDMA1_TR_OUT0 = 0x00000719u, /* cpuss.dw1_tr_out[0] */ 1045 TRIG_IN_MUX_7_PDMA1_TR_OUT1 = 0x0000071Au, /* cpuss.dw1_tr_out[1] */ 1046 TRIG_IN_MUX_7_PDMA1_TR_OUT2 = 0x0000071Bu, /* cpuss.dw1_tr_out[2] */ 1047 TRIG_IN_MUX_7_PDMA1_TR_OUT3 = 0x0000071Cu, /* cpuss.dw1_tr_out[3] */ 1048 TRIG_IN_MUX_7_PDMA1_TR_OUT4 = 0x0000071Du, /* cpuss.dw1_tr_out[4] */ 1049 TRIG_IN_MUX_7_PDMA1_TR_OUT5 = 0x0000071Eu, /* cpuss.dw1_tr_out[5] */ 1050 TRIG_IN_MUX_7_PDMA1_TR_OUT6 = 0x0000071Fu, /* cpuss.dw1_tr_out[6] */ 1051 TRIG_IN_MUX_7_PDMA1_TR_OUT7 = 0x00000720u, /* cpuss.dw1_tr_out[7] */ 1052 TRIG_IN_MUX_7_PDMA1_TR_OUT8 = 0x00000721u, /* cpuss.dw1_tr_out[8] */ 1053 TRIG_IN_MUX_7_PDMA1_TR_OUT9 = 0x00000722u, /* cpuss.dw1_tr_out[9] */ 1054 TRIG_IN_MUX_7_PDMA1_TR_OUT10 = 0x00000723u, /* cpuss.dw1_tr_out[10] */ 1055 TRIG_IN_MUX_7_PDMA1_TR_OUT11 = 0x00000724u, /* cpuss.dw1_tr_out[11] */ 1056 TRIG_IN_MUX_7_PDMA1_TR_OUT12 = 0x00000725u, /* cpuss.dw1_tr_out[12] */ 1057 TRIG_IN_MUX_7_PDMA1_TR_OUT13 = 0x00000726u, /* cpuss.dw1_tr_out[13] */ 1058 TRIG_IN_MUX_7_PDMA1_TR_OUT14 = 0x00000727u, /* cpuss.dw1_tr_out[14] */ 1059 TRIG_IN_MUX_7_PDMA1_TR_OUT15 = 0x00000728u, /* cpuss.dw1_tr_out[15] */ 1060 TRIG_IN_MUX_7_PDMA1_TR_OUT16 = 0x00000729u, /* cpuss.dw1_tr_out[16] */ 1061 TRIG_IN_MUX_7_PDMA1_TR_OUT17 = 0x0000072Au, /* cpuss.dw1_tr_out[17] */ 1062 TRIG_IN_MUX_7_PDMA1_TR_OUT18 = 0x0000072Bu, /* cpuss.dw1_tr_out[18] */ 1063 TRIG_IN_MUX_7_PDMA1_TR_OUT19 = 0x0000072Cu, /* cpuss.dw1_tr_out[19] */ 1064 TRIG_IN_MUX_7_PDMA1_TR_OUT20 = 0x0000072Du, /* cpuss.dw1_tr_out[20] */ 1065 TRIG_IN_MUX_7_PDMA1_TR_OUT21 = 0x0000072Eu, /* cpuss.dw1_tr_out[21] */ 1066 TRIG_IN_MUX_7_PDMA1_TR_OUT22 = 0x0000072Fu, /* cpuss.dw1_tr_out[22] */ 1067 TRIG_IN_MUX_7_PDMA1_TR_OUT23 = 0x00000730u, /* cpuss.dw1_tr_out[23] */ 1068 TRIG_IN_MUX_7_MDMA_TR_OUT0 = 0x00000731u, /* cpuss.dmac_tr_out[0] */ 1069 TRIG_IN_MUX_7_MDMA_TR_OUT1 = 0x00000732u, /* cpuss.dmac_tr_out[1] */ 1070 TRIG_IN_MUX_7_MDMA_TR_OUT2 = 0x00000733u, /* cpuss.dmac_tr_out[2] */ 1071 TRIG_IN_MUX_7_MDMA_TR_OUT3 = 0x00000734u, /* cpuss.dmac_tr_out[3] */ 1072 TRIG_IN_MUX_7_MDMA_TR_OUT4 = 0x00000735u, /* cpuss.dmac_tr_out[4] */ 1073 TRIG_IN_MUX_7_MDMA_TR_OUT5 = 0x00000736u, /* cpuss.dmac_tr_out[5] */ 1074 TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000737u, /* cpuss.cti_tr_out[0] */ 1075 TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000738u /* cpuss.cti_tr_out[1] */ 1076 } en_trig_input_usb_tr_in_t; 1077 1078 /* Trigger Input Group 8 - USBHSDEV DMA Trigger multiplexer */ 1079 typedef enum 1080 { 1081 TRIG_IN_MUX_8_PDMA0_TR_OUT0 = 0x00000801u, /* cpuss.dw0_tr_out[0] */ 1082 TRIG_IN_MUX_8_PDMA0_TR_OUT1 = 0x00000802u, /* cpuss.dw0_tr_out[1] */ 1083 TRIG_IN_MUX_8_PDMA0_TR_OUT2 = 0x00000803u, /* cpuss.dw0_tr_out[2] */ 1084 TRIG_IN_MUX_8_PDMA0_TR_OUT3 = 0x00000804u, /* cpuss.dw0_tr_out[3] */ 1085 TRIG_IN_MUX_8_PDMA0_TR_OUT4 = 0x00000805u, /* cpuss.dw0_tr_out[4] */ 1086 TRIG_IN_MUX_8_PDMA0_TR_OUT5 = 0x00000806u, /* cpuss.dw0_tr_out[5] */ 1087 TRIG_IN_MUX_8_PDMA0_TR_OUT6 = 0x00000807u, /* cpuss.dw0_tr_out[6] */ 1088 TRIG_IN_MUX_8_PDMA0_TR_OUT7 = 0x00000808u, /* cpuss.dw0_tr_out[7] */ 1089 TRIG_IN_MUX_8_PDMA0_TR_OUT8 = 0x00000809u, /* cpuss.dw0_tr_out[8] */ 1090 TRIG_IN_MUX_8_PDMA0_TR_OUT9 = 0x0000080Au, /* cpuss.dw0_tr_out[9] */ 1091 TRIG_IN_MUX_8_PDMA0_TR_OUT10 = 0x0000080Bu, /* cpuss.dw0_tr_out[10] */ 1092 TRIG_IN_MUX_8_PDMA0_TR_OUT11 = 0x0000080Cu, /* cpuss.dw0_tr_out[11] */ 1093 TRIG_IN_MUX_8_PDMA0_TR_OUT12 = 0x0000080Du, /* cpuss.dw0_tr_out[12] */ 1094 TRIG_IN_MUX_8_PDMA0_TR_OUT13 = 0x0000080Eu, /* cpuss.dw0_tr_out[13] */ 1095 TRIG_IN_MUX_8_PDMA0_TR_OUT14 = 0x0000080Fu, /* cpuss.dw0_tr_out[14] */ 1096 TRIG_IN_MUX_8_PDMA0_TR_OUT15 = 0x00000810u, /* cpuss.dw0_tr_out[15] */ 1097 TRIG_IN_MUX_8_PDMA0_TR_OUT16 = 0x00000811u, /* cpuss.dw0_tr_out[16] */ 1098 TRIG_IN_MUX_8_PDMA0_TR_OUT17 = 0x00000812u, /* cpuss.dw0_tr_out[17] */ 1099 TRIG_IN_MUX_8_PDMA0_TR_OUT18 = 0x00000813u, /* cpuss.dw0_tr_out[18] */ 1100 TRIG_IN_MUX_8_PDMA0_TR_OUT19 = 0x00000814u, /* cpuss.dw0_tr_out[19] */ 1101 TRIG_IN_MUX_8_PDMA0_TR_OUT20 = 0x00000815u, /* cpuss.dw0_tr_out[20] */ 1102 TRIG_IN_MUX_8_PDMA0_TR_OUT21 = 0x00000816u, /* cpuss.dw0_tr_out[21] */ 1103 TRIG_IN_MUX_8_PDMA0_TR_OUT22 = 0x00000817u, /* cpuss.dw0_tr_out[22] */ 1104 TRIG_IN_MUX_8_PDMA0_TR_OUT23 = 0x00000818u, /* cpuss.dw0_tr_out[23] */ 1105 TRIG_IN_MUX_8_PDMA1_TR_OUT0 = 0x00000819u, /* cpuss.dw1_tr_out[0] */ 1106 TRIG_IN_MUX_8_PDMA1_TR_OUT1 = 0x0000081Au, /* cpuss.dw1_tr_out[1] */ 1107 TRIG_IN_MUX_8_PDMA1_TR_OUT2 = 0x0000081Bu, /* cpuss.dw1_tr_out[2] */ 1108 TRIG_IN_MUX_8_PDMA1_TR_OUT3 = 0x0000081Cu, /* cpuss.dw1_tr_out[3] */ 1109 TRIG_IN_MUX_8_PDMA1_TR_OUT4 = 0x0000081Du, /* cpuss.dw1_tr_out[4] */ 1110 TRIG_IN_MUX_8_PDMA1_TR_OUT5 = 0x0000081Eu, /* cpuss.dw1_tr_out[5] */ 1111 TRIG_IN_MUX_8_PDMA1_TR_OUT6 = 0x0000081Fu, /* cpuss.dw1_tr_out[6] */ 1112 TRIG_IN_MUX_8_PDMA1_TR_OUT7 = 0x00000820u, /* cpuss.dw1_tr_out[7] */ 1113 TRIG_IN_MUX_8_PDMA1_TR_OUT8 = 0x00000821u, /* cpuss.dw1_tr_out[8] */ 1114 TRIG_IN_MUX_8_PDMA1_TR_OUT9 = 0x00000822u, /* cpuss.dw1_tr_out[9] */ 1115 TRIG_IN_MUX_8_PDMA1_TR_OUT10 = 0x00000823u, /* cpuss.dw1_tr_out[10] */ 1116 TRIG_IN_MUX_8_PDMA1_TR_OUT11 = 0x00000824u, /* cpuss.dw1_tr_out[11] */ 1117 TRIG_IN_MUX_8_PDMA1_TR_OUT12 = 0x00000825u, /* cpuss.dw1_tr_out[12] */ 1118 TRIG_IN_MUX_8_PDMA1_TR_OUT13 = 0x00000826u, /* cpuss.dw1_tr_out[13] */ 1119 TRIG_IN_MUX_8_PDMA1_TR_OUT14 = 0x00000827u, /* cpuss.dw1_tr_out[14] */ 1120 TRIG_IN_MUX_8_PDMA1_TR_OUT15 = 0x00000828u, /* cpuss.dw1_tr_out[15] */ 1121 TRIG_IN_MUX_8_PDMA1_TR_OUT16 = 0x00000829u, /* cpuss.dw1_tr_out[16] */ 1122 TRIG_IN_MUX_8_PDMA1_TR_OUT17 = 0x0000082Au, /* cpuss.dw1_tr_out[17] */ 1123 TRIG_IN_MUX_8_PDMA1_TR_OUT18 = 0x0000082Bu, /* cpuss.dw1_tr_out[18] */ 1124 TRIG_IN_MUX_8_PDMA1_TR_OUT19 = 0x0000082Cu, /* cpuss.dw1_tr_out[19] */ 1125 TRIG_IN_MUX_8_PDMA1_TR_OUT20 = 0x0000082Du, /* cpuss.dw1_tr_out[20] */ 1126 TRIG_IN_MUX_8_PDMA1_TR_OUT21 = 0x0000082Eu, /* cpuss.dw1_tr_out[21] */ 1127 TRIG_IN_MUX_8_PDMA1_TR_OUT22 = 0x0000082Fu, /* cpuss.dw1_tr_out[22] */ 1128 TRIG_IN_MUX_8_PDMA1_TR_OUT23 = 0x00000830u, /* cpuss.dw1_tr_out[23] */ 1129 TRIG_IN_MUX_8_MDMA_TR_OUT0 = 0x00000831u, /* cpuss.dmac_tr_out[0] */ 1130 TRIG_IN_MUX_8_MDMA_TR_OUT1 = 0x00000832u, /* cpuss.dmac_tr_out[1] */ 1131 TRIG_IN_MUX_8_MDMA_TR_OUT2 = 0x00000833u, /* cpuss.dmac_tr_out[2] */ 1132 TRIG_IN_MUX_8_MDMA_TR_OUT3 = 0x00000834u, /* cpuss.dmac_tr_out[3] */ 1133 TRIG_IN_MUX_8_MDMA_TR_OUT4 = 0x00000835u, /* cpuss.dmac_tr_out[4] */ 1134 TRIG_IN_MUX_8_MDMA_TR_OUT5 = 0x00000836u, /* cpuss.dmac_tr_out[5] */ 1135 TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x00000837u, /* peri.tr_io_input[0] */ 1136 TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x00000838u, /* peri.tr_io_input[1] */ 1137 TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x00000839u, /* peri.tr_io_input[2] */ 1138 TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x0000083Au, /* peri.tr_io_input[3] */ 1139 TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x0000083Bu, /* peri.tr_io_input[4] */ 1140 TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x0000083Cu, /* peri.tr_io_input[5] */ 1141 TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x0000083Du, /* peri.tr_io_input[6] */ 1142 TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x0000083Eu, /* peri.tr_io_input[7] */ 1143 TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x0000083Fu, /* peri.tr_io_input[8] */ 1144 TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000840u, /* peri.tr_io_input[9] */ 1145 TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000841u, /* peri.tr_io_input[10] */ 1146 TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000842u, /* peri.tr_io_input[11] */ 1147 TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000843u, /* peri.tr_io_input[12] */ 1148 TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x00000844u, /* peri.tr_io_input[13] */ 1149 TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x00000845u, /* peri.tr_io_input[14] */ 1150 TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x00000846u, /* peri.tr_io_input[15] */ 1151 TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x00000847u, /* peri.tr_io_input[16] */ 1152 TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x00000848u, /* peri.tr_io_input[17] */ 1153 TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x00000849u, /* peri.tr_io_input[18] */ 1154 TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x0000084Au, /* peri.tr_io_input[19] */ 1155 TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x0000084Bu, /* peri.tr_io_input[20] */ 1156 TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x0000084Cu, /* peri.tr_io_input[21] */ 1157 TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x0000084Du, /* peri.tr_io_input[22] */ 1158 TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x0000084Eu, /* peri.tr_io_input[23] */ 1159 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW0 = 0x0000084Fu, /* tcpwm[0].tr_overflow[0] */ 1160 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH0 = 0x00000850u, /* tcpwm[0].tr_compare_match[0] */ 1161 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW0 = 0x00000851u, /* tcpwm[0].tr_underflow[0] */ 1162 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW1 = 0x00000852u, /* tcpwm[0].tr_overflow[1] */ 1163 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH1 = 0x00000853u, /* tcpwm[0].tr_compare_match[1] */ 1164 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW1 = 0x00000854u, /* tcpwm[0].tr_underflow[1] */ 1165 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW2 = 0x00000855u, /* tcpwm[0].tr_overflow[2] */ 1166 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH2 = 0x00000856u, /* tcpwm[0].tr_compare_match[2] */ 1167 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW2 = 0x00000857u, /* tcpwm[0].tr_underflow[2] */ 1168 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW3 = 0x00000858u, /* tcpwm[0].tr_overflow[3] */ 1169 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH3 = 0x00000859u, /* tcpwm[0].tr_compare_match[3] */ 1170 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW3 = 0x0000085Au, /* tcpwm[0].tr_underflow[3] */ 1171 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW4 = 0x0000085Bu, /* tcpwm[0].tr_overflow[4] */ 1172 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH4 = 0x0000085Cu, /* tcpwm[0].tr_compare_match[4] */ 1173 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW4 = 0x0000085Du, /* tcpwm[0].tr_underflow[4] */ 1174 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW5 = 0x0000085Eu, /* tcpwm[0].tr_overflow[5] */ 1175 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH5 = 0x0000085Fu, /* tcpwm[0].tr_compare_match[5] */ 1176 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW5 = 0x00000860u, /* tcpwm[0].tr_underflow[5] */ 1177 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW6 = 0x00000861u, /* tcpwm[0].tr_overflow[6] */ 1178 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH6 = 0x00000862u, /* tcpwm[0].tr_compare_match[6] */ 1179 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW6 = 0x00000863u, /* tcpwm[0].tr_underflow[6] */ 1180 TRIG_IN_MUX_8_TCPWM_TR_OVERFLOW7 = 0x00000864u, /* tcpwm[0].tr_overflow[7] */ 1181 TRIG_IN_MUX_8_TCPWM_TR_COMPARE_MATCH7 = 0x00000865u, /* tcpwm[0].tr_compare_match[7] */ 1182 TRIG_IN_MUX_8_TCPWM_TR_UNDERFLOW7 = 0x00000866u, /* tcpwm[0].tr_underflow[7] */ 1183 TRIG_IN_MUX_8_USBHSDEV_TR_OUT0 = 0x00000867u, /* usbhsdev.u2d_tr_out[0] */ 1184 TRIG_IN_MUX_8_USBHSDEV_TR_OUT1 = 0x00000868u, /* usbhsdev.u2d_tr_out[1] */ 1185 TRIG_IN_MUX_8_USBHSDEV_TR_OUT2 = 0x00000869u, /* usbhsdev.u2d_tr_out[2] */ 1186 TRIG_IN_MUX_8_USBHSDEV_TR_OUT3 = 0x0000086Au, /* usbhsdev.u2d_tr_out[3] */ 1187 TRIG_IN_MUX_8_USBHSDEV_TR_OUT4 = 0x0000086Bu, /* usbhsdev.u2d_tr_out[4] */ 1188 TRIG_IN_MUX_8_USBHSDEV_TR_OUT5 = 0x0000086Cu, /* usbhsdev.u2d_tr_out[5] */ 1189 TRIG_IN_MUX_8_USBHSDEV_TR_OUT6 = 0x0000086Du, /* usbhsdev.u2d_tr_out[6] */ 1190 TRIG_IN_MUX_8_USBHSDEV_TR_OUT7 = 0x0000086Eu, /* usbhsdev.u2d_tr_out[7] */ 1191 TRIG_IN_MUX_8_USBHSDEV_TR_OUT8 = 0x0000086Fu, /* usbhsdev.u2d_tr_out[8] */ 1192 TRIG_IN_MUX_8_USBHSDEV_TR_OUT9 = 0x00000870u, /* usbhsdev.u2d_tr_out[9] */ 1193 TRIG_IN_MUX_8_USBHSDEV_TR_OUT10 = 0x00000871u, /* usbhsdev.u2d_tr_out[10] */ 1194 TRIG_IN_MUX_8_USBHSDEV_TR_OUT11 = 0x00000872u, /* usbhsdev.u2d_tr_out[11] */ 1195 TRIG_IN_MUX_8_USBHSDEV_TR_OUT12 = 0x00000873u, /* usbhsdev.u2d_tr_out[12] */ 1196 TRIG_IN_MUX_8_USBHSDEV_TR_OUT13 = 0x00000874u, /* usbhsdev.u2d_tr_out[13] */ 1197 TRIG_IN_MUX_8_USBHSDEV_TR_OUT14 = 0x00000875u, /* usbhsdev.u2d_tr_out[14] */ 1198 TRIG_IN_MUX_8_USBHSDEV_TR_OUT15 = 0x00000876u, /* usbhsdev.u2d_tr_out[15] */ 1199 TRIG_IN_MUX_8_USBHSDEV_TR_OUT16 = 0x00000877u, /* usbhsdev.u2d_tr_out[16] */ 1200 TRIG_IN_MUX_8_USBHSDEV_TR_OUT17 = 0x00000878u, /* usbhsdev.u2d_tr_out[17] */ 1201 TRIG_IN_MUX_8_USBHSDEV_TR_OUT18 = 0x00000879u, /* usbhsdev.u2d_tr_out[18] */ 1202 TRIG_IN_MUX_8_USBHSDEV_TR_OUT19 = 0x0000087Au, /* usbhsdev.u2d_tr_out[19] */ 1203 TRIG_IN_MUX_8_USBHSDEV_TR_OUT20 = 0x0000087Bu, /* usbhsdev.u2d_tr_out[20] */ 1204 TRIG_IN_MUX_8_USBHSDEV_TR_OUT21 = 0x0000087Cu, /* usbhsdev.u2d_tr_out[21] */ 1205 TRIG_IN_MUX_8_USBHSDEV_TR_OUT22 = 0x0000087Du, /* usbhsdev.u2d_tr_out[22] */ 1206 TRIG_IN_MUX_8_USBHSDEV_TR_OUT23 = 0x0000087Eu, /* usbhsdev.u2d_tr_out[23] */ 1207 TRIG_IN_MUX_8_USBHSDEV_TR_OUT24 = 0x0000087Fu, /* usbhsdev.u2d_tr_out[24] */ 1208 TRIG_IN_MUX_8_USBHSDEV_TR_OUT25 = 0x00000880u, /* usbhsdev.u2d_tr_out[25] */ 1209 TRIG_IN_MUX_8_USBHSDEV_TR_OUT26 = 0x00000881u, /* usbhsdev.u2d_tr_out[26] */ 1210 TRIG_IN_MUX_8_USBHSDEV_TR_OUT27 = 0x00000882u, /* usbhsdev.u2d_tr_out[27] */ 1211 TRIG_IN_MUX_8_USBHSDEV_TR_OUT28 = 0x00000883u, /* usbhsdev.u2d_tr_out[28] */ 1212 TRIG_IN_MUX_8_USBHSDEV_TR_OUT29 = 0x00000884u, /* usbhsdev.u2d_tr_out[29] */ 1213 TRIG_IN_MUX_8_USBHSDEV_TR_OUT30 = 0x00000885u, /* usbhsdev.u2d_tr_out[30] */ 1214 TRIG_IN_MUX_8_USBHSDEV_TR_OUT31 = 0x00000886u, /* usbhsdev.u2d_tr_out[31] */ 1215 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT0 = 0x00000887u, /* lvds2usb32ss.hbwss_otrig_o[0] */ 1216 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT1 = 0x00000888u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 1217 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT2 = 0x00000889u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 1218 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT3 = 0x0000088Au, /* lvds2usb32ss.hbwss_otrig_o[3] */ 1219 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT4 = 0x0000088Bu, /* lvds2usb32ss.hbwss_otrig_o[4] */ 1220 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT5 = 0x0000088Cu, /* lvds2usb32ss.hbwss_otrig_o[5] */ 1221 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT6 = 0x0000088Du, /* lvds2usb32ss.hbwss_otrig_o[6] */ 1222 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT7 = 0x0000088Eu, /* lvds2usb32ss.hbwss_otrig_o[7] */ 1223 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT8 = 0x0000088Fu, /* lvds2usb32ss.hbwss_otrig_o[8] */ 1224 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT9 = 0x00000890u, /* lvds2usb32ss.hbwss_otrig_o[9] */ 1225 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT10 = 0x00000891u, /* lvds2usb32ss.hbwss_otrig_o[10] */ 1226 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT11 = 0x00000892u, /* lvds2usb32ss.hbwss_otrig_o[11] */ 1227 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT12 = 0x00000893u, /* lvds2usb32ss.hbwss_otrig_o[12] */ 1228 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT13 = 0x00000894u, /* lvds2usb32ss.hbwss_otrig_o[13] */ 1229 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT14 = 0x00000895u, /* lvds2usb32ss.hbwss_otrig_o[14] */ 1230 TRIG_IN_MUX_8_LVDS2USB32SS_TR_OUT15 = 0x00000896u /* lvds2usb32ss.hbwss_otrig_o[15] */ 1231 } en_trig_input_usbhsdev_tr_in_t; 1232 1233 /* Trigger Input Group 9 - LVDS2USB32SS DMA Trigger multiplexer */ 1234 typedef enum 1235 { 1236 TRIG_IN_MUX_9_PDMA0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */ 1237 TRIG_IN_MUX_9_PDMA0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */ 1238 TRIG_IN_MUX_9_PDMA0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */ 1239 TRIG_IN_MUX_9_PDMA0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */ 1240 TRIG_IN_MUX_9_PDMA0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */ 1241 TRIG_IN_MUX_9_PDMA0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */ 1242 TRIG_IN_MUX_9_PDMA0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */ 1243 TRIG_IN_MUX_9_PDMA0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */ 1244 TRIG_IN_MUX_9_PDMA0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */ 1245 TRIG_IN_MUX_9_PDMA0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */ 1246 TRIG_IN_MUX_9_PDMA0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */ 1247 TRIG_IN_MUX_9_PDMA0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */ 1248 TRIG_IN_MUX_9_PDMA0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */ 1249 TRIG_IN_MUX_9_PDMA0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */ 1250 TRIG_IN_MUX_9_PDMA0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */ 1251 TRIG_IN_MUX_9_PDMA0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */ 1252 TRIG_IN_MUX_9_PDMA0_TR_OUT16 = 0x00000911u, /* cpuss.dw0_tr_out[16] */ 1253 TRIG_IN_MUX_9_PDMA0_TR_OUT17 = 0x00000912u, /* cpuss.dw0_tr_out[17] */ 1254 TRIG_IN_MUX_9_PDMA0_TR_OUT18 = 0x00000913u, /* cpuss.dw0_tr_out[18] */ 1255 TRIG_IN_MUX_9_PDMA0_TR_OUT19 = 0x00000914u, /* cpuss.dw0_tr_out[19] */ 1256 TRIG_IN_MUX_9_PDMA0_TR_OUT20 = 0x00000915u, /* cpuss.dw0_tr_out[20] */ 1257 TRIG_IN_MUX_9_PDMA0_TR_OUT21 = 0x00000916u, /* cpuss.dw0_tr_out[21] */ 1258 TRIG_IN_MUX_9_PDMA0_TR_OUT22 = 0x00000917u, /* cpuss.dw0_tr_out[22] */ 1259 TRIG_IN_MUX_9_PDMA0_TR_OUT23 = 0x00000918u, /* cpuss.dw0_tr_out[23] */ 1260 TRIG_IN_MUX_9_PDMA1_TR_OUT0 = 0x00000919u, /* cpuss.dw1_tr_out[0] */ 1261 TRIG_IN_MUX_9_PDMA1_TR_OUT1 = 0x0000091Au, /* cpuss.dw1_tr_out[1] */ 1262 TRIG_IN_MUX_9_PDMA1_TR_OUT2 = 0x0000091Bu, /* cpuss.dw1_tr_out[2] */ 1263 TRIG_IN_MUX_9_PDMA1_TR_OUT3 = 0x0000091Cu, /* cpuss.dw1_tr_out[3] */ 1264 TRIG_IN_MUX_9_PDMA1_TR_OUT4 = 0x0000091Du, /* cpuss.dw1_tr_out[4] */ 1265 TRIG_IN_MUX_9_PDMA1_TR_OUT5 = 0x0000091Eu, /* cpuss.dw1_tr_out[5] */ 1266 TRIG_IN_MUX_9_PDMA1_TR_OUT6 = 0x0000091Fu, /* cpuss.dw1_tr_out[6] */ 1267 TRIG_IN_MUX_9_PDMA1_TR_OUT7 = 0x00000920u, /* cpuss.dw1_tr_out[7] */ 1268 TRIG_IN_MUX_9_PDMA1_TR_OUT8 = 0x00000921u, /* cpuss.dw1_tr_out[8] */ 1269 TRIG_IN_MUX_9_PDMA1_TR_OUT9 = 0x00000922u, /* cpuss.dw1_tr_out[9] */ 1270 TRIG_IN_MUX_9_PDMA1_TR_OUT10 = 0x00000923u, /* cpuss.dw1_tr_out[10] */ 1271 TRIG_IN_MUX_9_PDMA1_TR_OUT11 = 0x00000924u, /* cpuss.dw1_tr_out[11] */ 1272 TRIG_IN_MUX_9_PDMA1_TR_OUT12 = 0x00000925u, /* cpuss.dw1_tr_out[12] */ 1273 TRIG_IN_MUX_9_PDMA1_TR_OUT13 = 0x00000926u, /* cpuss.dw1_tr_out[13] */ 1274 TRIG_IN_MUX_9_PDMA1_TR_OUT14 = 0x00000927u, /* cpuss.dw1_tr_out[14] */ 1275 TRIG_IN_MUX_9_PDMA1_TR_OUT15 = 0x00000928u, /* cpuss.dw1_tr_out[15] */ 1276 TRIG_IN_MUX_9_PDMA1_TR_OUT16 = 0x00000929u, /* cpuss.dw1_tr_out[16] */ 1277 TRIG_IN_MUX_9_PDMA1_TR_OUT17 = 0x0000092Au, /* cpuss.dw1_tr_out[17] */ 1278 TRIG_IN_MUX_9_PDMA1_TR_OUT18 = 0x0000092Bu, /* cpuss.dw1_tr_out[18] */ 1279 TRIG_IN_MUX_9_PDMA1_TR_OUT19 = 0x0000092Cu, /* cpuss.dw1_tr_out[19] */ 1280 TRIG_IN_MUX_9_PDMA1_TR_OUT20 = 0x0000092Du, /* cpuss.dw1_tr_out[20] */ 1281 TRIG_IN_MUX_9_PDMA1_TR_OUT21 = 0x0000092Eu, /* cpuss.dw1_tr_out[21] */ 1282 TRIG_IN_MUX_9_PDMA1_TR_OUT22 = 0x0000092Fu, /* cpuss.dw1_tr_out[22] */ 1283 TRIG_IN_MUX_9_PDMA1_TR_OUT23 = 0x00000930u, /* cpuss.dw1_tr_out[23] */ 1284 TRIG_IN_MUX_9_MDMA_TR_OUT0 = 0x00000931u, /* cpuss.dmac_tr_out[0] */ 1285 TRIG_IN_MUX_9_MDMA_TR_OUT1 = 0x00000932u, /* cpuss.dmac_tr_out[1] */ 1286 TRIG_IN_MUX_9_MDMA_TR_OUT2 = 0x00000933u, /* cpuss.dmac_tr_out[2] */ 1287 TRIG_IN_MUX_9_MDMA_TR_OUT3 = 0x00000934u, /* cpuss.dmac_tr_out[3] */ 1288 TRIG_IN_MUX_9_MDMA_TR_OUT4 = 0x00000935u, /* cpuss.dmac_tr_out[4] */ 1289 TRIG_IN_MUX_9_MDMA_TR_OUT5 = 0x00000936u, /* cpuss.dmac_tr_out[5] */ 1290 TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000937u, /* peri.tr_io_input[0] */ 1291 TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000938u, /* peri.tr_io_input[1] */ 1292 TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000939u, /* peri.tr_io_input[2] */ 1293 TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x0000093Au, /* peri.tr_io_input[3] */ 1294 TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x0000093Bu, /* peri.tr_io_input[4] */ 1295 TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x0000093Cu, /* peri.tr_io_input[5] */ 1296 TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x0000093Du, /* peri.tr_io_input[6] */ 1297 TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x0000093Eu, /* peri.tr_io_input[7] */ 1298 TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x0000093Fu, /* peri.tr_io_input[8] */ 1299 TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x00000940u, /* peri.tr_io_input[9] */ 1300 TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x00000941u, /* peri.tr_io_input[10] */ 1301 TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x00000942u, /* peri.tr_io_input[11] */ 1302 TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x00000943u, /* peri.tr_io_input[12] */ 1303 TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x00000944u, /* peri.tr_io_input[13] */ 1304 TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x00000945u, /* peri.tr_io_input[14] */ 1305 TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000946u, /* peri.tr_io_input[15] */ 1306 TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000947u, /* peri.tr_io_input[16] */ 1307 TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000948u, /* peri.tr_io_input[17] */ 1308 TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000949u, /* peri.tr_io_input[18] */ 1309 TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x0000094Au, /* peri.tr_io_input[19] */ 1310 TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x0000094Bu, /* peri.tr_io_input[20] */ 1311 TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x0000094Cu, /* peri.tr_io_input[21] */ 1312 TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x0000094Du, /* peri.tr_io_input[22] */ 1313 TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x0000094Eu, /* peri.tr_io_input[23] */ 1314 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW0 = 0x0000094Fu, /* tcpwm[0].tr_overflow[0] */ 1315 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH0 = 0x00000950u, /* tcpwm[0].tr_compare_match[0] */ 1316 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW0 = 0x00000951u, /* tcpwm[0].tr_underflow[0] */ 1317 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW1 = 0x00000952u, /* tcpwm[0].tr_overflow[1] */ 1318 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH1 = 0x00000953u, /* tcpwm[0].tr_compare_match[1] */ 1319 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW1 = 0x00000954u, /* tcpwm[0].tr_underflow[1] */ 1320 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW2 = 0x00000955u, /* tcpwm[0].tr_overflow[2] */ 1321 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH2 = 0x00000956u, /* tcpwm[0].tr_compare_match[2] */ 1322 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW2 = 0x00000957u, /* tcpwm[0].tr_underflow[2] */ 1323 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW3 = 0x00000958u, /* tcpwm[0].tr_overflow[3] */ 1324 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH3 = 0x00000959u, /* tcpwm[0].tr_compare_match[3] */ 1325 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW3 = 0x0000095Au, /* tcpwm[0].tr_underflow[3] */ 1326 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW4 = 0x0000095Bu, /* tcpwm[0].tr_overflow[4] */ 1327 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH4 = 0x0000095Cu, /* tcpwm[0].tr_compare_match[4] */ 1328 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW4 = 0x0000095Du, /* tcpwm[0].tr_underflow[4] */ 1329 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW5 = 0x0000095Eu, /* tcpwm[0].tr_overflow[5] */ 1330 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH5 = 0x0000095Fu, /* tcpwm[0].tr_compare_match[5] */ 1331 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW5 = 0x00000960u, /* tcpwm[0].tr_underflow[5] */ 1332 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW6 = 0x00000961u, /* tcpwm[0].tr_overflow[6] */ 1333 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH6 = 0x00000962u, /* tcpwm[0].tr_compare_match[6] */ 1334 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW6 = 0x00000963u, /* tcpwm[0].tr_underflow[6] */ 1335 TRIG_IN_MUX_9_TCPWM_TR_OVERFLOW7 = 0x00000964u, /* tcpwm[0].tr_overflow[7] */ 1336 TRIG_IN_MUX_9_TCPWM_TR_COMPARE_MATCH7 = 0x00000965u, /* tcpwm[0].tr_compare_match[7] */ 1337 TRIG_IN_MUX_9_TCPWM_TR_UNDERFLOW7 = 0x00000966u, /* tcpwm[0].tr_underflow[7] */ 1338 TRIG_IN_MUX_9_USBHSDEV_TR_OUT0 = 0x00000967u, /* usbhsdev.u2d_tr_out[0] */ 1339 TRIG_IN_MUX_9_USBHSDEV_TR_OUT1 = 0x00000968u, /* usbhsdev.u2d_tr_out[1] */ 1340 TRIG_IN_MUX_9_USBHSDEV_TR_OUT2 = 0x00000969u, /* usbhsdev.u2d_tr_out[2] */ 1341 TRIG_IN_MUX_9_USBHSDEV_TR_OUT3 = 0x0000096Au, /* usbhsdev.u2d_tr_out[3] */ 1342 TRIG_IN_MUX_9_USBHSDEV_TR_OUT4 = 0x0000096Bu, /* usbhsdev.u2d_tr_out[4] */ 1343 TRIG_IN_MUX_9_USBHSDEV_TR_OUT5 = 0x0000096Cu, /* usbhsdev.u2d_tr_out[5] */ 1344 TRIG_IN_MUX_9_USBHSDEV_TR_OUT6 = 0x0000096Du, /* usbhsdev.u2d_tr_out[6] */ 1345 TRIG_IN_MUX_9_USBHSDEV_TR_OUT7 = 0x0000096Eu, /* usbhsdev.u2d_tr_out[7] */ 1346 TRIG_IN_MUX_9_USBHSDEV_TR_OUT8 = 0x0000096Fu, /* usbhsdev.u2d_tr_out[8] */ 1347 TRIG_IN_MUX_9_USBHSDEV_TR_OUT9 = 0x00000970u, /* usbhsdev.u2d_tr_out[9] */ 1348 TRIG_IN_MUX_9_USBHSDEV_TR_OUT10 = 0x00000971u, /* usbhsdev.u2d_tr_out[10] */ 1349 TRIG_IN_MUX_9_USBHSDEV_TR_OUT11 = 0x00000972u, /* usbhsdev.u2d_tr_out[11] */ 1350 TRIG_IN_MUX_9_USBHSDEV_TR_OUT12 = 0x00000973u, /* usbhsdev.u2d_tr_out[12] */ 1351 TRIG_IN_MUX_9_USBHSDEV_TR_OUT13 = 0x00000974u, /* usbhsdev.u2d_tr_out[13] */ 1352 TRIG_IN_MUX_9_USBHSDEV_TR_OUT14 = 0x00000975u, /* usbhsdev.u2d_tr_out[14] */ 1353 TRIG_IN_MUX_9_USBHSDEV_TR_OUT15 = 0x00000976u, /* usbhsdev.u2d_tr_out[15] */ 1354 TRIG_IN_MUX_9_USBHSDEV_TR_OUT16 = 0x00000977u, /* usbhsdev.u2d_tr_out[16] */ 1355 TRIG_IN_MUX_9_USBHSDEV_TR_OUT17 = 0x00000978u, /* usbhsdev.u2d_tr_out[17] */ 1356 TRIG_IN_MUX_9_USBHSDEV_TR_OUT18 = 0x00000979u, /* usbhsdev.u2d_tr_out[18] */ 1357 TRIG_IN_MUX_9_USBHSDEV_TR_OUT19 = 0x0000097Au, /* usbhsdev.u2d_tr_out[19] */ 1358 TRIG_IN_MUX_9_USBHSDEV_TR_OUT20 = 0x0000097Bu, /* usbhsdev.u2d_tr_out[20] */ 1359 TRIG_IN_MUX_9_USBHSDEV_TR_OUT21 = 0x0000097Cu, /* usbhsdev.u2d_tr_out[21] */ 1360 TRIG_IN_MUX_9_USBHSDEV_TR_OUT22 = 0x0000097Du, /* usbhsdev.u2d_tr_out[22] */ 1361 TRIG_IN_MUX_9_USBHSDEV_TR_OUT23 = 0x0000097Eu, /* usbhsdev.u2d_tr_out[23] */ 1362 TRIG_IN_MUX_9_USBHSDEV_TR_OUT24 = 0x0000097Fu, /* usbhsdev.u2d_tr_out[24] */ 1363 TRIG_IN_MUX_9_USBHSDEV_TR_OUT25 = 0x00000980u, /* usbhsdev.u2d_tr_out[25] */ 1364 TRIG_IN_MUX_9_USBHSDEV_TR_OUT26 = 0x00000981u, /* usbhsdev.u2d_tr_out[26] */ 1365 TRIG_IN_MUX_9_USBHSDEV_TR_OUT27 = 0x00000982u, /* usbhsdev.u2d_tr_out[27] */ 1366 TRIG_IN_MUX_9_USBHSDEV_TR_OUT28 = 0x00000983u, /* usbhsdev.u2d_tr_out[28] */ 1367 TRIG_IN_MUX_9_USBHSDEV_TR_OUT29 = 0x00000984u, /* usbhsdev.u2d_tr_out[29] */ 1368 TRIG_IN_MUX_9_USBHSDEV_TR_OUT30 = 0x00000985u, /* usbhsdev.u2d_tr_out[30] */ 1369 TRIG_IN_MUX_9_USBHSDEV_TR_OUT31 = 0x00000986u, /* usbhsdev.u2d_tr_out[31] */ 1370 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT0 = 0x00000987u, /* lvds2usb32ss.hbwss_otrig_o[0] */ 1371 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT1 = 0x00000988u, /* lvds2usb32ss.hbwss_otrig_o[1] */ 1372 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT2 = 0x00000989u, /* lvds2usb32ss.hbwss_otrig_o[2] */ 1373 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT3 = 0x0000098Au, /* lvds2usb32ss.hbwss_otrig_o[3] */ 1374 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT4 = 0x0000098Bu, /* lvds2usb32ss.hbwss_otrig_o[4] */ 1375 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT5 = 0x0000098Cu, /* lvds2usb32ss.hbwss_otrig_o[5] */ 1376 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT6 = 0x0000098Du, /* lvds2usb32ss.hbwss_otrig_o[6] */ 1377 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT7 = 0x0000098Eu, /* lvds2usb32ss.hbwss_otrig_o[7] */ 1378 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT8 = 0x0000098Fu, /* lvds2usb32ss.hbwss_otrig_o[8] */ 1379 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT9 = 0x00000990u, /* lvds2usb32ss.hbwss_otrig_o[9] */ 1380 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT10 = 0x00000991u, /* lvds2usb32ss.hbwss_otrig_o[10] */ 1381 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT11 = 0x00000992u, /* lvds2usb32ss.hbwss_otrig_o[11] */ 1382 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT12 = 0x00000993u, /* lvds2usb32ss.hbwss_otrig_o[12] */ 1383 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT13 = 0x00000994u, /* lvds2usb32ss.hbwss_otrig_o[13] */ 1384 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT14 = 0x00000995u, /* lvds2usb32ss.hbwss_otrig_o[14] */ 1385 TRIG_IN_MUX_9_LVDS2USB32SS_TR_OUT15 = 0x00000996u /* lvds2usb32ss.hbwss_otrig_o[15] */ 1386 } en_trig_input_lvds2usb32ss_tr_in_t; 1387 1388 /* Trigger Input Group 10 - CAN TT Synchronization triggers */ 1389 typedef enum 1390 { 1391 TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A00u, /* canfd[0].tr_tmp_rtp_out[0] */ 1392 TRIG_IN_MUX_10_PDMA0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */ 1393 TRIG_IN_MUX_10_PDMA0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */ 1394 TRIG_IN_MUX_10_PDMA0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */ 1395 TRIG_IN_MUX_10_PDMA0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */ 1396 TRIG_IN_MUX_10_PDMA0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */ 1397 TRIG_IN_MUX_10_PDMA0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */ 1398 TRIG_IN_MUX_10_PDMA0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */ 1399 TRIG_IN_MUX_10_PDMA0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */ 1400 TRIG_IN_MUX_10_PDMA0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */ 1401 TRIG_IN_MUX_10_PDMA0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */ 1402 TRIG_IN_MUX_10_PDMA0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */ 1403 TRIG_IN_MUX_10_PDMA0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */ 1404 TRIG_IN_MUX_10_PDMA0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */ 1405 TRIG_IN_MUX_10_PDMA0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */ 1406 TRIG_IN_MUX_10_PDMA0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */ 1407 TRIG_IN_MUX_10_PDMA0_TR_OUT15 = 0x00000A10u /* cpuss.dw0_tr_out[15] */ 1408 } en_trig_input_cantt_t; 1409 1410 /* Trigger Input Group 11 - TCPWM and PDM trigger multiplexer */ 1411 typedef enum 1412 { 1413 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW0 = 0x00000B00u, /* tcpwm[0].tr_overflow[0] */ 1414 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH0 = 0x00000B01u, /* tcpwm[0].tr_compare_match[0] */ 1415 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW0 = 0x00000B02u, /* tcpwm[0].tr_underflow[0] */ 1416 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW1 = 0x00000B03u, /* tcpwm[0].tr_overflow[1] */ 1417 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH1 = 0x00000B04u, /* tcpwm[0].tr_compare_match[1] */ 1418 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW1 = 0x00000B05u, /* tcpwm[0].tr_underflow[1] */ 1419 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW2 = 0x00000B06u, /* tcpwm[0].tr_overflow[2] */ 1420 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH2 = 0x00000B07u, /* tcpwm[0].tr_compare_match[2] */ 1421 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW2 = 0x00000B08u, /* tcpwm[0].tr_underflow[2] */ 1422 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW3 = 0x00000B09u, /* tcpwm[0].tr_overflow[3] */ 1423 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH3 = 0x00000B0Au, /* tcpwm[0].tr_compare_match[3] */ 1424 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW3 = 0x00000B0Bu, /* tcpwm[0].tr_underflow[3] */ 1425 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW4 = 0x00000B0Cu, /* tcpwm[0].tr_overflow[4] */ 1426 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH4 = 0x00000B0Du, /* tcpwm[0].tr_compare_match[4] */ 1427 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW4 = 0x00000B0Eu, /* tcpwm[0].tr_underflow[4] */ 1428 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW5 = 0x00000B0Fu, /* tcpwm[0].tr_overflow[5] */ 1429 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH5 = 0x00000B10u, /* tcpwm[0].tr_compare_match[5] */ 1430 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW5 = 0x00000B11u, /* tcpwm[0].tr_underflow[5] */ 1431 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW6 = 0x00000B12u, /* tcpwm[0].tr_overflow[6] */ 1432 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH6 = 0x00000B13u, /* tcpwm[0].tr_compare_match[6] */ 1433 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW6 = 0x00000B14u, /* tcpwm[0].tr_underflow[6] */ 1434 TRIG_IN_MUX_11_TCPWM_TR_OVERFLOW7 = 0x00000B15u, /* tcpwm[0].tr_overflow[7] */ 1435 TRIG_IN_MUX_11_TCPWM_TR_COMPARE_MATCH7 = 0x00000B16u, /* tcpwm[0].tr_compare_match[7] */ 1436 TRIG_IN_MUX_11_TCPWM_TR_UNDERFLOW7 = 0x00000B17u, /* tcpwm[0].tr_underflow[7] */ 1437 TRIG_IN_MUX_11_HSIOM_TR_OUT0 = 0x00000B18u, /* peri.tr_io_input[0] */ 1438 TRIG_IN_MUX_11_HSIOM_TR_OUT1 = 0x00000B19u, /* peri.tr_io_input[1] */ 1439 TRIG_IN_MUX_11_HSIOM_TR_OUT2 = 0x00000B1Au, /* peri.tr_io_input[2] */ 1440 TRIG_IN_MUX_11_HSIOM_TR_OUT3 = 0x00000B1Bu, /* peri.tr_io_input[3] */ 1441 TRIG_IN_MUX_11_HSIOM_TR_OUT4 = 0x00000B1Cu, /* peri.tr_io_input[4] */ 1442 TRIG_IN_MUX_11_HSIOM_TR_OUT5 = 0x00000B1Du, /* peri.tr_io_input[5] */ 1443 TRIG_IN_MUX_11_HSIOM_TR_OUT6 = 0x00000B1Eu, /* peri.tr_io_input[6] */ 1444 TRIG_IN_MUX_11_HSIOM_TR_OUT7 = 0x00000B1Fu, /* peri.tr_io_input[7] */ 1445 TRIG_IN_MUX_11_HSIOM_TR_OUT8 = 0x00000B20u, /* peri.tr_io_input[8] */ 1446 TRIG_IN_MUX_11_HSIOM_TR_OUT9 = 0x00000B21u, /* peri.tr_io_input[9] */ 1447 TRIG_IN_MUX_11_HSIOM_TR_OUT10 = 0x00000B22u, /* peri.tr_io_input[10] */ 1448 TRIG_IN_MUX_11_HSIOM_TR_OUT11 = 0x00000B23u, /* peri.tr_io_input[11] */ 1449 TRIG_IN_MUX_11_HSIOM_TR_OUT12 = 0x00000B24u, /* peri.tr_io_input[12] */ 1450 TRIG_IN_MUX_11_HSIOM_TR_OUT13 = 0x00000B25u, /* peri.tr_io_input[13] */ 1451 TRIG_IN_MUX_11_HSIOM_TR_OUT14 = 0x00000B26u, /* peri.tr_io_input[14] */ 1452 TRIG_IN_MUX_11_HSIOM_TR_OUT15 = 0x00000B27u, /* peri.tr_io_input[15] */ 1453 TRIG_IN_MUX_11_HSIOM_TR_OUT16 = 0x00000B28u, /* peri.tr_io_input[16] */ 1454 TRIG_IN_MUX_11_HSIOM_TR_OUT17 = 0x00000B29u, /* peri.tr_io_input[17] */ 1455 TRIG_IN_MUX_11_HSIOM_TR_OUT18 = 0x00000B2Au, /* peri.tr_io_input[18] */ 1456 TRIG_IN_MUX_11_HSIOM_TR_OUT19 = 0x00000B2Bu, /* peri.tr_io_input[19] */ 1457 TRIG_IN_MUX_11_HSIOM_TR_OUT20 = 0x00000B2Cu, /* peri.tr_io_input[20] */ 1458 TRIG_IN_MUX_11_HSIOM_TR_OUT21 = 0x00000B2Du, /* peri.tr_io_input[21] */ 1459 TRIG_IN_MUX_11_HSIOM_TR_OUT22 = 0x00000B2Eu, /* peri.tr_io_input[22] */ 1460 TRIG_IN_MUX_11_HSIOM_TR_OUT23 = 0x00000B2Fu /* peri.tr_io_input[23] */ 1461 } en_trig_input_tcpwm_pdm_t; 1462 1463 /* Trigger Input Group 12 - PDM TDM Freeze trigger multiplexer */ 1464 typedef enum 1465 { 1466 TRIG_IN_MUX_12_CTI_TR_OUT0 = 0x00000C00u, /* cpuss.cti_tr_out[0] */ 1467 TRIG_IN_MUX_12_CTI_TR_OUT1 = 0x00000C01u /* cpuss.cti_tr_out[1] */ 1468 } en_trig_input_pdm_tdm_freeze_t; 1469 1470 /* Trigger Group Outputs */ 1471 /* Trigger Output Group 0 - PDMA0 Request Assignments */ 1472 typedef enum 1473 { 1474 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1475 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1476 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1477 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1478 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1479 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1480 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1481 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */ 1482 TRIG_OUT_MUX_0_PDMA0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */ 1483 TRIG_OUT_MUX_0_PDMA0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */ 1484 TRIG_OUT_MUX_0_PDMA0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */ 1485 TRIG_OUT_MUX_0_PDMA0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */ 1486 TRIG_OUT_MUX_0_PDMA0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */ 1487 TRIG_OUT_MUX_0_PDMA0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */ 1488 TRIG_OUT_MUX_0_PDMA0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */ 1489 TRIG_OUT_MUX_0_PDMA0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */ 1490 } en_trig_output_pdma0_tr_t; 1491 1492 /* Trigger Output Group 1 - PDMA1 Request Assignments */ 1493 typedef enum 1494 { 1495 TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ 1496 TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ 1497 TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ 1498 TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ 1499 TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ 1500 TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ 1501 TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ 1502 TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u, /* cpuss.dw1_tr_in[7] */ 1503 TRIG_OUT_MUX_1_PDMA1_TR_IN8 = 0x40000108u, /* cpuss.dw1_tr_in[8] */ 1504 TRIG_OUT_MUX_1_PDMA1_TR_IN9 = 0x40000109u, /* cpuss.dw1_tr_in[9] */ 1505 TRIG_OUT_MUX_1_PDMA1_TR_IN10 = 0x4000010Au, /* cpuss.dw1_tr_in[10] */ 1506 TRIG_OUT_MUX_1_PDMA1_TR_IN11 = 0x4000010Bu, /* cpuss.dw1_tr_in[11] */ 1507 TRIG_OUT_MUX_1_PDMA1_TR_IN12 = 0x4000010Cu, /* cpuss.dw1_tr_in[12] */ 1508 TRIG_OUT_MUX_1_PDMA1_TR_IN13 = 0x4000010Du, /* cpuss.dw1_tr_in[13] */ 1509 TRIG_OUT_MUX_1_PDMA1_TR_IN14 = 0x4000010Eu, /* cpuss.dw1_tr_in[14] */ 1510 TRIG_OUT_MUX_1_PDMA1_TR_IN15 = 0x4000010Fu /* cpuss.dw1_tr_in[15] */ 1511 } en_trig_output_pdma1_tr_t; 1512 1513 /* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ 1514 typedef enum 1515 { 1516 TRIG_OUT_MUX_2_TCPWM_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */ 1517 TRIG_OUT_MUX_2_TCPWM_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */ 1518 TRIG_OUT_MUX_2_TCPWM_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */ 1519 TRIG_OUT_MUX_2_TCPWM_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */ 1520 TRIG_OUT_MUX_2_TCPWM_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */ 1521 TRIG_OUT_MUX_2_TCPWM_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */ 1522 TRIG_OUT_MUX_2_TCPWM_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */ 1523 TRIG_OUT_MUX_2_TCPWM_TR_IN7 = 0x40000207u /* tcpwm[0].tr_in[7] */ 1524 } en_trig_output_tcpwm0_t; 1525 1526 /* Trigger Output Group 3 - IO trigger multiplexer */ 1527 typedef enum 1528 { 1529 TRIG_OUT_MUX_3_PERI_IO_OUT0 = 0x40000300u, /* peri.tr_io_output[0] */ 1530 TRIG_OUT_MUX_3_PERI_IO_OUT1 = 0x40000301u /* peri.tr_io_output[1] */ 1531 } en_trig_output_ioss_t; 1532 1533 /* Trigger Output Group 4 - IO trigger multiplexer */ 1534 typedef enum 1535 { 1536 TRIG_OUT_MUX_4_CPUSS_CTI_TR_IN0 = 0x40000400u, /* cpuss.cti_tr_in[0] */ 1537 TRIG_OUT_MUX_4_CPUSS_CTI_TR_IN1 = 0x40000401u /* cpuss.cti_tr_in[1] */ 1538 } en_trig_output_cpuss_cti_t; 1539 1540 /* Trigger Output Group 5 - MDMA trigger multiplexer */ 1541 typedef enum 1542 { 1543 TRIG_OUT_MUX_5_MDMA_TR_IN0 = 0x40000500u, /* cpuss.dmac_tr_in[0] */ 1544 TRIG_OUT_MUX_5_MDMA_TR_IN1 = 0x40000501u, /* cpuss.dmac_tr_in[1] */ 1545 TRIG_OUT_MUX_5_MDMA_TR_IN2 = 0x40000502u, /* cpuss.dmac_tr_in[2] */ 1546 TRIG_OUT_MUX_5_MDMA_TR_IN3 = 0x40000503u, /* cpuss.dmac_tr_in[3] */ 1547 TRIG_OUT_MUX_5_MDMA_TR_IN4 = 0x40000504u, /* cpuss.dmac_tr_in[4] */ 1548 TRIG_OUT_MUX_5_MDMA_TR_IN5 = 0x40000505u /* cpuss.dmac_tr_in[5] */ 1549 } en_trig_output_mdma_t; 1550 1551 /* Trigger Output Group 6 - PERI Freeze trigger multiplexer */ 1552 typedef enum 1553 { 1554 TRIG_OUT_MUX_6_PERI_DEBUG_FREEZE_TR_IN = 0x40000600u /* peri.tr_dbg_freeze */ 1555 } en_trig_output_peri_freeze_t; 1556 1557 /* Trigger Output Group 7 - usb DMA Trigger multiplexer */ 1558 typedef enum 1559 { 1560 TRIG_OUT_MUX_7_USB_DMA_BURSTEND0 = 0x40000700u, /* usb.dma_burstend[0] */ 1561 TRIG_OUT_MUX_7_USB_DMA_BURSTEND1 = 0x40000701u, /* usb.dma_burstend[1] */ 1562 TRIG_OUT_MUX_7_USB_DMA_BURSTEND2 = 0x40000702u, /* usb.dma_burstend[2] */ 1563 TRIG_OUT_MUX_7_USB_DMA_BURSTEND3 = 0x40000703u, /* usb.dma_burstend[3] */ 1564 TRIG_OUT_MUX_7_USB_DMA_BURSTEND4 = 0x40000704u, /* usb.dma_burstend[4] */ 1565 TRIG_OUT_MUX_7_USB_DMA_BURSTEND5 = 0x40000705u, /* usb.dma_burstend[5] */ 1566 TRIG_OUT_MUX_7_USB_DMA_BURSTEND6 = 0x40000706u, /* usb.dma_burstend[6] */ 1567 TRIG_OUT_MUX_7_USB_DMA_BURSTEND7 = 0x40000707u /* usb.dma_burstend[7] */ 1568 } en_trig_output_usb_tr_in_t; 1569 1570 /* Trigger Output Group 8 - USBHSDEV DMA Trigger multiplexer */ 1571 typedef enum 1572 { 1573 TRIG_OUT_MUX_8_USBHSDEV_TR_IN0 = 0x40000800u, /* usbhsdev.u2d_tr_in[0] */ 1574 TRIG_OUT_MUX_8_USBHSDEV_TR_IN1 = 0x40000801u, /* usbhsdev.u2d_tr_in[1] */ 1575 TRIG_OUT_MUX_8_USBHSDEV_TR_IN2 = 0x40000802u, /* usbhsdev.u2d_tr_in[2] */ 1576 TRIG_OUT_MUX_8_USBHSDEV_TR_IN3 = 0x40000803u, /* usbhsdev.u2d_tr_in[3] */ 1577 TRIG_OUT_MUX_8_USBHSDEV_TR_IN4 = 0x40000804u, /* usbhsdev.u2d_tr_in[4] */ 1578 TRIG_OUT_MUX_8_USBHSDEV_TR_IN5 = 0x40000805u, /* usbhsdev.u2d_tr_in[5] */ 1579 TRIG_OUT_MUX_8_USBHSDEV_TR_IN6 = 0x40000806u, /* usbhsdev.u2d_tr_in[6] */ 1580 TRIG_OUT_MUX_8_USBHSDEV_TR_IN7 = 0x40000807u, /* usbhsdev.u2d_tr_in[7] */ 1581 TRIG_OUT_MUX_8_USBHSDEV_TR_IN8 = 0x40000808u, /* usbhsdev.u2d_tr_in[8] */ 1582 TRIG_OUT_MUX_8_USBHSDEV_TR_IN9 = 0x40000809u, /* usbhsdev.u2d_tr_in[9] */ 1583 TRIG_OUT_MUX_8_USBHSDEV_TR_IN10 = 0x4000080Au, /* usbhsdev.u2d_tr_in[10] */ 1584 TRIG_OUT_MUX_8_USBHSDEV_TR_IN11 = 0x4000080Bu, /* usbhsdev.u2d_tr_in[11] */ 1585 TRIG_OUT_MUX_8_USBHSDEV_TR_IN12 = 0x4000080Cu, /* usbhsdev.u2d_tr_in[12] */ 1586 TRIG_OUT_MUX_8_USBHSDEV_TR_IN13 = 0x4000080Du, /* usbhsdev.u2d_tr_in[13] */ 1587 TRIG_OUT_MUX_8_USBHSDEV_TR_IN14 = 0x4000080Eu, /* usbhsdev.u2d_tr_in[14] */ 1588 TRIG_OUT_MUX_8_USBHSDEV_TR_IN15 = 0x4000080Fu, /* usbhsdev.u2d_tr_in[15] */ 1589 TRIG_OUT_MUX_8_USBHSDEV_TR_IN16 = 0x40000810u, /* usbhsdev.u2d_tr_in[16] */ 1590 TRIG_OUT_MUX_8_USBHSDEV_TR_IN17 = 0x40000811u, /* usbhsdev.u2d_tr_in[17] */ 1591 TRIG_OUT_MUX_8_USBHSDEV_TR_IN18 = 0x40000812u, /* usbhsdev.u2d_tr_in[18] */ 1592 TRIG_OUT_MUX_8_USBHSDEV_TR_IN19 = 0x40000813u, /* usbhsdev.u2d_tr_in[19] */ 1593 TRIG_OUT_MUX_8_USBHSDEV_TR_IN20 = 0x40000814u, /* usbhsdev.u2d_tr_in[20] */ 1594 TRIG_OUT_MUX_8_USBHSDEV_TR_IN21 = 0x40000815u, /* usbhsdev.u2d_tr_in[21] */ 1595 TRIG_OUT_MUX_8_USBHSDEV_TR_IN22 = 0x40000816u, /* usbhsdev.u2d_tr_in[22] */ 1596 TRIG_OUT_MUX_8_USBHSDEV_TR_IN23 = 0x40000817u, /* usbhsdev.u2d_tr_in[23] */ 1597 TRIG_OUT_MUX_8_USBHSDEV_TR_IN24 = 0x40000818u, /* usbhsdev.u2d_tr_in[24] */ 1598 TRIG_OUT_MUX_8_USBHSDEV_TR_IN25 = 0x40000819u, /* usbhsdev.u2d_tr_in[25] */ 1599 TRIG_OUT_MUX_8_USBHSDEV_TR_IN26 = 0x4000081Au, /* usbhsdev.u2d_tr_in[26] */ 1600 TRIG_OUT_MUX_8_USBHSDEV_TR_IN27 = 0x4000081Bu, /* usbhsdev.u2d_tr_in[27] */ 1601 TRIG_OUT_MUX_8_USBHSDEV_TR_IN28 = 0x4000081Cu, /* usbhsdev.u2d_tr_in[28] */ 1602 TRIG_OUT_MUX_8_USBHSDEV_TR_IN29 = 0x4000081Du, /* usbhsdev.u2d_tr_in[29] */ 1603 TRIG_OUT_MUX_8_USBHSDEV_TR_IN30 = 0x4000081Eu, /* usbhsdev.u2d_tr_in[30] */ 1604 TRIG_OUT_MUX_8_USBHSDEV_TR_IN31 = 0x4000081Fu /* usbhsdev.u2d_tr_in[31] */ 1605 } en_trig_output_usbhsdev_tr_in_t; 1606 1607 /* Trigger Output Group 9 - LVDS2USB32SS DMA Trigger multiplexer */ 1608 typedef enum 1609 { 1610 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN0 = 0x40000900u, /* lvds2usb32ss.hbwss_itrig_i[0] */ 1611 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN1 = 0x40000901u, /* lvds2usb32ss.hbwss_itrig_i[1] */ 1612 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN2 = 0x40000902u, /* lvds2usb32ss.hbwss_itrig_i[2] */ 1613 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN3 = 0x40000903u, /* lvds2usb32ss.hbwss_itrig_i[3] */ 1614 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN4 = 0x40000904u, /* lvds2usb32ss.hbwss_itrig_i[4] */ 1615 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN5 = 0x40000905u, /* lvds2usb32ss.hbwss_itrig_i[5] */ 1616 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN6 = 0x40000906u, /* lvds2usb32ss.hbwss_itrig_i[6] */ 1617 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN7 = 0x40000907u, /* lvds2usb32ss.hbwss_itrig_i[7] */ 1618 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN8 = 0x40000908u, /* lvds2usb32ss.hbwss_itrig_i[8] */ 1619 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN9 = 0x40000909u, /* lvds2usb32ss.hbwss_itrig_i[9] */ 1620 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN10 = 0x4000090Au, /* lvds2usb32ss.hbwss_itrig_i[10] */ 1621 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN11 = 0x4000090Bu, /* lvds2usb32ss.hbwss_itrig_i[11] */ 1622 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN12 = 0x4000090Cu, /* lvds2usb32ss.hbwss_itrig_i[12] */ 1623 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN13 = 0x4000090Du, /* lvds2usb32ss.hbwss_itrig_i[13] */ 1624 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN14 = 0x4000090Eu, /* lvds2usb32ss.hbwss_itrig_i[14] */ 1625 TRIG_OUT_MUX_9_LVDSUSB32SS_TR_IN15 = 0x4000090Fu /* lvds2usb32ss.hbwss_itrig_i[15] */ 1626 } en_trig_output_lvds2usb32ss_tr_in_t; 1627 1628 /* Trigger Output Group 10 - CAN TT Synchronization triggers */ 1629 typedef enum 1630 { 1631 TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u, /* canfd[0].tr_evt_swt_in[0] */ 1632 TRIG_OUT_MUX_10_CAN_TT_DBG_IN0 = 0x40000A01u /* canfd[0].tr_dbg_dma_ack[0] */ 1633 } en_trig_output_cantt_t; 1634 1635 /* Trigger Output Group 11 - TCPWM and PDM trigger multiplexer */ 1636 typedef enum 1637 { 1638 TRIG_OUT_MUX_11_PDM_TR_ACTIVATE0 = 0x40000B00u, /* pdm[0].tr_activate[0] */ 1639 TRIG_OUT_MUX_11_PDM_TR_ACTIVATE1 = 0x40000B01u /* pdm[0].tr_activate[1] */ 1640 } en_trig_output_tcpwm_pdm_t; 1641 1642 /* Trigger Output Group 12 - PDM TDM Freeze trigger multiplexer */ 1643 typedef enum 1644 { 1645 TRIG_OUT_MUX_12_TDM_DEBUG_FREEZE_TR_IN = 0x40000C00u, /* tdm[0].tr_dbg_freeze */ 1646 TRIG_OUT_MUX_12_PDM_DEBUG_FREEZE_TR_IN = 0x40000C01u /* pdm[0].tr_dbg_freeze */ 1647 } en_trig_output_pdm_tdm_freeze_t; 1648 1649 /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ 1650 typedef enum 1651 { 1652 TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ 1653 TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ 1654 TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ 1655 TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ 1656 } en_trig_output_1to1_scb_pdma0_tr_t; 1657 1658 /* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ 1659 typedef enum 1660 { 1661 TRIG_OUT_1TO1_1_SCB0_TX_TO_PDMA1_TR_IN16 = 0x40001100u, /* From scb[2].tr_tx_req to cpuss.dw1_tr_in[16] */ 1662 TRIG_OUT_1TO1_1_SCB0_RX_TO_PDMA1_TR_IN17 = 0x40001101u, /* From scb[2].tr_rx_req to cpuss.dw1_tr_in[17] */ 1663 TRIG_OUT_1TO1_1_SCB0_TX_TO_PDMA1_TR_IN18 = 0x40001102u, /* From scb[3].tr_tx_req to cpuss.dw1_tr_in[18] */ 1664 TRIG_OUT_1TO1_1_SCB0_RX_TO_PDMA1_TR_IN19 = 0x40001103u /* From scb[3].tr_rx_req to cpuss.dw1_tr_in[19] */ 1665 } en_trig_output_1to1_scb_pdma1_tr_t; 1666 1667 /* Trigger Output Group 2 - (OneToOne) */ 1668 typedef enum 1669 { 1670 TRIG_OUT_1TO1_2_SMIF_TX_TO_PDMA0_TR_IN20 = 0x40001200u, /* From smif.tr_tx_req to cpuss.dw0_tr_in[20] */ 1671 TRIG_OUT_1TO1_2_SMIF_RX_TO_PDMA0_TR_IN21 = 0x40001201u /* From smif.tr_rx_req to cpuss.dw0_tr_in[21] */ 1672 } en_trig_output_1to1_smif_to_pdma0_t; 1673 1674 /* Trigger Output Group 3 - USB PDMA0 Triggers (OneToOne) */ 1675 typedef enum 1676 { 1677 TRIG_OUT_1TO1_3_PDM_RX0_TO_PDMA1_TR_IN20 = 0x40001300u, /* From pdm[0].tr_rx_req[0] to cpuss.dw1_tr_in[20] */ 1678 TRIG_OUT_1TO1_3_PDM_RX1_TO_PDMA1_TR_IN21 = 0x40001301u /* From pdm[0].tr_rx_req[1] to cpuss.dw1_tr_in[21] */ 1679 } en_trig_output_1to1_pdm_pdma1_tr_t; 1680 1681 /* Trigger Output Group 4 - TDM PDMA1 Triggers (OneToOne) */ 1682 typedef enum 1683 { 1684 TRIG_OUT_1TO1_4_TDM_TX_TO_PDMA1_TR_IN22 = 0x40001400u, /* From tdm[0].tr_tx_req to cpuss.dw1_tr_in[22] */ 1685 TRIG_OUT_1TO1_4_TDM_TX_TO_PDMA1_TR_IN23 = 0x40001401u /* From tdm[0].tr_rx_req to cpuss.dw1_tr_in[23] */ 1686 } en_trig_output_1to1_tdm_pdma1_tr_t; 1687 1688 /* Trigger Output Group 5 - CAN DW triggers (OneToOne) */ 1689 typedef enum 1690 { 1691 TRIG_OUT_1TO1_5_CAN_FIFO0_TO_PDMA0_TR_IN22 = 0x40001500u, /* From canfd[0].tr_fifo0[0] to cpuss.dw0_tr_in[22] */ 1692 TRIG_OUT_1TO1_5_CAN_FIFO1_TO_PDMA0_TR_IN23 = 0x40001501u /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[23] */ 1693 } en_trig_output_1to1_can_dw_tr_t; 1694 1695 /* Level or edge detection setting for a trigger mux */ 1696 typedef enum 1697 { 1698 /* The trigger is a simple level output */ 1699 TRIGGER_TYPE_LEVEL = 0u, 1700 /* The trigger is synchronized to the consumer blocks clock 1701 and a two cycle pulse is generated on this clock */ 1702 TRIGGER_TYPE_EDGE = 1u 1703 } en_trig_type_t; 1704 1705 /* Trigger Type Defines */ 1706 /* CANFD Trigger Types */ 1707 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1708 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1709 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1710 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1711 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1712 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1713 /* CPUSS Trigger Types */ 1714 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1715 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1716 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1717 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1718 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1719 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1720 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1721 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1722 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1723 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1724 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1725 /* LVDS2USB32SS Trigger Types */ 1726 #define TRIGGER_TYPE_LVDS2USB32SS_HBWSS_ITRIG_I TRIGGER_TYPE_EDGE 1727 #define TRIGGER_TYPE_LVDS2USB32SS_HBWSS_OTRIG_O TRIGGER_TYPE_LEVEL 1728 #define TRIGGER_TYPE_LVDS2USB32SS_USB32_FRM_CNTR_VLD_O TRIGGER_TYPE_LEVEL 1729 /* PDM Trigger Types */ 1730 #define TRIGGER_TYPE_PDM_TR_ACTIVATE TRIGGER_TYPE_LEVEL 1731 #define TRIGGER_TYPE_PDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1732 #define TRIGGER_TYPE_PDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 1733 /* PERI Trigger Types */ 1734 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1735 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1736 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1737 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1738 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1739 /* SCB Trigger Types */ 1740 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1741 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1742 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1743 /* SMIF Trigger Types */ 1744 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 1745 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 1746 /* TCPWM Trigger Types */ 1747 #define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL 1748 #define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL 1749 #define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE 1750 #define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1751 #define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE 1752 #define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE 1753 #define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE 1754 /* TDM Trigger Types */ 1755 #define TRIGGER_TYPE_TDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1756 #define TRIGGER_TYPE_TDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 1757 #define TRIGGER_TYPE_TDM_TR_TX_REQ TRIGGER_TYPE_LEVEL 1758 /* USB Trigger Types */ 1759 #define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE 1760 #define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE 1761 /* USBHSDEV Trigger Types */ 1762 #define TRIGGER_TYPE_USBHSDEV_U2D_TR_IN TRIGGER_TYPE_EDGE 1763 #define TRIGGER_TYPE_USBHSDEV_U2D_TR_OUT TRIGGER_TYPE_LEVEL 1764 1765 /* Fault connections */ 1766 typedef enum 1767 { 1768 CPUSS_MPU_VIO_0 = 0x0000u, 1769 CPUSS_MPU_VIO_1 = 0x0001u, 1770 CPUSS_MPU_VIO_2 = 0x0002u, 1771 CPUSS_MPU_VIO_3 = 0x0003u, 1772 CPUSS_MPU_VIO_4 = 0x0004u, 1773 CPUSS_MPU_VIO_14 = 0x000Eu, 1774 CPUSS_MPU_VIO_15 = 0x000Fu, 1775 CPUSS_MPU_VIO_16 = 0x0010u, 1776 CPUSS_MPU_VIO_17 = 0x0011u, 1777 CPUSS_MPU_VIO_18 = 0x0012u, 1778 PERI_MS_VIO_0 = 0x001Cu, 1779 PERI_MS_VIO_1 = 0x001Du, 1780 PERI_MS_VIO_2 = 0x001Eu, 1781 PERI_MS_VIO_3 = 0x001Fu, 1782 PERI_GROUP_VIO_0 = 0x0020u, 1783 PERI_GROUP_VIO_1 = 0x0021u, 1784 PERI_GROUP_VIO_2 = 0x0022u, 1785 PERI_GROUP_VIO_3 = 0x0023u, 1786 PERI_GROUP_VIO_4 = 0x0024u, 1787 PERI_GROUP_VIO_5 = 0x0025u, 1788 PERI_GROUP_VIO_6 = 0x0026u, 1789 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u 1790 } en_sysfault_source_t; 1791 1792 /* Bus masters */ 1793 typedef enum 1794 { 1795 CPUSS_MS_ID_CM0 = 0, 1796 CPUSS_MS_ID_CRYPTO = 1, 1797 CPUSS_MS_ID_DW0 = 2, 1798 CPUSS_MS_ID_DW1 = 3, 1799 CPUSS_MS_ID_DMAC = 4, 1800 CPUSS_MS_ID_SLOW0 = 5, 1801 CPUSS_MS_ID_SLOW1 = 6, 1802 CPUSS_MS_ID_CM4 = 14, 1803 CPUSS_MS_ID_TC = 15 1804 } en_prot_master_t; 1805 1806 /* Pointer to device configuration structure */ 1807 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfgFX3G2) 1808 1809 /* Include IP definitions */ 1810 #include "ip/cyip_sflash_fx3g2.h" 1811 #include "ip/cyip_peri_v2.h" 1812 #include "ip/cyip_peri_ms_v2.h" 1813 #include "ip/cyip_crypto_v2.h" 1814 #include "ip/cyip_cpuss_v2.h" 1815 #include "ip/cyip_fault_v2.h" 1816 #include "ip/cyip_ipc_v2.h" 1817 #include "ip/cyip_prot_v2.h" 1818 #include "ip/cyip_flashc_v2.h" 1819 #include "ip/cyip_srss.h" 1820 #include "ip/cyip_dw_v2.h" 1821 #include "ip/cyip_dmac_v2.h" 1822 #include "ip/cyip_efuse.h" 1823 #include "ip/cyip_efuse_data_fx3g2.h" 1824 #include "ip/cyip_hsiom_v5.h" 1825 #include "ip/cyip_gpio_v5.h" 1826 #include "ip/cyip_mxpdm.h" 1827 #include "ip/cyip_tcpwm.h" 1828 #include "ip/cyip_smif.h" 1829 #include "ip/cyip_usbfs.h" 1830 #include "ip/cyip_mxs40usbhsdev.h" 1831 #include "ip/cyip_scb.h" 1832 #include "ip/cyip_canfd.h" 1833 #include "ip/cyip_tdm_v2.h" 1834 #include "ip/cyip_main_reg.h" 1835 #include "ip/cyip_usb32dev.h" 1836 #include "ip/cyip_lvdsss.h" 1837 #include "ip/cyip_smartio.h" 1838 #include "ip/cyip_backup.h" 1839 1840 /* IP type definitions */ 1841 typedef SFLASH_V1_Type SFLASH_Type; 1842 typedef PERI_GR_V2_Type PERI_GR_Type; 1843 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 1844 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 1845 typedef PERI_V2_Type PERI_Type; 1846 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 1847 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 1848 typedef PERI_MS_V2_Type PERI_MS_Type; 1849 typedef CRYPTO_V2_Type CRYPTO_Type; 1850 typedef CPUSS_V2_Type CPUSS_Type; 1851 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 1852 typedef FAULT_V2_Type FAULT_Type; 1853 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 1854 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 1855 typedef IPC_V2_Type IPC_Type; 1856 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 1857 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 1858 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 1859 typedef PROT_MPU_V2_Type PROT_MPU_Type; 1860 typedef PROT_V2_Type PROT_Type; 1861 typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; 1862 typedef FLASHC_V2_Type FLASHC_Type; 1863 typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; 1864 typedef SRSS_V1_Type SRSS_Type; 1865 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 1866 typedef DW_V2_Type DW_Type; 1867 typedef DMAC_CH_V2_Type DMAC_CH_Type; 1868 typedef DMAC_V2_Type DMAC_Type; 1869 typedef EFUSE_V1_Type EFUSE_Type; 1870 typedef HSIOM_PRT_V5_Type HSIOM_PRT_Type; 1871 typedef HSIOM_V5_Type HSIOM_Type; 1872 typedef GPIO_PRT_V5_Type GPIO_PRT_Type; 1873 typedef GPIO_V5_Type GPIO_Type; 1874 typedef PDM_CH_V1_Type PDM_CH_Type; 1875 typedef PDM_V1_Type PDM_Type; 1876 typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type; 1877 typedef TCPWM_V1_Type TCPWM_Type; 1878 typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; 1879 typedef SMIF_V1_Type SMIF_Type; 1880 typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; 1881 typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; 1882 typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; 1883 typedef USBFS_V1_Type USBFS_Type; 1884 typedef USBHSDEV_V1_Type USBHSDEV_Type; 1885 typedef USBHSPHY_V1_Type USBHSPHY_Type; 1886 typedef MXS40USBHSDEV_V1_Type MXS40USBHSDEV_Type; 1887 typedef CySCB_V1_Type CySCB_Type; 1888 typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; 1889 typedef CANFD_CH_V1_Type CANFD_CH_Type; 1890 typedef CANFD_V1_Type CANFD_Type; 1891 typedef SMARTIO_PRT_V1_Type SMARTIO_PRT_Type; 1892 typedef SMARTIO_V1_Type SMARTIO_Type; 1893 typedef BACKUP_V1_Type BACKUP_Type; 1894 typedef TDM_TDM_STRUCT_TDM_TX_STRUCT_V2_Type TDM_TDM_STRUCT_TDM_TX_STRUCT_Type; 1895 typedef TDM_TDM_STRUCT_TDM_RX_STRUCT_V2_Type TDM_TDM_STRUCT_TDM_RX_STRUCT_Type; 1896 typedef TDM_TDM_STRUCT_V2_Type TDM_TDM_STRUCT_Type; 1897 typedef TDM_V2_Type TDM_Type; 1898 typedef MAIN_REG_TR_GR_V1_Type MAIN_REG_TR_GR_Type; 1899 typedef MAIN_REG_TR_ASSIST_GR_V1_Type MAIN_REG_TR_ASSIST_GR_Type; 1900 typedef MAIN_REG_V1_Type MAIN_REG_Type; 1901 typedef USB32DEV_MAIN_V1_Type USB32DEV_MAIN_Type; 1902 typedef USB32DEV_EPM_V1_Type USB32DEV_EPM_Type; 1903 typedef USB32DEV_LNK_V1_Type USB32DEV_LNK_Type; 1904 typedef USB32DEV_PROT_V1_Type USB32DEV_PROT_Type; 1905 typedef USB32DEV_PHYSS_USB40PHY_TOP_V1_Type USB32DEV_PHYSS_USB40PHY_TOP_Type; 1906 typedef USB32DEV_PHYSS_USB40PHY_RX_V1_Type USB32DEV_PHYSS_USB40PHY_RX_Type; 1907 typedef USB32DEV_PHYSS_USB40PHY_PLL_SYS_V1_Type USB32DEV_PHYSS_USB40PHY_PLL_SYS_Type; 1908 typedef USB32DEV_PHYSS_USB40PHY_V1_Type USB32DEV_PHYSS_USB40PHY_Type; 1909 typedef USB32DEV_PHYSS_V1_Type USB32DEV_PHYSS_Type; 1910 typedef USB32DEV_ADAPTER_DMA_SCK_V1_Type USB32DEV_ADAPTER_DMA_SCK_Type; 1911 typedef USB32DEV_ADAPTER_DMA_SCK_GBL_V1_Type USB32DEV_ADAPTER_DMA_SCK_GBL_Type; 1912 typedef USB32DEV_ADAPTER_DMA_V1_Type USB32DEV_ADAPTER_DMA_Type; 1913 typedef USB32DEV_V1_Type USB32DEV_Type; 1914 typedef LVDSSS_LVDS_LVDS_LOW_PWR_INTR_V1_Type LVDSSS_LVDS_LVDS_LOW_PWR_INTR_Type; 1915 typedef LVDSSS_LVDS_THREAD_V1_Type LVDSSS_LVDS_THREAD_Type; 1916 typedef LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_V1_Type LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_Type; 1917 typedef LVDSSS_LVDS_GPIF_LEFT_V1_Type LVDSSS_LVDS_GPIF_LEFT_Type; 1918 typedef LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_V1_Type LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_Type; 1919 typedef LVDSSS_LVDS_GPIF_RIGHT_V1_Type LVDSSS_LVDS_GPIF_RIGHT_Type; 1920 typedef LVDSSS_LVDS_GPIF_V1_Type LVDSSS_LVDS_GPIF_Type; 1921 typedef LVDSSS_LVDS_AFE_V1_Type LVDSSS_LVDS_AFE_Type; 1922 typedef LVDSSS_LVDS_ADAPTER_DMA_SCK_V1_Type LVDSSS_LVDS_ADAPTER_DMA_SCK_Type; 1923 typedef LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_V1_Type LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_Type; 1924 typedef LVDSSS_LVDS_ADAPTER_DMA_V1_Type LVDSSS_LVDS_ADAPTER_DMA_Type; 1925 typedef LVDSSS_LVDS_V1_Type LVDSSS_LVDS_Type; 1926 typedef LVDSSS_V1_Type LVDSSS_Type; 1927 1928 /* Parameter Defines */ 1929 /* Number of TTCAN instances */ 1930 #define CANFD_CAN_NR 1u 1931 /* ECC logic present or not */ 1932 #define CANFD_ECC_PRESENT 0u 1933 /* address included in ECC logic or not */ 1934 #define CANFD_ECC_ADDR_PRESENT 0u 1935 /* Time Stamp counter present or not (required for instance 0, otherwise not 1936 allowed) */ 1937 #define CANFD_TS_PRESENT 1u 1938 /* Message RAM size in KB */ 1939 #define CANFD_MRAM_SIZE 4u 1940 /* Message RAM address width */ 1941 #define CANFD_MRAM_ADDR_WIDTH 10u 1942 /* UDB present or not ('0': no, '1': yes) */ 1943 #define CPUSS_UDB_PRESENT 0u 1944 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 1945 chips which doesn't use mxdft. */ 1946 #define CPUSS_MBIST_MMIO_PRESENT 1u 1947 /* System RAM 0 size in kilobytes */ 1948 #define CPUSS_SRAM0_SIZE 128u 1949 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System 1950 SRAM0 is implemented with 8 32KB macros. */ 1951 #define CPUSS_RAMC0_MACRO_NR 4u 1952 /* System RAM 1 present or not (0=No, 1=Yes) */ 1953 #define CPUSS_RAMC1_PRESENT 0u 1954 /* System RAM 1 size in kilobytes */ 1955 #define CPUSS_SRAM1_SIZE 1u 1956 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 1957 RAM 1 is implemented with 8 32KB macros. */ 1958 #define CPUSS_RAMC1_MACRO_NR 1u 1959 /* System RAM 2 present or not (0=No, 1=Yes) */ 1960 #define CPUSS_RAMC2_PRESENT 0u 1961 /* System RAM 2 size in kilobytes */ 1962 #define CPUSS_SRAM2_SIZE 1u 1963 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 1964 RAM 2 is implemented with 8 32KB macros. */ 1965 #define CPUSS_RAMC2_MACRO_NR 1u 1966 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 1967 #define CPUSS_RAMC_ECC_PRESENT 0u 1968 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 1969 #define CPUSS_RAMC_ECC_ADDR_PRESENT 0u 1970 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 1971 #define CPUSS_ECC_PRESENT 0u 1972 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1973 #define CPUSS_DW_ECC_PRESENT 0u 1974 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 1975 #define CPUSS_DW_ECC_ADDR_PRESENT 0u 1976 /* System ROM size in KB */ 1977 #define CPUSS_ROM_SIZE 128u 1978 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 1979 is implemented with 4 128KB macros. */ 1980 #define CPUSS_ROMC_MACRO_NR 2u 1981 /* Flash memory present or not ('0': no, '1': yes) */ 1982 #define CPUSS_FLASHC_PRESENT 1u 1983 /* Flash memory type ('0' : SONOS, '1': ECT) */ 1984 #define CPUSS_FLASHC_ECT 0u 1985 /* Flash main region size in KB */ 1986 #define CPUSS_FLASH_SIZE 512u 1987 /* Flash work region size in KB (EEPROM emulation, data) */ 1988 #define CPUSS_WFLASH_SIZE 32u 1989 /* Flash supervisory region size in KB */ 1990 #define CPUSS_SFLASH_SIZE 32u 1991 /* Flash data output word size (in Bytes) */ 1992 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u 1993 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 1994 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 1995 Flash, and no Work Flash present. */ 1996 #define CPUSS_FLASHC_SONOS_RWW 1u 1997 /* SONOS Flash, number of main sectors. */ 1998 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u 1999 /* SONOS Flash, number of rows per main sector. */ 2000 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u 2001 /* SONOS Flash, number of words per row of main sector. */ 2002 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u 2003 /* SONOS Flash, number of special sectors. */ 2004 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u 2005 /* SONOS Flash, number of rows per special sector. */ 2006 #define CPUSS_FLASHC_SONOS_SPL_ROWS 64u 2007 /* Flash memory ECC present or not ('0': no, '1': yes) */ 2008 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u 2009 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 2010 #define CPUSS_FLASHC_RAM_ECC_PRESENT 0u 2011 /* Number of external slaves directly connected to slow AHB-Lite infrastructure. 2012 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 2013 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 2014 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK 2015 parameters (for the slaves present) should be derived from the Memory Map. */ 2016 #define CPUSS_SLOW_SL_PRESENT 7u 2017 /* Number of external slaves directly connected to fast AHB-Lite infrastructure. 2018 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 2019 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 2020 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 2021 parameters (for the slaves present) should be derived from the Memory Map. */ 2022 #define CPUSS_FAST_SL_PRESENT 3u 2023 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum 2024 number of masters supported is 2. Width of this parameter is 2-bits. 1-bit 2025 mask for each master indicating present or not. Example: 2'b01 - master 0 is 2026 present. */ 2027 #define CPUSS_SLOW_MS_PRESENT 0u 2028 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 2029 CM0+ PCU, which always uses system interrupt functionality. */ 2030 #define CPUSS_SYSTEM_IRQ_PRESENT 0u 2031 /* Number of total interrupt request inputs to CPUSS */ 2032 #define CPUSS_SYSTEM_INT_NR 142u 2033 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */ 2034 #define CPUSS_SYSTEM_DPSLP_INT_NR 46u 2035 /* CM4 CPU present or not ('0': no, '1': yes) */ 2036 #define CPUSS_CM4_PRESENT 1u 2037 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 2038 levels of priority 8 = 256 levels of priority */ 2039 #define CPUSS_CM4_LVL_WIDTH 3u 2040 /* CM4 Floating point unit present or not (0=No, 1=Yes) */ 2041 #define CPUSS_CM4_FPU_PRESENT 1u 2042 /* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 2043 breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 2044 watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ 2045 #define CPUSS_DEBUG_LVL 3u 2046 /* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + 2047 ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace 2048 level is not supported in CPUSS. */ 2049 #define CPUSS_TRACE_LVL 2u 2050 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */ 2051 #define CPUSS_ETB_PRESENT 0u 2052 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2053 #define CPUSS_MTB_SRAM_SIZE 4u 2054 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2055 #define CPUSS_ETB_SRAM_SIZE 8u 2056 /* PTM interface present (0=No, 1=Yes) */ 2057 #define CPUSS_PTM_PRESENT 0u 2058 /* Width of the PTM interface in bits ([2,32]) */ 2059 #define CPUSS_PTM_WIDTH 1u 2060 /* Width of the TPIU interface in bits ([1,4]) */ 2061 #define CPUSS_TPIU_WIDTH 4u 2062 /* CoreSight Part Identification Number */ 2063 #define CPUSS_JEPID 52u 2064 /* CoreSight Part Identification Number */ 2065 #define CPUSS_JEPCONTINUATION 0u 2066 /* CoreSight Part Identification Number */ 2067 #define CPUSS_FAMILYID 284u 2068 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 2069 #define CPUSS_ROM_TRIM_WIDTH 5u 2070 /* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ 2071 #define CPUSS_ROM_TRIM_DEFAULT 18u 2072 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 2073 #define CPUSS_RAM_TRIM_WIDTH 15u 2074 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 2075 #define CPUSS_RAM_TRIM_DEFAULT 0x00006012u 2076 /* Cryptography IP present or not (0=No, 1=Yes) */ 2077 #define CPUSS_CRYPTO_PRESENT 1u 2078 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2079 #define CPUSS_SW_TR_PRESENT 0u 2080 /* DataWire 0 present or not (0=No, 1=Yes) */ 2081 #define CPUSS_DW0_PRESENT 1u 2082 /* Number of DataWire 0 channels (8, 16 or 32) */ 2083 #define CPUSS_DW0_CH_NR 24u 2084 /* DataWire 1 present or not (0=No, 1=Yes) */ 2085 #define CPUSS_DW1_PRESENT 1u 2086 /* Number of DataWire 1 channels (8, 16 or 32) */ 2087 #define CPUSS_DW1_CH_NR 24u 2088 /* DMA controller present or not ('0': no, '1': yes) */ 2089 #define CPUSS_DMAC_PRESENT 1u 2090 /* Number of DMA controller channels ([1, 8]) */ 2091 #define CPUSS_DMAC_CH_NR 6u 2092 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2093 #define CPUSS_CH_SW_TR_PRESENT 0u 2094 /* Copy value from Globals */ 2095 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 2096 /* ETAS Calibration support pin out present (automotive only) */ 2097 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u 2098 /* TRACE_LVL>0 */ 2099 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 2100 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 2101 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u 2102 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 2103 #define CPUSS_CPUSS_DW_DW_NR 2u 2104 /* Number of channels in each DataWire controller */ 2105 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 24u 2106 /* Width of a channel number in bits */ 2107 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u 2108 /* Number of channels in each DataWire controller */ 2109 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 24u 2110 /* Width of a channel number in bits */ 2111 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u 2112 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 2113 #define CPUSS_CRYPTO_ECC_PRESENT 0u 2114 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 2115 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u 2116 /* AES cipher support ('0': no, '1': yes) */ 2117 #define CPUSS_CRYPTO_AES 1u 2118 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 2119 #define CPUSS_CRYPTO_DES 1u 2120 /* Chacha support ('0': no, '1': yes) */ 2121 #define CPUSS_CRYPTO_CHACHA 1u 2122 /* Pseudo random number generation support ('0': no, '1': yes) */ 2123 #define CPUSS_CRYPTO_PR 1u 2124 /* SHA1 hash support ('0': no, '1': yes) */ 2125 #define CPUSS_CRYPTO_SHA1 1u 2126 /* SHA2 hash support ('0': no, '1': yes) */ 2127 #define CPUSS_CRYPTO_SHA2 1u 2128 /* SHA3 hash support ('0': no, '1': yes) */ 2129 #define CPUSS_CRYPTO_SHA3 1u 2130 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 2131 #define CPUSS_CRYPTO_CRC 1u 2132 /* True random number generation support ('0': no, '1': yes) */ 2133 #define CPUSS_CRYPTO_TR 1u 2134 /* Vector unit support ('0': no, '1': yes) */ 2135 #define CPUSS_CRYPTO_VU 1u 2136 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 2137 #define CPUSS_CRYPTO_GCM 1u 2138 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 2139 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 2140 kB and 16 kB memory buffer) */ 2141 #define CPUSS_CRYPTO_BUFF_SIZE 2048u 2142 /* Number of DMA controller channels ([1, 8]) */ 2143 #define CPUSS_DMAC_CH_NR 6u 2144 /* Number of DataWire controllers present (max 2) */ 2145 #define CPUSS_DW_NR 2u 2146 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2147 #define CPUSS_DW_ECC_PRESENT 0u 2148 /* Number of fault structures. Legal range [1, 4] */ 2149 #define CPUSS_FAULT_FAULT_NR 2u 2150 /* Number of Flash BIST_DATA registers */ 2151 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u 2152 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 2153 #define CPUSS_FLASHC_PA_SIZE 128u 2154 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2155 #define CPUSS_FLASHC_FLASHC_IS_SONOS 1u 2156 /* eCT Flash is used or not ('0': no, '1': yes) */ 2157 #define CPUSS_FLASHC_FLASHC_IS_ECT 0u 2158 /* CM4 CPU present or not ('0': no, '1': yes) */ 2159 #define CPUSS_FLASHC_CM4_PRESENT 1u 2160 /* Number of IPC structures. Legal range [1, 16] */ 2161 #define CPUSS_IPC_IPC_NR 16u 2162 /* Number of IPC interrupt structures. Legal range [1, 16] */ 2163 #define CPUSS_IPC_IPC_IRQ_NR 16u 2164 /* Master 0 protect contexts minus one */ 2165 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 2166 /* Master 1 protect contexts minus one */ 2167 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 2168 /* Master 2 protect contexts minus one */ 2169 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 2170 /* Master 3 protect contexts minus one */ 2171 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 2172 /* Master 4 protect contexts minus one */ 2173 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 2174 /* Master 5 protect contexts minus one */ 2175 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u 2176 /* Master 6 protect contexts minus one */ 2177 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 2178 /* Master 7 protect contexts minus one */ 2179 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 2180 /* Master 8 protect contexts minus one */ 2181 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 2182 /* Master 9 protect contexts minus one */ 2183 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 2184 /* Master 10 protect contexts minus one */ 2185 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 2186 /* Master 11 protect contexts minus one */ 2187 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 2188 /* Master 12 protect contexts minus one */ 2189 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 2190 /* Master 13 protect contexts minus one */ 2191 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u 2192 /* Master 14 protect contexts minus one */ 2193 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2194 /* Master 15 protect contexts minus one */ 2195 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2196 /* Number of SMPU protection structures */ 2197 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2198 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2199 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2200 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2201 #define EFUSE_EFUSE_NR 4u 2202 /* Number of GPIO ports in range 0..31 */ 2203 #define IOSS_GPIO_GPIO_PORT_NR_0_31 14u 2204 /* Number of GPIO ports in range 32..63 */ 2205 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 2206 /* Number of GPIO ports in range 64..95 */ 2207 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2208 /* Number of GPIO ports in range 96..127 */ 2209 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2210 /* Number of ports in device */ 2211 #define IOSS_GPIO_GPIO_PORT_NR 14u 2212 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2213 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2214 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2215 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2216 /* Indicates port supports drive select trims */ 2217 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DS_CTRL 0u 2218 /* Indicates port supports slew extension bits */ 2219 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_EXT 1u 2220 /* Indicates port supports drive select extension bits */ 2221 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_EXT 0u 2222 /* Indicates slew bit width */ 2223 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_WIDTH 3u 2224 /* Indicates drive sel bit width */ 2225 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_WIDTH 0u 2226 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2227 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 2228 /* Indicates that pin #0 exists for this port with slew control feature */ 2229 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 0u 2230 /* Indicates that pin #1 exists for this port with slew control feature */ 2231 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 0u 2232 /* Indicates that pin #2 exists for this port with slew control feature */ 2233 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 0u 2234 /* Indicates that pin #3 exists for this port with slew control feature */ 2235 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 0u 2236 /* Indicates that pin #4 exists for this port with slew control feature */ 2237 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 2238 /* Indicates that pin #5 exists for this port with slew control feature */ 2239 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 2240 /* Indicates that pin #6 exists for this port with slew control feature */ 2241 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 2242 /* Indicates that pin #7 exists for this port with slew control feature */ 2243 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 2244 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2245 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 2246 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2247 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 2248 /* Indicates port supports drive select trims */ 2249 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DS_CTRL 0u 2250 /* Indicates port supports slew extension bits */ 2251 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_EXT 1u 2252 /* Indicates port supports drive select extension bits */ 2253 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_EXT 0u 2254 /* Indicates slew bit width */ 2255 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_WIDTH 3u 2256 /* Indicates drive sel bit width */ 2257 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_WIDTH 0u 2258 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2259 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 1u 2260 /* Indicates that pin #0 exists for this port with slew control feature */ 2261 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 1u 2262 /* Indicates that pin #1 exists for this port with slew control feature */ 2263 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 1u 2264 /* Indicates that pin #2 exists for this port with slew control feature */ 2265 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 2266 /* Indicates that pin #3 exists for this port with slew control feature */ 2267 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 2268 /* Indicates that pin #4 exists for this port with slew control feature */ 2269 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 2270 /* Indicates that pin #5 exists for this port with slew control feature */ 2271 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 2272 /* Indicates that pin #6 exists for this port with slew control feature */ 2273 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 2274 /* Indicates that pin #7 exists for this port with slew control feature */ 2275 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 2276 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2277 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 0u 2278 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2279 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 2280 /* Indicates port supports drive select trims */ 2281 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DS_CTRL 0u 2282 /* Indicates port supports slew extension bits */ 2283 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_EXT 0u 2284 /* Indicates port supports drive select extension bits */ 2285 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_EXT 0u 2286 /* Indicates slew bit width */ 2287 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_WIDTH 0u 2288 /* Indicates drive sel bit width */ 2289 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_WIDTH 0u 2290 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2291 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u 2292 /* Indicates that pin #0 exists for this port with slew control feature */ 2293 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 2294 /* Indicates that pin #1 exists for this port with slew control feature */ 2295 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 2296 /* Indicates that pin #2 exists for this port with slew control feature */ 2297 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 2298 /* Indicates that pin #3 exists for this port with slew control feature */ 2299 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 2300 /* Indicates that pin #4 exists for this port with slew control feature */ 2301 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 2302 /* Indicates that pin #5 exists for this port with slew control feature */ 2303 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 2304 /* Indicates that pin #6 exists for this port with slew control feature */ 2305 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 2306 /* Indicates that pin #7 exists for this port with slew control feature */ 2307 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 2308 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2309 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 0u 2310 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2311 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 2312 /* Indicates port supports drive select trims */ 2313 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DS_CTRL 0u 2314 /* Indicates port supports slew extension bits */ 2315 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_EXT 0u 2316 /* Indicates port supports drive select extension bits */ 2317 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_EXT 0u 2318 /* Indicates slew bit width */ 2319 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_WIDTH 0u 2320 /* Indicates drive sel bit width */ 2321 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_WIDTH 0u 2322 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2323 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u 2324 /* Indicates that pin #0 exists for this port with slew control feature */ 2325 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 2326 /* Indicates that pin #1 exists for this port with slew control feature */ 2327 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 2328 /* Indicates that pin #2 exists for this port with slew control feature */ 2329 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 2330 /* Indicates that pin #3 exists for this port with slew control feature */ 2331 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 2332 /* Indicates that pin #4 exists for this port with slew control feature */ 2333 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 2334 /* Indicates that pin #5 exists for this port with slew control feature */ 2335 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 2336 /* Indicates that pin #6 exists for this port with slew control feature */ 2337 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 2338 /* Indicates that pin #7 exists for this port with slew control feature */ 2339 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 2340 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2341 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 2342 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2343 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 2344 /* Indicates port supports drive select trims */ 2345 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DS_CTRL 0u 2346 /* Indicates port supports slew extension bits */ 2347 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_EXT 1u 2348 /* Indicates port supports drive select extension bits */ 2349 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_EXT 0u 2350 /* Indicates slew bit width */ 2351 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_WIDTH 3u 2352 /* Indicates drive sel bit width */ 2353 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_WIDTH 0u 2354 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2355 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 1u 2356 /* Indicates that pin #0 exists for this port with slew control feature */ 2357 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 2358 /* Indicates that pin #1 exists for this port with slew control feature */ 2359 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 2360 /* Indicates that pin #2 exists for this port with slew control feature */ 2361 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 2362 /* Indicates that pin #3 exists for this port with slew control feature */ 2363 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 2364 /* Indicates that pin #4 exists for this port with slew control feature */ 2365 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 2366 /* Indicates that pin #5 exists for this port with slew control feature */ 2367 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 2368 /* Indicates that pin #6 exists for this port with slew control feature */ 2369 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 2370 /* Indicates that pin #7 exists for this port with slew control feature */ 2371 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 2372 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2373 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 2374 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2375 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 2376 /* Indicates port supports drive select trims */ 2377 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DS_CTRL 0u 2378 /* Indicates port supports slew extension bits */ 2379 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_EXT 1u 2380 /* Indicates port supports drive select extension bits */ 2381 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_EXT 0u 2382 /* Indicates slew bit width */ 2383 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_WIDTH 3u 2384 /* Indicates drive sel bit width */ 2385 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_WIDTH 0u 2386 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2387 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 2388 /* Indicates that pin #0 exists for this port with slew control feature */ 2389 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 2390 /* Indicates that pin #1 exists for this port with slew control feature */ 2391 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 2392 /* Indicates that pin #2 exists for this port with slew control feature */ 2393 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 2394 /* Indicates that pin #3 exists for this port with slew control feature */ 2395 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 2396 /* Indicates that pin #4 exists for this port with slew control feature */ 2397 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 2398 /* Indicates that pin #5 exists for this port with slew control feature */ 2399 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 2400 /* Indicates that pin #6 exists for this port with slew control feature */ 2401 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 2402 /* Indicates that pin #7 exists for this port with slew control feature */ 2403 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 2404 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2405 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 2406 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2407 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 2408 /* Indicates port supports drive select trims */ 2409 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_DS_CTRL 0u 2410 /* Indicates port supports slew extension bits */ 2411 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLEW_EXT 0u 2412 /* Indicates port supports drive select extension bits */ 2413 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_DRIVE_EXT 0u 2414 /* Indicates slew bit width */ 2415 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLEW_WIDTH 0u 2416 /* Indicates drive sel bit width */ 2417 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_DRIVE_WIDTH 0u 2418 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2419 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u 2420 /* Indicates that pin #0 exists for this port with slew control feature */ 2421 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 1u 2422 /* Indicates that pin #1 exists for this port with slew control feature */ 2423 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 1u 2424 /* Indicates that pin #2 exists for this port with slew control feature */ 2425 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u 2426 /* Indicates that pin #3 exists for this port with slew control feature */ 2427 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u 2428 /* Indicates that pin #4 exists for this port with slew control feature */ 2429 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u 2430 /* Indicates that pin #5 exists for this port with slew control feature */ 2431 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 0u 2432 /* Indicates that pin #6 exists for this port with slew control feature */ 2433 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 0u 2434 /* Indicates that pin #7 exists for this port with slew control feature */ 2435 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 0u 2436 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2437 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 2438 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2439 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 2440 /* Indicates port supports drive select trims */ 2441 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_DS_CTRL 0u 2442 /* Indicates port supports slew extension bits */ 2443 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLEW_EXT 0u 2444 /* Indicates port supports drive select extension bits */ 2445 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_DRIVE_EXT 0u 2446 /* Indicates slew bit width */ 2447 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLEW_WIDTH 0u 2448 /* Indicates drive sel bit width */ 2449 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_DRIVE_WIDTH 0u 2450 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2451 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u 2452 /* Indicates that pin #0 exists for this port with slew control feature */ 2453 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u 2454 /* Indicates that pin #1 exists for this port with slew control feature */ 2455 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u 2456 /* Indicates that pin #2 exists for this port with slew control feature */ 2457 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u 2458 /* Indicates that pin #3 exists for this port with slew control feature */ 2459 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u 2460 /* Indicates that pin #4 exists for this port with slew control feature */ 2461 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u 2462 /* Indicates that pin #5 exists for this port with slew control feature */ 2463 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u 2464 /* Indicates that pin #6 exists for this port with slew control feature */ 2465 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 1u 2466 /* Indicates that pin #7 exists for this port with slew control feature */ 2467 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u 2468 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2469 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 2470 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2471 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 2472 /* Indicates port supports drive select trims */ 2473 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_DS_CTRL 0u 2474 /* Indicates port supports slew extension bits */ 2475 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLEW_EXT 1u 2476 /* Indicates port supports drive select extension bits */ 2477 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_DRIVE_EXT 0u 2478 /* Indicates slew bit width */ 2479 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLEW_WIDTH 3u 2480 /* Indicates drive sel bit width */ 2481 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_DRIVE_WIDTH 0u 2482 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2483 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 2484 /* Indicates that pin #0 exists for this port with slew control feature */ 2485 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 0u 2486 /* Indicates that pin #1 exists for this port with slew control feature */ 2487 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 0u 2488 /* Indicates that pin #2 exists for this port with slew control feature */ 2489 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 2490 /* Indicates that pin #3 exists for this port with slew control feature */ 2491 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 2492 /* Indicates that pin #4 exists for this port with slew control feature */ 2493 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 2494 /* Indicates that pin #5 exists for this port with slew control feature */ 2495 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 2496 /* Indicates that pin #6 exists for this port with slew control feature */ 2497 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 2498 /* Indicates that pin #7 exists for this port with slew control feature */ 2499 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 2500 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2501 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 2502 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2503 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 2504 /* Indicates port supports drive select trims */ 2505 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_DS_CTRL 0u 2506 /* Indicates port supports slew extension bits */ 2507 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLEW_EXT 1u 2508 /* Indicates port supports drive select extension bits */ 2509 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_DRIVE_EXT 0u 2510 /* Indicates slew bit width */ 2511 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLEW_WIDTH 3u 2512 /* Indicates drive sel bit width */ 2513 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_DRIVE_WIDTH 0u 2514 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2515 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 2516 /* Indicates that pin #0 exists for this port with slew control feature */ 2517 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 0u 2518 /* Indicates that pin #1 exists for this port with slew control feature */ 2519 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 0u 2520 /* Indicates that pin #2 exists for this port with slew control feature */ 2521 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 0u 2522 /* Indicates that pin #3 exists for this port with slew control feature */ 2523 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 0u 2524 /* Indicates that pin #4 exists for this port with slew control feature */ 2525 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u 2526 /* Indicates that pin #5 exists for this port with slew control feature */ 2527 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u 2528 /* Indicates that pin #6 exists for this port with slew control feature */ 2529 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 2530 /* Indicates that pin #7 exists for this port with slew control feature */ 2531 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 2532 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2533 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 2534 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2535 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 2536 /* Indicates port supports drive select trims */ 2537 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_DS_CTRL 0u 2538 /* Indicates port supports slew extension bits */ 2539 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLEW_EXT 1u 2540 /* Indicates port supports drive select extension bits */ 2541 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_DRIVE_EXT 0u 2542 /* Indicates slew bit width */ 2543 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLEW_WIDTH 3u 2544 /* Indicates drive sel bit width */ 2545 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_DRIVE_WIDTH 0u 2546 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2547 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 2548 /* Indicates that pin #0 exists for this port with slew control feature */ 2549 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u 2550 /* Indicates that pin #1 exists for this port with slew control feature */ 2551 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u 2552 /* Indicates that pin #2 exists for this port with slew control feature */ 2553 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 0u 2554 /* Indicates that pin #3 exists for this port with slew control feature */ 2555 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 0u 2556 /* Indicates that pin #4 exists for this port with slew control feature */ 2557 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 0u 2558 /* Indicates that pin #5 exists for this port with slew control feature */ 2559 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 0u 2560 /* Indicates that pin #6 exists for this port with slew control feature */ 2561 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 0u 2562 /* Indicates that pin #7 exists for this port with slew control feature */ 2563 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 0u 2564 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2565 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 2566 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2567 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 2568 /* Indicates port supports drive select trims */ 2569 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_DS_CTRL 0u 2570 /* Indicates port supports slew extension bits */ 2571 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLEW_EXT 1u 2572 /* Indicates port supports drive select extension bits */ 2573 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_DRIVE_EXT 0u 2574 /* Indicates slew bit width */ 2575 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLEW_WIDTH 3u 2576 /* Indicates drive sel bit width */ 2577 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_DRIVE_WIDTH 0u 2578 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2579 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 2580 /* Indicates that pin #0 exists for this port with slew control feature */ 2581 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u 2582 /* Indicates that pin #1 exists for this port with slew control feature */ 2583 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 0u 2584 /* Indicates that pin #2 exists for this port with slew control feature */ 2585 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 0u 2586 /* Indicates that pin #3 exists for this port with slew control feature */ 2587 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 0u 2588 /* Indicates that pin #4 exists for this port with slew control feature */ 2589 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 0u 2590 /* Indicates that pin #5 exists for this port with slew control feature */ 2591 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 0u 2592 /* Indicates that pin #6 exists for this port with slew control feature */ 2593 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 0u 2594 /* Indicates that pin #7 exists for this port with slew control feature */ 2595 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 0u 2596 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2597 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 0u 2598 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2599 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 2600 /* Indicates port supports drive select trims */ 2601 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_DS_CTRL 0u 2602 /* Indicates port supports slew extension bits */ 2603 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLEW_EXT 0u 2604 /* Indicates port supports drive select extension bits */ 2605 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_DRIVE_EXT 0u 2606 /* Indicates slew bit width */ 2607 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLEW_WIDTH 0u 2608 /* Indicates drive sel bit width */ 2609 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_DRIVE_WIDTH 0u 2610 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2611 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u 2612 /* Indicates that pin #0 exists for this port with slew control feature */ 2613 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 1u 2614 /* Indicates that pin #1 exists for this port with slew control feature */ 2615 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 1u 2616 /* Indicates that pin #2 exists for this port with slew control feature */ 2617 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 2618 /* Indicates that pin #3 exists for this port with slew control feature */ 2619 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 2620 /* Indicates that pin #4 exists for this port with slew control feature */ 2621 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 2622 /* Indicates that pin #5 exists for this port with slew control feature */ 2623 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 2624 /* Indicates that pin #6 exists for this port with slew control feature */ 2625 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 0u 2626 /* Indicates that pin #7 exists for this port with slew control feature */ 2627 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 0u 2628 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2629 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 2630 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2631 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 2632 /* Indicates port supports drive select trims */ 2633 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_DS_CTRL 0u 2634 /* Indicates port supports slew extension bits */ 2635 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLEW_EXT 1u 2636 /* Indicates port supports drive select extension bits */ 2637 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_DRIVE_EXT 0u 2638 /* Indicates slew bit width */ 2639 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLEW_WIDTH 3u 2640 /* Indicates drive sel bit width */ 2641 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_DRIVE_WIDTH 0u 2642 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2643 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 1u 2644 /* Indicates that pin #0 exists for this port with slew control feature */ 2645 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 1u 2646 /* Indicates that pin #1 exists for this port with slew control feature */ 2647 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 1u 2648 /* Indicates that pin #2 exists for this port with slew control feature */ 2649 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 2650 /* Indicates that pin #3 exists for this port with slew control feature */ 2651 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 2652 /* Indicates that pin #4 exists for this port with slew control feature */ 2653 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 2654 /* Indicates that pin #5 exists for this port with slew control feature */ 2655 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 2656 /* Indicates that pin #6 exists for this port with slew control feature */ 2657 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 2658 /* Indicates that pin #7 exists for this port with slew control feature */ 2659 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 2660 /* Level Detector present */ 2661 #define IOSS_GPIO_LVL_DET_PRESENT 0u 2662 /* Number of AMUX splitter cells */ 2663 #define IOSS_HSIOM_AMUX_SPLIT_NR 3u 2664 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 2665 #define IOSS_HSIOM_HSIOM_PORT_NR 14u 2666 /* Number of PWR/GND MONITOR CELLs in the device */ 2667 #define IOSS_HSIOM_MONITOR_NR 0u 2668 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 2669 #define IOSS_HSIOM_MONITOR_NR_0_31 0u 2670 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 2671 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 2672 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 2673 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 2674 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 2675 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 2676 /* Indicates the presence of alternate JTAG interface */ 2677 #define IOSS_HSIOM_ALTJTAG_PRESENT 0u 2678 /* Mask of SMARTIO instances presence */ 2679 #define IOSS_SMARTIO_SMARTIO_MASK 0u 2680 /* Base address for USBHSDEV SLOW SLAV access */ 2681 #define MXS40USBHSDEV_CHIP_TOP_USBHSDEV_ADDR 0x30000000u 2682 /* Mask for USBHSDEV SLOW SLAV access */ 2683 #define MXS40USBHSDEV_CHIP_TOP_USBHSDEV_MASK 0xFF000000u 2684 /* Number of endpoints in Ingress path of EPM (16=Max) */ 2685 #define MXS40USBHSDEV_USBHSDEV_IGRS_NUM_EP 16u 2686 /* Number of endpoints in Egress path of EPM (16=Max) */ 2687 #define MXS40USBHSDEV_USBHSDEV_EGRS_NUM_EP 16u 2688 /* Allows direct map of EPM SRAMs on MMIO (0=None, 1=Supported) */ 2689 #define MXS40USBHSDEV_USBHSDEV_MMIO_EPM_SUPPORT 1u 2690 /* Instantiates PLL and dreive clk60 output */ 2691 #define MXS40USBHSDEV_USBHSPHY_PLL_EN 1u 2692 /* Instantiates USB as as PHY when enabled. When not enabled, eUSB PHY will be 2693 instantiated. */ 2694 #define MXS40USBHSDEV_USBHSPHY_USB_EN 1u 2695 /* Instantiates VREFGEN module */ 2696 #define MXS40USBHSDEV_USBHSPHY_VREFGEN_EN 1u 2697 /* Instantiates IREFGEN module */ 2698 #define MXS40USBHSDEV_USBHSPHY_IREFGEN_EN 1u 2699 /* Instantiates 2p5 regulator module */ 2700 #define MXS40USBHSDEV_USBHSPHY_REG_2P5_EN 1u 2701 /* Instantiates 1p1 regulator module */ 2702 #define MXS40USBHSDEV_USBHSPHY_REG_1P1_EN 1u 2703 /* Instantiates SW_1P2 regulator module */ 2704 #define MXS40USBHSDEV_USBHSPHY_REG_SW_1P2_EN 0u 2705 /* Number of PDM structures ({2, 4, 6, 8}]). */ 2706 #define PDM_NR 2u 2707 /* The number of protection contexts ([2, 16]). */ 2708 #define PERI_PC_NR 8u 2709 /* Master interface presence mask (4 bits) */ 2710 #define PERI_MS_PRESENT 15u 2711 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 2712 #define PERI_ECC_PRESENT 0u 2713 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 2714 #define PERI_ECC_ADDR_PRESENT 0u 2715 /* Clock control functionality present ('0': no, '1': yes) */ 2716 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2717 /* Slave present (0:No, 1:Yes) */ 2718 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2719 /* Slave present (0:No, 1:Yes) */ 2720 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2721 /* Slave present (0:No, 1:Yes) */ 2722 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2723 /* Slave present (0:No, 1:Yes) */ 2724 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2725 /* Slave present (0:No, 1:Yes) */ 2726 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2727 /* Slave present (0:No, 1:Yes) */ 2728 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2729 /* Slave present (0:No, 1:Yes) */ 2730 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2731 /* Slave present (0:No, 1:Yes) */ 2732 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2733 /* Slave present (0:No, 1:Yes) */ 2734 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2735 /* Slave present (0:No, 1:Yes) */ 2736 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2737 /* Slave present (0:No, 1:Yes) */ 2738 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2739 /* Slave present (0:No, 1:Yes) */ 2740 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2741 /* Slave present (0:No, 1:Yes) */ 2742 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2743 /* Slave present (0:No, 1:Yes) */ 2744 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2745 /* Slave present (0:No, 1:Yes) */ 2746 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2747 /* Slave present (0:No, 1:Yes) */ 2748 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2749 /* Clock control functionality present ('0': no, '1': yes) */ 2750 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2751 /* Slave present (0:No, 1:Yes) */ 2752 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2753 /* Slave present (0:No, 1:Yes) */ 2754 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2755 /* Slave present (0:No, 1:Yes) */ 2756 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2757 /* Slave present (0:No, 1:Yes) */ 2758 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2759 /* Slave present (0:No, 1:Yes) */ 2760 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2761 /* Slave present (0:No, 1:Yes) */ 2762 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2763 /* Slave present (0:No, 1:Yes) */ 2764 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2765 /* Slave present (0:No, 1:Yes) */ 2766 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2767 /* Slave present (0:No, 1:Yes) */ 2768 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2769 /* Slave present (0:No, 1:Yes) */ 2770 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2771 /* Slave present (0:No, 1:Yes) */ 2772 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2773 /* Slave present (0:No, 1:Yes) */ 2774 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2775 /* Slave present (0:No, 1:Yes) */ 2776 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2777 /* Slave present (0:No, 1:Yes) */ 2778 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2779 /* Slave present (0:No, 1:Yes) */ 2780 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2781 /* Slave present (0:No, 1:Yes) */ 2782 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2783 /* Clock control functionality present ('0': no, '1': yes) */ 2784 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2785 /* Slave present (0:No, 1:Yes) */ 2786 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2787 /* Slave present (0:No, 1:Yes) */ 2788 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2789 /* Slave present (0:No, 1:Yes) */ 2790 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2791 /* Slave present (0:No, 1:Yes) */ 2792 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2793 /* Slave present (0:No, 1:Yes) */ 2794 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2795 /* Slave present (0:No, 1:Yes) */ 2796 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2797 /* Slave present (0:No, 1:Yes) */ 2798 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2799 /* Slave present (0:No, 1:Yes) */ 2800 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2801 /* Slave present (0:No, 1:Yes) */ 2802 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2803 /* Slave present (0:No, 1:Yes) */ 2804 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2805 /* Slave present (0:No, 1:Yes) */ 2806 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2807 /* Slave present (0:No, 1:Yes) */ 2808 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2809 /* Slave present (0:No, 1:Yes) */ 2810 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u 2811 /* Slave present (0:No, 1:Yes) */ 2812 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2813 /* Slave present (0:No, 1:Yes) */ 2814 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2815 /* Slave present (0:No, 1:Yes) */ 2816 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2817 /* Clock control functionality present ('0': no, '1': yes) */ 2818 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2819 /* Slave present (0:No, 1:Yes) */ 2820 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2821 /* Slave present (0:No, 1:Yes) */ 2822 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2823 /* Slave present (0:No, 1:Yes) */ 2824 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2825 /* Slave present (0:No, 1:Yes) */ 2826 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2827 /* Slave present (0:No, 1:Yes) */ 2828 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2829 /* Slave present (0:No, 1:Yes) */ 2830 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2831 /* Slave present (0:No, 1:Yes) */ 2832 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2833 /* Slave present (0:No, 1:Yes) */ 2834 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2835 /* Slave present (0:No, 1:Yes) */ 2836 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2837 /* Slave present (0:No, 1:Yes) */ 2838 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2839 /* Slave present (0:No, 1:Yes) */ 2840 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2841 /* Slave present (0:No, 1:Yes) */ 2842 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2843 /* Slave present (0:No, 1:Yes) */ 2844 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2845 /* Slave present (0:No, 1:Yes) */ 2846 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2847 /* Slave present (0:No, 1:Yes) */ 2848 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2849 /* Slave present (0:No, 1:Yes) */ 2850 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2851 /* Clock control functionality present ('0': no, '1': yes) */ 2852 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2853 /* Slave present (0:No, 1:Yes) */ 2854 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2855 /* Slave present (0:No, 1:Yes) */ 2856 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2857 /* Slave present (0:No, 1:Yes) */ 2858 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2859 /* Slave present (0:No, 1:Yes) */ 2860 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2861 /* Slave present (0:No, 1:Yes) */ 2862 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2863 /* Slave present (0:No, 1:Yes) */ 2864 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2865 /* Slave present (0:No, 1:Yes) */ 2866 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2867 /* Slave present (0:No, 1:Yes) */ 2868 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2869 /* Slave present (0:No, 1:Yes) */ 2870 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2871 /* Slave present (0:No, 1:Yes) */ 2872 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2873 /* Slave present (0:No, 1:Yes) */ 2874 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2875 /* Slave present (0:No, 1:Yes) */ 2876 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2877 /* Slave present (0:No, 1:Yes) */ 2878 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2879 /* Slave present (0:No, 1:Yes) */ 2880 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2881 /* Slave present (0:No, 1:Yes) */ 2882 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2883 /* Slave present (0:No, 1:Yes) */ 2884 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2885 /* Clock control functionality present ('0': no, '1': yes) */ 2886 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2887 /* Slave present (0:No, 1:Yes) */ 2888 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2889 /* Slave present (0:No, 1:Yes) */ 2890 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2891 /* Slave present (0:No, 1:Yes) */ 2892 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2893 /* Slave present (0:No, 1:Yes) */ 2894 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2895 /* Slave present (0:No, 1:Yes) */ 2896 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2897 /* Slave present (0:No, 1:Yes) */ 2898 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2899 /* Slave present (0:No, 1:Yes) */ 2900 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2901 /* Slave present (0:No, 1:Yes) */ 2902 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2903 /* Slave present (0:No, 1:Yes) */ 2904 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2905 /* Slave present (0:No, 1:Yes) */ 2906 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2907 /* Slave present (0:No, 1:Yes) */ 2908 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2909 /* Slave present (0:No, 1:Yes) */ 2910 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2911 /* Slave present (0:No, 1:Yes) */ 2912 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2913 /* Slave present (0:No, 1:Yes) */ 2914 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2915 /* Slave present (0:No, 1:Yes) */ 2916 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2917 /* Slave present (0:No, 1:Yes) */ 2918 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2919 /* Clock control functionality present ('0': no, '1': yes) */ 2920 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2921 /* Slave present (0:No, 1:Yes) */ 2922 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2923 /* Slave present (0:No, 1:Yes) */ 2924 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2925 /* Slave present (0:No, 1:Yes) */ 2926 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2927 /* Slave present (0:No, 1:Yes) */ 2928 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2929 /* Slave present (0:No, 1:Yes) */ 2930 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2931 /* Slave present (0:No, 1:Yes) */ 2932 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2933 /* Slave present (0:No, 1:Yes) */ 2934 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2935 /* Slave present (0:No, 1:Yes) */ 2936 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2937 /* Slave present (0:No, 1:Yes) */ 2938 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2939 /* Slave present (0:No, 1:Yes) */ 2940 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2941 /* Slave present (0:No, 1:Yes) */ 2942 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2943 /* Slave present (0:No, 1:Yes) */ 2944 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2945 /* Slave present (0:No, 1:Yes) */ 2946 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 1u 2947 /* Slave present (0:No, 1:Yes) */ 2948 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2949 /* Slave present (0:No, 1:Yes) */ 2950 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2951 /* Slave present (0:No, 1:Yes) */ 2952 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2953 /* Clock control functionality present ('0': no, '1': yes) */ 2954 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2955 /* Slave present (0:No, 1:Yes) */ 2956 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2957 /* Slave present (0:No, 1:Yes) */ 2958 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2959 /* Slave present (0:No, 1:Yes) */ 2960 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2961 /* Slave present (0:No, 1:Yes) */ 2962 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2963 /* Slave present (0:No, 1:Yes) */ 2964 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2965 /* Slave present (0:No, 1:Yes) */ 2966 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2967 /* Slave present (0:No, 1:Yes) */ 2968 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2969 /* Slave present (0:No, 1:Yes) */ 2970 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2971 /* Slave present (0:No, 1:Yes) */ 2972 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2973 /* Slave present (0:No, 1:Yes) */ 2974 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2975 /* Slave present (0:No, 1:Yes) */ 2976 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2977 /* Slave present (0:No, 1:Yes) */ 2978 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2979 /* Slave present (0:No, 1:Yes) */ 2980 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2981 /* Slave present (0:No, 1:Yes) */ 2982 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2983 /* Slave present (0:No, 1:Yes) */ 2984 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2985 /* Slave present (0:No, 1:Yes) */ 2986 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2987 /* Clock control functionality present ('0': no, '1': yes) */ 2988 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2989 /* Slave present (0:No, 1:Yes) */ 2990 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2991 /* Slave present (0:No, 1:Yes) */ 2992 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2993 /* Slave present (0:No, 1:Yes) */ 2994 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2995 /* Slave present (0:No, 1:Yes) */ 2996 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2997 /* Slave present (0:No, 1:Yes) */ 2998 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2999 /* Slave present (0:No, 1:Yes) */ 3000 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3001 /* Slave present (0:No, 1:Yes) */ 3002 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3003 /* Slave present (0:No, 1:Yes) */ 3004 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3005 /* Slave present (0:No, 1:Yes) */ 3006 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3007 /* Slave present (0:No, 1:Yes) */ 3008 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3009 /* Slave present (0:No, 1:Yes) */ 3010 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3011 /* Slave present (0:No, 1:Yes) */ 3012 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3013 /* Slave present (0:No, 1:Yes) */ 3014 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3015 /* Slave present (0:No, 1:Yes) */ 3016 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3017 /* Slave present (0:No, 1:Yes) */ 3018 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3019 /* Slave present (0:No, 1:Yes) */ 3020 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3021 /* Clock control functionality present ('0': no, '1': yes) */ 3022 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3023 /* Slave present (0:No, 1:Yes) */ 3024 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3025 /* Slave present (0:No, 1:Yes) */ 3026 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3027 /* Slave present (0:No, 1:Yes) */ 3028 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3029 /* Slave present (0:No, 1:Yes) */ 3030 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3031 /* Slave present (0:No, 1:Yes) */ 3032 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3033 /* Slave present (0:No, 1:Yes) */ 3034 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3035 /* Slave present (0:No, 1:Yes) */ 3036 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3037 /* Slave present (0:No, 1:Yes) */ 3038 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3039 /* Slave present (0:No, 1:Yes) */ 3040 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3041 /* Slave present (0:No, 1:Yes) */ 3042 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3043 /* Slave present (0:No, 1:Yes) */ 3044 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3045 /* Slave present (0:No, 1:Yes) */ 3046 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3047 /* Slave present (0:No, 1:Yes) */ 3048 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3049 /* Slave present (0:No, 1:Yes) */ 3050 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3051 /* Slave present (0:No, 1:Yes) */ 3052 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3053 /* Slave present (0:No, 1:Yes) */ 3054 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3055 /* Clock control functionality present ('0': no, '1': yes) */ 3056 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3057 /* Slave present (0:No, 1:Yes) */ 3058 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3059 /* Slave present (0:No, 1:Yes) */ 3060 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3061 /* Slave present (0:No, 1:Yes) */ 3062 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3063 /* Slave present (0:No, 1:Yes) */ 3064 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3065 /* Slave present (0:No, 1:Yes) */ 3066 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3067 /* Slave present (0:No, 1:Yes) */ 3068 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3069 /* Slave present (0:No, 1:Yes) */ 3070 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3071 /* Slave present (0:No, 1:Yes) */ 3072 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3073 /* Slave present (0:No, 1:Yes) */ 3074 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3075 /* Slave present (0:No, 1:Yes) */ 3076 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3077 /* Slave present (0:No, 1:Yes) */ 3078 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3079 /* Slave present (0:No, 1:Yes) */ 3080 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3081 /* Slave present (0:No, 1:Yes) */ 3082 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3083 /* Slave present (0:No, 1:Yes) */ 3084 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3085 /* Slave present (0:No, 1:Yes) */ 3086 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3087 /* Slave present (0:No, 1:Yes) */ 3088 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3089 /* Clock control functionality present ('0': no, '1': yes) */ 3090 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3091 /* Slave present (0:No, 1:Yes) */ 3092 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3093 /* Slave present (0:No, 1:Yes) */ 3094 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3095 /* Slave present (0:No, 1:Yes) */ 3096 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3097 /* Slave present (0:No, 1:Yes) */ 3098 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3099 /* Slave present (0:No, 1:Yes) */ 3100 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3101 /* Slave present (0:No, 1:Yes) */ 3102 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3103 /* Slave present (0:No, 1:Yes) */ 3104 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3105 /* Slave present (0:No, 1:Yes) */ 3106 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3107 /* Slave present (0:No, 1:Yes) */ 3108 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3109 /* Slave present (0:No, 1:Yes) */ 3110 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3111 /* Slave present (0:No, 1:Yes) */ 3112 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3113 /* Slave present (0:No, 1:Yes) */ 3114 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3115 /* Slave present (0:No, 1:Yes) */ 3116 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3117 /* Slave present (0:No, 1:Yes) */ 3118 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3119 /* Slave present (0:No, 1:Yes) */ 3120 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3121 /* Slave present (0:No, 1:Yes) */ 3122 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3123 /* Clock control functionality present ('0': no, '1': yes) */ 3124 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3125 /* Slave present (0:No, 1:Yes) */ 3126 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3127 /* Slave present (0:No, 1:Yes) */ 3128 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3129 /* Slave present (0:No, 1:Yes) */ 3130 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3131 /* Slave present (0:No, 1:Yes) */ 3132 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3133 /* Slave present (0:No, 1:Yes) */ 3134 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3135 /* Slave present (0:No, 1:Yes) */ 3136 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3137 /* Slave present (0:No, 1:Yes) */ 3138 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3139 /* Slave present (0:No, 1:Yes) */ 3140 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3141 /* Slave present (0:No, 1:Yes) */ 3142 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3143 /* Slave present (0:No, 1:Yes) */ 3144 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3145 /* Slave present (0:No, 1:Yes) */ 3146 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3147 /* Slave present (0:No, 1:Yes) */ 3148 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3149 /* Slave present (0:No, 1:Yes) */ 3150 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3151 /* Slave present (0:No, 1:Yes) */ 3152 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3153 /* Slave present (0:No, 1:Yes) */ 3154 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3155 /* Slave present (0:No, 1:Yes) */ 3156 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3157 /* Clock control functionality present ('0': no, '1': yes) */ 3158 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3159 /* Slave present (0:No, 1:Yes) */ 3160 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3161 /* Slave present (0:No, 1:Yes) */ 3162 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3163 /* Slave present (0:No, 1:Yes) */ 3164 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3165 /* Slave present (0:No, 1:Yes) */ 3166 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3167 /* Slave present (0:No, 1:Yes) */ 3168 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3169 /* Slave present (0:No, 1:Yes) */ 3170 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3171 /* Slave present (0:No, 1:Yes) */ 3172 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3173 /* Slave present (0:No, 1:Yes) */ 3174 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3175 /* Slave present (0:No, 1:Yes) */ 3176 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3177 /* Slave present (0:No, 1:Yes) */ 3178 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3179 /* Slave present (0:No, 1:Yes) */ 3180 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3181 /* Slave present (0:No, 1:Yes) */ 3182 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3183 /* Slave present (0:No, 1:Yes) */ 3184 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3185 /* Slave present (0:No, 1:Yes) */ 3186 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3187 /* Slave present (0:No, 1:Yes) */ 3188 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3189 /* Slave present (0:No, 1:Yes) */ 3190 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3191 /* Clock control functionality present ('0': no, '1': yes) */ 3192 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3193 /* Slave present (0:No, 1:Yes) */ 3194 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3195 /* Slave present (0:No, 1:Yes) */ 3196 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3197 /* Slave present (0:No, 1:Yes) */ 3198 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3199 /* Slave present (0:No, 1:Yes) */ 3200 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3201 /* Slave present (0:No, 1:Yes) */ 3202 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3203 /* Slave present (0:No, 1:Yes) */ 3204 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3205 /* Slave present (0:No, 1:Yes) */ 3206 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3207 /* Slave present (0:No, 1:Yes) */ 3208 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3209 /* Slave present (0:No, 1:Yes) */ 3210 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3211 /* Slave present (0:No, 1:Yes) */ 3212 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3213 /* Slave present (0:No, 1:Yes) */ 3214 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3215 /* Slave present (0:No, 1:Yes) */ 3216 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3217 /* Slave present (0:No, 1:Yes) */ 3218 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3219 /* Slave present (0:No, 1:Yes) */ 3220 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3221 /* Slave present (0:No, 1:Yes) */ 3222 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3223 /* Slave present (0:No, 1:Yes) */ 3224 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3225 /* Clock control functionality present ('0': no, '1': yes) */ 3226 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3227 /* Slave present (0:No, 1:Yes) */ 3228 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3229 /* Slave present (0:No, 1:Yes) */ 3230 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3231 /* Slave present (0:No, 1:Yes) */ 3232 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3233 /* Slave present (0:No, 1:Yes) */ 3234 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3235 /* Slave present (0:No, 1:Yes) */ 3236 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3237 /* Slave present (0:No, 1:Yes) */ 3238 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3239 /* Slave present (0:No, 1:Yes) */ 3240 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3241 /* Slave present (0:No, 1:Yes) */ 3242 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3243 /* Slave present (0:No, 1:Yes) */ 3244 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3245 /* Slave present (0:No, 1:Yes) */ 3246 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3247 /* Slave present (0:No, 1:Yes) */ 3248 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3249 /* Slave present (0:No, 1:Yes) */ 3250 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3251 /* Slave present (0:No, 1:Yes) */ 3252 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3253 /* Slave present (0:No, 1:Yes) */ 3254 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3255 /* Slave present (0:No, 1:Yes) */ 3256 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3257 /* Slave present (0:No, 1:Yes) */ 3258 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3259 /* Number of programmable clocks (outputs) */ 3260 #define PERI_CLOCK_NR 19u 3261 /* Number of 8.0 dividers */ 3262 #define PERI_DIV_8_NR 8u 3263 /* Number of 16.0 dividers */ 3264 #define PERI_DIV_16_NR 8u 3265 /* Number of 16.5 (fractional) dividers */ 3266 #define PERI_DIV_16_5_NR 2u 3267 /* Number of 24.5 (fractional) dividers */ 3268 #define PERI_DIV_24_5_NR 1u 3269 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 3270 #define PERI_DIV_ADDR_WIDTH 3u 3271 /* Timeout functionality present ('0': no, '1': yes) */ 3272 #define PERI_TIMEOUT_PRESENT 1u 3273 /* Trigger module present (0=No, 1=Yes) */ 3274 #define PERI_TR 1u 3275 /* Number of trigger groups */ 3276 #define PERI_TR_GROUP_NR 13u 3277 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3278 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3279 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3280 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3281 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3282 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3283 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3284 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3285 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3286 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3287 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3288 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3289 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3290 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3291 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3292 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3293 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3294 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3295 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3296 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3297 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3298 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3299 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3300 #define PERI_TR_GROUP_NR11_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3301 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3302 #define PERI_TR_GROUP_NR12_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3303 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3304 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3305 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3306 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3307 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3308 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3309 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3310 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3311 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3312 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3313 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3314 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3315 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3316 #define PERI_MASTER_WIDTH 8u 3317 /* DeepSleep support ('0':no, '1': yes) */ 3318 #define SCB0_DEEPSLEEP 1u 3319 /* Externally clocked support? ('0': no, '1': yes) */ 3320 #define SCB0_EC 1u 3321 /* I2C master support? ('0': no, '1': yes) */ 3322 #define SCB0_I2C_M 1u 3323 /* I2C slave support? ('0': no, '1': yes) */ 3324 #define SCB0_I2C_S 1u 3325 /* I2C support? (I2C_M | I2C_S) */ 3326 #define SCB0_I2C 1u 3327 /* I2C glitch filters present? ('0': no, '1': yes) */ 3328 #define SCB0_I2C_GLITCH 1u 3329 /* I2C externally clocked support? ('0': no, '1': yes) */ 3330 #define SCB0_I2C_EC 1u 3331 /* I2C master and slave support? (I2C_M & I2C_S) */ 3332 #define SCB0_I2C_M_S 1u 3333 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3334 #define SCB0_I2C_S_EC 1u 3335 /* SPI master support? ('0': no, '1': yes) */ 3336 #define SCB0_SPI_M 0u 3337 /* SPI slave support? ('0': no, '1': yes) */ 3338 #define SCB0_SPI_S 0u 3339 /* SPI support? (SPI_M | SPI_S) */ 3340 #define SCB0_SPI 0u 3341 /* SPI externally clocked support? ('0': no, '1': yes) */ 3342 #define SCB0_SPI_EC 0u 3343 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3344 #define SCB0_SPI_S_EC 0u 3345 /* UART support? ('0': no, '1': yes) */ 3346 #define SCB0_UART 1u 3347 /* SPI or UART (SPI | UART) */ 3348 #define SCB0_SPI_UART 0u 3349 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3350 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3351 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3352 #define SCB0_EZ_DATA_NR 256u 3353 /* Command/response mode support? ('0': no, '1': yes) */ 3354 #define SCB0_CMD_RESP 1u 3355 /* EZ mode support? ('0': no, '1': yes) */ 3356 #define SCB0_EZ 1u 3357 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3358 #define SCB0_EZ_CMD_RESP 1u 3359 /* I2C slave with EZ mode (I2C_S & EZ) */ 3360 #define SCB0_I2C_S_EZ 1u 3361 /* SPI slave with EZ mode (SPI_S & EZ) */ 3362 #define SCB0_SPI_S_EZ 0u 3363 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3364 #define SCB0_I2C_FAST_PLUS 1u 3365 /* Number of used spi_select signals (max 4) */ 3366 #define SCB0_CHIP_TOP_SPI_SEL_NR 0u 3367 /* DeepSleep support ('0':no, '1': yes) */ 3368 #define SCB1_DEEPSLEEP 0u 3369 /* Externally clocked support? ('0': no, '1': yes) */ 3370 #define SCB1_EC 0u 3371 /* I2C master support? ('0': no, '1': yes) */ 3372 #define SCB1_I2C_M 1u 3373 /* I2C slave support? ('0': no, '1': yes) */ 3374 #define SCB1_I2C_S 1u 3375 /* I2C support? (I2C_M | I2C_S) */ 3376 #define SCB1_I2C 1u 3377 /* I2C glitch filters present? ('0': no, '1': yes) */ 3378 #define SCB1_I2C_GLITCH 1u 3379 /* I2C externally clocked support? ('0': no, '1': yes) */ 3380 #define SCB1_I2C_EC 0u 3381 /* I2C master and slave support? (I2C_M & I2C_S) */ 3382 #define SCB1_I2C_M_S 1u 3383 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3384 #define SCB1_I2C_S_EC 0u 3385 /* SPI master support? ('0': no, '1': yes) */ 3386 #define SCB1_SPI_M 1u 3387 /* SPI slave support? ('0': no, '1': yes) */ 3388 #define SCB1_SPI_S 1u 3389 /* SPI support? (SPI_M | SPI_S) */ 3390 #define SCB1_SPI 1u 3391 /* SPI externally clocked support? ('0': no, '1': yes) */ 3392 #define SCB1_SPI_EC 0u 3393 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3394 #define SCB1_SPI_S_EC 0u 3395 /* UART support? ('0': no, '1': yes) */ 3396 #define SCB1_UART 1u 3397 /* SPI or UART (SPI | UART) */ 3398 #define SCB1_SPI_UART 1u 3399 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3400 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3401 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3402 #define SCB1_EZ_DATA_NR 256u 3403 /* Command/response mode support? ('0': no, '1': yes) */ 3404 #define SCB1_CMD_RESP 0u 3405 /* EZ mode support? ('0': no, '1': yes) */ 3406 #define SCB1_EZ 0u 3407 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3408 #define SCB1_EZ_CMD_RESP 0u 3409 /* I2C slave with EZ mode (I2C_S & EZ) */ 3410 #define SCB1_I2C_S_EZ 0u 3411 /* SPI slave with EZ mode (SPI_S & EZ) */ 3412 #define SCB1_SPI_S_EZ 0u 3413 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3414 #define SCB1_I2C_FAST_PLUS 1u 3415 /* Number of used spi_select signals (max 4) */ 3416 #define SCB1_CHIP_TOP_SPI_SEL_NR 1u 3417 /* DeepSleep support ('0':no, '1': yes) */ 3418 #define SCB2_DEEPSLEEP 0u 3419 /* Externally clocked support? ('0': no, '1': yes) */ 3420 #define SCB2_EC 1u 3421 /* I2C master support? ('0': no, '1': yes) */ 3422 #define SCB2_I2C_M 1u 3423 /* I2C slave support? ('0': no, '1': yes) */ 3424 #define SCB2_I2C_S 1u 3425 /* I2C support? (I2C_M | I2C_S) */ 3426 #define SCB2_I2C 1u 3427 /* I2C glitch filters present? ('0': no, '1': yes) */ 3428 #define SCB2_I2C_GLITCH 1u 3429 /* I2C externally clocked support? ('0': no, '1': yes) */ 3430 #define SCB2_I2C_EC 1u 3431 /* I2C master and slave support? (I2C_M & I2C_S) */ 3432 #define SCB2_I2C_M_S 1u 3433 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3434 #define SCB2_I2C_S_EC 1u 3435 /* SPI master support? ('0': no, '1': yes) */ 3436 #define SCB2_SPI_M 1u 3437 /* SPI slave support? ('0': no, '1': yes) */ 3438 #define SCB2_SPI_S 1u 3439 /* SPI support? (SPI_M | SPI_S) */ 3440 #define SCB2_SPI 1u 3441 /* SPI externally clocked support? ('0': no, '1': yes) */ 3442 #define SCB2_SPI_EC 1u 3443 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3444 #define SCB2_SPI_S_EC 1u 3445 /* UART support? ('0': no, '1': yes) */ 3446 #define SCB2_UART 1u 3447 /* SPI or UART (SPI | UART) */ 3448 #define SCB2_SPI_UART 0u 3449 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3450 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3451 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3452 #define SCB2_EZ_DATA_NR 256u 3453 /* Command/response mode support? ('0': no, '1': yes) */ 3454 #define SCB2_CMD_RESP 1u 3455 /* EZ mode support? ('0': no, '1': yes) */ 3456 #define SCB2_EZ 1u 3457 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3458 #define SCB2_EZ_CMD_RESP 1u 3459 /* I2C slave with EZ mode (I2C_S & EZ) */ 3460 #define SCB2_I2C_S_EZ 1u 3461 /* SPI slave with EZ mode (SPI_S & EZ) */ 3462 #define SCB2_SPI_S_EZ 1u 3463 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3464 #define SCB2_I2C_FAST_PLUS 1u 3465 /* Number of used spi_select signals (max 4) */ 3466 #define SCB2_CHIP_TOP_SPI_SEL_NR 1u 3467 /* DeepSleep support ('0':no, '1': yes) */ 3468 #define SCB3_DEEPSLEEP 0u 3469 /* Externally clocked support? ('0': no, '1': yes) */ 3470 #define SCB3_EC 1u 3471 /* I2C master support? ('0': no, '1': yes) */ 3472 #define SCB3_I2C_M 1u 3473 /* I2C slave support? ('0': no, '1': yes) */ 3474 #define SCB3_I2C_S 1u 3475 /* I2C support? (I2C_M | I2C_S) */ 3476 #define SCB3_I2C 1u 3477 /* I2C glitch filters present? ('0': no, '1': yes) */ 3478 #define SCB3_I2C_GLITCH 1u 3479 /* I2C externally clocked support? ('0': no, '1': yes) */ 3480 #define SCB3_I2C_EC 1u 3481 /* I2C master and slave support? (I2C_M & I2C_S) */ 3482 #define SCB3_I2C_M_S 1u 3483 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3484 #define SCB3_I2C_S_EC 1u 3485 /* SPI master support? ('0': no, '1': yes) */ 3486 #define SCB3_SPI_M 1u 3487 /* SPI slave support? ('0': no, '1': yes) */ 3488 #define SCB3_SPI_S 1u 3489 /* SPI support? (SPI_M | SPI_S) */ 3490 #define SCB3_SPI 1u 3491 /* SPI externally clocked support? ('0': no, '1': yes) */ 3492 #define SCB3_SPI_EC 1u 3493 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3494 #define SCB3_SPI_S_EC 1u 3495 /* UART support? ('0': no, '1': yes) */ 3496 #define SCB3_UART 1u 3497 /* SPI or UART (SPI | UART) */ 3498 #define SCB3_SPI_UART 0u 3499 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3500 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3501 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3502 #define SCB3_EZ_DATA_NR 256u 3503 /* Command/response mode support? ('0': no, '1': yes) */ 3504 #define SCB3_CMD_RESP 1u 3505 /* EZ mode support? ('0': no, '1': yes) */ 3506 #define SCB3_EZ 1u 3507 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3508 #define SCB3_EZ_CMD_RESP 1u 3509 /* I2C slave with EZ mode (I2C_S & EZ) */ 3510 #define SCB3_I2C_S_EZ 1u 3511 /* SPI slave with EZ mode (SPI_S & EZ) */ 3512 #define SCB3_SPI_S_EZ 1u 3513 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3514 #define SCB3_I2C_FAST_PLUS 1u 3515 /* Number of used spi_select signals (max 4) */ 3516 #define SCB3_CHIP_TOP_SPI_SEL_NR 1u 3517 /* DeepSleep support ('0':no, '1': yes) */ 3518 #define SCB4_DEEPSLEEP 0u 3519 /* Externally clocked support? ('0': no, '1': yes) */ 3520 #define SCB4_EC 1u 3521 /* I2C master support? ('0': no, '1': yes) */ 3522 #define SCB4_I2C_M 1u 3523 /* I2C slave support? ('0': no, '1': yes) */ 3524 #define SCB4_I2C_S 1u 3525 /* I2C support? (I2C_M | I2C_S) */ 3526 #define SCB4_I2C 1u 3527 /* I2C glitch filters present? ('0': no, '1': yes) */ 3528 #define SCB4_I2C_GLITCH 1u 3529 /* I2C externally clocked support? ('0': no, '1': yes) */ 3530 #define SCB4_I2C_EC 1u 3531 /* I2C master and slave support? (I2C_M & I2C_S) */ 3532 #define SCB4_I2C_M_S 1u 3533 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3534 #define SCB4_I2C_S_EC 1u 3535 /* SPI master support? ('0': no, '1': yes) */ 3536 #define SCB4_SPI_M 1u 3537 /* SPI slave support? ('0': no, '1': yes) */ 3538 #define SCB4_SPI_S 1u 3539 /* SPI support? (SPI_M | SPI_S) */ 3540 #define SCB4_SPI 1u 3541 /* SPI externally clocked support? ('0': no, '1': yes) */ 3542 #define SCB4_SPI_EC 1u 3543 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3544 #define SCB4_SPI_S_EC 1u 3545 /* UART support? ('0': no, '1': yes) */ 3546 #define SCB4_UART 1u 3547 /* SPI or UART (SPI | UART) */ 3548 #define SCB4_SPI_UART 0u 3549 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3550 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3551 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3552 #define SCB4_EZ_DATA_NR 256u 3553 /* Command/response mode support? ('0': no, '1': yes) */ 3554 #define SCB4_CMD_RESP 1u 3555 /* EZ mode support? ('0': no, '1': yes) */ 3556 #define SCB4_EZ 1u 3557 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3558 #define SCB4_EZ_CMD_RESP 1u 3559 /* I2C slave with EZ mode (I2C_S & EZ) */ 3560 #define SCB4_I2C_S_EZ 1u 3561 /* SPI slave with EZ mode (SPI_S & EZ) */ 3562 #define SCB4_SPI_S_EZ 1u 3563 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3564 #define SCB4_I2C_FAST_PLUS 1u 3565 /* Number of used spi_select signals (max 4) */ 3566 #define SCB4_CHIP_TOP_SPI_SEL_NR 1u 3567 /* DeepSleep support ('0':no, '1': yes) */ 3568 #define SCB5_DEEPSLEEP 0u 3569 /* Externally clocked support? ('0': no, '1': yes) */ 3570 #define SCB5_EC 1u 3571 /* I2C master support? ('0': no, '1': yes) */ 3572 #define SCB5_I2C_M 1u 3573 /* I2C slave support? ('0': no, '1': yes) */ 3574 #define SCB5_I2C_S 1u 3575 /* I2C support? (I2C_M | I2C_S) */ 3576 #define SCB5_I2C 1u 3577 /* I2C glitch filters present? ('0': no, '1': yes) */ 3578 #define SCB5_I2C_GLITCH 1u 3579 /* I2C externally clocked support? ('0': no, '1': yes) */ 3580 #define SCB5_I2C_EC 1u 3581 /* I2C master and slave support? (I2C_M & I2C_S) */ 3582 #define SCB5_I2C_M_S 1u 3583 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3584 #define SCB5_I2C_S_EC 1u 3585 /* SPI master support? ('0': no, '1': yes) */ 3586 #define SCB5_SPI_M 1u 3587 /* SPI slave support? ('0': no, '1': yes) */ 3588 #define SCB5_SPI_S 1u 3589 /* SPI support? (SPI_M | SPI_S) */ 3590 #define SCB5_SPI 1u 3591 /* SPI externally clocked support? ('0': no, '1': yes) */ 3592 #define SCB5_SPI_EC 1u 3593 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3594 #define SCB5_SPI_S_EC 1u 3595 /* UART support? ('0': no, '1': yes) */ 3596 #define SCB5_UART 1u 3597 /* SPI or UART (SPI | UART) */ 3598 #define SCB5_SPI_UART 0u 3599 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3600 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3601 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3602 #define SCB5_EZ_DATA_NR 256u 3603 /* Command/response mode support? ('0': no, '1': yes) */ 3604 #define SCB5_CMD_RESP 1u 3605 /* EZ mode support? ('0': no, '1': yes) */ 3606 #define SCB5_EZ 1u 3607 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3608 #define SCB5_EZ_CMD_RESP 1u 3609 /* I2C slave with EZ mode (I2C_S & EZ) */ 3610 #define SCB5_I2C_S_EZ 1u 3611 /* SPI slave with EZ mode (SPI_S & EZ) */ 3612 #define SCB5_SPI_S_EZ 1u 3613 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3614 #define SCB5_I2C_FAST_PLUS 1u 3615 /* Number of used spi_select signals (max 4) */ 3616 #define SCB5_CHIP_TOP_SPI_SEL_NR 1u 3617 /* DeepSleep support ('0':no, '1': yes) */ 3618 #define SCB6_DEEPSLEEP 0u 3619 /* Externally clocked support? ('0': no, '1': yes) */ 3620 #define SCB6_EC 1u 3621 /* I2C master support? ('0': no, '1': yes) */ 3622 #define SCB6_I2C_M 1u 3623 /* I2C slave support? ('0': no, '1': yes) */ 3624 #define SCB6_I2C_S 1u 3625 /* I2C support? (I2C_M | I2C_S) */ 3626 #define SCB6_I2C 1u 3627 /* I2C glitch filters present? ('0': no, '1': yes) */ 3628 #define SCB6_I2C_GLITCH 1u 3629 /* I2C externally clocked support? ('0': no, '1': yes) */ 3630 #define SCB6_I2C_EC 1u 3631 /* I2C master and slave support? (I2C_M & I2C_S) */ 3632 #define SCB6_I2C_M_S 1u 3633 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3634 #define SCB6_I2C_S_EC 1u 3635 /* SPI master support? ('0': no, '1': yes) */ 3636 #define SCB6_SPI_M 1u 3637 /* SPI slave support? ('0': no, '1': yes) */ 3638 #define SCB6_SPI_S 1u 3639 /* SPI support? (SPI_M | SPI_S) */ 3640 #define SCB6_SPI 1u 3641 /* SPI externally clocked support? ('0': no, '1': yes) */ 3642 #define SCB6_SPI_EC 1u 3643 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3644 #define SCB6_SPI_S_EC 1u 3645 /* UART support? ('0': no, '1': yes) */ 3646 #define SCB6_UART 1u 3647 /* SPI or UART (SPI | UART) */ 3648 #define SCB6_SPI_UART 0u 3649 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3650 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3651 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3652 #define SCB6_EZ_DATA_NR 256u 3653 /* Command/response mode support? ('0': no, '1': yes) */ 3654 #define SCB6_CMD_RESP 1u 3655 /* EZ mode support? ('0': no, '1': yes) */ 3656 #define SCB6_EZ 1u 3657 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3658 #define SCB6_EZ_CMD_RESP 1u 3659 /* I2C slave with EZ mode (I2C_S & EZ) */ 3660 #define SCB6_I2C_S_EZ 1u 3661 /* SPI slave with EZ mode (SPI_S & EZ) */ 3662 #define SCB6_SPI_S_EZ 1u 3663 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3664 #define SCB6_I2C_FAST_PLUS 1u 3665 /* Number of used spi_select signals (max 4) */ 3666 #define SCB6_CHIP_TOP_SPI_SEL_NR 4u 3667 /* SONOS Flash is used or not ('0': no, '1': yes) */ 3668 #define SFLASH_FLASHC_IS_SONOS 1u 3669 /* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ 3670 #define SFLASH_CPUSS_WOUNDING_PRESENT 0u 3671 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */ 3672 #define SMIF_MASTER_WIDTH 8u 3673 /* Base address of the SMIF XIP memory region. This address must be a multiple of 3674 the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This 3675 address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP 3676 memory region should NOT overlap with other memory regions. */ 3677 #define SMIF_SMIF_XIP_ADDR 0x18000000u 3678 /* Capacity of the SMIF XIP memory region. The more significant bits of this 3679 parameter must be '1' and the lesser significant bits of this paramter must 3680 be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are 3681 {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 3682 0xffe0:0000, ..., 0xe000:0000}. */ 3683 #define SMIF_SMIF_XIP_MASK 0xFC000000u 3684 /* Cryptography (AES) support ('0' = no support, '1' = support) */ 3685 #define SMIF_CRYPTO 1u 3686 /* Number of external devices supported ([1,4]) */ 3687 #define SMIF_DEVICE_NR 4u 3688 /* External device write support. This is a 4-bit field. Each external device has 3689 a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ 3690 #define SMIF_DEVICE_WR_EN 15u 3691 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 3692 pins) */ 3693 #define SMIF_CHIP_TOP_DATA8_PRESENT 1u 3694 /* Number of used spi_select signals (max 4) */ 3695 #define SMIF_CHIP_TOP_SPI_SEL_NR 4u 3696 /* Number of regulator modules instantiated within SRSS, start with estimate, 3697 update after CMR feedback */ 3698 #define SRSS_NUM_ACTREG_PWRMOD 4u 3699 /* Number of shorting switches between vccd and vccact (target dynamic voltage 3700 drop < 10mV) */ 3701 #define SRSS_NUM_ACTIVE_SWITCH 6u 3702 /* ULP linear regulator system is present */ 3703 #define SRSS_ULPLINREG_PRESENT 1u 3704 /* HT linear regulator system is present */ 3705 #define SRSS_HTLINREG_PRESENT 0u 3706 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 3707 or SIMOBUCK_PRESENT. */ 3708 #define SRSS_BUCKCTL_PRESENT 0u 3709 /* Low-current SISO buck core regulator is present. Only compatible with ULP 3710 linear regulator system (ULPLINREG_PRESENT==1). */ 3711 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 3712 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 3713 system (ULPLINREG_PRESENT==1). */ 3714 #define SRSS_SIMOBUCK_PRESENT 0u 3715 /* Precision ILO (PILO) is present */ 3716 #define SRSS_PILO_PRESENT 0u 3717 /* External Crystal Oscillator is present (high frequency) */ 3718 #define SRSS_ECO_PRESENT 1u 3719 /* System Buck-Boost is present */ 3720 #define SRSS_SYSBB_PRESENT 0u 3721 /* Number of clock paths. Must be > 0 */ 3722 #define SRSS_NUM_CLKPATH 5u 3723 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 3724 #define SRSS_NUM_PLL 2u 3725 /* Number of HFCLK roots present. Must be > 0 */ 3726 #define SRSS_NUM_HFROOT 6u 3727 /* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ 3728 #define SRSS_NUM_HIBDATA 1u 3729 /* Backup domain is present (includes RTC and WCO) */ 3730 #define SRSS_BACKUP_PRESENT 0u 3731 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 3732 mask indicates presence of a CSV. */ 3733 #define SRSS_MASK_HFCSV 0u 3734 /* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ 3735 #define SRSS_WCOCSV_PRESENT 0u 3736 /* Number of software watchdog timers. */ 3737 #define SRSS_NUM_MCWDT 2u 3738 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 3739 #define SRSS_NUM_DSI 0u 3740 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 3741 #define SRSS_ALTHF_PRESENT 1u 3742 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 3743 #define SRSS_ALTLF_PRESENT 0u 3744 /* Use the hardened clkactfllmux block */ 3745 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 3746 /* Number of clock paths, including direct paths in hardened clkactfllmux block 3747 (Must be >= NUM_CLKPATH) */ 3748 #define SRSS_HARD_CLKPATH 6u 3749 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= 3750 NUM_PLL+1) */ 3751 #define SRSS_HARD_CLKPATHMUX 6u 3752 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ 3753 #define SRSS_HARD_HFROOT 6u 3754 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ 3755 #define SRSS_HARD_ECOMUX_PRESENT 1u 3756 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ 3757 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 3758 /* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for 3759 PSoC6ABLE2, PSoC6A2M. */ 3760 #define SRSS_SRSS_VER1P3 1u 3761 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 3762 #define SRSS_BACKUP_BMEM_PRESENT 0u 3763 /* Number of Backup registers to include (each is 32b). Only used when 3764 BACKUP_PRESENT==1. */ 3765 #define SRSS_BACKUP_NUM_BREG 16u 3766 /* Number of counters per IP (1..32) */ 3767 #define TCPWM_CNT_NR 8u 3768 /* Counter width (in number of bits) */ 3769 #define TCPWM_CNT_CNT_WIDTH 32u 3770 /* Number of AHB-Lite "hmaster[]" bits ([4, 8]). */ 3771 #define TDM_MASTER_WIDTH 8u 3772 /* Number of TDM structures ({1, 2, 3, 4}]). */ 3773 #define TDM_NR 1u 3774 /* Number of channels per TDM structure. */ 3775 #define TDM_NR_CH_NR 2u 3776 /* Number of channels per TDM structure. */ 3777 #define TDM_NR_TDM_RX_STRUCT_CH_NR 2u 3778 /* Number of channels per TDM structure. */ 3779 #define TDM_NR_TDM_TX_STRUCT_CH_NR 2u 3780 /* Spare Enable 0=no spare, 1=max, 2=min */ 3781 #define TDM_SPARE_EN 1u 3782 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 3783 8=T28HPL, 9=T28HPC */ 3784 #define TDM_PLATFORM_VARIANT 1u 3785 /* SRAM vendor ({0=Cypress, 1=Synopsys, 2=ARM, 3=BRCM}) */ 3786 #define TDM_RAM_VEND 1u 3787 /* Use mxsramwrap IP */ 3788 #define TDM_MXSRAMWRAP_EN 1u 3789 /* Number of connected clocks at the IP's top level ([1, 4]). */ 3790 #define TDM_CHIP_TOP_CLK_NR 1u 3791 /* Replay functionality for transmitter. This functionality adds significant 3792 silicon area. */ 3793 #define TDM_TDM_TX_STRUCT_REPLAY_PRESENT 0u 3794 3795 /* MMIO Targets Defines */ 3796 /* MMIO1.CRYPTO */ 3797 #define CY_MMIO_CRYPTO_GROUP_NR 1u 3798 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 3799 /* MMIO2.CPUSS */ 3800 #define CY_MMIO_CPUSS_GROUP_NR 2u 3801 #define CY_MMIO_CPUSS_SLAVE_NR 0u 3802 /* MMIO2.FAULT */ 3803 #define CY_MMIO_FAULT_GROUP_NR 2u 3804 #define CY_MMIO_FAULT_SLAVE_NR 1u 3805 /* MMIO2.IPC */ 3806 #define CY_MMIO_IPC_GROUP_NR 2u 3807 #define CY_MMIO_IPC_SLAVE_NR 2u 3808 /* MMIO2.PROT */ 3809 #define CY_MMIO_PROT_GROUP_NR 2u 3810 #define CY_MMIO_PROT_SLAVE_NR 3u 3811 /* MMIO2.FLASHC */ 3812 #define CY_MMIO_FLASHC_GROUP_NR 2u 3813 #define CY_MMIO_FLASHC_SLAVE_NR 4u 3814 /* MMIO2.SRSS */ 3815 #define CY_MMIO_SRSS_GROUP_NR 2u 3816 #define CY_MMIO_SRSS_SLAVE_NR 6u 3817 /* MMIO2.DW */ 3818 #define CY_MMIO_DW_GROUP_NR 2u 3819 #define CY_MMIO_DW_SLAVE_NR 8u 3820 /* MMIO2.DMAC */ 3821 #define CY_MMIO_DMAC_GROUP_NR 2u 3822 #define CY_MMIO_DMAC_SLAVE_NR 10u 3823 /* MMIO2.EFUSE */ 3824 #define CY_MMIO_EFUSE_GROUP_NR 2u 3825 #define CY_MMIO_EFUSE_SLAVE_NR 12u 3826 /* MMIO3.HSIOM */ 3827 #define CY_MMIO_HSIOM_GROUP_NR 3u 3828 #define CY_MMIO_HSIOM_SLAVE_NR 0u 3829 /* MMIO3.GPIO */ 3830 #define CY_MMIO_GPIO_GROUP_NR 3u 3831 #define CY_MMIO_GPIO_SLAVE_NR 1u 3832 /* MMIO3.PDM0 */ 3833 #define CY_MMIO_PDM0_GROUP_NR 3u 3834 #define CY_MMIO_PDM0_SLAVE_NR 2u 3835 /* MMIO4.TCPWM0 */ 3836 #define CY_MMIO_TCPWM0_GROUP_NR 4u 3837 #define CY_MMIO_TCPWM0_SLAVE_NR 0u 3838 /* MMIO4.SMIF0 */ 3839 #define CY_MMIO_SMIF0_GROUP_NR 4u 3840 #define CY_MMIO_SMIF0_SLAVE_NR 1u 3841 /* MMIO4.USBFS0 */ 3842 #define CY_MMIO_USBFS0_GROUP_NR 4u 3843 #define CY_MMIO_USBFS0_SLAVE_NR 2u 3844 /* MMIO4.USBHSDEV */ 3845 #define CY_MMIO_USBHSDEV_GROUP_NR 4u 3846 #define CY_MMIO_USBHSDEV_SLAVE_NR 3u 3847 /* MMIO5.SCB0 */ 3848 #define CY_MMIO_SCB0_GROUP_NR 5u 3849 #define CY_MMIO_SCB0_SLAVE_NR 0u 3850 /* MMIO5.SCB1 */ 3851 #define CY_MMIO_SCB1_GROUP_NR 5u 3852 #define CY_MMIO_SCB1_SLAVE_NR 1u 3853 /* MMIO5.SCB2 */ 3854 #define CY_MMIO_SCB2_GROUP_NR 5u 3855 #define CY_MMIO_SCB2_SLAVE_NR 2u 3856 /* MMIO5.SCB3 */ 3857 #define CY_MMIO_SCB3_GROUP_NR 5u 3858 #define CY_MMIO_SCB3_SLAVE_NR 3u 3859 /* MMIO5.SCB4 */ 3860 #define CY_MMIO_SCB4_GROUP_NR 5u 3861 #define CY_MMIO_SCB4_SLAVE_NR 4u 3862 /* MMIO5.SCB5 */ 3863 #define CY_MMIO_SCB5_GROUP_NR 5u 3864 #define CY_MMIO_SCB5_SLAVE_NR 5u 3865 /* MMIO5.SCB6 */ 3866 #define CY_MMIO_SCB6_GROUP_NR 5u 3867 #define CY_MMIO_SCB6_SLAVE_NR 6u 3868 /* MMIO5.CANFD0 */ 3869 #define CY_MMIO_CANFD0_GROUP_NR 5u 3870 #define CY_MMIO_CANFD0_SLAVE_NR 8u 3871 /* MMIO5.TDM0 */ 3872 #define CY_MMIO_TDM0_GROUP_NR 5u 3873 #define CY_MMIO_TDM0_SLAVE_NR 10u 3874 /* MMIO6.MAIN_REG */ 3875 #define CY_MMIO_MAIN_REG_GROUP_NR 6u 3876 #define CY_MMIO_MAIN_REG_SLAVE_NR 4u 3877 /* MMIO6.USB32DEV */ 3878 #define CY_MMIO_USB32DEV_GROUP_NR 6u 3879 #define CY_MMIO_USB32DEV_SLAVE_NR 8u 3880 /* MMIO6.LVDSSS */ 3881 #define CY_MMIO_LVDSSS_GROUP_NR 6u 3882 #define CY_MMIO_LVDSSS_SLAVE_NR 12u 3883 3884 /* Backward compatibility definitions */ 3885 #define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR 3886 #define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR 3887 3888 /******************************************************************************* 3889 * BACKUP 3890 *******************************************************************************/ 3891 #define BACKUP_BASE 0x40270000UL 3892 #define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ 3893 3894 /* Protection regions */ 3895 typedef enum 3896 { 3897 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00002000 */ 3898 PROT_PERI_GR0_GROUP = 1, /* Address 0x40004010, size 0x00000004 */ 3899 PROT_PERI_GR1_GROUP = 2, /* Address 0x40004030, size 0x00000004 */ 3900 PROT_PERI_GR2_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 3901 PROT_PERI_GR3_GROUP = 4, /* Address 0x40004060, size 0x00000020 */ 3902 PROT_PERI_GR4_GROUP = 5, /* Address 0x40004080, size 0x00000020 */ 3903 PROT_PERI_GR5_GROUP = 6, /* Address 0x400040a0, size 0x00000020 */ 3904 PROT_PERI_GR6_GROUP = 7, /* Address 0x400040c0, size 0x00000020 */ 3905 PROT_PERI_TR = 8, /* Address 0x40008000, size 0x00008000 */ 3906 PROT_CRYPTO_MAIN = 9, /* Address 0x40100000, size 0x00000400 */ 3907 PROT_CRYPTO_CRYPTO = 10, /* Address 0x40101000, size 0x00000800 */ 3908 PROT_CRYPTO_BOOT = 11, /* Address 0x40102000, size 0x00000100 */ 3909 PROT_CRYPTO_KEY0 = 12, /* Address 0x40102100, size 0x00000004 */ 3910 PROT_CRYPTO_KEY1 = 13, /* Address 0x40102120, size 0x00000004 */ 3911 PROT_CRYPTO_BUF = 14, /* Address 0x40108000, size 0x00002000 */ 3912 PROT_CPUSS_CM4 = 15, /* Address 0x40200000, size 0x00000400 */ 3913 PROT_CPUSS_CM0 = 16, /* Address 0x40201000, size 0x00001000 */ 3914 PROT_CPUSS_BOOT = 17, /* Address 0x40202000, size 0x00000200 */ 3915 PROT_CPUSS_CM0_INT = 18, /* Address 0x40208000, size 0x00000400 */ 3916 PROT_CPUSS_CM4_INT = 19, /* Address 0x4020a000, size 0x00000400 */ 3917 PROT_IPC_STRUCT0_IPC = 20, /* Address 0x40220000, size 0x00000020 */ 3918 PROT_IPC_STRUCT1_IPC = 21, /* Address 0x40220020, size 0x00000020 */ 3919 PROT_IPC_STRUCT2_IPC = 22, /* Address 0x40220040, size 0x00000020 */ 3920 PROT_IPC_STRUCT3_IPC = 23, /* Address 0x40220060, size 0x00000020 */ 3921 PROT_IPC_STRUCT4_IPC = 24, /* Address 0x40220080, size 0x00000020 */ 3922 PROT_IPC_STRUCT5_IPC = 25, /* Address 0x402200a0, size 0x00000020 */ 3923 PROT_IPC_STRUCT6_IPC = 26, /* Address 0x402200c0, size 0x00000020 */ 3924 PROT_IPC_STRUCT7_IPC = 27, /* Address 0x402200e0, size 0x00000020 */ 3925 PROT_IPC_STRUCT8_IPC = 28, /* Address 0x40220100, size 0x00000020 */ 3926 PROT_IPC_STRUCT9_IPC = 29, /* Address 0x40220120, size 0x00000020 */ 3927 PROT_IPC_STRUCT10_IPC = 30, /* Address 0x40220140, size 0x00000020 */ 3928 PROT_IPC_STRUCT11_IPC = 31, /* Address 0x40220160, size 0x00000020 */ 3929 PROT_IPC_STRUCT12_IPC = 32, /* Address 0x40220180, size 0x00000020 */ 3930 PROT_IPC_STRUCT13_IPC = 33, /* Address 0x402201a0, size 0x00000020 */ 3931 PROT_IPC_STRUCT14_IPC = 34, /* Address 0x402201c0, size 0x00000020 */ 3932 PROT_IPC_STRUCT15_IPC = 35, /* Address 0x402201e0, size 0x00000020 */ 3933 PROT_IPC_INTR_STRUCT0_INTR = 36, /* Address 0x40221000, size 0x00000010 */ 3934 PROT_IPC_INTR_STRUCT1_INTR = 37, /* Address 0x40221020, size 0x00000010 */ 3935 PROT_IPC_INTR_STRUCT2_INTR = 38, /* Address 0x40221040, size 0x00000010 */ 3936 PROT_IPC_INTR_STRUCT3_INTR = 39, /* Address 0x40221060, size 0x00000010 */ 3937 PROT_IPC_INTR_STRUCT4_INTR = 40, /* Address 0x40221080, size 0x00000010 */ 3938 PROT_IPC_INTR_STRUCT5_INTR = 41, /* Address 0x402210a0, size 0x00000010 */ 3939 PROT_IPC_INTR_STRUCT6_INTR = 42, /* Address 0x402210c0, size 0x00000010 */ 3940 PROT_IPC_INTR_STRUCT7_INTR = 43, /* Address 0x402210e0, size 0x00000010 */ 3941 PROT_IPC_INTR_STRUCT8_INTR = 44, /* Address 0x40221100, size 0x00000010 */ 3942 PROT_IPC_INTR_STRUCT9_INTR = 45, /* Address 0x40221120, size 0x00000010 */ 3943 PROT_IPC_INTR_STRUCT10_INTR = 46, /* Address 0x40221140, size 0x00000010 */ 3944 PROT_IPC_INTR_STRUCT11_INTR = 47, /* Address 0x40221160, size 0x00000010 */ 3945 PROT_IPC_INTR_STRUCT12_INTR = 48, /* Address 0x40221180, size 0x00000010 */ 3946 PROT_IPC_INTR_STRUCT13_INTR = 49, /* Address 0x402211a0, size 0x00000010 */ 3947 PROT_IPC_INTR_STRUCT14_INTR = 50, /* Address 0x402211c0, size 0x00000010 */ 3948 PROT_IPC_INTR_STRUCT15_INTR = 51, /* Address 0x402211e0, size 0x00000010 */ 3949 PROT_PROT_SMPU_MAIN = 52, /* Address 0x40230000, size 0x00000040 */ 3950 PROT_PROT_MPU0_MAIN = 53, /* Address 0x40234000, size 0x00000004 */ 3951 PROT_PROT_MPU14_MAIN = 54, /* Address 0x40237800, size 0x00000004 */ 3952 PROT_PROT_MPU15_MAIN = 55, /* Address 0x40237c00, size 0x00000400 */ 3953 PROT_FLASHC_MAIN = 56, /* Address 0x40240000, size 0x00000008 */ 3954 PROT_FLASHC_CMD = 57, /* Address 0x40240008, size 0x00000004 */ 3955 PROT_FLASHC_DFT = 58, /* Address 0x40240200, size 0x00000100 */ 3956 PROT_FLASHC_CM0 = 59, /* Address 0x40240400, size 0x00000080 */ 3957 PROT_FLASHC_CM4 = 60, /* Address 0x40240480, size 0x00000080 */ 3958 PROT_FLASHC_CRYPTO = 61, /* Address 0x40240500, size 0x00000004 */ 3959 PROT_FLASHC_DW0 = 62, /* Address 0x40240580, size 0x00000004 */ 3960 PROT_FLASHC_DW1 = 63, /* Address 0x40240600, size 0x00000004 */ 3961 PROT_FLASHC_DMAC = 64, /* Address 0x40240680, size 0x00000004 */ 3962 PROT_FLASHC_FM = 65, /* Address 0x4024f000, size 0x00001000 */ 3963 PROT_SRSS_MAIN1 = 66, /* Address 0x40260000, size 0x00000100 */ 3964 PROT_SRSS_MAIN2 = 67, /* Address 0x40260100, size 0x00000010 */ 3965 PROT_WDT = 68, /* Address 0x40260180, size 0x00000010 */ 3966 PROT_MAIN = 69, /* Address 0x40260200, size 0x00000080 */ 3967 PROT_SRSS_MAIN3 = 70, /* Address 0x40260300, size 0x00000100 */ 3968 PROT_SRSS_MAIN4 = 71, /* Address 0x40260400, size 0x00000400 */ 3969 PROT_SRSS_MAIN5 = 72, /* Address 0x40260800, size 0x00000008 */ 3970 PROT_SRSS_MAIN6 = 73, /* Address 0x40267000, size 0x00001000 */ 3971 PROT_SRSS_MAIN7 = 74, /* Address 0x4026ff00, size 0x00000080 */ 3972 PROT_DW0_DW = 75, /* Address 0x40280000, size 0x00000080 */ 3973 PROT_DW1_DW = 76, /* Address 0x40290000, size 0x00000080 */ 3974 PROT_DW0_DW_CRC = 77, /* Address 0x40280100, size 0x00000080 */ 3975 PROT_DW1_DW_CRC = 78, /* Address 0x40290100, size 0x00000080 */ 3976 PROT_DW0_CH_STRUCT0_CH = 79, /* Address 0x40288000, size 0x00000040 */ 3977 PROT_DW0_CH_STRUCT1_CH = 80, /* Address 0x40288040, size 0x00000040 */ 3978 PROT_DW0_CH_STRUCT2_CH = 81, /* Address 0x40288080, size 0x00000040 */ 3979 PROT_DW0_CH_STRUCT3_CH = 82, /* Address 0x402880c0, size 0x00000040 */ 3980 PROT_DW0_CH_STRUCT4_CH = 83, /* Address 0x40288100, size 0x00000040 */ 3981 PROT_DW0_CH_STRUCT5_CH = 84, /* Address 0x40288140, size 0x00000040 */ 3982 PROT_DW0_CH_STRUCT6_CH = 85, /* Address 0x40288180, size 0x00000040 */ 3983 PROT_DW0_CH_STRUCT7_CH = 86, /* Address 0x402881c0, size 0x00000040 */ 3984 PROT_DW0_CH_STRUCT8_CH = 87, /* Address 0x40288200, size 0x00000040 */ 3985 PROT_DW0_CH_STRUCT9_CH = 88, /* Address 0x40288240, size 0x00000040 */ 3986 PROT_DW0_CH_STRUCT10_CH = 89, /* Address 0x40288280, size 0x00000040 */ 3987 PROT_DW0_CH_STRUCT11_CH = 90, /* Address 0x402882c0, size 0x00000040 */ 3988 PROT_DW0_CH_STRUCT12_CH = 91, /* Address 0x40288300, size 0x00000040 */ 3989 PROT_DW0_CH_STRUCT13_CH = 92, /* Address 0x40288340, size 0x00000040 */ 3990 PROT_DW0_CH_STRUCT14_CH = 93, /* Address 0x40288380, size 0x00000040 */ 3991 PROT_DW0_CH_STRUCT15_CH = 94, /* Address 0x402883c0, size 0x00000040 */ 3992 PROT_DW0_CH_STRUCT16_CH = 95, /* Address 0x40288400, size 0x00000040 */ 3993 PROT_DW0_CH_STRUCT17_CH = 96, /* Address 0x40288440, size 0x00000040 */ 3994 PROT_DW0_CH_STRUCT18_CH = 97, /* Address 0x40288480, size 0x00000040 */ 3995 PROT_DW0_CH_STRUCT19_CH = 98, /* Address 0x402884c0, size 0x00000040 */ 3996 PROT_DW0_CH_STRUCT20_CH = 99, /* Address 0x40288500, size 0x00000040 */ 3997 PROT_DW0_CH_STRUCT21_CH = 100, /* Address 0x40288540, size 0x00000040 */ 3998 PROT_DW0_CH_STRUCT22_CH = 101, /* Address 0x40288580, size 0x00000040 */ 3999 PROT_DW0_CH_STRUCT23_CH = 102, /* Address 0x402885c0, size 0x00000040 */ 4000 PROT_DW0_CH_STRUCT24_CH = 103, /* Address 0x40288600, size 0x00000040 */ 4001 PROT_DW0_CH_STRUCT25_CH = 104, /* Address 0x40288640, size 0x00000040 */ 4002 PROT_DW0_CH_STRUCT26_CH = 105, /* Address 0x40288680, size 0x00000040 */ 4003 PROT_DW0_CH_STRUCT27_CH = 106, /* Address 0x402886c0, size 0x00000040 */ 4004 PROT_DW0_CH_STRUCT28_CH = 107, /* Address 0x40288700, size 0x00000040 */ 4005 PROT_DW0_CH_STRUCT29_CH = 108, /* Address 0x40288740, size 0x00000040 */ 4006 PROT_DW0_CH_STRUCT30_CH = 109, /* Address 0x40288780, size 0x00000040 */ 4007 PROT_DW0_CH_STRUCT31_CH = 110, /* Address 0x402887c0, size 0x00000040 */ 4008 PROT_DW1_CH_STRUCT0_CH = 111, /* Address 0x40298000, size 0x00000040 */ 4009 PROT_DW1_CH_STRUCT1_CH = 112, /* Address 0x40298040, size 0x00000040 */ 4010 PROT_DW1_CH_STRUCT2_CH = 113, /* Address 0x40298080, size 0x00000040 */ 4011 PROT_DW1_CH_STRUCT3_CH = 114, /* Address 0x402980c0, size 0x00000040 */ 4012 PROT_DW1_CH_STRUCT4_CH = 115, /* Address 0x40298100, size 0x00000040 */ 4013 PROT_DW1_CH_STRUCT5_CH = 116, /* Address 0x40298140, size 0x00000040 */ 4014 PROT_DW1_CH_STRUCT6_CH = 117, /* Address 0x40298180, size 0x00000040 */ 4015 PROT_DW1_CH_STRUCT7_CH = 118, /* Address 0x402981c0, size 0x00000040 */ 4016 PROT_DW1_CH_STRUCT8_CH = 119, /* Address 0x40298200, size 0x00000040 */ 4017 PROT_DW1_CH_STRUCT9_CH = 120, /* Address 0x40298240, size 0x00000040 */ 4018 PROT_DW1_CH_STRUCT10_CH = 121, /* Address 0x40298280, size 0x00000040 */ 4019 PROT_DW1_CH_STRUCT11_CH = 122, /* Address 0x402982c0, size 0x00000040 */ 4020 PROT_DW1_CH_STRUCT12_CH = 123, /* Address 0x40298300, size 0x00000040 */ 4021 PROT_DW1_CH_STRUCT13_CH = 124, /* Address 0x40298340, size 0x00000040 */ 4022 PROT_DW1_CH_STRUCT14_CH = 125, /* Address 0x40298380, size 0x00000040 */ 4023 PROT_DW1_CH_STRUCT15_CH = 126, /* Address 0x402983c0, size 0x00000040 */ 4024 PROT_DW1_CH_STRUCT16_CH = 127, /* Address 0x40298400, size 0x00000040 */ 4025 PROT_DW1_CH_STRUCT17_CH = 128, /* Address 0x40298440, size 0x00000040 */ 4026 PROT_DW1_CH_STRUCT18_CH = 129, /* Address 0x40298480, size 0x00000040 */ 4027 PROT_DW1_CH_STRUCT19_CH = 130, /* Address 0x402984c0, size 0x00000040 */ 4028 PROT_DW1_CH_STRUCT20_CH = 131, /* Address 0x40298500, size 0x00000040 */ 4029 PROT_DW1_CH_STRUCT21_CH = 132, /* Address 0x40298540, size 0x00000040 */ 4030 PROT_DW1_CH_STRUCT22_CH = 133, /* Address 0x40298580, size 0x00000040 */ 4031 PROT_DW1_CH_STRUCT23_CH = 134, /* Address 0x402985c0, size 0x00000040 */ 4032 PROT_DW1_CH_STRUCT24_CH = 135, /* Address 0x40298600, size 0x00000040 */ 4033 PROT_DW1_CH_STRUCT25_CH = 136, /* Address 0x40298640, size 0x00000040 */ 4034 PROT_DW1_CH_STRUCT26_CH = 137, /* Address 0x40298680, size 0x00000040 */ 4035 PROT_DW1_CH_STRUCT27_CH = 138, /* Address 0x402986c0, size 0x00000040 */ 4036 PROT_DW1_CH_STRUCT28_CH = 139, /* Address 0x40298700, size 0x00000040 */ 4037 PROT_DW1_CH_STRUCT29_CH = 140, /* Address 0x40298740, size 0x00000040 */ 4038 PROT_DW1_CH_STRUCT30_CH = 141, /* Address 0x40298780, size 0x00000040 */ 4039 PROT_DW1_CH_STRUCT31_CH = 142, /* Address 0x402987c0, size 0x00000040 */ 4040 PROT_DMAC_TOP = 143, /* Address 0x402a0000, size 0x00000010 */ 4041 PROT_DMAC_CH0_CH = 144, /* Address 0x402a1000, size 0x00000100 */ 4042 PROT_DMAC_CH1_CH = 145, /* Address 0x402a1100, size 0x00000100 */ 4043 PROT_DMAC_CH2_CH = 146, /* Address 0x402a1200, size 0x00000100 */ 4044 PROT_DMAC_CH3_CH = 147, /* Address 0x402a1300, size 0x00000100 */ 4045 PROT_DMAC_CH4_CH = 148, /* Address 0x402a1400, size 0x00000100 */ 4046 PROT_DMAC_CH5_CH = 149, /* Address 0x402a1500, size 0x00000100 */ 4047 PROT_EFUSE_CTL = 150, /* Address 0x402c0000, size 0x00000080 */ 4048 PROT_EFUSE_DATA = 151, /* Address 0x402c0800, size 0x00000200 */ 4049 PROT_HSIOM_PRT0_PRT = 152, /* Address 0x40300000, size 0x00000008 */ 4050 PROT_HSIOM_PRT1_PRT = 153, /* Address 0x40300010, size 0x00000008 */ 4051 PROT_HSIOM_PRT2_PRT = 154, /* Address 0x40300020, size 0x00000008 */ 4052 PROT_HSIOM_PRT3_PRT = 155, /* Address 0x40300030, size 0x00000008 */ 4053 PROT_HSIOM_PRT4_PRT = 156, /* Address 0x40300040, size 0x00000008 */ 4054 PROT_HSIOM_PRT5_PRT = 157, /* Address 0x40300050, size 0x00000008 */ 4055 PROT_HSIOM_PRT6_PRT = 158, /* Address 0x40300060, size 0x00000008 */ 4056 PROT_HSIOM_PRT7_PRT = 159, /* Address 0x40300070, size 0x00000008 */ 4057 PROT_HSIOM_PRT8_PRT = 160, /* Address 0x40300080, size 0x00000008 */ 4058 PROT_HSIOM_PRT9_PRT = 161, /* Address 0x40300090, size 0x00000008 */ 4059 PROT_HSIOM_PRT10_PRT = 162, /* Address 0x403000a0, size 0x00000008 */ 4060 PROT_HSIOM_PRT11_PRT = 163, /* Address 0x403000b0, size 0x00000008 */ 4061 PROT_HSIOM_PRT12_PRT = 164, /* Address 0x403000c0, size 0x00000008 */ 4062 PROT_HSIOM_PRT13_PRT = 165, /* Address 0x403000d0, size 0x00000008 */ 4063 PROT_HSIOM_AMUX = 166, /* Address 0x40302000, size 0x00000010 */ 4064 PROT_HSIOM_MON = 167, /* Address 0x40302200, size 0x00000010 */ 4065 PROT_GPIO_PRT0_PRT = 168, /* Address 0x40310000, size 0x00000040 */ 4066 PROT_GPIO_PRT1_PRT = 169, /* Address 0x40310080, size 0x00000040 */ 4067 PROT_GPIO_PRT2_PRT = 170, /* Address 0x40310100, size 0x00000040 */ 4068 PROT_GPIO_PRT3_PRT = 171, /* Address 0x40310180, size 0x00000040 */ 4069 PROT_GPIO_PRT4_PRT = 172, /* Address 0x40310200, size 0x00000040 */ 4070 PROT_GPIO_PRT5_PRT = 173, /* Address 0x40310280, size 0x00000040 */ 4071 PROT_GPIO_PRT6_PRT = 174, /* Address 0x40310300, size 0x00000040 */ 4072 PROT_GPIO_PRT7_PRT = 175, /* Address 0x40310380, size 0x00000040 */ 4073 PROT_GPIO_PRT8_PRT = 176, /* Address 0x40310400, size 0x00000040 */ 4074 PROT_GPIO_PRT9_PRT = 177, /* Address 0x40310480, size 0x00000040 */ 4075 PROT_GPIO_PRT10_PRT = 178, /* Address 0x40310500, size 0x00000040 */ 4076 PROT_GPIO_PRT11_PRT = 179, /* Address 0x40310580, size 0x00000040 */ 4077 PROT_GPIO_PRT12_PRT = 180, /* Address 0x40310600, size 0x00000040 */ 4078 PROT_GPIO_PRT13_PRT = 181, /* Address 0x40310680, size 0x00000040 */ 4079 PROT_GPIO_PRT0_CFG = 182, /* Address 0x40310040, size 0x00000040 */ 4080 PROT_GPIO_PRT1_CFG = 183, /* Address 0x403100c0, size 0x00000040 */ 4081 PROT_GPIO_PRT2_CFG = 184, /* Address 0x40310140, size 0x00000008 */ 4082 PROT_GPIO_PRT3_CFG = 185, /* Address 0x403101c0, size 0x00000008 */ 4083 PROT_GPIO_PRT4_CFG = 186, /* Address 0x40310240, size 0x00000040 */ 4084 PROT_GPIO_PRT5_CFG = 187, /* Address 0x403102c0, size 0x00000040 */ 4085 PROT_GPIO_PRT6_CFG = 188, /* Address 0x40310340, size 0x00000010 */ 4086 PROT_GPIO_PRT7_CFG = 189, /* Address 0x403103c0, size 0x00000010 */ 4087 PROT_GPIO_PRT8_CFG = 190, /* Address 0x40310440, size 0x00000040 */ 4088 PROT_GPIO_PRT9_CFG = 191, /* Address 0x403104c0, size 0x00000040 */ 4089 PROT_GPIO_PRT10_CFG = 192, /* Address 0x40310540, size 0x00000040 */ 4090 PROT_GPIO_PRT11_CFG = 193, /* Address 0x403105c0, size 0x00000040 */ 4091 PROT_GPIO_PRT12_CFG = 194, /* Address 0x40310640, size 0x00000008 */ 4092 PROT_GPIO_PRT13_CFG = 195, /* Address 0x403106c0, size 0x00000040 */ 4093 PROT_GPIO_GPIO = 196, /* Address 0x40314000, size 0x00000040 */ 4094 PROT_GPIO_TEST = 197, /* Address 0x40315000, size 0x00000008 */ 4095 PROT_PDM0_MAIN = 198, /* Address 0x40320000, size 0x00000200 */ 4096 PROT_PDM0_CH0_RX = 199, /* Address 0x40328000, size 0x00000100 */ 4097 PROT_PDM0_CH1_RX = 200, /* Address 0x40328100, size 0x00000100 */ 4098 PROT_TCPWM0 = 201, /* Address 0x40400000, size 0x00010000 */ 4099 PROT_SMIF0 = 202, /* Address 0x40410000, size 0x00010000 */ 4100 PROT_USBFS0 = 203, /* Address 0x40420000, size 0x00010000 */ 4101 PROT_MXS40USBHSDEV = 204, /* Address 0x40430000, size 0x00010000 */ 4102 PROT_SCB0 = 205, /* Address 0x40500000, size 0x00010000 */ 4103 PROT_SCB1 = 206, /* Address 0x40510000, size 0x00010000 */ 4104 PROT_SCB2 = 207, /* Address 0x40520000, size 0x00010000 */ 4105 PROT_SCB3 = 208, /* Address 0x40530000, size 0x00010000 */ 4106 PROT_SCB4 = 209, /* Address 0x40540000, size 0x00010000 */ 4107 PROT_SCB5 = 210, /* Address 0x40550000, size 0x00010000 */ 4108 PROT_SCB6 = 211, /* Address 0x40560000, size 0x00010000 */ 4109 PROT_CANFD0_CH0_CH = 212, /* Address 0x40580000, size 0x00000200 */ 4110 PROT_CANFD0_MAIN = 213, /* Address 0x40581000, size 0x00000040 */ 4111 PROT_CANFD0_BUF = 214, /* Address 0x40590000, size 0x00010000 */ 4112 PROT_TDM0_TDM_STRUCT0_TDM_TX_STRUCT_TX = 215, /* Address 0x405a8000, size 0x00000100 */ 4113 PROT_TDM0_TDM_STRUCT0_TDM_RX_STRUCT_RX = 216, /* Address 0x405a8100, size 0x00000100 */ 4114 PROT_MAIN_REG = 217, /* Address 0x40640000, size 0x00001000 */ 4115 PROT_USB32DEV = 218, /* Address 0x40680000, size 0x00040000 */ 4116 PROT_LVDSSS = 219 /* Address 0x406c0000, size 0x00040000 */ 4117 } cy_en_prot_region_t; 4118 4119 #endif /* _FX3G2_CONFIG_H_ */ 4120 4121 4122 /* [] END OF FILE */ 4123
