1 /***************************************************************************//** 2 * \file psoc6_03_config.h 3 * 4 * \brief 5 * PSoC6_03 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _PSOC6_03_CONFIG_H_ 28 #define _PSOC6_03_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ 34 PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ 35 PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ 36 PCLK_SCB3_CLOCK = 0x0003u, /* scb[3].clock */ 37 PCLK_SCB4_CLOCK = 0x0004u, /* scb[4].clock */ 38 PCLK_SCB5_CLOCK = 0x0005u, /* scb[5].clock */ 39 PCLK_SCB6_CLOCK = 0x0006u, /* scb[6].clock */ 40 PCLK_SMARTIO8_CLOCK = 0x0007u, /* smartio[8].clock */ 41 PCLK_SMARTIO9_CLOCK = 0x0008u, /* smartio[9].clock */ 42 PCLK_TCPWM0_CLOCKS0 = 0x0009u, /* tcpwm[0].clocks[0] */ 43 PCLK_TCPWM0_CLOCKS1 = 0x000Au, /* tcpwm[0].clocks[1] */ 44 PCLK_TCPWM0_CLOCKS2 = 0x000Bu, /* tcpwm[0].clocks[2] */ 45 PCLK_TCPWM0_CLOCKS3 = 0x000Cu, /* tcpwm[0].clocks[3] */ 46 PCLK_TCPWM1_CLOCKS0 = 0x000Du, /* tcpwm[1].clocks[0] */ 47 PCLK_TCPWM1_CLOCKS1 = 0x000Eu, /* tcpwm[1].clocks[1] */ 48 PCLK_TCPWM1_CLOCKS2 = 0x000Fu, /* tcpwm[1].clocks[2] */ 49 PCLK_TCPWM1_CLOCKS3 = 0x0010u, /* tcpwm[1].clocks[3] */ 50 PCLK_TCPWM1_CLOCKS4 = 0x0011u, /* tcpwm[1].clocks[4] */ 51 PCLK_TCPWM1_CLOCKS5 = 0x0012u, /* tcpwm[1].clocks[5] */ 52 PCLK_TCPWM1_CLOCKS6 = 0x0013u, /* tcpwm[1].clocks[6] */ 53 PCLK_TCPWM1_CLOCKS7 = 0x0014u, /* tcpwm[1].clocks[7] */ 54 PCLK_CSD_CLOCK = 0x0015u, /* csd.clock */ 55 PCLK_LCD_CLOCK = 0x0016u, /* lcd.clock */ 56 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0017u, /* cpuss.clock_trace_in */ 57 PCLK_PASS_CLOCK_PUMP_PERI = 0x0018u, /* pass.clock_pump_peri */ 58 PCLK_PASS_CLOCK_SAR = 0x0019u, /* pass.clock_sar */ 59 PCLK_CANFD0_CLOCK_CAN0 = 0x001Au, /* canfd[0].clock_can[0] */ 60 PCLK_USB_CLOCK_DEV_BRS = 0x001Bu /* usb.clock_dev_brs */ 61 } en_clk_dst_t; 62 63 /* Trigger Group */ 64 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 65 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 66 */ 67 /* Trigger Group Inputs */ 68 /* Trigger Input Group 0 - PDMA0 Request Assignments */ 69 typedef enum 70 { 71 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 72 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 73 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 74 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 75 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 76 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 77 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 78 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 79 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ 80 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ 81 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ 82 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ 83 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ 84 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ 85 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ 86 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ 87 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 = 0x00000011u, /* tcpwm[0].tr_overflow[0] */ 88 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH0 = 0x00000012u, /* tcpwm[0].tr_compare_match[0] */ 89 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW0 = 0x00000013u, /* tcpwm[0].tr_underflow[0] */ 90 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW1 = 0x00000014u, /* tcpwm[0].tr_overflow[1] */ 91 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH1 = 0x00000015u, /* tcpwm[0].tr_compare_match[1] */ 92 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW1 = 0x00000016u, /* tcpwm[0].tr_underflow[1] */ 93 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW2 = 0x00000017u, /* tcpwm[0].tr_overflow[2] */ 94 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH2 = 0x00000018u, /* tcpwm[0].tr_compare_match[2] */ 95 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW2 = 0x00000019u, /* tcpwm[0].tr_underflow[2] */ 96 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW3 = 0x0000001Au, /* tcpwm[0].tr_overflow[3] */ 97 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH3 = 0x0000001Bu, /* tcpwm[0].tr_compare_match[3] */ 98 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW3 = 0x0000001Cu, /* tcpwm[0].tr_underflow[3] */ 99 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW0 = 0x0000001Du, /* tcpwm[1].tr_overflow[0] */ 100 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH0 = 0x0000001Eu, /* tcpwm[1].tr_compare_match[0] */ 101 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW0 = 0x0000001Fu, /* tcpwm[1].tr_underflow[0] */ 102 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW1 = 0x00000020u, /* tcpwm[1].tr_overflow[1] */ 103 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH1 = 0x00000021u, /* tcpwm[1].tr_compare_match[1] */ 104 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW1 = 0x00000022u, /* tcpwm[1].tr_underflow[1] */ 105 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW2 = 0x00000023u, /* tcpwm[1].tr_overflow[2] */ 106 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH2 = 0x00000024u, /* tcpwm[1].tr_compare_match[2] */ 107 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW2 = 0x00000025u, /* tcpwm[1].tr_underflow[2] */ 108 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW3 = 0x00000026u, /* tcpwm[1].tr_overflow[3] */ 109 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH3 = 0x00000027u, /* tcpwm[1].tr_compare_match[3] */ 110 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW3 = 0x00000028u, /* tcpwm[1].tr_underflow[3] */ 111 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW4 = 0x00000029u, /* tcpwm[1].tr_overflow[4] */ 112 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH4 = 0x0000002Au, /* tcpwm[1].tr_compare_match[4] */ 113 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW4 = 0x0000002Bu, /* tcpwm[1].tr_underflow[4] */ 114 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW5 = 0x0000002Cu, /* tcpwm[1].tr_overflow[5] */ 115 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH5 = 0x0000002Du, /* tcpwm[1].tr_compare_match[5] */ 116 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW5 = 0x0000002Eu, /* tcpwm[1].tr_underflow[5] */ 117 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW6 = 0x0000002Fu, /* tcpwm[1].tr_overflow[6] */ 118 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH6 = 0x00000030u, /* tcpwm[1].tr_compare_match[6] */ 119 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW6 = 0x00000031u, /* tcpwm[1].tr_underflow[6] */ 120 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW7 = 0x00000032u, /* tcpwm[1].tr_overflow[7] */ 121 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH7 = 0x00000033u, /* tcpwm[1].tr_compare_match[7] */ 122 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW7 = 0x00000034u, /* tcpwm[1].tr_underflow[7] */ 123 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ 124 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ 125 TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ 126 TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ 127 TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ 128 TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ 129 TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ 130 TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ 131 TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ 132 TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ 133 TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ 134 TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ 135 TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ 136 TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ 137 TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ 138 TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ 139 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ 140 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ 141 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ 142 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ 143 } en_trig_input_pdma0_tr_t; 144 145 /* Trigger Input Group 1 - PDMA1 Request Assignments */ 146 typedef enum 147 { 148 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 149 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 150 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 151 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 152 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 153 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 154 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 155 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 156 TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ 157 TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ 158 TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ 159 TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ 160 TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ 161 TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ 162 TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ 163 TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ 164 TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ 165 TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ 166 TRIG_IN_MUX_1_CSD_ADC_DONE = 0x00000145u, /* csd.tr_adc_done */ 167 TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ 168 TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ 169 TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ 170 TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ 171 TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ 172 TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ 173 TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ 174 TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ 175 TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ 176 TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ 177 TRIG_IN_MUX_1_HSIOM_TR_OUT24 = 0x00000150u, /* peri.tr_io_input[24] */ 178 TRIG_IN_MUX_1_HSIOM_TR_OUT25 = 0x00000151u, /* peri.tr_io_input[25] */ 179 TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ 180 TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u, /* lpcomp.dsi_comp1 */ 181 TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000156u /* canfd[0].tr_tmp_rtp_out[0] */ 182 } en_trig_input_pdma1_tr_t; 183 184 /* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ 185 typedef enum 186 { 187 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ 188 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ 189 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ 190 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ 191 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ 192 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ 193 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ 194 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ 195 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW0 = 0x00000209u, /* tcpwm[0].tr_overflow[0] */ 196 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH0 = 0x0000020Au, /* tcpwm[0].tr_compare_match[0] */ 197 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW0 = 0x0000020Bu, /* tcpwm[0].tr_underflow[0] */ 198 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW1 = 0x0000020Cu, /* tcpwm[0].tr_overflow[1] */ 199 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH1 = 0x0000020Du, /* tcpwm[0].tr_compare_match[1] */ 200 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW1 = 0x0000020Eu, /* tcpwm[0].tr_underflow[1] */ 201 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW2 = 0x0000020Fu, /* tcpwm[0].tr_overflow[2] */ 202 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH2 = 0x00000210u, /* tcpwm[0].tr_compare_match[2] */ 203 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW2 = 0x00000211u, /* tcpwm[0].tr_underflow[2] */ 204 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW3 = 0x00000212u, /* tcpwm[0].tr_overflow[3] */ 205 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH3 = 0x00000213u, /* tcpwm[0].tr_compare_match[3] */ 206 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW3 = 0x00000214u, /* tcpwm[0].tr_underflow[3] */ 207 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW0 = 0x00000221u, /* tcpwm[1].tr_overflow[0] */ 208 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH0 = 0x00000222u, /* tcpwm[1].tr_compare_match[0] */ 209 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW0 = 0x00000223u, /* tcpwm[1].tr_underflow[0] */ 210 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW1 = 0x00000224u, /* tcpwm[1].tr_overflow[1] */ 211 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH1 = 0x00000225u, /* tcpwm[1].tr_compare_match[1] */ 212 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW1 = 0x00000226u, /* tcpwm[1].tr_underflow[1] */ 213 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW2 = 0x00000227u, /* tcpwm[1].tr_overflow[2] */ 214 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH2 = 0x00000228u, /* tcpwm[1].tr_compare_match[2] */ 215 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW2 = 0x00000229u, /* tcpwm[1].tr_underflow[2] */ 216 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW3 = 0x0000022Au, /* tcpwm[1].tr_overflow[3] */ 217 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH3 = 0x0000022Bu, /* tcpwm[1].tr_compare_match[3] */ 218 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW3 = 0x0000022Cu, /* tcpwm[1].tr_underflow[3] */ 219 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW4 = 0x0000022Du, /* tcpwm[1].tr_overflow[4] */ 220 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH4 = 0x0000022Eu, /* tcpwm[1].tr_compare_match[4] */ 221 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW4 = 0x0000022Fu, /* tcpwm[1].tr_underflow[4] */ 222 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW5 = 0x00000230u, /* tcpwm[1].tr_overflow[5] */ 223 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH5 = 0x00000231u, /* tcpwm[1].tr_compare_match[5] */ 224 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW5 = 0x00000232u, /* tcpwm[1].tr_underflow[5] */ 225 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW6 = 0x00000233u, /* tcpwm[1].tr_overflow[6] */ 226 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH6 = 0x00000234u, /* tcpwm[1].tr_compare_match[6] */ 227 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW6 = 0x00000235u, /* tcpwm[1].tr_underflow[6] */ 228 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW7 = 0x00000236u, /* tcpwm[1].tr_overflow[7] */ 229 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH7 = 0x00000237u, /* tcpwm[1].tr_compare_match[7] */ 230 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW7 = 0x00000238u, /* tcpwm[1].tr_underflow[7] */ 231 TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ 232 TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ 233 TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ 234 TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ 235 TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ 236 TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ 237 TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ 238 TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ 239 TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ 240 TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ 241 TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ 242 TRIG_IN_MUX_2_SCB_I2C_SCL3 = 0x00000246u, /* scb[3].tr_i2c_scl_filtered */ 243 TRIG_IN_MUX_2_SCB_TX3 = 0x00000247u, /* scb[3].tr_tx_req */ 244 TRIG_IN_MUX_2_SCB_RX3 = 0x00000248u, /* scb[3].tr_rx_req */ 245 TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ 246 TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ 247 TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ 248 TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ 249 TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ 250 TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ 251 TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ 252 TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ 253 TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ 254 TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ 255 TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ 256 TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ 257 TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ 258 TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ 259 TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ 260 TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ 261 TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ 262 TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ 263 TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ 264 TRIG_IN_MUX_2_PASS_SAR_DONE = 0x00000273u, /* pass.tr_sar_out */ 265 TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ 266 TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ 267 TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ 268 TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ 269 TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ 270 TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ 271 TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ 272 TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ 273 TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ 274 TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ 275 TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ 276 TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ 277 TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ 278 TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ 279 TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ 280 TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ 281 TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ 282 TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ 283 TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u, /* lpcomp.dsi_comp1 */ 284 TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000287u /* canfd[0].tr_tmp_rtp_out[0] */ 285 } en_trig_input_tcpwm0_t; 286 287 /* Trigger Input Group 3 - TCPWM1 trigger multiplexer */ 288 typedef enum 289 { 290 TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ 291 TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ 292 TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ 293 TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ 294 TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ 295 TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ 296 TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ 297 TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ 298 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW0 = 0x00000309u, /* tcpwm[0].tr_overflow[0] */ 299 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH0 = 0x0000030Au, /* tcpwm[0].tr_compare_match[0] */ 300 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW0 = 0x0000030Bu, /* tcpwm[0].tr_underflow[0] */ 301 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW1 = 0x0000030Cu, /* tcpwm[0].tr_overflow[1] */ 302 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH1 = 0x0000030Du, /* tcpwm[0].tr_compare_match[1] */ 303 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW1 = 0x0000030Eu, /* tcpwm[0].tr_underflow[1] */ 304 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW2 = 0x0000030Fu, /* tcpwm[0].tr_overflow[2] */ 305 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH2 = 0x00000310u, /* tcpwm[0].tr_compare_match[2] */ 306 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW2 = 0x00000311u, /* tcpwm[0].tr_underflow[2] */ 307 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW3 = 0x00000312u, /* tcpwm[0].tr_overflow[3] */ 308 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH3 = 0x00000313u, /* tcpwm[0].tr_compare_match[3] */ 309 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW3 = 0x00000314u, /* tcpwm[0].tr_underflow[3] */ 310 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW0 = 0x00000321u, /* tcpwm[1].tr_overflow[0] */ 311 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH0 = 0x00000322u, /* tcpwm[1].tr_compare_match[0] */ 312 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW0 = 0x00000323u, /* tcpwm[1].tr_underflow[0] */ 313 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW1 = 0x00000324u, /* tcpwm[1].tr_overflow[1] */ 314 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH1 = 0x00000325u, /* tcpwm[1].tr_compare_match[1] */ 315 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW1 = 0x00000326u, /* tcpwm[1].tr_underflow[1] */ 316 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW2 = 0x00000327u, /* tcpwm[1].tr_overflow[2] */ 317 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH2 = 0x00000328u, /* tcpwm[1].tr_compare_match[2] */ 318 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW2 = 0x00000329u, /* tcpwm[1].tr_underflow[2] */ 319 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW3 = 0x0000032Au, /* tcpwm[1].tr_overflow[3] */ 320 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH3 = 0x0000032Bu, /* tcpwm[1].tr_compare_match[3] */ 321 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW3 = 0x0000032Cu, /* tcpwm[1].tr_underflow[3] */ 322 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW4 = 0x0000032Du, /* tcpwm[1].tr_overflow[4] */ 323 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH4 = 0x0000032Eu, /* tcpwm[1].tr_compare_match[4] */ 324 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW4 = 0x0000032Fu, /* tcpwm[1].tr_underflow[4] */ 325 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW5 = 0x00000330u, /* tcpwm[1].tr_overflow[5] */ 326 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH5 = 0x00000331u, /* tcpwm[1].tr_compare_match[5] */ 327 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW5 = 0x00000332u, /* tcpwm[1].tr_underflow[5] */ 328 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW6 = 0x00000333u, /* tcpwm[1].tr_overflow[6] */ 329 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH6 = 0x00000334u, /* tcpwm[1].tr_compare_match[6] */ 330 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW6 = 0x00000335u, /* tcpwm[1].tr_underflow[6] */ 331 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW7 = 0x00000336u, /* tcpwm[1].tr_overflow[7] */ 332 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH7 = 0x00000337u, /* tcpwm[1].tr_compare_match[7] */ 333 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW7 = 0x00000338u, /* tcpwm[1].tr_underflow[7] */ 334 TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ 335 TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ 336 TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ 337 TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ 338 TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ 339 TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ 340 TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ 341 TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ 342 TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ 343 TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ 344 TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ 345 TRIG_IN_MUX_3_SCB_I2C_SCL3 = 0x00000346u, /* scb[3].tr_i2c_scl_filtered */ 346 TRIG_IN_MUX_3_SCB_TX3 = 0x00000347u, /* scb[3].tr_tx_req */ 347 TRIG_IN_MUX_3_SCB_RX3 = 0x00000348u, /* scb[3].tr_rx_req */ 348 TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ 349 TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ 350 TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ 351 TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ 352 TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ 353 TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ 354 TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ 355 TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ 356 TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ 357 TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ 358 TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ 359 TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ 360 TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ 361 TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ 362 TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ 363 TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ 364 TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ 365 TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ 366 TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ 367 TRIG_IN_MUX_3_PASS_SAR_DONE = 0x00000373u, /* pass.tr_sar_out */ 368 TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ 369 TRIG_IN_MUX_3_HSIOM_TR_OUT14 = 0x00000375u, /* peri.tr_io_input[14] */ 370 TRIG_IN_MUX_3_HSIOM_TR_OUT15 = 0x00000376u, /* peri.tr_io_input[15] */ 371 TRIG_IN_MUX_3_HSIOM_TR_OUT16 = 0x00000377u, /* peri.tr_io_input[16] */ 372 TRIG_IN_MUX_3_HSIOM_TR_OUT17 = 0x00000378u, /* peri.tr_io_input[17] */ 373 TRIG_IN_MUX_3_HSIOM_TR_OUT18 = 0x00000379u, /* peri.tr_io_input[18] */ 374 TRIG_IN_MUX_3_HSIOM_TR_OUT19 = 0x0000037Au, /* peri.tr_io_input[19] */ 375 TRIG_IN_MUX_3_HSIOM_TR_OUT20 = 0x0000037Bu, /* peri.tr_io_input[20] */ 376 TRIG_IN_MUX_3_HSIOM_TR_OUT21 = 0x0000037Cu, /* peri.tr_io_input[21] */ 377 TRIG_IN_MUX_3_HSIOM_TR_OUT22 = 0x0000037Du, /* peri.tr_io_input[22] */ 378 TRIG_IN_MUX_3_HSIOM_TR_OUT23 = 0x0000037Eu, /* peri.tr_io_input[23] */ 379 TRIG_IN_MUX_3_HSIOM_TR_OUT24 = 0x0000037Fu, /* peri.tr_io_input[24] */ 380 TRIG_IN_MUX_3_HSIOM_TR_OUT25 = 0x00000380u, /* peri.tr_io_input[25] */ 381 TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ 382 TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ 383 TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ 384 TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u, /* lpcomp.dsi_comp1 */ 385 TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x00000387u /* canfd[0].tr_tmp_rtp_out[0] */ 386 } en_trig_input_tcpwm1_t; 387 388 /* Trigger Input Group 4 - HSIOM trigger multiplexer */ 389 typedef enum 390 { 391 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 392 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 393 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 394 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 395 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 396 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 397 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 398 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 399 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 400 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 401 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 402 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 403 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 404 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 405 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 406 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 407 TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ 408 TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ 409 TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ 410 TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ 411 TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ 412 TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ 413 TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ 414 TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ 415 TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ 416 TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ 417 TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ 418 TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ 419 TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ 420 TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ 421 TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ 422 TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ 423 TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ 424 TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ 425 TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ 426 TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ 427 TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ 428 TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ 429 TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ 430 TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ 431 TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ 432 TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ 433 TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ 434 TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ 435 TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ 436 TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ 437 TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ 438 TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ 439 TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ 440 TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ 441 TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ 442 TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ 443 TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ 444 TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ 445 TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ 446 TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ 447 TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ 448 TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ 449 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW0 = 0x0000043Bu, /* tcpwm[0].tr_overflow[0] */ 450 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH0 = 0x0000043Cu, /* tcpwm[0].tr_compare_match[0] */ 451 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW0 = 0x0000043Du, /* tcpwm[0].tr_underflow[0] */ 452 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW1 = 0x0000043Eu, /* tcpwm[0].tr_overflow[1] */ 453 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH1 = 0x0000043Fu, /* tcpwm[0].tr_compare_match[1] */ 454 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW1 = 0x00000440u, /* tcpwm[0].tr_underflow[1] */ 455 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW2 = 0x00000441u, /* tcpwm[0].tr_overflow[2] */ 456 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH2 = 0x00000442u, /* tcpwm[0].tr_compare_match[2] */ 457 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW2 = 0x00000443u, /* tcpwm[0].tr_underflow[2] */ 458 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW3 = 0x00000444u, /* tcpwm[0].tr_overflow[3] */ 459 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH3 = 0x00000445u, /* tcpwm[0].tr_compare_match[3] */ 460 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW3 = 0x00000446u, /* tcpwm[0].tr_underflow[3] */ 461 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW0 = 0x00000453u, /* tcpwm[1].tr_overflow[0] */ 462 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH0 = 0x00000454u, /* tcpwm[1].tr_compare_match[0] */ 463 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW0 = 0x00000455u, /* tcpwm[1].tr_underflow[0] */ 464 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW1 = 0x00000456u, /* tcpwm[1].tr_overflow[1] */ 465 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH1 = 0x00000457u, /* tcpwm[1].tr_compare_match[1] */ 466 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW1 = 0x00000458u, /* tcpwm[1].tr_underflow[1] */ 467 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW2 = 0x00000459u, /* tcpwm[1].tr_overflow[2] */ 468 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH2 = 0x0000045Au, /* tcpwm[1].tr_compare_match[2] */ 469 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW2 = 0x0000045Bu, /* tcpwm[1].tr_underflow[2] */ 470 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW3 = 0x0000045Cu, /* tcpwm[1].tr_overflow[3] */ 471 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH3 = 0x0000045Du, /* tcpwm[1].tr_compare_match[3] */ 472 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW3 = 0x0000045Eu, /* tcpwm[1].tr_underflow[3] */ 473 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW4 = 0x0000045Fu, /* tcpwm[1].tr_overflow[4] */ 474 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH4 = 0x00000460u, /* tcpwm[1].tr_compare_match[4] */ 475 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW4 = 0x00000461u, /* tcpwm[1].tr_underflow[4] */ 476 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW5 = 0x00000462u, /* tcpwm[1].tr_overflow[5] */ 477 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH5 = 0x00000463u, /* tcpwm[1].tr_compare_match[5] */ 478 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW5 = 0x00000464u, /* tcpwm[1].tr_underflow[5] */ 479 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW6 = 0x00000465u, /* tcpwm[1].tr_overflow[6] */ 480 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH6 = 0x00000466u, /* tcpwm[1].tr_compare_match[6] */ 481 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW6 = 0x00000467u, /* tcpwm[1].tr_underflow[6] */ 482 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW7 = 0x00000468u, /* tcpwm[1].tr_overflow[7] */ 483 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH7 = 0x00000469u, /* tcpwm[1].tr_compare_match[7] */ 484 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW7 = 0x0000046Au, /* tcpwm[1].tr_underflow[7] */ 485 TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ 486 TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ 487 TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ 488 TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ 489 TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ 490 TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ 491 TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ 492 TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ 493 TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ 494 TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ 495 TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ 496 TRIG_IN_MUX_4_SCB_I2C_SCL3 = 0x000004A8u, /* scb[3].tr_i2c_scl_filtered */ 497 TRIG_IN_MUX_4_SCB_TX3 = 0x000004A9u, /* scb[3].tr_tx_req */ 498 TRIG_IN_MUX_4_SCB_RX3 = 0x000004AAu, /* scb[3].tr_rx_req */ 499 TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ 500 TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ 501 TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ 502 TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ 503 TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ 504 TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ 505 TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ 506 TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ 507 TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ 508 TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ 509 TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ 510 TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ 511 TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ 512 TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ 513 TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ 514 TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ 515 TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ 516 TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ 517 TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ 518 TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ 519 TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ 520 TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ 521 TRIG_IN_MUX_4_PASS_SAR_DONE = 0x000004D8u, /* pass.tr_sar_out */ 522 TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ 523 TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ 524 TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ 525 TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ 526 TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ 527 TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu, /* lpcomp.dsi_comp1 */ 528 TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x000004DFu, /* canfd[0].tr_tmp_rtp_out[0] */ 529 TRIG_IN_MUX_4_PDMA1_TR_OUT29 = 0x000004E0u, /* cpuss.dw1_tr_out[29] */ 530 TRIG_IN_MUX_4_PDMA1_TR_OUT30 = 0x000004E1u, /* cpuss.dw1_tr_out[30] */ 531 TRIG_IN_MUX_4_PDMA1_TR_OUT31 = 0x000004E2u /* cpuss.dw1_tr_out[31] */ 532 } en_trig_input_hsiom_t; 533 534 /* Trigger Input Group 5 - CPUSS Debug trigger multiplexer */ 535 typedef enum 536 { 537 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ 538 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ 539 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ 540 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ 541 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ 542 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ 543 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ 544 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ 545 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ 546 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ 547 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ 548 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ 549 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ 550 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ 551 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ 552 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ 553 TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ 554 TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ 555 TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ 556 TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ 557 TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ 558 TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ 559 TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ 560 TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ 561 TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ 562 TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ 563 TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ 564 TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ 565 TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ 566 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ 567 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ 568 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ 569 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ 570 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ 571 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ 572 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ 573 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ 574 TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ 575 TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ 576 TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ 577 TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ 578 TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ 579 TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ 580 TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ 581 TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ 582 TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ 583 TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ 584 TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ 585 TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ 586 TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ 587 TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ 588 TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ 589 TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ 590 TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ 591 TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ 592 TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ 593 TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ 594 TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ 595 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW0 = 0x0000053Bu, /* tcpwm[0].tr_overflow[0] */ 596 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH0 = 0x0000053Cu, /* tcpwm[0].tr_compare_match[0] */ 597 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW0 = 0x0000053Du, /* tcpwm[0].tr_underflow[0] */ 598 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW1 = 0x0000053Eu, /* tcpwm[0].tr_overflow[1] */ 599 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH1 = 0x0000053Fu, /* tcpwm[0].tr_compare_match[1] */ 600 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW1 = 0x00000540u, /* tcpwm[0].tr_underflow[1] */ 601 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW2 = 0x00000541u, /* tcpwm[0].tr_overflow[2] */ 602 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH2 = 0x00000542u, /* tcpwm[0].tr_compare_match[2] */ 603 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW2 = 0x00000543u, /* tcpwm[0].tr_underflow[2] */ 604 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW3 = 0x00000544u, /* tcpwm[0].tr_overflow[3] */ 605 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH3 = 0x00000545u, /* tcpwm[0].tr_compare_match[3] */ 606 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW3 = 0x00000546u, /* tcpwm[0].tr_underflow[3] */ 607 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW0 = 0x00000553u, /* tcpwm[1].tr_overflow[0] */ 608 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH0 = 0x00000554u, /* tcpwm[1].tr_compare_match[0] */ 609 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW0 = 0x00000555u, /* tcpwm[1].tr_underflow[0] */ 610 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW1 = 0x00000556u, /* tcpwm[1].tr_overflow[1] */ 611 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH1 = 0x00000557u, /* tcpwm[1].tr_compare_match[1] */ 612 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW1 = 0x00000558u, /* tcpwm[1].tr_underflow[1] */ 613 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW2 = 0x00000559u, /* tcpwm[1].tr_overflow[2] */ 614 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH2 = 0x0000055Au, /* tcpwm[1].tr_compare_match[2] */ 615 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW2 = 0x0000055Bu, /* tcpwm[1].tr_underflow[2] */ 616 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW3 = 0x0000055Cu, /* tcpwm[1].tr_overflow[3] */ 617 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH3 = 0x0000055Du, /* tcpwm[1].tr_compare_match[3] */ 618 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW3 = 0x0000055Eu, /* tcpwm[1].tr_underflow[3] */ 619 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW4 = 0x0000055Fu, /* tcpwm[1].tr_overflow[4] */ 620 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH4 = 0x00000560u, /* tcpwm[1].tr_compare_match[4] */ 621 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW4 = 0x00000561u, /* tcpwm[1].tr_underflow[4] */ 622 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW5 = 0x00000562u, /* tcpwm[1].tr_overflow[5] */ 623 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH5 = 0x00000563u, /* tcpwm[1].tr_compare_match[5] */ 624 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW5 = 0x00000564u, /* tcpwm[1].tr_underflow[5] */ 625 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW6 = 0x00000565u, /* tcpwm[1].tr_overflow[6] */ 626 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH6 = 0x00000566u, /* tcpwm[1].tr_compare_match[6] */ 627 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW6 = 0x00000567u, /* tcpwm[1].tr_underflow[6] */ 628 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW7 = 0x00000568u, /* tcpwm[1].tr_overflow[7] */ 629 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH7 = 0x00000569u, /* tcpwm[1].tr_compare_match[7] */ 630 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW7 = 0x0000056Au, /* tcpwm[1].tr_underflow[7] */ 631 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ 632 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ 633 TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ 634 TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ 635 TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ 636 TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ 637 TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ 638 TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ 639 TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ 640 TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ 641 TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ 642 TRIG_IN_MUX_5_SCB_I2C_SCL3 = 0x000005A8u, /* scb[3].tr_i2c_scl_filtered */ 643 TRIG_IN_MUX_5_SCB_TX3 = 0x000005A9u, /* scb[3].tr_tx_req */ 644 TRIG_IN_MUX_5_SCB_RX3 = 0x000005AAu, /* scb[3].tr_rx_req */ 645 TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ 646 TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ 647 TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ 648 TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ 649 TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ 650 TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ 651 TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ 652 TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ 653 TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ 654 TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ 655 TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ 656 TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ 657 TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ 658 TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ 659 TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ 660 TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ 661 TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ 662 TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ 663 TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ 664 TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ 665 TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ 666 TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ 667 TRIG_IN_MUX_5_PASS_SAR_DONE = 0x000005D8u, /* pass.tr_sar_out */ 668 TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ 669 TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ 670 TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ 671 TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ 672 TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ 673 TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ 674 TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ 675 TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ 676 TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ 677 TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ 678 TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ 679 TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ 680 TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ 681 TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ 682 TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ 683 TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ 684 TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ 685 TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ 686 TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ 687 TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ 688 TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ 689 TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ 690 TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ 691 TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ 692 TRIG_IN_MUX_5_HSIOM_TR_OUT24 = 0x000005F1u, /* peri.tr_io_input[24] */ 693 TRIG_IN_MUX_5_HSIOM_TR_OUT25 = 0x000005F2u, /* peri.tr_io_input[25] */ 694 TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ 695 TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ 696 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ 697 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ 698 TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ 699 TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu, /* lpcomp.dsi_comp1 */ 700 TRIG_IN_MUX_5_CANFD_TT_TR_OUT0 = 0x000005FBu, /* canfd[0].tr_tmp_rtp_out[0] */ 701 TRIG_IN_MUX_5_PDMA1_TR_OUT29 = 0x000005FCu, /* cpuss.dw1_tr_out[29] */ 702 TRIG_IN_MUX_5_PDMA1_TR_OUT30 = 0x000005FDu, /* cpuss.dw1_tr_out[30] */ 703 TRIG_IN_MUX_5_PDMA1_TR_OUT31 = 0x000005FEu /* cpuss.dw1_tr_out[31] */ 704 } en_trig_input_cpuss_cti_t; 705 706 /* Trigger Input Group 6 - MDMA trigger multiplexer */ 707 typedef enum 708 { 709 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW0 = 0x00000601u, /* tcpwm[1].tr_overflow[0] */ 710 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH0 = 0x00000602u, /* tcpwm[1].tr_compare_match[0] */ 711 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW0 = 0x00000603u, /* tcpwm[1].tr_underflow[0] */ 712 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW1 = 0x00000604u, /* tcpwm[1].tr_overflow[1] */ 713 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH1 = 0x00000605u, /* tcpwm[1].tr_compare_match[1] */ 714 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW1 = 0x00000606u, /* tcpwm[1].tr_underflow[1] */ 715 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW2 = 0x00000607u, /* tcpwm[1].tr_overflow[2] */ 716 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH2 = 0x00000608u, /* tcpwm[1].tr_compare_match[2] */ 717 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW2 = 0x00000609u, /* tcpwm[1].tr_underflow[2] */ 718 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW3 = 0x0000060Au, /* tcpwm[1].tr_overflow[3] */ 719 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH3 = 0x0000060Bu, /* tcpwm[1].tr_compare_match[3] */ 720 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW3 = 0x0000060Cu, /* tcpwm[1].tr_underflow[3] */ 721 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW4 = 0x0000060Du, /* tcpwm[1].tr_overflow[4] */ 722 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH4 = 0x0000060Eu, /* tcpwm[1].tr_compare_match[4] */ 723 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW4 = 0x0000060Fu, /* tcpwm[1].tr_underflow[4] */ 724 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW5 = 0x00000610u, /* tcpwm[1].tr_overflow[5] */ 725 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH5 = 0x00000611u, /* tcpwm[1].tr_compare_match[5] */ 726 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW5 = 0x00000612u, /* tcpwm[1].tr_underflow[5] */ 727 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW6 = 0x00000613u, /* tcpwm[1].tr_overflow[6] */ 728 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH6 = 0x00000614u, /* tcpwm[1].tr_compare_match[6] */ 729 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW6 = 0x00000615u, /* tcpwm[1].tr_underflow[6] */ 730 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW7 = 0x00000616u, /* tcpwm[1].tr_overflow[7] */ 731 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH7 = 0x00000617u, /* tcpwm[1].tr_compare_match[7] */ 732 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW7 = 0x00000618u, /* tcpwm[1].tr_underflow[7] */ 733 TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ 734 TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ 735 } en_trig_input_mdma_t; 736 737 /* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ 738 typedef enum 739 { 740 TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ 741 TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ 742 } en_trig_input_peri_freeze_t; 743 744 /* Trigger Input Group 8 - Capsense trigger multiplexer */ 745 typedef enum 746 { 747 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW0 = 0x00000801u, /* tcpwm[0].tr_overflow[0] */ 748 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH0 = 0x00000802u, /* tcpwm[0].tr_compare_match[0] */ 749 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW0 = 0x00000803u, /* tcpwm[0].tr_underflow[0] */ 750 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW1 = 0x00000804u, /* tcpwm[0].tr_overflow[1] */ 751 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH1 = 0x00000805u, /* tcpwm[0].tr_compare_match[1] */ 752 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW1 = 0x00000806u, /* tcpwm[0].tr_underflow[1] */ 753 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW2 = 0x00000807u, /* tcpwm[0].tr_overflow[2] */ 754 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH2 = 0x00000808u, /* tcpwm[0].tr_compare_match[2] */ 755 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW2 = 0x00000809u, /* tcpwm[0].tr_underflow[2] */ 756 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW3 = 0x0000080Au, /* tcpwm[0].tr_overflow[3] */ 757 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH3 = 0x0000080Bu, /* tcpwm[0].tr_compare_match[3] */ 758 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW3 = 0x0000080Cu, /* tcpwm[0].tr_underflow[3] */ 759 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW0 = 0x00000819u, /* tcpwm[1].tr_overflow[0] */ 760 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH0 = 0x0000081Au, /* tcpwm[1].tr_compare_match[0] */ 761 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW0 = 0x0000081Bu, /* tcpwm[1].tr_underflow[0] */ 762 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW1 = 0x0000081Cu, /* tcpwm[1].tr_overflow[1] */ 763 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH1 = 0x0000081Du, /* tcpwm[1].tr_compare_match[1] */ 764 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW1 = 0x0000081Eu, /* tcpwm[1].tr_underflow[1] */ 765 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW2 = 0x0000081Fu, /* tcpwm[1].tr_overflow[2] */ 766 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH2 = 0x00000820u, /* tcpwm[1].tr_compare_match[2] */ 767 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW2 = 0x00000821u, /* tcpwm[1].tr_underflow[2] */ 768 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW3 = 0x00000822u, /* tcpwm[1].tr_overflow[3] */ 769 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH3 = 0x00000823u, /* tcpwm[1].tr_compare_match[3] */ 770 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW3 = 0x00000824u, /* tcpwm[1].tr_underflow[3] */ 771 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW4 = 0x00000825u, /* tcpwm[1].tr_overflow[4] */ 772 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH4 = 0x00000826u, /* tcpwm[1].tr_compare_match[4] */ 773 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW4 = 0x00000827u, /* tcpwm[1].tr_underflow[4] */ 774 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW5 = 0x00000828u, /* tcpwm[1].tr_overflow[5] */ 775 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH5 = 0x00000829u, /* tcpwm[1].tr_compare_match[5] */ 776 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW5 = 0x0000082Au, /* tcpwm[1].tr_underflow[5] */ 777 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW6 = 0x0000082Bu, /* tcpwm[1].tr_overflow[6] */ 778 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH6 = 0x0000082Cu, /* tcpwm[1].tr_compare_match[6] */ 779 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW6 = 0x0000082Du, /* tcpwm[1].tr_underflow[6] */ 780 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW7 = 0x0000082Eu, /* tcpwm[1].tr_overflow[7] */ 781 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH7 = 0x0000082Fu, /* tcpwm[1].tr_compare_match[7] */ 782 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW7 = 0x00000830u, /* tcpwm[1].tr_underflow[7] */ 783 TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x0000086Du, /* peri.tr_io_input[0] */ 784 TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x0000086Eu, /* peri.tr_io_input[1] */ 785 TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x0000086Fu, /* peri.tr_io_input[2] */ 786 TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000870u, /* peri.tr_io_input[3] */ 787 TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000871u, /* peri.tr_io_input[4] */ 788 TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000872u, /* peri.tr_io_input[5] */ 789 TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000873u, /* peri.tr_io_input[6] */ 790 TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000874u, /* peri.tr_io_input[7] */ 791 TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000875u, /* peri.tr_io_input[8] */ 792 TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000876u, /* peri.tr_io_input[9] */ 793 TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000877u, /* peri.tr_io_input[10] */ 794 TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000878u, /* peri.tr_io_input[11] */ 795 TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000879u, /* peri.tr_io_input[12] */ 796 TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000087Au, /* peri.tr_io_input[13] */ 797 TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000087Bu, /* peri.tr_io_input[14] */ 798 TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x0000087Cu, /* peri.tr_io_input[15] */ 799 TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x0000087Du, /* peri.tr_io_input[16] */ 800 TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x0000087Eu, /* peri.tr_io_input[17] */ 801 TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x0000087Fu, /* peri.tr_io_input[18] */ 802 TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000880u, /* peri.tr_io_input[19] */ 803 TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000881u, /* peri.tr_io_input[20] */ 804 TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000882u, /* peri.tr_io_input[21] */ 805 TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000883u, /* peri.tr_io_input[22] */ 806 TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000884u, /* peri.tr_io_input[23] */ 807 TRIG_IN_MUX_8_HSIOM_TR_OUT24 = 0x00000885u, /* peri.tr_io_input[24] */ 808 TRIG_IN_MUX_8_HSIOM_TR_OUT25 = 0x00000886u, /* peri.tr_io_input[25] */ 809 TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x00000889u, /* lpcomp.dsi_comp0 */ 810 TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000088Au /* lpcomp.dsi_comp1 */ 811 } en_trig_input_csd_t; 812 813 /* Trigger Input Group 9 - ADC trigger multiplexer */ 814 typedef enum 815 { 816 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW0 = 0x00000901u, /* tcpwm[0].tr_overflow[0] */ 817 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH0 = 0x00000902u, /* tcpwm[0].tr_compare_match[0] */ 818 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW0 = 0x00000903u, /* tcpwm[0].tr_underflow[0] */ 819 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW1 = 0x00000904u, /* tcpwm[0].tr_overflow[1] */ 820 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH1 = 0x00000905u, /* tcpwm[0].tr_compare_match[1] */ 821 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW1 = 0x00000906u, /* tcpwm[0].tr_underflow[1] */ 822 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW2 = 0x00000907u, /* tcpwm[0].tr_overflow[2] */ 823 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH2 = 0x00000908u, /* tcpwm[0].tr_compare_match[2] */ 824 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW2 = 0x00000909u, /* tcpwm[0].tr_underflow[2] */ 825 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW3 = 0x0000090Au, /* tcpwm[0].tr_overflow[3] */ 826 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH3 = 0x0000090Bu, /* tcpwm[0].tr_compare_match[3] */ 827 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW3 = 0x0000090Cu, /* tcpwm[0].tr_underflow[3] */ 828 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW0 = 0x00000919u, /* tcpwm[1].tr_overflow[0] */ 829 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH0 = 0x0000091Au, /* tcpwm[1].tr_compare_match[0] */ 830 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW0 = 0x0000091Bu, /* tcpwm[1].tr_underflow[0] */ 831 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW1 = 0x0000091Cu, /* tcpwm[1].tr_overflow[1] */ 832 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH1 = 0x0000091Du, /* tcpwm[1].tr_compare_match[1] */ 833 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW1 = 0x0000091Eu, /* tcpwm[1].tr_underflow[1] */ 834 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW2 = 0x0000091Fu, /* tcpwm[1].tr_overflow[2] */ 835 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH2 = 0x00000920u, /* tcpwm[1].tr_compare_match[2] */ 836 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW2 = 0x00000921u, /* tcpwm[1].tr_underflow[2] */ 837 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW3 = 0x00000922u, /* tcpwm[1].tr_overflow[3] */ 838 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH3 = 0x00000923u, /* tcpwm[1].tr_compare_match[3] */ 839 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW3 = 0x00000924u, /* tcpwm[1].tr_underflow[3] */ 840 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW4 = 0x00000925u, /* tcpwm[1].tr_overflow[4] */ 841 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH4 = 0x00000926u, /* tcpwm[1].tr_compare_match[4] */ 842 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW4 = 0x00000927u, /* tcpwm[1].tr_underflow[4] */ 843 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW5 = 0x00000928u, /* tcpwm[1].tr_overflow[5] */ 844 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH5 = 0x00000929u, /* tcpwm[1].tr_compare_match[5] */ 845 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW5 = 0x0000092Au, /* tcpwm[1].tr_underflow[5] */ 846 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW6 = 0x0000092Bu, /* tcpwm[1].tr_overflow[6] */ 847 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH6 = 0x0000092Cu, /* tcpwm[1].tr_compare_match[6] */ 848 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW6 = 0x0000092Du, /* tcpwm[1].tr_underflow[6] */ 849 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW7 = 0x0000092Eu, /* tcpwm[1].tr_overflow[7] */ 850 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH7 = 0x0000092Fu, /* tcpwm[1].tr_compare_match[7] */ 851 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW7 = 0x00000930u, /* tcpwm[1].tr_underflow[7] */ 852 TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ 853 TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ 854 TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ 855 TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ 856 TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ 857 TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ 858 TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ 859 TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ 860 TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ 861 TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ 862 TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ 863 TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ 864 TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ 865 TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ 866 TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ 867 TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ 868 TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ 869 TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ 870 TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ 871 TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ 872 TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ 873 TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ 874 TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ 875 TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ 876 TRIG_IN_MUX_9_HSIOM_TR_OUT24 = 0x00000979u, /* peri.tr_io_input[24] */ 877 TRIG_IN_MUX_9_HSIOM_TR_OUT25 = 0x0000097Au, /* peri.tr_io_input[25] */ 878 TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ 879 TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ 880 } en_trig_input_sar_adc_start_t; 881 882 /* Trigger Input Group 10 - CAN TT Synchronization triggers */ 883 typedef enum 884 { 885 TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ 886 } en_trig_input_cantt_t; 887 888 /* Trigger Group Outputs */ 889 /* Trigger Output Group 0 - PDMA0 Request Assignments */ 890 typedef enum 891 { 892 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 893 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 894 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 895 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 896 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 897 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 898 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 899 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ 900 } en_trig_output_pdma0_tr_t; 901 902 /* Trigger Output Group 1 - PDMA1 Request Assignments */ 903 typedef enum 904 { 905 TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ 906 TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ 907 TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ 908 TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ 909 TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ 910 TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ 911 TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ 912 TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ 913 } en_trig_output_pdma1_tr_t; 914 915 /* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ 916 typedef enum 917 { 918 TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */ 919 TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */ 920 TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */ 921 TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */ 922 TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */ 923 TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */ 924 TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */ 925 TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */ 926 TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */ 927 TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */ 928 TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */ 929 TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ 930 TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */ 931 TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */ 932 } en_trig_output_tcpwm0_t; 933 934 /* Trigger Output Group 3 - TCPWM1 trigger multiplexer */ 935 typedef enum 936 { 937 TRIG_OUT_MUX_3_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */ 938 TRIG_OUT_MUX_3_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */ 939 TRIG_OUT_MUX_3_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */ 940 TRIG_OUT_MUX_3_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */ 941 TRIG_OUT_MUX_3_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */ 942 TRIG_OUT_MUX_3_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */ 943 TRIG_OUT_MUX_3_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */ 944 TRIG_OUT_MUX_3_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */ 945 TRIG_OUT_MUX_3_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */ 946 TRIG_OUT_MUX_3_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */ 947 TRIG_OUT_MUX_3_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */ 948 TRIG_OUT_MUX_3_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */ 949 TRIG_OUT_MUX_3_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */ 950 TRIG_OUT_MUX_3_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */ 951 } en_trig_output_tcpwm1_t; 952 953 /* Trigger Output Group 4 - HSIOM trigger multiplexer */ 954 typedef enum 955 { 956 TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ 957 TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ 958 } en_trig_output_hsiom_t; 959 960 /* Trigger Output Group 5 - CPUSS Debug trigger multiplexer */ 961 typedef enum 962 { 963 TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ 964 TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ 965 } en_trig_output_cpuss_cti_t; 966 967 /* Trigger Output Group 6 - MDMA trigger multiplexer */ 968 typedef enum 969 { 970 TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ 971 TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u /* cpuss.dmac_tr_in[1] */ 972 } en_trig_output_mdma_t; 973 974 /* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ 975 typedef enum 976 { 977 TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u /* peri.tr_dbg_freeze */ 978 } en_trig_output_peri_freeze_t; 979 980 /* Trigger Output Group 8 - Capsense trigger multiplexer */ 981 typedef enum 982 { 983 TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ 984 } en_trig_output_csd_t; 985 986 /* Trigger Output Group 9 - ADC trigger multiplexer */ 987 typedef enum 988 { 989 TRIG_OUT_MUX_9_PASS_TR_SAR_IN = 0x40000900u /* pass.tr_sar_in */ 990 } en_trig_output_sar_adc_start_t; 991 992 /* Trigger Output Group 10 - CAN TT Synchronization triggers */ 993 typedef enum 994 { 995 TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ 996 } en_trig_output_cantt_t; 997 998 /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ 999 typedef enum 1000 { 1001 TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ 1002 TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ 1003 TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ 1004 TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ 1005 TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ 1006 TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ 1007 TRIG_OUT_1TO1_0_SCB3_TX_TO_PDMA0_TR_IN22 = 0x40001006u, /* From scb[3].tr_tx_req to cpuss.dw0_tr_in[22] */ 1008 TRIG_OUT_1TO1_0_SCB3_RX_TO_PDMA0_TR_IN23 = 0x40001007u, /* From scb[3].tr_rx_req to cpuss.dw0_tr_in[23] */ 1009 TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ 1010 TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ 1011 TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ 1012 TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ 1013 } en_trig_output_1to1_scb_pdma0_tr_t; 1014 1015 /* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ 1016 typedef enum 1017 { 1018 TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ 1019 TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ 1020 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN10 = 0x40001102u, /* From cpuss.zero to cpuss.dw1_tr_in[10] */ 1021 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN11 = 0x40001103u, /* From cpuss.zero to cpuss.dw1_tr_in[11] */ 1022 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN12 = 0x40001104u, /* From cpuss.zero to cpuss.dw1_tr_in[12] */ 1023 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN13 = 0x40001105u, /* From cpuss.zero to cpuss.dw1_tr_in[13] */ 1024 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN14 = 0x40001106u, /* From cpuss.zero to cpuss.dw1_tr_in[14] */ 1025 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN15 = 0x40001107u, /* From cpuss.zero to cpuss.dw1_tr_in[15] */ 1026 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN16 = 0x40001108u, /* From cpuss.zero to cpuss.dw1_tr_in[16] */ 1027 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN17 = 0x40001109u, /* From cpuss.zero to cpuss.dw1_tr_in[17] */ 1028 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN18 = 0x4000110Au, /* From cpuss.zero to cpuss.dw1_tr_in[18] */ 1029 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN19 = 0x4000110Bu, /* From cpuss.zero to cpuss.dw1_tr_in[19] */ 1030 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN20 = 0x4000110Cu, /* From cpuss.zero to cpuss.dw1_tr_in[20] */ 1031 TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN21 = 0x4000110Du /* From cpuss.zero to cpuss.dw1_tr_in[21] */ 1032 } en_trig_output_1to1_scb_pdma1_tr_t; 1033 1034 /* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ 1035 typedef enum 1036 { 1037 TRIG_OUT_1TO1_2_PASS_SAR_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out to cpuss.dw0_tr_in[28] */ 1038 } en_trig_output_1to1_sar_to_pdma1_t; 1039 1040 /* Trigger Output Group 3 - (OneToOne) */ 1041 typedef enum 1042 { 1043 TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ 1044 TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u, /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ 1045 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN24 = 0x40001302u, /* From cpuss.zero to cpuss.dw1_tr_in[24] */ 1046 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN25 = 0x40001303u, /* From cpuss.zero to cpuss.dw1_tr_in[25] */ 1047 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN26 = 0x40001304u, /* From cpuss.zero to cpuss.dw1_tr_in[26] */ 1048 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN27 = 0x40001305u, /* From cpuss.zero to cpuss.dw1_tr_in[27] */ 1049 TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN28 = 0x40001306u /* From cpuss.zero to cpuss.dw1_tr_in[28] */ 1050 } en_trig_output_1to1_smif_to_pdma1_t; 1051 1052 /* Trigger Output Group 4 - CAN DW triggers (OneToOne) */ 1053 typedef enum 1054 { 1055 TRIG_OUT_1TO1_4_CAN_DBG_TO_PDMA1_TR_IN29 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[29] */ 1056 TRIG_OUT_1TO1_4_CAN_FIFO0_TO_PDMA1_TR_IN30 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw1_tr_in[30] */ 1057 TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ 1058 } en_trig_output_1to1_can_dw_tr_t; 1059 1060 /* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ 1061 typedef enum 1062 { 1063 TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ 1064 TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ 1065 TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ 1066 TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ 1067 TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ 1068 TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ 1069 TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ 1070 TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ 1071 } en_trig_output_1to1_usb_pdma0_tr_t; 1072 1073 /* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ 1074 typedef enum 1075 { 1076 TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ 1077 TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ 1078 TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ 1079 TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ 1080 TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ 1081 TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ 1082 TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ 1083 TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ 1084 } en_trig_output_1to1_usb_pdma0_ack_tr_t; 1085 1086 /* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ 1087 typedef enum 1088 { 1089 TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ 1090 } en_trig_output_1to1_can0_dw_ack_t; 1091 1092 /* Level or edge detection setting for a trigger mux */ 1093 typedef enum 1094 { 1095 /* The trigger is a simple level output */ 1096 TRIGGER_TYPE_LEVEL = 0u, 1097 /* The trigger is synchronized to the consumer blocks clock 1098 and a two cycle pulse is generated on this clock */ 1099 TRIGGER_TYPE_EDGE = 1u 1100 } en_trig_type_t; 1101 1102 /* Trigger Type Defines */ 1103 /* CANFD Trigger Types */ 1104 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1105 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1106 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1107 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1108 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1109 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1110 /* CPUSS Trigger Types */ 1111 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1112 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1113 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1114 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1115 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1116 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1117 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1118 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1119 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1120 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1121 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1122 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1123 /* CSD Trigger Types */ 1124 #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE 1125 /* LPCOMP Trigger Types */ 1126 #define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL 1127 #define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL 1128 /* PASS Trigger Types */ 1129 #define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL 1130 #define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE 1131 #define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE 1132 /* PERI Trigger Types */ 1133 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1134 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1135 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1136 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1137 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1138 /* SCB Trigger Types */ 1139 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1140 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1141 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1142 /* SMIF Trigger Types */ 1143 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 1144 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 1145 /* TCPWM Trigger Types */ 1146 #define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL 1147 #define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL 1148 #define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE 1149 #define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1150 #define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE 1151 #define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE 1152 #define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE 1153 /* USB Trigger Types */ 1154 #define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE 1155 #define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE 1156 1157 /* Fault connections */ 1158 typedef enum 1159 { 1160 CPUSS_MPU_VIO_0 = 0x0000u, 1161 CPUSS_MPU_VIO_1 = 0x0001u, 1162 CPUSS_MPU_VIO_2 = 0x0002u, 1163 CPUSS_MPU_VIO_3 = 0x0003u, 1164 CPUSS_MPU_VIO_4 = 0x0004u, 1165 CPUSS_MPU_VIO_5 = 0x0005u, 1166 CPUSS_MPU_VIO_15 = 0x000Fu, 1167 CPUSS_MPU_VIO_16 = 0x0010u, 1168 CPUSS_MPU_VIO_17 = 0x0011u, 1169 CPUSS_MPU_VIO_18 = 0x0012u, 1170 PERI_MS_VIO_0 = 0x001Cu, 1171 PERI_MS_VIO_1 = 0x001Du, 1172 PERI_MS_VIO_2 = 0x001Eu, 1173 PERI_MS_VIO_3 = 0x001Fu, 1174 PERI_GROUP_VIO_0 = 0x0020u, 1175 PERI_GROUP_VIO_1 = 0x0021u, 1176 PERI_GROUP_VIO_2 = 0x0022u, 1177 PERI_GROUP_VIO_3 = 0x0023u, 1178 PERI_GROUP_VIO_4 = 0x0024u, 1179 PERI_GROUP_VIO_5 = 0x0025u, 1180 PERI_GROUP_VIO_6 = 0x0026u, 1181 PERI_GROUP_VIO_9 = 0x0029u, 1182 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u 1183 } en_sysfault_source_t; 1184 1185 /* Bus masters */ 1186 typedef enum 1187 { 1188 CPUSS_MS_ID_CM0 = 0, 1189 CPUSS_MS_ID_CRYPTO = 1, 1190 CPUSS_MS_ID_DW0 = 2, 1191 CPUSS_MS_ID_DW1 = 3, 1192 CPUSS_MS_ID_DMAC = 4, 1193 CPUSS_MS_ID_SLOW0 = 5, 1194 CPUSS_MS_ID_SLOW1 = 6, 1195 CPUSS_MS_ID_CM4 = 14, 1196 CPUSS_MS_ID_TC = 15 1197 } en_prot_master_t; 1198 1199 /* Pointer to device configuration structure */ 1200 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_03) 1201 1202 /* Include IP definitions */ 1203 #include "ip/cyip_sflash_psoc6_03.h" 1204 #include "ip/cyip_peri_v2.h" 1205 #include "ip/cyip_peri_ms_v2.h" 1206 #include "ip/cyip_crypto_v2.h" 1207 #include "ip/cyip_cpuss_v2.h" 1208 #include "ip/cyip_fault_v2.h" 1209 #include "ip/cyip_ipc_v2.h" 1210 #include "ip/cyip_prot_v2.h" 1211 #include "ip/cyip_flashc_v2.h" 1212 #include "ip/cyip_srss.h" 1213 #include "ip/cyip_backup.h" 1214 #include "ip/cyip_dw_v2.h" 1215 #include "ip/cyip_dmac_v2.h" 1216 #include "ip/cyip_efuse.h" 1217 #include "ip/cyip_efuse_data_psoc6_03.h" 1218 #include "ip/cyip_hsiom_v2.h" 1219 #include "ip/cyip_gpio_v2.h" 1220 #include "ip/cyip_smartio_v2.h" 1221 #include "ip/cyip_lpcomp.h" 1222 #include "ip/cyip_csd.h" 1223 #include "ip/cyip_tcpwm.h" 1224 #include "ip/cyip_lcd_v2.h" 1225 #include "ip/cyip_usbfs.h" 1226 #include "ip/cyip_smif.h" 1227 #include "ip/cyip_sdhc.h" 1228 #include "ip/cyip_canfd.h" 1229 #include "ip/cyip_scb.h" 1230 #include "ip/cyip_ctbm.h" 1231 #include "ip/cyip_ctdac.h" 1232 #include "ip/cyip_sar.h" 1233 #include "ip/cyip_pass.h" 1234 1235 /* IP type definitions */ 1236 typedef SFLASH_V1_Type SFLASH_Type; 1237 typedef PERI_GR_V2_Type PERI_GR_Type; 1238 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 1239 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 1240 typedef PERI_V2_Type PERI_Type; 1241 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 1242 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 1243 typedef PERI_MS_V2_Type PERI_MS_Type; 1244 typedef CRYPTO_V2_Type CRYPTO_Type; 1245 typedef CPUSS_V2_Type CPUSS_Type; 1246 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 1247 typedef FAULT_V2_Type FAULT_Type; 1248 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 1249 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 1250 typedef IPC_V2_Type IPC_Type; 1251 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 1252 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 1253 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 1254 typedef PROT_MPU_V2_Type PROT_MPU_Type; 1255 typedef PROT_V2_Type PROT_Type; 1256 typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; 1257 typedef FLASHC_V2_Type FLASHC_Type; 1258 typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; 1259 typedef SRSS_V1_Type SRSS_Type; 1260 typedef BACKUP_V1_Type BACKUP_Type; 1261 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 1262 typedef DW_V2_Type DW_Type; 1263 typedef DMAC_CH_V2_Type DMAC_CH_Type; 1264 typedef DMAC_V2_Type DMAC_Type; 1265 typedef EFUSE_V1_Type EFUSE_Type; 1266 typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; 1267 typedef HSIOM_V2_Type HSIOM_Type; 1268 typedef GPIO_PRT_V2_Type GPIO_PRT_Type; 1269 typedef GPIO_V2_Type GPIO_Type; 1270 typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; 1271 typedef SMARTIO_V2_Type SMARTIO_Type; 1272 typedef LPCOMP_V1_Type LPCOMP_Type; 1273 typedef CSD_V1_Type CSD_Type; 1274 typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type; 1275 typedef TCPWM_V1_Type TCPWM_Type; 1276 typedef LCD_V2_Type LCD_Type; 1277 typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; 1278 typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; 1279 typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; 1280 typedef USBFS_V1_Type USBFS_Type; 1281 typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; 1282 typedef SMIF_V1_Type SMIF_Type; 1283 typedef SDHC_WRAP_V1_Type SDHC_WRAP_Type; 1284 typedef SDHC_CORE_V1_Type SDHC_CORE_Type; 1285 typedef SDHC_V1_Type SDHC_Type; 1286 typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; 1287 typedef CANFD_CH_V1_Type CANFD_CH_Type; 1288 typedef CANFD_V1_Type CANFD_Type; 1289 typedef CySCB_V1_Type CySCB_Type; 1290 typedef CTBM_V1_Type CTBM_Type; 1291 typedef CTDAC_V1_Type CTDAC_Type; 1292 typedef SAR_V1_Type SAR_Type; 1293 typedef PASS_AREF_V1_Type PASS_AREF_Type; 1294 typedef PASS_V1_Type PASS_Type; 1295 1296 /* Parameter Defines */ 1297 /* Number of TTCAN instances */ 1298 #define CANFD_CAN_NR 1u 1299 /* ECC logic present or not */ 1300 #define CANFD_ECC_PRESENT 0u 1301 /* address included in ECC logic or not */ 1302 #define CANFD_ECC_ADDR_PRESENT 0u 1303 /* Time Stamp counter present or not (required for instance 0, otherwise not 1304 allowed) */ 1305 #define CANFD_TS_PRESENT 1u 1306 /* Message RAM size in KB */ 1307 #define CANFD_MRAM_SIZE 4u 1308 /* Message RAM address width */ 1309 #define CANFD_MRAM_ADDR_WIDTH 10u 1310 /* UDB present or not ('0': no, '1': yes) */ 1311 #define CPUSS_UDB_PRESENT 0u 1312 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 1313 chips which doesn't use mxdft. */ 1314 #define CPUSS_MBIST_MMIO_PRESENT 1u 1315 /* System RAM 0 size in kilobytes */ 1316 #define CPUSS_SRAM0_SIZE 256u 1317 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System 1318 SRAM0 is implemented with 8 32KB macros. */ 1319 #define CPUSS_RAMC0_MACRO_NR 8u 1320 /* System RAM 1 present or not (0=No, 1=Yes) */ 1321 #define CPUSS_RAMC1_PRESENT 0u 1322 /* System RAM 1 size in kilobytes */ 1323 #define CPUSS_SRAM1_SIZE 1u 1324 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 1325 RAM 1 is implemented with 8 32KB macros. */ 1326 #define CPUSS_RAMC1_MACRO_NR 1u 1327 /* System RAM 2 present or not (0=No, 1=Yes) */ 1328 #define CPUSS_RAMC2_PRESENT 0u 1329 /* System RAM 2 size in kilobytes */ 1330 #define CPUSS_SRAM2_SIZE 1u 1331 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 1332 RAM 2 is implemented with 8 32KB macros. */ 1333 #define CPUSS_RAMC2_MACRO_NR 1u 1334 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 1335 #define CPUSS_RAMC_ECC_PRESENT 0u 1336 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 1337 #define CPUSS_RAMC_ECC_ADDR_PRESENT 0u 1338 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 1339 #define CPUSS_ECC_PRESENT 0u 1340 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1341 #define CPUSS_DW_ECC_PRESENT 0u 1342 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 1343 #define CPUSS_DW_ECC_ADDR_PRESENT 0u 1344 /* System ROM size in KB */ 1345 #define CPUSS_ROM_SIZE 64u 1346 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 1347 is implemented with 4 128KB macros. */ 1348 #define CPUSS_ROMC_MACRO_NR 1u 1349 /* Flash memory type ('0' : SONOS, '1': ECT) */ 1350 #define CPUSS_FLASHC_ECT 0u 1351 /* Flash main region size in KB */ 1352 #define CPUSS_FLASH_SIZE 512u 1353 /* Flash work region size in KB (EEPROM emulation, data) */ 1354 #define CPUSS_WFLASH_SIZE 32u 1355 /* Flash supervisory region size in KB */ 1356 #define CPUSS_SFLASH_SIZE 32u 1357 /* Flash data output word size (in Bytes) */ 1358 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u 1359 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 1360 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 1361 Flash, and no Work Flash present. */ 1362 #define CPUSS_FLASHC_SONOS_RWW 1u 1363 /* SONOS Flash, number of main sectors. */ 1364 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u 1365 /* SONOS Flash, number of rows per main sector. */ 1366 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u 1367 /* SONOS Flash, number of words per row of main sector. */ 1368 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u 1369 /* SONOS Flash, number of special sectors. */ 1370 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u 1371 /* SONOS Flash, number of rows per special sector. */ 1372 #define CPUSS_FLASHC_SONOS_SPL_ROWS 64u 1373 /* Flash memory ECC present or not ('0': no, '1': yes) */ 1374 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u 1375 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 1376 #define CPUSS_FLASHC_RAM_ECC_PRESENT 0u 1377 /* Number of external slaves directly connected to slow AHB-Lite infrastructure. 1378 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1379 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1380 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK 1381 parameters (for the slaves present) should be derived from the Memory Map. */ 1382 #define CPUSS_SLOW_SL_PRESENT 1u 1383 /* Number of external slaves directly connected to fast AHB-Lite infrastructure. 1384 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1385 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1386 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 1387 parameters (for the slaves present) should be derived from the Memory Map. */ 1388 #define CPUSS_FAST_SL_PRESENT 1u 1389 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum 1390 number of masters supported is 2. Width of this parameter is 2-bits. 1-bit 1391 mask for each master indicating present or not. Example: 2'b01 - master 0 is 1392 present. */ 1393 #define CPUSS_SLOW_MS_PRESENT 1u 1394 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 1395 CM0+ PCU, which always uses system interrupt functionality. */ 1396 #define CPUSS_SYSTEM_IRQ_PRESENT 0u 1397 /* Number of total interrupt request inputs to CPUSS */ 1398 #define CPUSS_SYSTEM_INT_NR 174u 1399 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */ 1400 #define CPUSS_SYSTEM_DPSLP_INT_NR 39u 1401 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 1402 levels of priority 8 = 256 levels of priority */ 1403 #define CPUSS_CM4_LVL_WIDTH 3u 1404 /* CM4 Floating point unit present or not (0=No, 1=Yes) */ 1405 #define CPUSS_CM4_FPU_PRESENT 1u 1406 /* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 1407 breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 1408 watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ 1409 #define CPUSS_DEBUG_LVL 3u 1410 /* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + 1411 ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace 1412 level is not supported in CPUSS. */ 1413 #define CPUSS_TRACE_LVL 2u 1414 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */ 1415 #define CPUSS_ETB_PRESENT 0u 1416 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1417 #define CPUSS_MTB_SRAM_SIZE 4u 1418 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1419 #define CPUSS_ETB_SRAM_SIZE 8u 1420 /* PTM interface present (0=No, 1=Yes) */ 1421 #define CPUSS_PTM_PRESENT 0u 1422 /* Width of the PTM interface in bits ([2,32]) */ 1423 #define CPUSS_PTM_WIDTH 1u 1424 /* Width of the TPIU interface in bits ([1,4]) */ 1425 #define CPUSS_TPIU_WIDTH 4u 1426 /* CoreSight Part Identification Number */ 1427 #define CPUSS_JEPID 52u 1428 /* CoreSight Part Identification Number */ 1429 #define CPUSS_JEPCONTINUATION 0u 1430 /* CoreSight Part Identification Number */ 1431 #define CPUSS_FAMILYID 261u 1432 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 1433 #define CPUSS_ROM_TRIM_WIDTH 5u 1434 /* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ 1435 #define CPUSS_ROM_TRIM_DEFAULT 18u 1436 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 1437 #define CPUSS_RAM_TRIM_WIDTH 15u 1438 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 1439 #define CPUSS_RAM_TRIM_DEFAULT 0x00006012u 1440 /* Cryptography IP present or not (0=No, 1=Yes) */ 1441 #define CPUSS_CRYPTO_PRESENT 1u 1442 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1443 #define CPUSS_SW_TR_PRESENT 0u 1444 /* DataWire 0 present or not (0=No, 1=Yes) */ 1445 #define CPUSS_DW0_PRESENT 1u 1446 /* Number of DataWire 0 channels (8, 16 or 32) */ 1447 #define CPUSS_DW0_CH_NR 29u 1448 /* DataWire 1 present or not (0=No, 1=Yes) */ 1449 #define CPUSS_DW1_PRESENT 1u 1450 /* Number of DataWire 1 channels (8, 16 or 32) */ 1451 #define CPUSS_DW1_CH_NR 32u 1452 /* DMA controller present or not ('0': no, '1': yes) */ 1453 #define CPUSS_DMAC_PRESENT 1u 1454 /* Number of DMA controller channels ([1, 8]) */ 1455 #define CPUSS_DMAC_CH_NR 2u 1456 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1457 #define CPUSS_CH_SW_TR_PRESENT 0u 1458 /* Copy value from Globals */ 1459 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 1460 /* ETAS Calibration support pin out present (automotive only) */ 1461 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u 1462 /* TRACE_LVL>0 */ 1463 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 1464 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 1465 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u 1466 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 1467 #define CPUSS_CPUSS_DW_DW_NR 2u 1468 /* Number of channels in each DataWire controller */ 1469 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u 1470 /* Width of a channel number in bits */ 1471 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u 1472 /* Number of channels in each DataWire controller */ 1473 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u 1474 /* Width of a channel number in bits */ 1475 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u 1476 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 1477 #define CPUSS_CRYPTO_ECC_PRESENT 0u 1478 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 1479 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u 1480 /* AES cipher support ('0': no, '1': yes) */ 1481 #define CPUSS_CRYPTO_AES 1u 1482 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 1483 #define CPUSS_CRYPTO_DES 1u 1484 /* Chacha support ('0': no, '1': yes) */ 1485 #define CPUSS_CRYPTO_CHACHA 1u 1486 /* Pseudo random number generation support ('0': no, '1': yes) */ 1487 #define CPUSS_CRYPTO_PR 1u 1488 /* SHA1 hash support ('0': no, '1': yes) */ 1489 #define CPUSS_CRYPTO_SHA1 1u 1490 /* SHA2 hash support ('0': no, '1': yes) */ 1491 #define CPUSS_CRYPTO_SHA2 1u 1492 /* SHA3 hash support ('0': no, '1': yes) */ 1493 #define CPUSS_CRYPTO_SHA3 1u 1494 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 1495 #define CPUSS_CRYPTO_CRC 1u 1496 /* True random number generation support ('0': no, '1': yes) */ 1497 #define CPUSS_CRYPTO_TR 1u 1498 /* Vector unit support ('0': no, '1': yes) */ 1499 #define CPUSS_CRYPTO_VU 1u 1500 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 1501 #define CPUSS_CRYPTO_GCM 1u 1502 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 1503 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 1504 kB and 16 kB memory buffer) */ 1505 #define CPUSS_CRYPTO_BUFF_SIZE 1024u 1506 /* Number of DMA controller channels ([1, 8]) */ 1507 #define CPUSS_DMAC_CH_NR 2u 1508 /* Number of DataWire controllers present (max 2) */ 1509 #define CPUSS_DW_NR 2u 1510 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1511 #define CPUSS_DW_ECC_PRESENT 0u 1512 /* Number of fault structures. Legal range [1, 4] */ 1513 #define CPUSS_FAULT_FAULT_NR 2u 1514 /* Number of Flash BIST_DATA registers */ 1515 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u 1516 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 1517 #define CPUSS_FLASHC_PA_SIZE 128u 1518 /* SONOS Flash is used or not ('0': no, '1': yes) */ 1519 #define CPUSS_FLASHC_FLASHC_IS_SONOS 1u 1520 /* eCT Flash is used or not ('0': no, '1': yes) */ 1521 #define CPUSS_FLASHC_FLASHC_IS_ECT 0u 1522 /* Number of IPC structures. Legal range [1, 16] */ 1523 #define CPUSS_IPC_IPC_NR 16u 1524 /* Number of IPC interrupt structures. Legal range [1, 16] */ 1525 #define CPUSS_IPC_IPC_IRQ_NR 16u 1526 /* Master 0 protect contexts minus one */ 1527 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 1528 /* Master 1 protect contexts minus one */ 1529 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 1530 /* Master 2 protect contexts minus one */ 1531 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 1532 /* Master 3 protect contexts minus one */ 1533 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 1534 /* Master 4 protect contexts minus one */ 1535 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 1536 /* Master 5 protect contexts minus one */ 1537 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u 1538 /* Master 6 protect contexts minus one */ 1539 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 1540 /* Master 7 protect contexts minus one */ 1541 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 1542 /* Master 8 protect contexts minus one */ 1543 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 1544 /* Master 9 protect contexts minus one */ 1545 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 1546 /* Master 10 protect contexts minus one */ 1547 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 1548 /* Master 11 protect contexts minus one */ 1549 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 1550 /* Master 12 protect contexts minus one */ 1551 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 1552 /* Master 13 protect contexts minus one */ 1553 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u 1554 /* Master 14 protect contexts minus one */ 1555 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 1556 /* Master 15 protect contexts minus one */ 1557 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 1558 /* Number of SMPU protection structures */ 1559 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 1560 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 1561 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 1562 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 1563 #define EFUSE_EFUSE_NR 4u 1564 /* Number of GPIO ports in range 0..31 */ 1565 #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u 1566 /* Number of GPIO ports in range 32..63 */ 1567 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 1568 /* Number of GPIO ports in range 64..95 */ 1569 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 1570 /* Number of GPIO ports in range 96..127 */ 1571 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 1572 /* Number of ports in device */ 1573 #define IOSS_GPIO_GPIO_PORT_NR 15u 1574 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1575 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 1576 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1577 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 1578 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1579 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 1580 /* Indicates that pin #0 exists for this port with slew control feature */ 1581 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 1582 /* Indicates that pin #1 exists for this port with slew control feature */ 1583 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 1584 /* Indicates that pin #2 exists for this port with slew control feature */ 1585 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 1586 /* Indicates that pin #3 exists for this port with slew control feature */ 1587 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 1588 /* Indicates that pin #4 exists for this port with slew control feature */ 1589 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u 1590 /* Indicates that pin #5 exists for this port with slew control feature */ 1591 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u 1592 /* Indicates that pin #6 exists for this port with slew control feature */ 1593 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 1594 /* Indicates that pin #7 exists for this port with slew control feature */ 1595 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 1596 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1597 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 0u 1598 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1599 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 1600 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1601 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u 1602 /* Indicates that pin #0 exists for this port with slew control feature */ 1603 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 1604 /* Indicates that pin #1 exists for this port with slew control feature */ 1605 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 1606 /* Indicates that pin #2 exists for this port with slew control feature */ 1607 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 1608 /* Indicates that pin #3 exists for this port with slew control feature */ 1609 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 1610 /* Indicates that pin #4 exists for this port with slew control feature */ 1611 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 1612 /* Indicates that pin #5 exists for this port with slew control feature */ 1613 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 1614 /* Indicates that pin #6 exists for this port with slew control feature */ 1615 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 1616 /* Indicates that pin #7 exists for this port with slew control feature */ 1617 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 1618 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1619 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 1620 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1621 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 1622 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1623 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 1u 1624 /* Indicates that pin #0 exists for this port with slew control feature */ 1625 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u 1626 /* Indicates that pin #1 exists for this port with slew control feature */ 1627 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u 1628 /* Indicates that pin #2 exists for this port with slew control feature */ 1629 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u 1630 /* Indicates that pin #3 exists for this port with slew control feature */ 1631 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u 1632 /* Indicates that pin #4 exists for this port with slew control feature */ 1633 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u 1634 /* Indicates that pin #5 exists for this port with slew control feature */ 1635 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u 1636 /* Indicates that pin #6 exists for this port with slew control feature */ 1637 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u 1638 /* Indicates that pin #7 exists for this port with slew control feature */ 1639 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u 1640 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1641 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 1642 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1643 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 1644 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1645 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 1u 1646 /* Indicates that pin #0 exists for this port with slew control feature */ 1647 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u 1648 /* Indicates that pin #1 exists for this port with slew control feature */ 1649 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u 1650 /* Indicates that pin #2 exists for this port with slew control feature */ 1651 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 1652 /* Indicates that pin #3 exists for this port with slew control feature */ 1653 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 1654 /* Indicates that pin #4 exists for this port with slew control feature */ 1655 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 1656 /* Indicates that pin #5 exists for this port with slew control feature */ 1657 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 1658 /* Indicates that pin #6 exists for this port with slew control feature */ 1659 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 1660 /* Indicates that pin #7 exists for this port with slew control feature */ 1661 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 1662 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1663 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 0u 1664 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1665 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 1666 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1667 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u 1668 /* Indicates that pin #0 exists for this port with slew control feature */ 1669 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 1670 /* Indicates that pin #1 exists for this port with slew control feature */ 1671 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 1672 /* Indicates that pin #2 exists for this port with slew control feature */ 1673 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 1674 /* Indicates that pin #3 exists for this port with slew control feature */ 1675 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 1676 /* Indicates that pin #4 exists for this port with slew control feature */ 1677 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 1678 /* Indicates that pin #5 exists for this port with slew control feature */ 1679 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 1680 /* Indicates that pin #6 exists for this port with slew control feature */ 1681 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 1682 /* Indicates that pin #7 exists for this port with slew control feature */ 1683 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 1684 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1685 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 1686 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1687 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 1688 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1689 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 1690 /* Indicates that pin #0 exists for this port with slew control feature */ 1691 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u 1692 /* Indicates that pin #1 exists for this port with slew control feature */ 1693 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u 1694 /* Indicates that pin #2 exists for this port with slew control feature */ 1695 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 1696 /* Indicates that pin #3 exists for this port with slew control feature */ 1697 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 1698 /* Indicates that pin #4 exists for this port with slew control feature */ 1699 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 1700 /* Indicates that pin #5 exists for this port with slew control feature */ 1701 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 1702 /* Indicates that pin #6 exists for this port with slew control feature */ 1703 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u 1704 /* Indicates that pin #7 exists for this port with slew control feature */ 1705 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u 1706 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1707 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 1708 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1709 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 1710 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1711 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 1u 1712 /* Indicates that pin #0 exists for this port with slew control feature */ 1713 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 1u 1714 /* Indicates that pin #1 exists for this port with slew control feature */ 1715 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 1u 1716 /* Indicates that pin #2 exists for this port with slew control feature */ 1717 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u 1718 /* Indicates that pin #3 exists for this port with slew control feature */ 1719 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u 1720 /* Indicates that pin #4 exists for this port with slew control feature */ 1721 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u 1722 /* Indicates that pin #5 exists for this port with slew control feature */ 1723 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u 1724 /* Indicates that pin #6 exists for this port with slew control feature */ 1725 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u 1726 /* Indicates that pin #7 exists for this port with slew control feature */ 1727 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u 1728 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1729 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 1730 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1731 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 1732 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1733 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 1u 1734 /* Indicates that pin #0 exists for this port with slew control feature */ 1735 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u 1736 /* Indicates that pin #1 exists for this port with slew control feature */ 1737 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u 1738 /* Indicates that pin #2 exists for this port with slew control feature */ 1739 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u 1740 /* Indicates that pin #3 exists for this port with slew control feature */ 1741 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u 1742 /* Indicates that pin #4 exists for this port with slew control feature */ 1743 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u 1744 /* Indicates that pin #5 exists for this port with slew control feature */ 1745 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u 1746 /* Indicates that pin #6 exists for this port with slew control feature */ 1747 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 1u 1748 /* Indicates that pin #7 exists for this port with slew control feature */ 1749 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u 1750 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1751 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 1752 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1753 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 1754 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1755 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 1756 /* Indicates that pin #0 exists for this port with slew control feature */ 1757 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u 1758 /* Indicates that pin #1 exists for this port with slew control feature */ 1759 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u 1760 /* Indicates that pin #2 exists for this port with slew control feature */ 1761 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 1u 1762 /* Indicates that pin #3 exists for this port with slew control feature */ 1763 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 1u 1764 /* Indicates that pin #4 exists for this port with slew control feature */ 1765 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 1766 /* Indicates that pin #5 exists for this port with slew control feature */ 1767 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 1768 /* Indicates that pin #6 exists for this port with slew control feature */ 1769 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 1770 /* Indicates that pin #7 exists for this port with slew control feature */ 1771 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 1772 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1773 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 1774 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1775 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 1776 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1777 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 1778 /* Indicates that pin #0 exists for this port with slew control feature */ 1779 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u 1780 /* Indicates that pin #1 exists for this port with slew control feature */ 1781 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u 1782 /* Indicates that pin #2 exists for this port with slew control feature */ 1783 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u 1784 /* Indicates that pin #3 exists for this port with slew control feature */ 1785 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u 1786 /* Indicates that pin #4 exists for this port with slew control feature */ 1787 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u 1788 /* Indicates that pin #5 exists for this port with slew control feature */ 1789 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u 1790 /* Indicates that pin #6 exists for this port with slew control feature */ 1791 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 1792 /* Indicates that pin #7 exists for this port with slew control feature */ 1793 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 1794 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1795 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 1796 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1797 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 1798 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1799 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 1800 /* Indicates that pin #0 exists for this port with slew control feature */ 1801 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u 1802 /* Indicates that pin #1 exists for this port with slew control feature */ 1803 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u 1804 /* Indicates that pin #2 exists for this port with slew control feature */ 1805 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u 1806 /* Indicates that pin #3 exists for this port with slew control feature */ 1807 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u 1808 /* Indicates that pin #4 exists for this port with slew control feature */ 1809 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u 1810 /* Indicates that pin #5 exists for this port with slew control feature */ 1811 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u 1812 /* Indicates that pin #6 exists for this port with slew control feature */ 1813 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u 1814 /* Indicates that pin #7 exists for this port with slew control feature */ 1815 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u 1816 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1817 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 1818 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1819 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 1820 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1821 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 1822 /* Indicates that pin #0 exists for this port with slew control feature */ 1823 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 1u 1824 /* Indicates that pin #1 exists for this port with slew control feature */ 1825 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u 1826 /* Indicates that pin #2 exists for this port with slew control feature */ 1827 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u 1828 /* Indicates that pin #3 exists for this port with slew control feature */ 1829 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u 1830 /* Indicates that pin #4 exists for this port with slew control feature */ 1831 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u 1832 /* Indicates that pin #5 exists for this port with slew control feature */ 1833 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u 1834 /* Indicates that pin #6 exists for this port with slew control feature */ 1835 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u 1836 /* Indicates that pin #7 exists for this port with slew control feature */ 1837 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u 1838 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1839 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 1840 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1841 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 1842 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1843 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 1u 1844 /* Indicates that pin #0 exists for this port with slew control feature */ 1845 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 1u 1846 /* Indicates that pin #1 exists for this port with slew control feature */ 1847 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 1u 1848 /* Indicates that pin #2 exists for this port with slew control feature */ 1849 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 1850 /* Indicates that pin #3 exists for this port with slew control feature */ 1851 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 1852 /* Indicates that pin #4 exists for this port with slew control feature */ 1853 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 1854 /* Indicates that pin #5 exists for this port with slew control feature */ 1855 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 1856 /* Indicates that pin #6 exists for this port with slew control feature */ 1857 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u 1858 /* Indicates that pin #7 exists for this port with slew control feature */ 1859 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u 1860 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1861 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 0u 1862 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1863 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 1864 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1865 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u 1866 /* Indicates that pin #0 exists for this port with slew control feature */ 1867 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 1868 /* Indicates that pin #1 exists for this port with slew control feature */ 1869 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 1870 /* Indicates that pin #2 exists for this port with slew control feature */ 1871 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 1872 /* Indicates that pin #3 exists for this port with slew control feature */ 1873 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 1874 /* Indicates that pin #4 exists for this port with slew control feature */ 1875 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 1876 /* Indicates that pin #5 exists for this port with slew control feature */ 1877 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 1878 /* Indicates that pin #6 exists for this port with slew control feature */ 1879 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 1880 /* Indicates that pin #7 exists for this port with slew control feature */ 1881 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 1882 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1883 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u 1884 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1885 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 1886 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1887 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u 1888 /* Indicates that pin #0 exists for this port with slew control feature */ 1889 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u 1890 /* Indicates that pin #1 exists for this port with slew control feature */ 1891 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u 1892 /* Indicates that pin #2 exists for this port with slew control feature */ 1893 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 1894 /* Indicates that pin #3 exists for this port with slew control feature */ 1895 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 1896 /* Indicates that pin #4 exists for this port with slew control feature */ 1897 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 1898 /* Indicates that pin #5 exists for this port with slew control feature */ 1899 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 1900 /* Indicates that pin #6 exists for this port with slew control feature */ 1901 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 1902 /* Indicates that pin #7 exists for this port with slew control feature */ 1903 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 1904 /* Number of AMUX splitter cells */ 1905 #define IOSS_HSIOM_AMUX_SPLIT_NR 6u 1906 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 1907 #define IOSS_HSIOM_HSIOM_PORT_NR 15u 1908 /* Number of PWR/GND MONITOR CELLs in the device */ 1909 #define IOSS_HSIOM_MONITOR_NR 0u 1910 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 1911 #define IOSS_HSIOM_MONITOR_NR_0_31 0u 1912 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 1913 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 1914 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 1915 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 1916 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 1917 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 1918 /* Indicates the presence of alternate JTAG interface */ 1919 #define IOSS_HSIOM_ALTJTAG_PRESENT 0u 1920 /* Mask of SMARTIO instances presence */ 1921 #define IOSS_SMARTIO_SMARTIO_MASK 768u 1922 /* Number of ports supoprting up to 4 COMs */ 1923 #define LCD_NUMPORTS 8u 1924 /* Number of ports supporting up to 8 COMs */ 1925 #define LCD_NUMPORTS8 8u 1926 /* Number of ports supporting up to 16 COMs */ 1927 #define LCD_NUMPORTS16 0u 1928 /* Max number of LCD commons supported */ 1929 #define LCD_CHIP_TOP_COM_NR 8u 1930 /* Max number of LCD pins (total) supported */ 1931 #define LCD_CHIP_TOP_PIN_NR 60u 1932 /* Number of IREF outputs from AREF */ 1933 #define PASS_NR_IREFS 4u 1934 /* Number of CTBs in the Subsystem */ 1935 #define PASS_NR_CTBS 0u 1936 /* Number of CTDACs in the Subsystem */ 1937 #define PASS_NR_CTDACS 0u 1938 /* CTB0 Exists */ 1939 #define PASS_CTB0_EXISTS 0u 1940 /* CTB1 Exists */ 1941 #define PASS_CTB1_EXISTS 0u 1942 /* CTB2 Exists */ 1943 #define PASS_CTB2_EXISTS 0u 1944 /* CTB3 Exists */ 1945 #define PASS_CTB3_EXISTS 0u 1946 /* CTDAC0 Exists */ 1947 #define PASS_CTDAC0_EXISTS 0u 1948 /* CTDAC1 Exists */ 1949 #define PASS_CTDAC1_EXISTS 0u 1950 /* CTDAC2 Exists */ 1951 #define PASS_CTDAC2_EXISTS 0u 1952 /* CTDAC3 Exists */ 1953 #define PASS_CTDAC3_EXISTS 0u 1954 #define PASS_CTBM_CTDAC_PRESENT 0u 1955 /* Number of SAR channels */ 1956 #define PASS_SAR_SAR_CHANNELS 16u 1957 /* Averaging logic present in SAR */ 1958 #define PASS_SAR_SAR_AVERAGE 1u 1959 /* Range detect logic present in SAR */ 1960 #define PASS_SAR_SAR_RANGEDET 1u 1961 /* Support for UAB sampling */ 1962 #define PASS_SAR_SAR_UAB 0u 1963 /* The number of protection contexts ([2, 16]). */ 1964 #define PERI_PC_NR 8u 1965 /* Master interface presence mask (4 bits) */ 1966 #define PERI_MS_PRESENT 15u 1967 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 1968 #define PERI_ECC_PRESENT 0u 1969 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 1970 #define PERI_ECC_ADDR_PRESENT 0u 1971 /* Clock control functionality present ('0': no, '1': yes) */ 1972 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 1973 /* Slave present (0:No, 1:Yes) */ 1974 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 1975 /* Slave present (0:No, 1:Yes) */ 1976 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 1977 /* Slave present (0:No, 1:Yes) */ 1978 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u 1979 /* Slave present (0:No, 1:Yes) */ 1980 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 1981 /* Slave present (0:No, 1:Yes) */ 1982 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 1983 /* Slave present (0:No, 1:Yes) */ 1984 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 1985 /* Slave present (0:No, 1:Yes) */ 1986 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 1987 /* Slave present (0:No, 1:Yes) */ 1988 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 1989 /* Slave present (0:No, 1:Yes) */ 1990 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 1991 /* Slave present (0:No, 1:Yes) */ 1992 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 1993 /* Slave present (0:No, 1:Yes) */ 1994 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 1995 /* Slave present (0:No, 1:Yes) */ 1996 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 1997 /* Slave present (0:No, 1:Yes) */ 1998 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 1999 /* Slave present (0:No, 1:Yes) */ 2000 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2001 /* Slave present (0:No, 1:Yes) */ 2002 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2003 /* Slave present (0:No, 1:Yes) */ 2004 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2005 /* Clock control functionality present ('0': no, '1': yes) */ 2006 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2007 /* Slave present (0:No, 1:Yes) */ 2008 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2009 /* Slave present (0:No, 1:Yes) */ 2010 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2011 /* Slave present (0:No, 1:Yes) */ 2012 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2013 /* Slave present (0:No, 1:Yes) */ 2014 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2015 /* Slave present (0:No, 1:Yes) */ 2016 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2017 /* Slave present (0:No, 1:Yes) */ 2018 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2019 /* Slave present (0:No, 1:Yes) */ 2020 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2021 /* Slave present (0:No, 1:Yes) */ 2022 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2023 /* Slave present (0:No, 1:Yes) */ 2024 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2025 /* Slave present (0:No, 1:Yes) */ 2026 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2027 /* Slave present (0:No, 1:Yes) */ 2028 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2029 /* Slave present (0:No, 1:Yes) */ 2030 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2031 /* Slave present (0:No, 1:Yes) */ 2032 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2033 /* Slave present (0:No, 1:Yes) */ 2034 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2035 /* Slave present (0:No, 1:Yes) */ 2036 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2037 /* Slave present (0:No, 1:Yes) */ 2038 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2039 /* Clock control functionality present ('0': no, '1': yes) */ 2040 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2041 /* Slave present (0:No, 1:Yes) */ 2042 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2043 /* Slave present (0:No, 1:Yes) */ 2044 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2045 /* Slave present (0:No, 1:Yes) */ 2046 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2047 /* Slave present (0:No, 1:Yes) */ 2048 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2049 /* Slave present (0:No, 1:Yes) */ 2050 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2051 /* Slave present (0:No, 1:Yes) */ 2052 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2053 /* Slave present (0:No, 1:Yes) */ 2054 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2055 /* Slave present (0:No, 1:Yes) */ 2056 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2057 /* Slave present (0:No, 1:Yes) */ 2058 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2059 /* Slave present (0:No, 1:Yes) */ 2060 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2061 /* Slave present (0:No, 1:Yes) */ 2062 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2063 /* Slave present (0:No, 1:Yes) */ 2064 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2065 /* Slave present (0:No, 1:Yes) */ 2066 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u 2067 /* Slave present (0:No, 1:Yes) */ 2068 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2069 /* Slave present (0:No, 1:Yes) */ 2070 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2071 /* Slave present (0:No, 1:Yes) */ 2072 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2073 /* Clock control functionality present ('0': no, '1': yes) */ 2074 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2075 /* Slave present (0:No, 1:Yes) */ 2076 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2077 /* Slave present (0:No, 1:Yes) */ 2078 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2079 /* Slave present (0:No, 1:Yes) */ 2080 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2081 /* Slave present (0:No, 1:Yes) */ 2082 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2083 /* Slave present (0:No, 1:Yes) */ 2084 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2085 /* Slave present (0:No, 1:Yes) */ 2086 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2087 /* Slave present (0:No, 1:Yes) */ 2088 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2089 /* Slave present (0:No, 1:Yes) */ 2090 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2091 /* Slave present (0:No, 1:Yes) */ 2092 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2093 /* Slave present (0:No, 1:Yes) */ 2094 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2095 /* Slave present (0:No, 1:Yes) */ 2096 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2097 /* Slave present (0:No, 1:Yes) */ 2098 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u 2099 /* Slave present (0:No, 1:Yes) */ 2100 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2101 /* Slave present (0:No, 1:Yes) */ 2102 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2103 /* Slave present (0:No, 1:Yes) */ 2104 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2105 /* Slave present (0:No, 1:Yes) */ 2106 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u 2107 /* Clock control functionality present ('0': no, '1': yes) */ 2108 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2109 /* Slave present (0:No, 1:Yes) */ 2110 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2111 /* Slave present (0:No, 1:Yes) */ 2112 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2113 /* Slave present (0:No, 1:Yes) */ 2114 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2115 /* Slave present (0:No, 1:Yes) */ 2116 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2117 /* Slave present (0:No, 1:Yes) */ 2118 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2119 /* Slave present (0:No, 1:Yes) */ 2120 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2121 /* Slave present (0:No, 1:Yes) */ 2122 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2123 /* Slave present (0:No, 1:Yes) */ 2124 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2125 /* Slave present (0:No, 1:Yes) */ 2126 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2127 /* Slave present (0:No, 1:Yes) */ 2128 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2129 /* Slave present (0:No, 1:Yes) */ 2130 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2131 /* Slave present (0:No, 1:Yes) */ 2132 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2133 /* Slave present (0:No, 1:Yes) */ 2134 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2135 /* Slave present (0:No, 1:Yes) */ 2136 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2137 /* Slave present (0:No, 1:Yes) */ 2138 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2139 /* Slave present (0:No, 1:Yes) */ 2140 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2141 /* Clock control functionality present ('0': no, '1': yes) */ 2142 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2143 /* Slave present (0:No, 1:Yes) */ 2144 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2145 /* Slave present (0:No, 1:Yes) */ 2146 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2147 /* Slave present (0:No, 1:Yes) */ 2148 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2149 /* Slave present (0:No, 1:Yes) */ 2150 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2151 /* Slave present (0:No, 1:Yes) */ 2152 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2153 /* Slave present (0:No, 1:Yes) */ 2154 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2155 /* Slave present (0:No, 1:Yes) */ 2156 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2157 /* Slave present (0:No, 1:Yes) */ 2158 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2159 /* Slave present (0:No, 1:Yes) */ 2160 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2161 /* Slave present (0:No, 1:Yes) */ 2162 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2163 /* Slave present (0:No, 1:Yes) */ 2164 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2165 /* Slave present (0:No, 1:Yes) */ 2166 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2167 /* Slave present (0:No, 1:Yes) */ 2168 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2169 /* Slave present (0:No, 1:Yes) */ 2170 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2171 /* Slave present (0:No, 1:Yes) */ 2172 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2173 /* Slave present (0:No, 1:Yes) */ 2174 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2175 /* Clock control functionality present ('0': no, '1': yes) */ 2176 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2177 /* Slave present (0:No, 1:Yes) */ 2178 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2179 /* Slave present (0:No, 1:Yes) */ 2180 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2181 /* Slave present (0:No, 1:Yes) */ 2182 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2183 /* Slave present (0:No, 1:Yes) */ 2184 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2185 /* Slave present (0:No, 1:Yes) */ 2186 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2187 /* Slave present (0:No, 1:Yes) */ 2188 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2189 /* Slave present (0:No, 1:Yes) */ 2190 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2191 /* Slave present (0:No, 1:Yes) */ 2192 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2193 /* Slave present (0:No, 1:Yes) */ 2194 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2195 /* Slave present (0:No, 1:Yes) */ 2196 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2197 /* Slave present (0:No, 1:Yes) */ 2198 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2199 /* Slave present (0:No, 1:Yes) */ 2200 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2201 /* Slave present (0:No, 1:Yes) */ 2202 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2203 /* Slave present (0:No, 1:Yes) */ 2204 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2205 /* Slave present (0:No, 1:Yes) */ 2206 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2207 /* Slave present (0:No, 1:Yes) */ 2208 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2209 /* Clock control functionality present ('0': no, '1': yes) */ 2210 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2211 /* Slave present (0:No, 1:Yes) */ 2212 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2213 /* Slave present (0:No, 1:Yes) */ 2214 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2215 /* Slave present (0:No, 1:Yes) */ 2216 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2217 /* Slave present (0:No, 1:Yes) */ 2218 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2219 /* Slave present (0:No, 1:Yes) */ 2220 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2221 /* Slave present (0:No, 1:Yes) */ 2222 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2223 /* Slave present (0:No, 1:Yes) */ 2224 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2225 /* Slave present (0:No, 1:Yes) */ 2226 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2227 /* Slave present (0:No, 1:Yes) */ 2228 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2229 /* Slave present (0:No, 1:Yes) */ 2230 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2231 /* Slave present (0:No, 1:Yes) */ 2232 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2233 /* Slave present (0:No, 1:Yes) */ 2234 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2235 /* Slave present (0:No, 1:Yes) */ 2236 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2237 /* Slave present (0:No, 1:Yes) */ 2238 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2239 /* Slave present (0:No, 1:Yes) */ 2240 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2241 /* Slave present (0:No, 1:Yes) */ 2242 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2243 /* Clock control functionality present ('0': no, '1': yes) */ 2244 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2245 /* Slave present (0:No, 1:Yes) */ 2246 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2247 /* Slave present (0:No, 1:Yes) */ 2248 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2249 /* Slave present (0:No, 1:Yes) */ 2250 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2251 /* Slave present (0:No, 1:Yes) */ 2252 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2253 /* Slave present (0:No, 1:Yes) */ 2254 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2255 /* Slave present (0:No, 1:Yes) */ 2256 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2257 /* Slave present (0:No, 1:Yes) */ 2258 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2259 /* Slave present (0:No, 1:Yes) */ 2260 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2261 /* Slave present (0:No, 1:Yes) */ 2262 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2263 /* Slave present (0:No, 1:Yes) */ 2264 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2265 /* Slave present (0:No, 1:Yes) */ 2266 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2267 /* Slave present (0:No, 1:Yes) */ 2268 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2269 /* Slave present (0:No, 1:Yes) */ 2270 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2271 /* Slave present (0:No, 1:Yes) */ 2272 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2273 /* Slave present (0:No, 1:Yes) */ 2274 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2275 /* Slave present (0:No, 1:Yes) */ 2276 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2277 /* Clock control functionality present ('0': no, '1': yes) */ 2278 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2279 /* Slave present (0:No, 1:Yes) */ 2280 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2281 /* Slave present (0:No, 1:Yes) */ 2282 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2283 /* Slave present (0:No, 1:Yes) */ 2284 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2285 /* Slave present (0:No, 1:Yes) */ 2286 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2287 /* Slave present (0:No, 1:Yes) */ 2288 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2289 /* Slave present (0:No, 1:Yes) */ 2290 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2291 /* Slave present (0:No, 1:Yes) */ 2292 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2293 /* Slave present (0:No, 1:Yes) */ 2294 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2295 /* Slave present (0:No, 1:Yes) */ 2296 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2297 /* Slave present (0:No, 1:Yes) */ 2298 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2299 /* Slave present (0:No, 1:Yes) */ 2300 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2301 /* Slave present (0:No, 1:Yes) */ 2302 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2303 /* Slave present (0:No, 1:Yes) */ 2304 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2305 /* Slave present (0:No, 1:Yes) */ 2306 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2307 /* Slave present (0:No, 1:Yes) */ 2308 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2309 /* Slave present (0:No, 1:Yes) */ 2310 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2311 /* Clock control functionality present ('0': no, '1': yes) */ 2312 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2313 /* Slave present (0:No, 1:Yes) */ 2314 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2315 /* Slave present (0:No, 1:Yes) */ 2316 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2317 /* Slave present (0:No, 1:Yes) */ 2318 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2319 /* Slave present (0:No, 1:Yes) */ 2320 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2321 /* Slave present (0:No, 1:Yes) */ 2322 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2323 /* Slave present (0:No, 1:Yes) */ 2324 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2325 /* Slave present (0:No, 1:Yes) */ 2326 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2327 /* Slave present (0:No, 1:Yes) */ 2328 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2329 /* Slave present (0:No, 1:Yes) */ 2330 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2331 /* Slave present (0:No, 1:Yes) */ 2332 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2333 /* Slave present (0:No, 1:Yes) */ 2334 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2335 /* Slave present (0:No, 1:Yes) */ 2336 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2337 /* Slave present (0:No, 1:Yes) */ 2338 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2339 /* Slave present (0:No, 1:Yes) */ 2340 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2341 /* Slave present (0:No, 1:Yes) */ 2342 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2343 /* Slave present (0:No, 1:Yes) */ 2344 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2345 /* Clock control functionality present ('0': no, '1': yes) */ 2346 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2347 /* Slave present (0:No, 1:Yes) */ 2348 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2349 /* Slave present (0:No, 1:Yes) */ 2350 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2351 /* Slave present (0:No, 1:Yes) */ 2352 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2353 /* Slave present (0:No, 1:Yes) */ 2354 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2355 /* Slave present (0:No, 1:Yes) */ 2356 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2357 /* Slave present (0:No, 1:Yes) */ 2358 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2359 /* Slave present (0:No, 1:Yes) */ 2360 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2361 /* Slave present (0:No, 1:Yes) */ 2362 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2363 /* Slave present (0:No, 1:Yes) */ 2364 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2365 /* Slave present (0:No, 1:Yes) */ 2366 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2367 /* Slave present (0:No, 1:Yes) */ 2368 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2369 /* Slave present (0:No, 1:Yes) */ 2370 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2371 /* Slave present (0:No, 1:Yes) */ 2372 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2373 /* Slave present (0:No, 1:Yes) */ 2374 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2375 /* Slave present (0:No, 1:Yes) */ 2376 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2377 /* Slave present (0:No, 1:Yes) */ 2378 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2379 /* Clock control functionality present ('0': no, '1': yes) */ 2380 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2381 /* Slave present (0:No, 1:Yes) */ 2382 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2383 /* Slave present (0:No, 1:Yes) */ 2384 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2385 /* Slave present (0:No, 1:Yes) */ 2386 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2387 /* Slave present (0:No, 1:Yes) */ 2388 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2389 /* Slave present (0:No, 1:Yes) */ 2390 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2391 /* Slave present (0:No, 1:Yes) */ 2392 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2393 /* Slave present (0:No, 1:Yes) */ 2394 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2395 /* Slave present (0:No, 1:Yes) */ 2396 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2397 /* Slave present (0:No, 1:Yes) */ 2398 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2399 /* Slave present (0:No, 1:Yes) */ 2400 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2401 /* Slave present (0:No, 1:Yes) */ 2402 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2403 /* Slave present (0:No, 1:Yes) */ 2404 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2405 /* Slave present (0:No, 1:Yes) */ 2406 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2407 /* Slave present (0:No, 1:Yes) */ 2408 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2409 /* Slave present (0:No, 1:Yes) */ 2410 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2411 /* Slave present (0:No, 1:Yes) */ 2412 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2413 /* Clock control functionality present ('0': no, '1': yes) */ 2414 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2415 /* Slave present (0:No, 1:Yes) */ 2416 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2417 /* Slave present (0:No, 1:Yes) */ 2418 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2419 /* Slave present (0:No, 1:Yes) */ 2420 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2421 /* Slave present (0:No, 1:Yes) */ 2422 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2423 /* Slave present (0:No, 1:Yes) */ 2424 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2425 /* Slave present (0:No, 1:Yes) */ 2426 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2427 /* Slave present (0:No, 1:Yes) */ 2428 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2429 /* Slave present (0:No, 1:Yes) */ 2430 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2431 /* Slave present (0:No, 1:Yes) */ 2432 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2433 /* Slave present (0:No, 1:Yes) */ 2434 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2435 /* Slave present (0:No, 1:Yes) */ 2436 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2437 /* Slave present (0:No, 1:Yes) */ 2438 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2439 /* Slave present (0:No, 1:Yes) */ 2440 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2441 /* Slave present (0:No, 1:Yes) */ 2442 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2443 /* Slave present (0:No, 1:Yes) */ 2444 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2445 /* Slave present (0:No, 1:Yes) */ 2446 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2447 /* Clock control functionality present ('0': no, '1': yes) */ 2448 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2449 /* Slave present (0:No, 1:Yes) */ 2450 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2451 /* Slave present (0:No, 1:Yes) */ 2452 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2453 /* Slave present (0:No, 1:Yes) */ 2454 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2455 /* Slave present (0:No, 1:Yes) */ 2456 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2457 /* Slave present (0:No, 1:Yes) */ 2458 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2459 /* Slave present (0:No, 1:Yes) */ 2460 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2461 /* Slave present (0:No, 1:Yes) */ 2462 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2463 /* Slave present (0:No, 1:Yes) */ 2464 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2465 /* Slave present (0:No, 1:Yes) */ 2466 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2467 /* Slave present (0:No, 1:Yes) */ 2468 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2469 /* Slave present (0:No, 1:Yes) */ 2470 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2471 /* Slave present (0:No, 1:Yes) */ 2472 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2473 /* Slave present (0:No, 1:Yes) */ 2474 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2475 /* Slave present (0:No, 1:Yes) */ 2476 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2477 /* Slave present (0:No, 1:Yes) */ 2478 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2479 /* Slave present (0:No, 1:Yes) */ 2480 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2481 /* Clock control functionality present ('0': no, '1': yes) */ 2482 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2483 /* Slave present (0:No, 1:Yes) */ 2484 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2485 /* Slave present (0:No, 1:Yes) */ 2486 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2487 /* Slave present (0:No, 1:Yes) */ 2488 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2489 /* Slave present (0:No, 1:Yes) */ 2490 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2491 /* Slave present (0:No, 1:Yes) */ 2492 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2493 /* Slave present (0:No, 1:Yes) */ 2494 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2495 /* Slave present (0:No, 1:Yes) */ 2496 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2497 /* Slave present (0:No, 1:Yes) */ 2498 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2499 /* Slave present (0:No, 1:Yes) */ 2500 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2501 /* Slave present (0:No, 1:Yes) */ 2502 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2503 /* Slave present (0:No, 1:Yes) */ 2504 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2505 /* Slave present (0:No, 1:Yes) */ 2506 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2507 /* Slave present (0:No, 1:Yes) */ 2508 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2509 /* Slave present (0:No, 1:Yes) */ 2510 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2511 /* Slave present (0:No, 1:Yes) */ 2512 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2513 /* Slave present (0:No, 1:Yes) */ 2514 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2515 /* Number of programmable clocks (outputs) */ 2516 #define PERI_CLOCK_NR 28u 2517 /* Number of 8.0 dividers */ 2518 #define PERI_DIV_8_NR 4u 2519 /* Number of 16.0 dividers */ 2520 #define PERI_DIV_16_NR 8u 2521 /* Number of 16.5 (fractional) dividers */ 2522 #define PERI_DIV_16_5_NR 2u 2523 /* Number of 24.5 (fractional) dividers */ 2524 #define PERI_DIV_24_5_NR 1u 2525 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 2526 #define PERI_DIV_ADDR_WIDTH 3u 2527 /* Timeout functionality present ('0': no, '1': yes) */ 2528 #define PERI_TIMEOUT_PRESENT 1u 2529 /* Trigger module present (0=No, 1=Yes) */ 2530 #define PERI_TR 1u 2531 /* Number of trigger groups */ 2532 #define PERI_TR_GROUP_NR 11u 2533 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2534 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2535 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2536 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2537 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2538 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2539 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2540 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2541 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2542 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2543 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2544 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2545 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2546 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2547 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2548 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2549 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2550 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2551 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2552 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2553 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 2554 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u 2555 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2556 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2557 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2558 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2559 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2560 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2561 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2562 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2563 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2564 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2565 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2566 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2567 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2568 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2569 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 2570 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 2571 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2572 #define PERI_MASTER_WIDTH 8u 2573 /* DeepSleep support ('0':no, '1': yes) */ 2574 #define SCB0_DEEPSLEEP 0u 2575 /* Externally clocked support? ('0': no, '1': yes) */ 2576 #define SCB0_EC 0u 2577 /* I2C master support? ('0': no, '1': yes) */ 2578 #define SCB0_I2C_M 1u 2579 /* I2C slave support? ('0': no, '1': yes) */ 2580 #define SCB0_I2C_S 1u 2581 /* I2C support? (I2C_M | I2C_S) */ 2582 #define SCB0_I2C 1u 2583 /* I2C glitch filters present? ('0': no, '1': yes) */ 2584 #define SCB0_I2C_GLITCH 1u 2585 /* I2C externally clocked support? ('0': no, '1': yes) */ 2586 #define SCB0_I2C_EC 0u 2587 /* I2C master and slave support? (I2C_M & I2C_S) */ 2588 #define SCB0_I2C_M_S 1u 2589 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2590 #define SCB0_I2C_S_EC 0u 2591 /* SPI master support? ('0': no, '1': yes) */ 2592 #define SCB0_SPI_M 1u 2593 /* SPI slave support? ('0': no, '1': yes) */ 2594 #define SCB0_SPI_S 1u 2595 /* SPI support? (SPI_M | SPI_S) */ 2596 #define SCB0_SPI 1u 2597 /* SPI externally clocked support? ('0': no, '1': yes) */ 2598 #define SCB0_SPI_EC 0u 2599 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2600 #define SCB0_SPI_S_EC 0u 2601 /* UART support? ('0': no, '1': yes) */ 2602 #define SCB0_UART 1u 2603 /* SPI or UART (SPI | UART) */ 2604 #define SCB0_SPI_UART 1u 2605 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2606 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2607 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2608 #define SCB0_EZ_DATA_NR 256u 2609 /* Command/response mode support? ('0': no, '1': yes) */ 2610 #define SCB0_CMD_RESP 0u 2611 /* EZ mode support? ('0': no, '1': yes) */ 2612 #define SCB0_EZ 0u 2613 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2614 #define SCB0_EZ_CMD_RESP 0u 2615 /* I2C slave with EZ mode (I2C_S & EZ) */ 2616 #define SCB0_I2C_S_EZ 0u 2617 /* SPI slave with EZ mode (SPI_S & EZ) */ 2618 #define SCB0_SPI_S_EZ 0u 2619 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2620 #define SCB0_I2C_FAST_PLUS 1u 2621 /* Number of used spi_select signals (max 4) */ 2622 #define SCB0_CHIP_TOP_SPI_SEL_NR 3u 2623 /* DeepSleep support ('0':no, '1': yes) */ 2624 #define SCB1_DEEPSLEEP 0u 2625 /* Externally clocked support? ('0': no, '1': yes) */ 2626 #define SCB1_EC 0u 2627 /* I2C master support? ('0': no, '1': yes) */ 2628 #define SCB1_I2C_M 1u 2629 /* I2C slave support? ('0': no, '1': yes) */ 2630 #define SCB1_I2C_S 1u 2631 /* I2C support? (I2C_M | I2C_S) */ 2632 #define SCB1_I2C 1u 2633 /* I2C glitch filters present? ('0': no, '1': yes) */ 2634 #define SCB1_I2C_GLITCH 1u 2635 /* I2C externally clocked support? ('0': no, '1': yes) */ 2636 #define SCB1_I2C_EC 0u 2637 /* I2C master and slave support? (I2C_M & I2C_S) */ 2638 #define SCB1_I2C_M_S 1u 2639 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2640 #define SCB1_I2C_S_EC 0u 2641 /* SPI master support? ('0': no, '1': yes) */ 2642 #define SCB1_SPI_M 1u 2643 /* SPI slave support? ('0': no, '1': yes) */ 2644 #define SCB1_SPI_S 1u 2645 /* SPI support? (SPI_M | SPI_S) */ 2646 #define SCB1_SPI 1u 2647 /* SPI externally clocked support? ('0': no, '1': yes) */ 2648 #define SCB1_SPI_EC 0u 2649 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2650 #define SCB1_SPI_S_EC 0u 2651 /* UART support? ('0': no, '1': yes) */ 2652 #define SCB1_UART 1u 2653 /* SPI or UART (SPI | UART) */ 2654 #define SCB1_SPI_UART 1u 2655 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2656 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2657 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2658 #define SCB1_EZ_DATA_NR 256u 2659 /* Command/response mode support? ('0': no, '1': yes) */ 2660 #define SCB1_CMD_RESP 0u 2661 /* EZ mode support? ('0': no, '1': yes) */ 2662 #define SCB1_EZ 0u 2663 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2664 #define SCB1_EZ_CMD_RESP 0u 2665 /* I2C slave with EZ mode (I2C_S & EZ) */ 2666 #define SCB1_I2C_S_EZ 0u 2667 /* SPI slave with EZ mode (SPI_S & EZ) */ 2668 #define SCB1_SPI_S_EZ 0u 2669 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2670 #define SCB1_I2C_FAST_PLUS 1u 2671 /* Number of used spi_select signals (max 4) */ 2672 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 2673 /* DeepSleep support ('0':no, '1': yes) */ 2674 #define SCB2_DEEPSLEEP 0u 2675 /* Externally clocked support? ('0': no, '1': yes) */ 2676 #define SCB2_EC 0u 2677 /* I2C master support? ('0': no, '1': yes) */ 2678 #define SCB2_I2C_M 1u 2679 /* I2C slave support? ('0': no, '1': yes) */ 2680 #define SCB2_I2C_S 1u 2681 /* I2C support? (I2C_M | I2C_S) */ 2682 #define SCB2_I2C 1u 2683 /* I2C glitch filters present? ('0': no, '1': yes) */ 2684 #define SCB2_I2C_GLITCH 1u 2685 /* I2C externally clocked support? ('0': no, '1': yes) */ 2686 #define SCB2_I2C_EC 0u 2687 /* I2C master and slave support? (I2C_M & I2C_S) */ 2688 #define SCB2_I2C_M_S 1u 2689 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2690 #define SCB2_I2C_S_EC 0u 2691 /* SPI master support? ('0': no, '1': yes) */ 2692 #define SCB2_SPI_M 1u 2693 /* SPI slave support? ('0': no, '1': yes) */ 2694 #define SCB2_SPI_S 1u 2695 /* SPI support? (SPI_M | SPI_S) */ 2696 #define SCB2_SPI 1u 2697 /* SPI externally clocked support? ('0': no, '1': yes) */ 2698 #define SCB2_SPI_EC 0u 2699 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2700 #define SCB2_SPI_S_EC 0u 2701 /* UART support? ('0': no, '1': yes) */ 2702 #define SCB2_UART 1u 2703 /* SPI or UART (SPI | UART) */ 2704 #define SCB2_SPI_UART 1u 2705 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2706 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2707 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2708 #define SCB2_EZ_DATA_NR 256u 2709 /* Command/response mode support? ('0': no, '1': yes) */ 2710 #define SCB2_CMD_RESP 0u 2711 /* EZ mode support? ('0': no, '1': yes) */ 2712 #define SCB2_EZ 0u 2713 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2714 #define SCB2_EZ_CMD_RESP 0u 2715 /* I2C slave with EZ mode (I2C_S & EZ) */ 2716 #define SCB2_I2C_S_EZ 0u 2717 /* SPI slave with EZ mode (SPI_S & EZ) */ 2718 #define SCB2_SPI_S_EZ 0u 2719 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2720 #define SCB2_I2C_FAST_PLUS 1u 2721 /* Number of used spi_select signals (max 4) */ 2722 #define SCB2_CHIP_TOP_SPI_SEL_NR 1u 2723 /* DeepSleep support ('0':no, '1': yes) */ 2724 #define SCB3_DEEPSLEEP 0u 2725 /* Externally clocked support? ('0': no, '1': yes) */ 2726 #define SCB3_EC 0u 2727 /* I2C master support? ('0': no, '1': yes) */ 2728 #define SCB3_I2C_M 1u 2729 /* I2C slave support? ('0': no, '1': yes) */ 2730 #define SCB3_I2C_S 1u 2731 /* I2C support? (I2C_M | I2C_S) */ 2732 #define SCB3_I2C 1u 2733 /* I2C glitch filters present? ('0': no, '1': yes) */ 2734 #define SCB3_I2C_GLITCH 1u 2735 /* I2C externally clocked support? ('0': no, '1': yes) */ 2736 #define SCB3_I2C_EC 0u 2737 /* I2C master and slave support? (I2C_M & I2C_S) */ 2738 #define SCB3_I2C_M_S 1u 2739 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2740 #define SCB3_I2C_S_EC 0u 2741 /* SPI master support? ('0': no, '1': yes) */ 2742 #define SCB3_SPI_M 1u 2743 /* SPI slave support? ('0': no, '1': yes) */ 2744 #define SCB3_SPI_S 1u 2745 /* SPI support? (SPI_M | SPI_S) */ 2746 #define SCB3_SPI 1u 2747 /* SPI externally clocked support? ('0': no, '1': yes) */ 2748 #define SCB3_SPI_EC 0u 2749 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2750 #define SCB3_SPI_S_EC 0u 2751 /* UART support? ('0': no, '1': yes) */ 2752 #define SCB3_UART 1u 2753 /* SPI or UART (SPI | UART) */ 2754 #define SCB3_SPI_UART 1u 2755 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2756 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2757 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2758 #define SCB3_EZ_DATA_NR 256u 2759 /* Command/response mode support? ('0': no, '1': yes) */ 2760 #define SCB3_CMD_RESP 0u 2761 /* EZ mode support? ('0': no, '1': yes) */ 2762 #define SCB3_EZ 0u 2763 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2764 #define SCB3_EZ_CMD_RESP 0u 2765 /* I2C slave with EZ mode (I2C_S & EZ) */ 2766 #define SCB3_I2C_S_EZ 0u 2767 /* SPI slave with EZ mode (SPI_S & EZ) */ 2768 #define SCB3_SPI_S_EZ 0u 2769 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2770 #define SCB3_I2C_FAST_PLUS 1u 2771 /* Number of used spi_select signals (max 4) */ 2772 #define SCB3_CHIP_TOP_SPI_SEL_NR 1u 2773 /* DeepSleep support ('0':no, '1': yes) */ 2774 #define SCB4_DEEPSLEEP 0u 2775 /* Externally clocked support? ('0': no, '1': yes) */ 2776 #define SCB4_EC 0u 2777 /* I2C master support? ('0': no, '1': yes) */ 2778 #define SCB4_I2C_M 1u 2779 /* I2C slave support? ('0': no, '1': yes) */ 2780 #define SCB4_I2C_S 1u 2781 /* I2C support? (I2C_M | I2C_S) */ 2782 #define SCB4_I2C 1u 2783 /* I2C glitch filters present? ('0': no, '1': yes) */ 2784 #define SCB4_I2C_GLITCH 1u 2785 /* I2C externally clocked support? ('0': no, '1': yes) */ 2786 #define SCB4_I2C_EC 0u 2787 /* I2C master and slave support? (I2C_M & I2C_S) */ 2788 #define SCB4_I2C_M_S 1u 2789 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2790 #define SCB4_I2C_S_EC 0u 2791 /* SPI master support? ('0': no, '1': yes) */ 2792 #define SCB4_SPI_M 1u 2793 /* SPI slave support? ('0': no, '1': yes) */ 2794 #define SCB4_SPI_S 1u 2795 /* SPI support? (SPI_M | SPI_S) */ 2796 #define SCB4_SPI 1u 2797 /* SPI externally clocked support? ('0': no, '1': yes) */ 2798 #define SCB4_SPI_EC 0u 2799 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2800 #define SCB4_SPI_S_EC 0u 2801 /* UART support? ('0': no, '1': yes) */ 2802 #define SCB4_UART 1u 2803 /* SPI or UART (SPI | UART) */ 2804 #define SCB4_SPI_UART 1u 2805 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2806 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2807 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2808 #define SCB4_EZ_DATA_NR 256u 2809 /* Command/response mode support? ('0': no, '1': yes) */ 2810 #define SCB4_CMD_RESP 0u 2811 /* EZ mode support? ('0': no, '1': yes) */ 2812 #define SCB4_EZ 0u 2813 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2814 #define SCB4_EZ_CMD_RESP 0u 2815 /* I2C slave with EZ mode (I2C_S & EZ) */ 2816 #define SCB4_I2C_S_EZ 0u 2817 /* SPI slave with EZ mode (SPI_S & EZ) */ 2818 #define SCB4_SPI_S_EZ 0u 2819 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2820 #define SCB4_I2C_FAST_PLUS 1u 2821 /* Number of used spi_select signals (max 4) */ 2822 #define SCB4_CHIP_TOP_SPI_SEL_NR 4u 2823 /* DeepSleep support ('0':no, '1': yes) */ 2824 #define SCB5_DEEPSLEEP 0u 2825 /* Externally clocked support? ('0': no, '1': yes) */ 2826 #define SCB5_EC 0u 2827 /* I2C master support? ('0': no, '1': yes) */ 2828 #define SCB5_I2C_M 1u 2829 /* I2C slave support? ('0': no, '1': yes) */ 2830 #define SCB5_I2C_S 1u 2831 /* I2C support? (I2C_M | I2C_S) */ 2832 #define SCB5_I2C 1u 2833 /* I2C glitch filters present? ('0': no, '1': yes) */ 2834 #define SCB5_I2C_GLITCH 1u 2835 /* I2C externally clocked support? ('0': no, '1': yes) */ 2836 #define SCB5_I2C_EC 0u 2837 /* I2C master and slave support? (I2C_M & I2C_S) */ 2838 #define SCB5_I2C_M_S 1u 2839 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2840 #define SCB5_I2C_S_EC 0u 2841 /* SPI master support? ('0': no, '1': yes) */ 2842 #define SCB5_SPI_M 1u 2843 /* SPI slave support? ('0': no, '1': yes) */ 2844 #define SCB5_SPI_S 1u 2845 /* SPI support? (SPI_M | SPI_S) */ 2846 #define SCB5_SPI 1u 2847 /* SPI externally clocked support? ('0': no, '1': yes) */ 2848 #define SCB5_SPI_EC 0u 2849 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2850 #define SCB5_SPI_S_EC 0u 2851 /* UART support? ('0': no, '1': yes) */ 2852 #define SCB5_UART 1u 2853 /* SPI or UART (SPI | UART) */ 2854 #define SCB5_SPI_UART 1u 2855 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2856 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2857 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2858 #define SCB5_EZ_DATA_NR 256u 2859 /* Command/response mode support? ('0': no, '1': yes) */ 2860 #define SCB5_CMD_RESP 0u 2861 /* EZ mode support? ('0': no, '1': yes) */ 2862 #define SCB5_EZ 0u 2863 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2864 #define SCB5_EZ_CMD_RESP 0u 2865 /* I2C slave with EZ mode (I2C_S & EZ) */ 2866 #define SCB5_I2C_S_EZ 0u 2867 /* SPI slave with EZ mode (SPI_S & EZ) */ 2868 #define SCB5_SPI_S_EZ 0u 2869 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2870 #define SCB5_I2C_FAST_PLUS 1u 2871 /* Number of used spi_select signals (max 4) */ 2872 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 2873 /* DeepSleep support ('0':no, '1': yes) */ 2874 #define SCB6_DEEPSLEEP 1u 2875 /* Externally clocked support? ('0': no, '1': yes) */ 2876 #define SCB6_EC 1u 2877 /* I2C master support? ('0': no, '1': yes) */ 2878 #define SCB6_I2C_M 1u 2879 /* I2C slave support? ('0': no, '1': yes) */ 2880 #define SCB6_I2C_S 1u 2881 /* I2C support? (I2C_M | I2C_S) */ 2882 #define SCB6_I2C 1u 2883 /* I2C glitch filters present? ('0': no, '1': yes) */ 2884 #define SCB6_I2C_GLITCH 1u 2885 /* I2C externally clocked support? ('0': no, '1': yes) */ 2886 #define SCB6_I2C_EC 1u 2887 /* I2C master and slave support? (I2C_M & I2C_S) */ 2888 #define SCB6_I2C_M_S 1u 2889 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2890 #define SCB6_I2C_S_EC 1u 2891 /* SPI master support? ('0': no, '1': yes) */ 2892 #define SCB6_SPI_M 1u 2893 /* SPI slave support? ('0': no, '1': yes) */ 2894 #define SCB6_SPI_S 1u 2895 /* SPI support? (SPI_M | SPI_S) */ 2896 #define SCB6_SPI 1u 2897 /* SPI externally clocked support? ('0': no, '1': yes) */ 2898 #define SCB6_SPI_EC 1u 2899 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2900 #define SCB6_SPI_S_EC 1u 2901 /* UART support? ('0': no, '1': yes) */ 2902 #define SCB6_UART 0u 2903 /* SPI or UART (SPI | UART) */ 2904 #define SCB6_SPI_UART 1u 2905 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2906 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2907 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2908 #define SCB6_EZ_DATA_NR 256u 2909 /* Command/response mode support? ('0': no, '1': yes) */ 2910 #define SCB6_CMD_RESP 1u 2911 /* EZ mode support? ('0': no, '1': yes) */ 2912 #define SCB6_EZ 1u 2913 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2914 #define SCB6_EZ_CMD_RESP 1u 2915 /* I2C slave with EZ mode (I2C_S & EZ) */ 2916 #define SCB6_I2C_S_EZ 1u 2917 /* SPI slave with EZ mode (SPI_S & EZ) */ 2918 #define SCB6_SPI_S_EZ 1u 2919 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2920 #define SCB6_I2C_FAST_PLUS 1u 2921 /* Number of used spi_select signals (max 4) */ 2922 #define SCB6_CHIP_TOP_SPI_SEL_NR 1u 2923 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 2924 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 2925 data) */ 2926 #define SDHC_MAX_BLK_SIZE 0u 2927 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 2928 adds 288 bytes of space to the RAM for this purpose. */ 2929 #define SDHC_CQE_PRESENT 0u 2930 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 2931 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 2932 parameter) */ 2933 #define SDHC_RETENTION_PRESENT 1u 2934 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 2935 pins) */ 2936 #define SDHC_CHIP_TOP_DATA8_PRESENT 0u 2937 /* Chip top connect card_detect */ 2938 #define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u 2939 /* Chip top connect card_mech_write_prot_in */ 2940 #define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u 2941 /* Chip top connect led_ctrl_out and led_ctrl_out_en */ 2942 #define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u 2943 /* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ 2944 #define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u 2945 /* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ 2946 #define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u 2947 /* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ 2948 #define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u 2949 /* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ 2950 #define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u 2951 /* Chip top connect interrupt_wakeup (not used for eMMC) */ 2952 #define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u 2953 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 2954 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 2955 data) */ 2956 #define SDHC_CORE_MAX_BLK_SIZE 0u 2957 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 2958 adds 288 bytes of space to the RAM for this purpose. */ 2959 #define SDHC_CORE_CQE_PRESENT 0u 2960 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 2961 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 2962 parameter) */ 2963 #define SDHC_CORE_RETENTION_PRESENT 1u 2964 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2965 #define SFLASH_FLASHC_IS_SONOS 1u 2966 /* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ 2967 #define SFLASH_CPUSS_WOUNDING_PRESENT 0u 2968 /* Base address of the SMIF XIP memory region. This address must be a multiple of 2969 the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This 2970 address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP 2971 memory region should NOT overlap with other memory regions. */ 2972 #define SMIF_SMIF_XIP_ADDR 0x18000000u 2973 /* Capacity of the SMIF XIP memory region. The more significant bits of this 2974 parameter must be '1' and the lesser significant bits of this paramter must 2975 be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are 2976 {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 2977 0xffe0:0000, ..., 0xe000:0000}. */ 2978 #define SMIF_SMIF_XIP_MASK 0xF8000000u 2979 /* Cryptography (AES) support ('0' = no support, '1' = support) */ 2980 #define SMIF_CRYPTO 1u 2981 /* Number of external devices supported ([1,4]) */ 2982 #define SMIF_DEVICE_NR 3u 2983 /* External device write support. This is a 4-bit field. Each external device has 2984 a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ 2985 #define SMIF_DEVICE_WR_EN 15u 2986 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2987 #define SMIF_MASTER_WIDTH 8u 2988 /* Chip top connect all 8 data pins (0= connect 4 or 6 data pins based on 2989 DATA6_PRESENT, 1= connect 8 data pins) */ 2990 #define SMIF_CHIP_TOP_DATA8_PRESENT 0u 2991 /* Number of used spi_select signals (max 4) */ 2992 #define SMIF_CHIP_TOP_SPI_SEL_NR 3u 2993 /* Number of regulator modules instantiated within SRSS, start with estimate, 2994 update after CMR feedback */ 2995 #define SRSS_NUM_ACTREG_PWRMOD 2u 2996 /* Number of shorting switches between vccd and vccact (target dynamic voltage 2997 drop < 10mV) */ 2998 #define SRSS_NUM_ACTIVE_SWITCH 3u 2999 /* ULP linear regulator system is present */ 3000 #define SRSS_ULPLINREG_PRESENT 1u 3001 /* HT linear regulator system is present */ 3002 #define SRSS_HTLINREG_PRESENT 0u 3003 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 3004 or SIMOBUCK_PRESENT. */ 3005 #define SRSS_BUCKCTL_PRESENT 1u 3006 /* Low-current SISO buck core regulator is present. Only compatible with ULP 3007 linear regulator system (ULPLINREG_PRESENT==1). */ 3008 #define SRSS_S40S_SISOBUCKLC_PRESENT 1u 3009 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 3010 system (ULPLINREG_PRESENT==1). */ 3011 #define SRSS_SIMOBUCK_PRESENT 0u 3012 /* Precision ILO (PILO) is present */ 3013 #define SRSS_PILO_PRESENT 0u 3014 /* External Crystal Oscillator is present (high frequency) */ 3015 #define SRSS_ECO_PRESENT 1u 3016 /* System Buck-Boost is present */ 3017 #define SRSS_SYSBB_PRESENT 0u 3018 /* Number of clock paths. Must be > 0 */ 3019 #define SRSS_NUM_CLKPATH 5u 3020 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 3021 #define SRSS_NUM_PLL 1u 3022 /* Number of HFCLK roots present. Must be > 0 */ 3023 #define SRSS_NUM_HFROOT 5u 3024 /* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ 3025 #define SRSS_NUM_HIBDATA 1u 3026 /* Backup domain is present (includes RTC and WCO) */ 3027 #define SRSS_BACKUP_PRESENT 1u 3028 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 3029 mask indicates presence of a CSV. */ 3030 #define SRSS_MASK_HFCSV 0u 3031 /* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ 3032 #define SRSS_WCOCSV_PRESENT 0u 3033 /* Number of software watchdog timers. */ 3034 #define SRSS_NUM_MCWDT 2u 3035 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 3036 #define SRSS_NUM_DSI 0u 3037 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 3038 #define SRSS_ALTHF_PRESENT 0u 3039 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 3040 #define SRSS_ALTLF_PRESENT 0u 3041 /* Use the hardened clkactfllmux block */ 3042 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 3043 /* Number of clock paths, including direct paths in hardened clkactfllmux block 3044 (Must be >= NUM_CLKPATH) */ 3045 #define SRSS_HARD_CLKPATH 6u 3046 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= 3047 NUM_PLL+1) */ 3048 #define SRSS_HARD_CLKPATHMUX 6u 3049 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ 3050 #define SRSS_HARD_HFROOT 6u 3051 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ 3052 #define SRSS_HARD_ECOMUX_PRESENT 1u 3053 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ 3054 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 3055 /* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for 3056 PSoC6ABLE2, PSoC6A2M. */ 3057 #define SRSS_SRSS_VER1P3 1u 3058 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 3059 #define SRSS_BACKUP_BMEM_PRESENT 0u 3060 /* Number of Backup registers to include (each is 32b). Only used when 3061 BACKUP_PRESENT==1. */ 3062 #define SRSS_BACKUP_NUM_BREG 16u 3063 /* Number of counters per IP (1..32) */ 3064 #define TCPWM0_CNT_NR 4u 3065 /* Counter width (in number of bits) */ 3066 #define TCPWM0_CNT_CNT_WIDTH 32u 3067 /* Number of counters per IP (1..32) */ 3068 #define TCPWM1_CNT_NR 8u 3069 /* Counter width (in number of bits) */ 3070 #define TCPWM1_CNT_CNT_WIDTH 16u 3071 3072 /* MMIO Targets Defines */ 3073 /* MMIO1.CRYPTO */ 3074 #define CY_MMIO_CRYPTO_GROUP_NR 1u 3075 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 3076 /* MMIO2.CPUSS */ 3077 #define CY_MMIO_CPUSS_GROUP_NR 2u 3078 #define CY_MMIO_CPUSS_SLAVE_NR 0u 3079 /* MMIO2.FAULT */ 3080 #define CY_MMIO_FAULT_GROUP_NR 2u 3081 #define CY_MMIO_FAULT_SLAVE_NR 1u 3082 /* MMIO2.IPC */ 3083 #define CY_MMIO_IPC_GROUP_NR 2u 3084 #define CY_MMIO_IPC_SLAVE_NR 2u 3085 /* MMIO2.PROT */ 3086 #define CY_MMIO_PROT_GROUP_NR 2u 3087 #define CY_MMIO_PROT_SLAVE_NR 3u 3088 /* MMIO2.FLASHC */ 3089 #define CY_MMIO_FLASHC_GROUP_NR 2u 3090 #define CY_MMIO_FLASHC_SLAVE_NR 4u 3091 /* MMIO2.SRSS */ 3092 #define CY_MMIO_SRSS_GROUP_NR 2u 3093 #define CY_MMIO_SRSS_SLAVE_NR 6u 3094 /* MMIO2.BACKUP */ 3095 #define CY_MMIO_BACKUP_GROUP_NR 2u 3096 #define CY_MMIO_BACKUP_SLAVE_NR 7u 3097 /* MMIO2.DW */ 3098 #define CY_MMIO_DW_GROUP_NR 2u 3099 #define CY_MMIO_DW_SLAVE_NR 8u 3100 /* MMIO2.DMAC */ 3101 #define CY_MMIO_DMAC_GROUP_NR 2u 3102 #define CY_MMIO_DMAC_SLAVE_NR 10u 3103 /* MMIO2.EFUSE */ 3104 #define CY_MMIO_EFUSE_GROUP_NR 2u 3105 #define CY_MMIO_EFUSE_SLAVE_NR 12u 3106 /* MMIO3.HSIOM */ 3107 #define CY_MMIO_HSIOM_GROUP_NR 3u 3108 #define CY_MMIO_HSIOM_SLAVE_NR 0u 3109 /* MMIO3.GPIO */ 3110 #define CY_MMIO_GPIO_GROUP_NR 3u 3111 #define CY_MMIO_GPIO_SLAVE_NR 1u 3112 /* MMIO3.SMARTIO */ 3113 #define CY_MMIO_SMARTIO_GROUP_NR 3u 3114 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 3115 /* MMIO3.LPCOMP */ 3116 #define CY_MMIO_LPCOMP_GROUP_NR 3u 3117 #define CY_MMIO_LPCOMP_SLAVE_NR 5u 3118 /* MMIO3.CSD0 */ 3119 #define CY_MMIO_CSD0_GROUP_NR 3u 3120 #define CY_MMIO_CSD0_SLAVE_NR 6u 3121 /* MMIO3.TCPWM0 */ 3122 #define CY_MMIO_TCPWM0_GROUP_NR 3u 3123 #define CY_MMIO_TCPWM0_SLAVE_NR 8u 3124 /* MMIO3.TCPWM1 */ 3125 #define CY_MMIO_TCPWM1_GROUP_NR 3u 3126 #define CY_MMIO_TCPWM1_SLAVE_NR 9u 3127 /* MMIO3.LCD0 */ 3128 #define CY_MMIO_LCD0_GROUP_NR 3u 3129 #define CY_MMIO_LCD0_SLAVE_NR 11u 3130 /* MMIO3.USBFS0 */ 3131 #define CY_MMIO_USBFS0_GROUP_NR 3u 3132 #define CY_MMIO_USBFS0_SLAVE_NR 15u 3133 /* MMIO4.SMIF0 */ 3134 #define CY_MMIO_SMIF0_GROUP_NR 4u 3135 #define CY_MMIO_SMIF0_SLAVE_NR 2u 3136 /* MMIO4.SDHC0 */ 3137 #define CY_MMIO_SDHC0_GROUP_NR 4u 3138 #define CY_MMIO_SDHC0_SLAVE_NR 6u 3139 /* MMIO5.CANFD0 */ 3140 #define CY_MMIO_CANFD0_GROUP_NR 5u 3141 #define CY_MMIO_CANFD0_SLAVE_NR 2u 3142 /* MMIO6.SCB0 */ 3143 #define CY_MMIO_SCB0_GROUP_NR 6u 3144 #define CY_MMIO_SCB0_SLAVE_NR 0u 3145 /* MMIO6.SCB1 */ 3146 #define CY_MMIO_SCB1_GROUP_NR 6u 3147 #define CY_MMIO_SCB1_SLAVE_NR 1u 3148 /* MMIO6.SCB2 */ 3149 #define CY_MMIO_SCB2_GROUP_NR 6u 3150 #define CY_MMIO_SCB2_SLAVE_NR 2u 3151 /* MMIO6.SCB3 */ 3152 #define CY_MMIO_SCB3_GROUP_NR 6u 3153 #define CY_MMIO_SCB3_SLAVE_NR 3u 3154 /* MMIO6.SCB4 */ 3155 #define CY_MMIO_SCB4_GROUP_NR 6u 3156 #define CY_MMIO_SCB4_SLAVE_NR 4u 3157 /* MMIO6.SCB5 */ 3158 #define CY_MMIO_SCB5_GROUP_NR 6u 3159 #define CY_MMIO_SCB5_SLAVE_NR 5u 3160 /* MMIO6.SCB6 */ 3161 #define CY_MMIO_SCB6_GROUP_NR 6u 3162 #define CY_MMIO_SCB6_SLAVE_NR 6u 3163 /* MMIO9.PASS */ 3164 #define CY_MMIO_PASS_GROUP_NR 9u 3165 #define CY_MMIO_PASS_SLAVE_NR 0u 3166 3167 /* Backward compatibility definitions */ 3168 #define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR 3169 #define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR 3170 3171 /* Protection regions */ 3172 typedef enum 3173 { 3174 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00002000 */ 3175 PROT_PERI_GR0_GROUP = 1, /* Address 0x40004010, size 0x00000004 */ 3176 PROT_PERI_GR1_GROUP = 2, /* Address 0x40004030, size 0x00000004 */ 3177 PROT_PERI_GR2_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 3178 PROT_PERI_GR3_GROUP = 4, /* Address 0x40004060, size 0x00000020 */ 3179 PROT_PERI_GR4_GROUP = 5, /* Address 0x40004080, size 0x00000020 */ 3180 PROT_PERI_GR5_GROUP = 6, /* Address 0x400040a0, size 0x00000020 */ 3181 PROT_PERI_GR6_GROUP = 7, /* Address 0x400040c0, size 0x00000020 */ 3182 PROT_PERI_GR9_GROUP = 8, /* Address 0x40004120, size 0x00000020 */ 3183 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 3184 PROT_CRYPTO_MAIN = 10, /* Address 0x40100000, size 0x00000400 */ 3185 PROT_CRYPTO_CRYPTO = 11, /* Address 0x40101000, size 0x00000800 */ 3186 PROT_CRYPTO_BOOT = 12, /* Address 0x40102000, size 0x00000100 */ 3187 PROT_CRYPTO_KEY0 = 13, /* Address 0x40102100, size 0x00000004 */ 3188 PROT_CRYPTO_KEY1 = 14, /* Address 0x40102120, size 0x00000004 */ 3189 PROT_CRYPTO_BUF = 15, /* Address 0x40108000, size 0x00001000 */ 3190 PROT_CPUSS_CM4 = 16, /* Address 0x40200000, size 0x00000400 */ 3191 PROT_CPUSS_CM0 = 17, /* Address 0x40201000, size 0x00001000 */ 3192 PROT_CPUSS_BOOT = 18, /* Address 0x40202000, size 0x00000200 */ 3193 PROT_CPUSS_CM0_INT = 19, /* Address 0x40208000, size 0x00000400 */ 3194 PROT_CPUSS_CM4_INT = 20, /* Address 0x4020a000, size 0x00000400 */ 3195 PROT_FAULT_STRUCT0_MAIN = 21, /* Address 0x40210000, size 0x00000100 */ 3196 PROT_FAULT_STRUCT1_MAIN = 22, /* Address 0x40210100, size 0x00000100 */ 3197 PROT_IPC_STRUCT0_IPC = 23, /* Address 0x40220000, size 0x00000020 */ 3198 PROT_IPC_STRUCT1_IPC = 24, /* Address 0x40220020, size 0x00000020 */ 3199 PROT_IPC_STRUCT2_IPC = 25, /* Address 0x40220040, size 0x00000020 */ 3200 PROT_IPC_STRUCT3_IPC = 26, /* Address 0x40220060, size 0x00000020 */ 3201 PROT_IPC_STRUCT4_IPC = 27, /* Address 0x40220080, size 0x00000020 */ 3202 PROT_IPC_STRUCT5_IPC = 28, /* Address 0x402200a0, size 0x00000020 */ 3203 PROT_IPC_STRUCT6_IPC = 29, /* Address 0x402200c0, size 0x00000020 */ 3204 PROT_IPC_STRUCT7_IPC = 30, /* Address 0x402200e0, size 0x00000020 */ 3205 PROT_IPC_STRUCT8_IPC = 31, /* Address 0x40220100, size 0x00000020 */ 3206 PROT_IPC_STRUCT9_IPC = 32, /* Address 0x40220120, size 0x00000020 */ 3207 PROT_IPC_STRUCT10_IPC = 33, /* Address 0x40220140, size 0x00000020 */ 3208 PROT_IPC_STRUCT11_IPC = 34, /* Address 0x40220160, size 0x00000020 */ 3209 PROT_IPC_STRUCT12_IPC = 35, /* Address 0x40220180, size 0x00000020 */ 3210 PROT_IPC_STRUCT13_IPC = 36, /* Address 0x402201a0, size 0x00000020 */ 3211 PROT_IPC_STRUCT14_IPC = 37, /* Address 0x402201c0, size 0x00000020 */ 3212 PROT_IPC_STRUCT15_IPC = 38, /* Address 0x402201e0, size 0x00000020 */ 3213 PROT_IPC_INTR_STRUCT0_INTR = 39, /* Address 0x40221000, size 0x00000010 */ 3214 PROT_IPC_INTR_STRUCT1_INTR = 40, /* Address 0x40221020, size 0x00000010 */ 3215 PROT_IPC_INTR_STRUCT2_INTR = 41, /* Address 0x40221040, size 0x00000010 */ 3216 PROT_IPC_INTR_STRUCT3_INTR = 42, /* Address 0x40221060, size 0x00000010 */ 3217 PROT_IPC_INTR_STRUCT4_INTR = 43, /* Address 0x40221080, size 0x00000010 */ 3218 PROT_IPC_INTR_STRUCT5_INTR = 44, /* Address 0x402210a0, size 0x00000010 */ 3219 PROT_IPC_INTR_STRUCT6_INTR = 45, /* Address 0x402210c0, size 0x00000010 */ 3220 PROT_IPC_INTR_STRUCT7_INTR = 46, /* Address 0x402210e0, size 0x00000010 */ 3221 PROT_IPC_INTR_STRUCT8_INTR = 47, /* Address 0x40221100, size 0x00000010 */ 3222 PROT_IPC_INTR_STRUCT9_INTR = 48, /* Address 0x40221120, size 0x00000010 */ 3223 PROT_IPC_INTR_STRUCT10_INTR = 49, /* Address 0x40221140, size 0x00000010 */ 3224 PROT_IPC_INTR_STRUCT11_INTR = 50, /* Address 0x40221160, size 0x00000010 */ 3225 PROT_IPC_INTR_STRUCT12_INTR = 51, /* Address 0x40221180, size 0x00000010 */ 3226 PROT_IPC_INTR_STRUCT13_INTR = 52, /* Address 0x402211a0, size 0x00000010 */ 3227 PROT_IPC_INTR_STRUCT14_INTR = 53, /* Address 0x402211c0, size 0x00000010 */ 3228 PROT_IPC_INTR_STRUCT15_INTR = 54, /* Address 0x402211e0, size 0x00000010 */ 3229 PROT_PROT_SMPU_MAIN = 55, /* Address 0x40230000, size 0x00000040 */ 3230 PROT_PROT_MPU0_MAIN = 56, /* Address 0x40234000, size 0x00000004 */ 3231 PROT_PROT_MPU5_MAIN = 57, /* Address 0x40235400, size 0x00000400 */ 3232 PROT_PROT_MPU14_MAIN = 58, /* Address 0x40237800, size 0x00000004 */ 3233 PROT_PROT_MPU15_MAIN = 59, /* Address 0x40237c00, size 0x00000400 */ 3234 PROT_FLASHC_MAIN = 60, /* Address 0x40240000, size 0x00000008 */ 3235 PROT_FLASHC_CMD = 61, /* Address 0x40240008, size 0x00000004 */ 3236 PROT_FLASHC_DFT = 62, /* Address 0x40240200, size 0x00000100 */ 3237 PROT_FLASHC_CM0 = 63, /* Address 0x40240400, size 0x00000080 */ 3238 PROT_FLASHC_CM4 = 64, /* Address 0x40240480, size 0x00000080 */ 3239 PROT_FLASHC_CRYPTO = 65, /* Address 0x40240500, size 0x00000004 */ 3240 PROT_FLASHC_DW0 = 66, /* Address 0x40240580, size 0x00000004 */ 3241 PROT_FLASHC_DW1 = 67, /* Address 0x40240600, size 0x00000004 */ 3242 PROT_FLASHC_DMAC = 68, /* Address 0x40240680, size 0x00000004 */ 3243 PROT_FLASHC_EXT_MS0 = 69, /* Address 0x40240700, size 0x00000004 */ 3244 PROT_FLASHC_FM = 70, /* Address 0x4024f000, size 0x00001000 */ 3245 PROT_SRSS_MAIN1 = 71, /* Address 0x40260000, size 0x00000100 */ 3246 PROT_SRSS_MAIN2 = 72, /* Address 0x40260100, size 0x00000010 */ 3247 PROT_WDT = 73, /* Address 0x40260180, size 0x00000010 */ 3248 PROT_MAIN = 74, /* Address 0x40260200, size 0x00000080 */ 3249 PROT_SRSS_MAIN3 = 75, /* Address 0x40260300, size 0x00000100 */ 3250 PROT_SRSS_MAIN4 = 76, /* Address 0x40260400, size 0x00000400 */ 3251 PROT_SRSS_MAIN5 = 77, /* Address 0x40260800, size 0x00000008 */ 3252 PROT_SRSS_MAIN6 = 78, /* Address 0x40267000, size 0x00001000 */ 3253 PROT_SRSS_MAIN7 = 79, /* Address 0x4026ff00, size 0x00000080 */ 3254 PROT_BACKUP_BACKUP = 80, /* Address 0x40270000, size 0x00010000 */ 3255 PROT_DW0_DW = 81, /* Address 0x40280000, size 0x00000080 */ 3256 PROT_DW1_DW = 82, /* Address 0x40290000, size 0x00000080 */ 3257 PROT_DW0_DW_CRC = 83, /* Address 0x40280100, size 0x00000080 */ 3258 PROT_DW1_DW_CRC = 84, /* Address 0x40290100, size 0x00000080 */ 3259 PROT_DW0_CH_STRUCT0_CH = 85, /* Address 0x40288000, size 0x00000040 */ 3260 PROT_DW0_CH_STRUCT1_CH = 86, /* Address 0x40288040, size 0x00000040 */ 3261 PROT_DW0_CH_STRUCT2_CH = 87, /* Address 0x40288080, size 0x00000040 */ 3262 PROT_DW0_CH_STRUCT3_CH = 88, /* Address 0x402880c0, size 0x00000040 */ 3263 PROT_DW0_CH_STRUCT4_CH = 89, /* Address 0x40288100, size 0x00000040 */ 3264 PROT_DW0_CH_STRUCT5_CH = 90, /* Address 0x40288140, size 0x00000040 */ 3265 PROT_DW0_CH_STRUCT6_CH = 91, /* Address 0x40288180, size 0x00000040 */ 3266 PROT_DW0_CH_STRUCT7_CH = 92, /* Address 0x402881c0, size 0x00000040 */ 3267 PROT_DW0_CH_STRUCT8_CH = 93, /* Address 0x40288200, size 0x00000040 */ 3268 PROT_DW0_CH_STRUCT9_CH = 94, /* Address 0x40288240, size 0x00000040 */ 3269 PROT_DW0_CH_STRUCT10_CH = 95, /* Address 0x40288280, size 0x00000040 */ 3270 PROT_DW0_CH_STRUCT11_CH = 96, /* Address 0x402882c0, size 0x00000040 */ 3271 PROT_DW0_CH_STRUCT12_CH = 97, /* Address 0x40288300, size 0x00000040 */ 3272 PROT_DW0_CH_STRUCT13_CH = 98, /* Address 0x40288340, size 0x00000040 */ 3273 PROT_DW0_CH_STRUCT14_CH = 99, /* Address 0x40288380, size 0x00000040 */ 3274 PROT_DW0_CH_STRUCT15_CH = 100, /* Address 0x402883c0, size 0x00000040 */ 3275 PROT_DW0_CH_STRUCT16_CH = 101, /* Address 0x40288400, size 0x00000040 */ 3276 PROT_DW0_CH_STRUCT17_CH = 102, /* Address 0x40288440, size 0x00000040 */ 3277 PROT_DW0_CH_STRUCT18_CH = 103, /* Address 0x40288480, size 0x00000040 */ 3278 PROT_DW0_CH_STRUCT19_CH = 104, /* Address 0x402884c0, size 0x00000040 */ 3279 PROT_DW0_CH_STRUCT20_CH = 105, /* Address 0x40288500, size 0x00000040 */ 3280 PROT_DW0_CH_STRUCT21_CH = 106, /* Address 0x40288540, size 0x00000040 */ 3281 PROT_DW0_CH_STRUCT22_CH = 107, /* Address 0x40288580, size 0x00000040 */ 3282 PROT_DW0_CH_STRUCT23_CH = 108, /* Address 0x402885c0, size 0x00000040 */ 3283 PROT_DW0_CH_STRUCT24_CH = 109, /* Address 0x40288600, size 0x00000040 */ 3284 PROT_DW0_CH_STRUCT25_CH = 110, /* Address 0x40288640, size 0x00000040 */ 3285 PROT_DW0_CH_STRUCT26_CH = 111, /* Address 0x40288680, size 0x00000040 */ 3286 PROT_DW0_CH_STRUCT27_CH = 112, /* Address 0x402886c0, size 0x00000040 */ 3287 PROT_DW0_CH_STRUCT28_CH = 113, /* Address 0x40288700, size 0x00000040 */ 3288 PROT_DW1_CH_STRUCT0_CH = 114, /* Address 0x40298000, size 0x00000040 */ 3289 PROT_DW1_CH_STRUCT1_CH = 115, /* Address 0x40298040, size 0x00000040 */ 3290 PROT_DW1_CH_STRUCT2_CH = 116, /* Address 0x40298080, size 0x00000040 */ 3291 PROT_DW1_CH_STRUCT3_CH = 117, /* Address 0x402980c0, size 0x00000040 */ 3292 PROT_DW1_CH_STRUCT4_CH = 118, /* Address 0x40298100, size 0x00000040 */ 3293 PROT_DW1_CH_STRUCT5_CH = 119, /* Address 0x40298140, size 0x00000040 */ 3294 PROT_DW1_CH_STRUCT6_CH = 120, /* Address 0x40298180, size 0x00000040 */ 3295 PROT_DW1_CH_STRUCT7_CH = 121, /* Address 0x402981c0, size 0x00000040 */ 3296 PROT_DW1_CH_STRUCT8_CH = 122, /* Address 0x40298200, size 0x00000040 */ 3297 PROT_DW1_CH_STRUCT9_CH = 123, /* Address 0x40298240, size 0x00000040 */ 3298 PROT_DW1_CH_STRUCT10_CH = 124, /* Address 0x40298280, size 0x00000040 */ 3299 PROT_DW1_CH_STRUCT11_CH = 125, /* Address 0x402982c0, size 0x00000040 */ 3300 PROT_DW1_CH_STRUCT12_CH = 126, /* Address 0x40298300, size 0x00000040 */ 3301 PROT_DW1_CH_STRUCT13_CH = 127, /* Address 0x40298340, size 0x00000040 */ 3302 PROT_DW1_CH_STRUCT14_CH = 128, /* Address 0x40298380, size 0x00000040 */ 3303 PROT_DW1_CH_STRUCT15_CH = 129, /* Address 0x402983c0, size 0x00000040 */ 3304 PROT_DW1_CH_STRUCT16_CH = 130, /* Address 0x40298400, size 0x00000040 */ 3305 PROT_DW1_CH_STRUCT17_CH = 131, /* Address 0x40298440, size 0x00000040 */ 3306 PROT_DW1_CH_STRUCT18_CH = 132, /* Address 0x40298480, size 0x00000040 */ 3307 PROT_DW1_CH_STRUCT19_CH = 133, /* Address 0x402984c0, size 0x00000040 */ 3308 PROT_DW1_CH_STRUCT20_CH = 134, /* Address 0x40298500, size 0x00000040 */ 3309 PROT_DW1_CH_STRUCT21_CH = 135, /* Address 0x40298540, size 0x00000040 */ 3310 PROT_DW1_CH_STRUCT22_CH = 136, /* Address 0x40298580, size 0x00000040 */ 3311 PROT_DW1_CH_STRUCT23_CH = 137, /* Address 0x402985c0, size 0x00000040 */ 3312 PROT_DW1_CH_STRUCT24_CH = 138, /* Address 0x40298600, size 0x00000040 */ 3313 PROT_DW1_CH_STRUCT25_CH = 139, /* Address 0x40298640, size 0x00000040 */ 3314 PROT_DW1_CH_STRUCT26_CH = 140, /* Address 0x40298680, size 0x00000040 */ 3315 PROT_DW1_CH_STRUCT27_CH = 141, /* Address 0x402986c0, size 0x00000040 */ 3316 PROT_DW1_CH_STRUCT28_CH = 142, /* Address 0x40298700, size 0x00000040 */ 3317 PROT_DW1_CH_STRUCT29_CH = 143, /* Address 0x40298740, size 0x00000040 */ 3318 PROT_DW1_CH_STRUCT30_CH = 144, /* Address 0x40298780, size 0x00000040 */ 3319 PROT_DW1_CH_STRUCT31_CH = 145, /* Address 0x402987c0, size 0x00000040 */ 3320 PROT_DMAC_TOP = 146, /* Address 0x402a0000, size 0x00000010 */ 3321 PROT_DMAC_CH0_CH = 147, /* Address 0x402a1000, size 0x00000100 */ 3322 PROT_DMAC_CH1_CH = 148, /* Address 0x402a1100, size 0x00000100 */ 3323 PROT_EFUSE_CTL = 149, /* Address 0x402c0000, size 0x00000080 */ 3324 PROT_EFUSE_DATA = 150, /* Address 0x402c0800, size 0x00000200 */ 3325 PROT_HSIOM_PRT0_PRT = 151, /* Address 0x40300000, size 0x00000008 */ 3326 PROT_HSIOM_PRT1_PRT = 152, /* Address 0x40300010, size 0x00000008 */ 3327 PROT_HSIOM_PRT2_PRT = 153, /* Address 0x40300020, size 0x00000008 */ 3328 PROT_HSIOM_PRT3_PRT = 154, /* Address 0x40300030, size 0x00000008 */ 3329 PROT_HSIOM_PRT4_PRT = 155, /* Address 0x40300040, size 0x00000008 */ 3330 PROT_HSIOM_PRT5_PRT = 156, /* Address 0x40300050, size 0x00000008 */ 3331 PROT_HSIOM_PRT6_PRT = 157, /* Address 0x40300060, size 0x00000008 */ 3332 PROT_HSIOM_PRT7_PRT = 158, /* Address 0x40300070, size 0x00000008 */ 3333 PROT_HSIOM_PRT8_PRT = 159, /* Address 0x40300080, size 0x00000008 */ 3334 PROT_HSIOM_PRT9_PRT = 160, /* Address 0x40300090, size 0x00000008 */ 3335 PROT_HSIOM_PRT10_PRT = 161, /* Address 0x403000a0, size 0x00000008 */ 3336 PROT_HSIOM_PRT11_PRT = 162, /* Address 0x403000b0, size 0x00000008 */ 3337 PROT_HSIOM_PRT12_PRT = 163, /* Address 0x403000c0, size 0x00000008 */ 3338 PROT_HSIOM_PRT13_PRT = 164, /* Address 0x403000d0, size 0x00000008 */ 3339 PROT_HSIOM_PRT14_PRT = 165, /* Address 0x403000e0, size 0x00000008 */ 3340 PROT_HSIOM_AMUX = 166, /* Address 0x40302000, size 0x00000020 */ 3341 PROT_HSIOM_MON = 167, /* Address 0x40302200, size 0x00000010 */ 3342 PROT_GPIO_PRT0_PRT = 168, /* Address 0x40310000, size 0x00000040 */ 3343 PROT_GPIO_PRT1_PRT = 169, /* Address 0x40310080, size 0x00000040 */ 3344 PROT_GPIO_PRT2_PRT = 170, /* Address 0x40310100, size 0x00000040 */ 3345 PROT_GPIO_PRT3_PRT = 171, /* Address 0x40310180, size 0x00000040 */ 3346 PROT_GPIO_PRT4_PRT = 172, /* Address 0x40310200, size 0x00000040 */ 3347 PROT_GPIO_PRT5_PRT = 173, /* Address 0x40310280, size 0x00000040 */ 3348 PROT_GPIO_PRT6_PRT = 174, /* Address 0x40310300, size 0x00000040 */ 3349 PROT_GPIO_PRT7_PRT = 175, /* Address 0x40310380, size 0x00000040 */ 3350 PROT_GPIO_PRT8_PRT = 176, /* Address 0x40310400, size 0x00000040 */ 3351 PROT_GPIO_PRT9_PRT = 177, /* Address 0x40310480, size 0x00000040 */ 3352 PROT_GPIO_PRT10_PRT = 178, /* Address 0x40310500, size 0x00000040 */ 3353 PROT_GPIO_PRT11_PRT = 179, /* Address 0x40310580, size 0x00000040 */ 3354 PROT_GPIO_PRT12_PRT = 180, /* Address 0x40310600, size 0x00000040 */ 3355 PROT_GPIO_PRT13_PRT = 181, /* Address 0x40310680, size 0x00000040 */ 3356 PROT_GPIO_PRT14_PRT = 182, /* Address 0x40310700, size 0x00000040 */ 3357 PROT_GPIO_PRT0_CFG = 183, /* Address 0x40310040, size 0x00000020 */ 3358 PROT_GPIO_PRT1_CFG = 184, /* Address 0x403100c0, size 0x00000008 */ 3359 PROT_GPIO_PRT2_CFG = 185, /* Address 0x40310140, size 0x00000020 */ 3360 PROT_GPIO_PRT3_CFG = 186, /* Address 0x403101c0, size 0x00000020 */ 3361 PROT_GPIO_PRT4_CFG = 187, /* Address 0x40310240, size 0x00000008 */ 3362 PROT_GPIO_PRT5_CFG = 188, /* Address 0x403102c0, size 0x00000020 */ 3363 PROT_GPIO_PRT6_CFG = 189, /* Address 0x40310340, size 0x00000020 */ 3364 PROT_GPIO_PRT7_CFG = 190, /* Address 0x403103c0, size 0x00000020 */ 3365 PROT_GPIO_PRT8_CFG = 191, /* Address 0x40310440, size 0x00000020 */ 3366 PROT_GPIO_PRT9_CFG = 192, /* Address 0x403104c0, size 0x00000020 */ 3367 PROT_GPIO_PRT10_CFG = 193, /* Address 0x40310540, size 0x00000020 */ 3368 PROT_GPIO_PRT11_CFG = 194, /* Address 0x403105c0, size 0x00000020 */ 3369 PROT_GPIO_PRT12_CFG = 195, /* Address 0x40310640, size 0x00000020 */ 3370 PROT_GPIO_PRT13_CFG = 196, /* Address 0x403106c0, size 0x00000008 */ 3371 PROT_GPIO_PRT14_CFG = 197, /* Address 0x40310740, size 0x00000008 */ 3372 PROT_GPIO_GPIO = 198, /* Address 0x40314000, size 0x00000040 */ 3373 PROT_GPIO_TEST = 199, /* Address 0x40315000, size 0x00000008 */ 3374 PROT_SMARTIO_PRT8_PRT = 200, /* Address 0x40320800, size 0x00000100 */ 3375 PROT_SMARTIO_PRT9_PRT = 201, /* Address 0x40320900, size 0x00000100 */ 3376 PROT_LPCOMP = 202, /* Address 0x40350000, size 0x00010000 */ 3377 PROT_CSD0 = 203, /* Address 0x40360000, size 0x00001000 */ 3378 PROT_TCPWM0 = 204, /* Address 0x40380000, size 0x00010000 */ 3379 PROT_TCPWM1 = 205, /* Address 0x40390000, size 0x00010000 */ 3380 PROT_LCD0 = 206, /* Address 0x403b0000, size 0x00010000 */ 3381 PROT_USBFS0 = 207, /* Address 0x403f0000, size 0x00010000 */ 3382 PROT_SMIF0 = 208, /* Address 0x40420000, size 0x00010000 */ 3383 PROT_SDHC0 = 209, /* Address 0x40460000, size 0x00010000 */ 3384 PROT_CANFD0_CH0_CH = 210, /* Address 0x40520000, size 0x00000200 */ 3385 PROT_CANFD0_MAIN = 211, /* Address 0x40521000, size 0x00000040 */ 3386 PROT_CANFD0_BUF = 212, /* Address 0x40530000, size 0x00010000 */ 3387 PROT_SCB0 = 213, /* Address 0x40600000, size 0x00010000 */ 3388 PROT_SCB1 = 214, /* Address 0x40610000, size 0x00010000 */ 3389 PROT_SCB2 = 215, /* Address 0x40620000, size 0x00010000 */ 3390 PROT_SCB3 = 216, /* Address 0x40630000, size 0x00010000 */ 3391 PROT_SCB4 = 217, /* Address 0x40640000, size 0x00010000 */ 3392 PROT_SCB5 = 218, /* Address 0x40650000, size 0x00010000 */ 3393 PROT_SCB6 = 219, /* Address 0x40660000, size 0x00010000 */ 3394 PROT_PASS = 220 /* Address 0x40900000, size 0x00100000 */ 3395 } cy_en_prot_region_t; 3396 3397 #endif /* _PSOC6_03_CONFIG_H_ */ 3398 3399 3400 /* [] END OF FILE */ 3401
