1 /***************************************************************************//** 2 * \file tviibe4m_config.h 3 * 4 * \brief 5 * TVIIBE4M device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _TVIIBE4M_CONFIG_H_ 28 #define _TVIIBE4M_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0000u, /* cpuss.clock_trace_in */ 34 PCLK_SMARTIO12_CLOCK = 0x0001u, /* smartio[12].clock */ 35 PCLK_SMARTIO13_CLOCK = 0x0002u, /* smartio[13].clock */ 36 PCLK_SMARTIO14_CLOCK = 0x0003u, /* smartio[14].clock */ 37 PCLK_SMARTIO15_CLOCK = 0x0004u, /* smartio[15].clock */ 38 PCLK_SMARTIO17_CLOCK = 0x0005u, /* smartio[17].clock */ 39 PCLK_CANFD0_CLOCK_CAN0 = 0x0006u, /* canfd[0].clock_can[0] */ 40 PCLK_CANFD0_CLOCK_CAN1 = 0x0007u, /* canfd[0].clock_can[1] */ 41 PCLK_CANFD0_CLOCK_CAN2 = 0x0008u, /* canfd[0].clock_can[2] */ 42 PCLK_CANFD0_CLOCK_CAN3 = 0x0009u, /* canfd[0].clock_can[3] */ 43 PCLK_CANFD1_CLOCK_CAN0 = 0x000Au, /* canfd[1].clock_can[0] */ 44 PCLK_CANFD1_CLOCK_CAN1 = 0x000Bu, /* canfd[1].clock_can[1] */ 45 PCLK_CANFD1_CLOCK_CAN2 = 0x000Cu, /* canfd[1].clock_can[2] */ 46 PCLK_CANFD1_CLOCK_CAN3 = 0x000Du, /* canfd[1].clock_can[3] */ 47 PCLK_LIN0_CLOCK_CH_EN0 = 0x000Eu, /* lin[0].clock_ch_en[0] */ 48 PCLK_LIN0_CLOCK_CH_EN1 = 0x000Fu, /* lin[0].clock_ch_en[1] */ 49 PCLK_LIN0_CLOCK_CH_EN2 = 0x0010u, /* lin[0].clock_ch_en[2] */ 50 PCLK_LIN0_CLOCK_CH_EN3 = 0x0011u, /* lin[0].clock_ch_en[3] */ 51 PCLK_LIN0_CLOCK_CH_EN4 = 0x0012u, /* lin[0].clock_ch_en[4] */ 52 PCLK_LIN0_CLOCK_CH_EN5 = 0x0013u, /* lin[0].clock_ch_en[5] */ 53 PCLK_LIN0_CLOCK_CH_EN6 = 0x0014u, /* lin[0].clock_ch_en[6] */ 54 PCLK_LIN0_CLOCK_CH_EN7 = 0x0015u, /* lin[0].clock_ch_en[7] */ 55 PCLK_LIN0_CLOCK_CH_EN8 = 0x0016u, /* lin[0].clock_ch_en[8] */ 56 PCLK_LIN0_CLOCK_CH_EN9 = 0x0017u, /* lin[0].clock_ch_en[9] */ 57 PCLK_LIN0_CLOCK_CH_EN10 = 0x0018u, /* lin[0].clock_ch_en[10] */ 58 PCLK_LIN0_CLOCK_CH_EN11 = 0x0019u, /* lin[0].clock_ch_en[11] */ 59 PCLK_CXPI0_CLOCK_CH_EN0 = 0x001Au, /* cxpi[0].clock_ch_en[0] */ 60 PCLK_CXPI0_CLOCK_CH_EN1 = 0x001Bu, /* cxpi[0].clock_ch_en[1] */ 61 PCLK_CXPI0_CLOCK_CH_EN2 = 0x001Cu, /* cxpi[0].clock_ch_en[2] */ 62 PCLK_CXPI0_CLOCK_CH_EN3 = 0x001Du, /* cxpi[0].clock_ch_en[3] */ 63 PCLK_SCB0_CLOCK = 0x001Eu, /* scb[0].clock */ 64 PCLK_SCB1_CLOCK = 0x001Fu, /* scb[1].clock */ 65 PCLK_SCB2_CLOCK = 0x0020u, /* scb[2].clock */ 66 PCLK_SCB3_CLOCK = 0x0021u, /* scb[3].clock */ 67 PCLK_SCB4_CLOCK = 0x0022u, /* scb[4].clock */ 68 PCLK_SCB5_CLOCK = 0x0023u, /* scb[5].clock */ 69 PCLK_SCB6_CLOCK = 0x0024u, /* scb[6].clock */ 70 PCLK_SCB7_CLOCK = 0x0025u, /* scb[7].clock */ 71 PCLK_PASS0_CLOCK_SAR0 = 0x0026u, /* pass[0].clock_sar[0] */ 72 PCLK_PASS0_CLOCK_SAR1 = 0x0027u, /* pass[0].clock_sar[1] */ 73 PCLK_PASS0_CLOCK_SAR2 = 0x0028u, /* pass[0].clock_sar[2] */ 74 PCLK_TCPWM0_CLOCKS0 = 0x0029u, /* tcpwm[0].clocks[0] */ 75 PCLK_TCPWM0_CLOCKS1 = 0x002Au, /* tcpwm[0].clocks[1] */ 76 PCLK_TCPWM0_CLOCKS2 = 0x002Bu, /* tcpwm[0].clocks[2] */ 77 PCLK_TCPWM0_CLOCKS3 = 0x002Cu, /* tcpwm[0].clocks[3] */ 78 PCLK_TCPWM0_CLOCKS4 = 0x002Du, /* tcpwm[0].clocks[4] */ 79 PCLK_TCPWM0_CLOCKS5 = 0x002Eu, /* tcpwm[0].clocks[5] */ 80 PCLK_TCPWM0_CLOCKS6 = 0x002Fu, /* tcpwm[0].clocks[6] */ 81 PCLK_TCPWM0_CLOCKS7 = 0x0030u, /* tcpwm[0].clocks[7] */ 82 PCLK_TCPWM0_CLOCKS8 = 0x0031u, /* tcpwm[0].clocks[8] */ 83 PCLK_TCPWM0_CLOCKS9 = 0x0032u, /* tcpwm[0].clocks[9] */ 84 PCLK_TCPWM0_CLOCKS10 = 0x0033u, /* tcpwm[0].clocks[10] */ 85 PCLK_TCPWM0_CLOCKS11 = 0x0034u, /* tcpwm[0].clocks[11] */ 86 PCLK_TCPWM0_CLOCKS12 = 0x0035u, /* tcpwm[0].clocks[12] */ 87 PCLK_TCPWM0_CLOCKS13 = 0x0036u, /* tcpwm[0].clocks[13] */ 88 PCLK_TCPWM0_CLOCKS14 = 0x0037u, /* tcpwm[0].clocks[14] */ 89 PCLK_TCPWM0_CLOCKS15 = 0x0038u, /* tcpwm[0].clocks[15] */ 90 PCLK_TCPWM0_CLOCKS16 = 0x0039u, /* tcpwm[0].clocks[16] */ 91 PCLK_TCPWM0_CLOCKS17 = 0x003Au, /* tcpwm[0].clocks[17] */ 92 PCLK_TCPWM0_CLOCKS18 = 0x003Bu, /* tcpwm[0].clocks[18] */ 93 PCLK_TCPWM0_CLOCKS19 = 0x003Cu, /* tcpwm[0].clocks[19] */ 94 PCLK_TCPWM0_CLOCKS20 = 0x003Du, /* tcpwm[0].clocks[20] */ 95 PCLK_TCPWM0_CLOCKS21 = 0x003Eu, /* tcpwm[0].clocks[21] */ 96 PCLK_TCPWM0_CLOCKS22 = 0x003Fu, /* tcpwm[0].clocks[22] */ 97 PCLK_TCPWM0_CLOCKS23 = 0x0040u, /* tcpwm[0].clocks[23] */ 98 PCLK_TCPWM0_CLOCKS24 = 0x0041u, /* tcpwm[0].clocks[24] */ 99 PCLK_TCPWM0_CLOCKS25 = 0x0042u, /* tcpwm[0].clocks[25] */ 100 PCLK_TCPWM0_CLOCKS26 = 0x0043u, /* tcpwm[0].clocks[26] */ 101 PCLK_TCPWM0_CLOCKS27 = 0x0044u, /* tcpwm[0].clocks[27] */ 102 PCLK_TCPWM0_CLOCKS28 = 0x0045u, /* tcpwm[0].clocks[28] */ 103 PCLK_TCPWM0_CLOCKS29 = 0x0046u, /* tcpwm[0].clocks[29] */ 104 PCLK_TCPWM0_CLOCKS30 = 0x0047u, /* tcpwm[0].clocks[30] */ 105 PCLK_TCPWM0_CLOCKS31 = 0x0048u, /* tcpwm[0].clocks[31] */ 106 PCLK_TCPWM0_CLOCKS32 = 0x0049u, /* tcpwm[0].clocks[32] */ 107 PCLK_TCPWM0_CLOCKS33 = 0x004Au, /* tcpwm[0].clocks[33] */ 108 PCLK_TCPWM0_CLOCKS34 = 0x004Bu, /* tcpwm[0].clocks[34] */ 109 PCLK_TCPWM0_CLOCKS35 = 0x004Cu, /* tcpwm[0].clocks[35] */ 110 PCLK_TCPWM0_CLOCKS36 = 0x004Du, /* tcpwm[0].clocks[36] */ 111 PCLK_TCPWM0_CLOCKS37 = 0x004Eu, /* tcpwm[0].clocks[37] */ 112 PCLK_TCPWM0_CLOCKS38 = 0x004Fu, /* tcpwm[0].clocks[38] */ 113 PCLK_TCPWM0_CLOCKS39 = 0x0050u, /* tcpwm[0].clocks[39] */ 114 PCLK_TCPWM0_CLOCKS40 = 0x0051u, /* tcpwm[0].clocks[40] */ 115 PCLK_TCPWM0_CLOCKS41 = 0x0052u, /* tcpwm[0].clocks[41] */ 116 PCLK_TCPWM0_CLOCKS42 = 0x0053u, /* tcpwm[0].clocks[42] */ 117 PCLK_TCPWM0_CLOCKS43 = 0x0054u, /* tcpwm[0].clocks[43] */ 118 PCLK_TCPWM0_CLOCKS44 = 0x0055u, /* tcpwm[0].clocks[44] */ 119 PCLK_TCPWM0_CLOCKS45 = 0x0056u, /* tcpwm[0].clocks[45] */ 120 PCLK_TCPWM0_CLOCKS46 = 0x0057u, /* tcpwm[0].clocks[46] */ 121 PCLK_TCPWM0_CLOCKS47 = 0x0058u, /* tcpwm[0].clocks[47] */ 122 PCLK_TCPWM0_CLOCKS48 = 0x0059u, /* tcpwm[0].clocks[48] */ 123 PCLK_TCPWM0_CLOCKS49 = 0x005Au, /* tcpwm[0].clocks[49] */ 124 PCLK_TCPWM0_CLOCKS50 = 0x005Bu, /* tcpwm[0].clocks[50] */ 125 PCLK_TCPWM0_CLOCKS51 = 0x005Cu, /* tcpwm[0].clocks[51] */ 126 PCLK_TCPWM0_CLOCKS52 = 0x005Du, /* tcpwm[0].clocks[52] */ 127 PCLK_TCPWM0_CLOCKS53 = 0x005Eu, /* tcpwm[0].clocks[53] */ 128 PCLK_TCPWM0_CLOCKS54 = 0x005Fu, /* tcpwm[0].clocks[54] */ 129 PCLK_TCPWM0_CLOCKS55 = 0x0060u, /* tcpwm[0].clocks[55] */ 130 PCLK_TCPWM0_CLOCKS56 = 0x0061u, /* tcpwm[0].clocks[56] */ 131 PCLK_TCPWM0_CLOCKS57 = 0x0062u, /* tcpwm[0].clocks[57] */ 132 PCLK_TCPWM0_CLOCKS58 = 0x0063u, /* tcpwm[0].clocks[58] */ 133 PCLK_TCPWM0_CLOCKS59 = 0x0064u, /* tcpwm[0].clocks[59] */ 134 PCLK_TCPWM0_CLOCKS60 = 0x0065u, /* tcpwm[0].clocks[60] */ 135 PCLK_TCPWM0_CLOCKS61 = 0x0066u, /* tcpwm[0].clocks[61] */ 136 PCLK_TCPWM0_CLOCKS62 = 0x0067u, /* tcpwm[0].clocks[62] */ 137 PCLK_TCPWM0_CLOCKS256 = 0x0068u, /* tcpwm[0].clocks[256] */ 138 PCLK_TCPWM0_CLOCKS257 = 0x0069u, /* tcpwm[0].clocks[257] */ 139 PCLK_TCPWM0_CLOCKS258 = 0x006Au, /* tcpwm[0].clocks[258] */ 140 PCLK_TCPWM0_CLOCKS259 = 0x006Bu, /* tcpwm[0].clocks[259] */ 141 PCLK_TCPWM0_CLOCKS260 = 0x006Cu, /* tcpwm[0].clocks[260] */ 142 PCLK_TCPWM0_CLOCKS261 = 0x006Du, /* tcpwm[0].clocks[261] */ 143 PCLK_TCPWM0_CLOCKS262 = 0x006Eu, /* tcpwm[0].clocks[262] */ 144 PCLK_TCPWM0_CLOCKS263 = 0x006Fu, /* tcpwm[0].clocks[263] */ 145 PCLK_TCPWM0_CLOCKS264 = 0x0070u, /* tcpwm[0].clocks[264] */ 146 PCLK_TCPWM0_CLOCKS265 = 0x0071u, /* tcpwm[0].clocks[265] */ 147 PCLK_TCPWM0_CLOCKS266 = 0x0072u, /* tcpwm[0].clocks[266] */ 148 PCLK_TCPWM0_CLOCKS267 = 0x0073u, /* tcpwm[0].clocks[267] */ 149 PCLK_TCPWM0_CLOCKS512 = 0x0074u, /* tcpwm[0].clocks[512] */ 150 PCLK_TCPWM0_CLOCKS513 = 0x0075u, /* tcpwm[0].clocks[513] */ 151 PCLK_TCPWM0_CLOCKS514 = 0x0076u, /* tcpwm[0].clocks[514] */ 152 PCLK_TCPWM0_CLOCKS515 = 0x0077u, /* tcpwm[0].clocks[515] */ 153 PCLK_TCPWM0_CLOCKS516 = 0x0078u, /* tcpwm[0].clocks[516] */ 154 PCLK_TCPWM0_CLOCKS517 = 0x0079u, /* tcpwm[0].clocks[517] */ 155 PCLK_TCPWM0_CLOCKS518 = 0x007Au, /* tcpwm[0].clocks[518] */ 156 PCLK_TCPWM0_CLOCKS519 = 0x007Bu /* tcpwm[0].clocks[519] */ 157 } en_clk_dst_t; 158 159 /* Trigger Group */ 160 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 161 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 162 */ 163 /* Trigger Group Inputs */ 164 /* Trigger Input Group 0 - P-DMA0 Request Assignments */ 165 typedef enum 166 { 167 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 168 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 169 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 170 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 171 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 172 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 173 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 174 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 175 TRIG_IN_MUX_0_PDMA0_TR_OUT8 = 0x00000009u, /* cpuss.dw0_tr_out[8] */ 176 TRIG_IN_MUX_0_PDMA0_TR_OUT9 = 0x0000000Au, /* cpuss.dw0_tr_out[9] */ 177 TRIG_IN_MUX_0_PDMA0_TR_OUT10 = 0x0000000Bu, /* cpuss.dw0_tr_out[10] */ 178 TRIG_IN_MUX_0_PDMA0_TR_OUT11 = 0x0000000Cu, /* cpuss.dw0_tr_out[11] */ 179 TRIG_IN_MUX_0_PDMA0_TR_OUT12 = 0x0000000Du, /* cpuss.dw0_tr_out[12] */ 180 TRIG_IN_MUX_0_PDMA0_TR_OUT13 = 0x0000000Eu, /* cpuss.dw0_tr_out[13] */ 181 TRIG_IN_MUX_0_PDMA0_TR_OUT14 = 0x0000000Fu, /* cpuss.dw0_tr_out[14] */ 182 TRIG_IN_MUX_0_PDMA0_TR_OUT15 = 0x00000010u, /* cpuss.dw0_tr_out[15] */ 183 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000011u, /* cpuss.dw1_tr_out[0] */ 184 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x00000012u, /* cpuss.dw1_tr_out[1] */ 185 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x00000013u, /* cpuss.dw1_tr_out[2] */ 186 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x00000014u, /* cpuss.dw1_tr_out[3] */ 187 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x00000015u, /* cpuss.dw1_tr_out[4] */ 188 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x00000016u, /* cpuss.dw1_tr_out[5] */ 189 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x00000017u, /* cpuss.dw1_tr_out[6] */ 190 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000018u, /* cpuss.dw1_tr_out[7] */ 191 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000019u, /* cpuss.dmac_tr_out[0] */ 192 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x0000001Au, /* cpuss.dmac_tr_out[1] */ 193 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x0000001Bu, /* cpuss.dmac_tr_out[2] */ 194 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x0000001Cu, /* cpuss.dmac_tr_out[3] */ 195 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x0000001Du, /* cpuss.tr_fault[0] */ 196 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x0000001Eu, /* cpuss.tr_fault[1] */ 197 TRIG_IN_MUX_0_FAULT_TR_OUT2 = 0x0000001Fu, /* cpuss.tr_fault[2] */ 198 TRIG_IN_MUX_0_FAULT_TR_OUT3 = 0x00000020u, /* cpuss.tr_fault[3] */ 199 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000021u, /* cpuss.cti_tr_out[0] */ 200 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000022u, /* cpuss.cti_tr_out[1] */ 201 TRIG_IN_MUX_0_EVTGEN_TR_OUT3 = 0x00000023u, /* evtgen[0].tr_out[3] */ 202 TRIG_IN_MUX_0_EVTGEN_TR_OUT4 = 0x00000024u, /* evtgen[0].tr_out[4] */ 203 TRIG_IN_MUX_0_EVTGEN_TR_OUT5 = 0x00000025u, /* evtgen[0].tr_out[5] */ 204 TRIG_IN_MUX_0_EVTGEN_TR_OUT6 = 0x00000026u, /* evtgen[0].tr_out[6] */ 205 TRIG_IN_MUX_0_HSIOM_IO_INPUT0 = 0x00000027u, /* peri.tr_io_input[0] */ 206 TRIG_IN_MUX_0_HSIOM_IO_INPUT1 = 0x00000028u, /* peri.tr_io_input[1] */ 207 TRIG_IN_MUX_0_HSIOM_IO_INPUT2 = 0x00000029u, /* peri.tr_io_input[2] */ 208 TRIG_IN_MUX_0_HSIOM_IO_INPUT3 = 0x0000002Au, /* peri.tr_io_input[3] */ 209 TRIG_IN_MUX_0_HSIOM_IO_INPUT4 = 0x0000002Bu, /* peri.tr_io_input[4] */ 210 TRIG_IN_MUX_0_HSIOM_IO_INPUT5 = 0x0000002Cu, /* peri.tr_io_input[5] */ 211 TRIG_IN_MUX_0_HSIOM_IO_INPUT6 = 0x0000002Du, /* peri.tr_io_input[6] */ 212 TRIG_IN_MUX_0_HSIOM_IO_INPUT7 = 0x0000002Eu, /* peri.tr_io_input[7] */ 213 TRIG_IN_MUX_0_HSIOM_IO_INPUT8 = 0x0000002Fu, /* peri.tr_io_input[8] */ 214 TRIG_IN_MUX_0_HSIOM_IO_INPUT9 = 0x00000030u, /* peri.tr_io_input[9] */ 215 TRIG_IN_MUX_0_HSIOM_IO_INPUT10 = 0x00000031u, /* peri.tr_io_input[10] */ 216 TRIG_IN_MUX_0_HSIOM_IO_INPUT11 = 0x00000032u, /* peri.tr_io_input[11] */ 217 TRIG_IN_MUX_0_HSIOM_IO_INPUT12 = 0x00000033u, /* peri.tr_io_input[12] */ 218 TRIG_IN_MUX_0_HSIOM_IO_INPUT13 = 0x00000034u, /* peri.tr_io_input[13] */ 219 TRIG_IN_MUX_0_HSIOM_IO_INPUT14 = 0x00000035u, /* peri.tr_io_input[14] */ 220 TRIG_IN_MUX_0_HSIOM_IO_INPUT15 = 0x00000036u /* peri.tr_io_input[15] */ 221 } en_trig_input_pdma0_tr_0_t; 222 223 /* Trigger Input Group 1 - P-DMA1 Request Assignments */ 224 typedef enum 225 { 226 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 227 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 228 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 229 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 230 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 231 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 232 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 233 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 234 TRIG_IN_MUX_1_PDMA0_TR_OUT8 = 0x00000109u, /* cpuss.dw0_tr_out[8] */ 235 TRIG_IN_MUX_1_PDMA0_TR_OUT9 = 0x0000010Au, /* cpuss.dw0_tr_out[9] */ 236 TRIG_IN_MUX_1_PDMA0_TR_OUT10 = 0x0000010Bu, /* cpuss.dw0_tr_out[10] */ 237 TRIG_IN_MUX_1_PDMA0_TR_OUT11 = 0x0000010Cu, /* cpuss.dw0_tr_out[11] */ 238 TRIG_IN_MUX_1_PDMA0_TR_OUT12 = 0x0000010Du, /* cpuss.dw0_tr_out[12] */ 239 TRIG_IN_MUX_1_PDMA0_TR_OUT13 = 0x0000010Eu, /* cpuss.dw0_tr_out[13] */ 240 TRIG_IN_MUX_1_PDMA0_TR_OUT14 = 0x0000010Fu, /* cpuss.dw0_tr_out[14] */ 241 TRIG_IN_MUX_1_PDMA0_TR_OUT15 = 0x00000110u, /* cpuss.dw0_tr_out[15] */ 242 TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000111u, /* cpuss.dw1_tr_out[0] */ 243 TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x00000112u, /* cpuss.dw1_tr_out[1] */ 244 TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x00000113u, /* cpuss.dw1_tr_out[2] */ 245 TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x00000114u, /* cpuss.dw1_tr_out[3] */ 246 TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x00000115u, /* cpuss.dw1_tr_out[4] */ 247 TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x00000116u, /* cpuss.dw1_tr_out[5] */ 248 TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x00000117u, /* cpuss.dw1_tr_out[6] */ 249 TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000118u, /* cpuss.dw1_tr_out[7] */ 250 TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000119u, /* cpuss.dmac_tr_out[0] */ 251 TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x0000011Au, /* cpuss.dmac_tr_out[1] */ 252 TRIG_IN_MUX_1_MDMA_TR_OUT2 = 0x0000011Bu, /* cpuss.dmac_tr_out[2] */ 253 TRIG_IN_MUX_1_MDMA_TR_OUT3 = 0x0000011Cu, /* cpuss.dmac_tr_out[3] */ 254 TRIG_IN_MUX_1_FAULT_TR_OUT0 = 0x0000011Du, /* cpuss.tr_fault[0] */ 255 TRIG_IN_MUX_1_FAULT_TR_OUT1 = 0x0000011Eu, /* cpuss.tr_fault[1] */ 256 TRIG_IN_MUX_1_FAULT_TR_OUT2 = 0x0000011Fu, /* cpuss.tr_fault[2] */ 257 TRIG_IN_MUX_1_FAULT_TR_OUT3 = 0x00000120u, /* cpuss.tr_fault[3] */ 258 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x00000121u, /* cpuss.cti_tr_out[0] */ 259 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x00000122u, /* cpuss.cti_tr_out[1] */ 260 TRIG_IN_MUX_1_EVTGEN_TR_OUT7 = 0x00000123u, /* evtgen[0].tr_out[7] */ 261 TRIG_IN_MUX_1_EVTGEN_TR_OUT8 = 0x00000124u, /* evtgen[0].tr_out[8] */ 262 TRIG_IN_MUX_1_EVTGEN_TR_OUT9 = 0x00000125u, /* evtgen[0].tr_out[9] */ 263 TRIG_IN_MUX_1_EVTGEN_TR_OUT10 = 0x00000126u, /* evtgen[0].tr_out[10] */ 264 TRIG_IN_MUX_1_HSIOM_IO_INPUT16 = 0x00000127u, /* peri.tr_io_input[16] */ 265 TRIG_IN_MUX_1_HSIOM_IO_INPUT17 = 0x00000128u, /* peri.tr_io_input[17] */ 266 TRIG_IN_MUX_1_HSIOM_IO_INPUT18 = 0x00000129u, /* peri.tr_io_input[18] */ 267 TRIG_IN_MUX_1_HSIOM_IO_INPUT19 = 0x0000012Au, /* peri.tr_io_input[19] */ 268 TRIG_IN_MUX_1_HSIOM_IO_INPUT20 = 0x0000012Bu, /* peri.tr_io_input[20] */ 269 TRIG_IN_MUX_1_HSIOM_IO_INPUT21 = 0x0000012Cu, /* peri.tr_io_input[21] */ 270 TRIG_IN_MUX_1_HSIOM_IO_INPUT22 = 0x0000012Du, /* peri.tr_io_input[22] */ 271 TRIG_IN_MUX_1_HSIOM_IO_INPUT23 = 0x0000012Eu, /* peri.tr_io_input[23] */ 272 TRIG_IN_MUX_1_HSIOM_IO_INPUT24 = 0x0000012Fu, /* peri.tr_io_input[24] */ 273 TRIG_IN_MUX_1_HSIOM_IO_INPUT25 = 0x00000130u, /* peri.tr_io_input[25] */ 274 TRIG_IN_MUX_1_HSIOM_IO_INPUT26 = 0x00000131u, /* peri.tr_io_input[26] */ 275 TRIG_IN_MUX_1_HSIOM_IO_INPUT27 = 0x00000132u, /* peri.tr_io_input[27] */ 276 TRIG_IN_MUX_1_HSIOM_IO_INPUT28 = 0x00000133u, /* peri.tr_io_input[28] */ 277 TRIG_IN_MUX_1_HSIOM_IO_INPUT29 = 0x00000134u, /* peri.tr_io_input[29] */ 278 TRIG_IN_MUX_1_HSIOM_IO_INPUT30 = 0x00000135u, /* peri.tr_io_input[30] */ 279 TRIG_IN_MUX_1_HSIOM_IO_INPUT31 = 0x00000136u, /* peri.tr_io_input[31] */ 280 TRIG_IN_MUX_1_PASS_GEN_TR_OUT0 = 0x00000137u, /* pass[0].tr_sar_gen_out[0] */ 281 TRIG_IN_MUX_1_PASS_GEN_TR_OUT1 = 0x00000138u, /* pass[0].tr_sar_gen_out[1] */ 282 TRIG_IN_MUX_1_PASS_GEN_TR_OUT2 = 0x00000139u, /* pass[0].tr_sar_gen_out[2] */ 283 TRIG_IN_MUX_1_PASS_GEN_TR_OUT3 = 0x0000013Au, /* pass[0].tr_sar_gen_out[3] */ 284 TRIG_IN_MUX_1_PASS_GEN_TR_OUT4 = 0x0000013Bu, /* pass[0].tr_sar_gen_out[4] */ 285 TRIG_IN_MUX_1_PASS_GEN_TR_OUT5 = 0x0000013Cu /* pass[0].tr_sar_gen_out[5] */ 286 } en_trig_input_pdma1_tr_t; 287 288 /* Trigger Input Group 2 - DMA Request Assignments */ 289 typedef enum 290 { 291 TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000201u, /* cpuss.dmac_tr_out[0] */ 292 TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x00000202u, /* cpuss.dmac_tr_out[1] */ 293 TRIG_IN_MUX_2_MDMA_TR_OUT2 = 0x00000203u, /* cpuss.dmac_tr_out[2] */ 294 TRIG_IN_MUX_2_MDMA_TR_OUT3 = 0x00000204u /* cpuss.dmac_tr_out[3] */ 295 } en_trig_input_mdma_t; 296 297 /* Trigger Input Group 3 - Dedicated mux for TCPWM to P-DMA0 triggers */ 298 typedef enum 299 { 300 TRIG_IN_MUX_3_TCPWM_32_TR_OUT00 = 0x00000301u, /* tcpwm[0].tr_out0[512] */ 301 TRIG_IN_MUX_3_TCPWM_32_TR_OUT01 = 0x00000302u, /* tcpwm[0].tr_out0[513] */ 302 TRIG_IN_MUX_3_TCPWM_32_TR_OUT02 = 0x00000303u, /* tcpwm[0].tr_out0[514] */ 303 TRIG_IN_MUX_3_TCPWM_32_TR_OUT03 = 0x00000304u, /* tcpwm[0].tr_out0[515] */ 304 TRIG_IN_MUX_3_TCPWM_32_TR_OUT04 = 0x00000305u, /* tcpwm[0].tr_out0[516] */ 305 TRIG_IN_MUX_3_TCPWM_32_TR_OUT05 = 0x00000306u, /* tcpwm[0].tr_out0[517] */ 306 TRIG_IN_MUX_3_TCPWM_32_TR_OUT06 = 0x00000307u, /* tcpwm[0].tr_out0[518] */ 307 TRIG_IN_MUX_3_TCPWM_32_TR_OUT07 = 0x00000308u, /* tcpwm[0].tr_out0[519] */ 308 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[256] */ 309 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT01 = 0x0000030Au, /* tcpwm[0].tr_out0[257] */ 310 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT02 = 0x0000030Bu, /* tcpwm[0].tr_out0[258] */ 311 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT03 = 0x0000030Cu, /* tcpwm[0].tr_out0[259] */ 312 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT04 = 0x0000030Du, /* tcpwm[0].tr_out0[260] */ 313 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT05 = 0x0000030Eu, /* tcpwm[0].tr_out0[261] */ 314 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT06 = 0x0000030Fu, /* tcpwm[0].tr_out0[262] */ 315 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT07 = 0x00000310u, /* tcpwm[0].tr_out0[263] */ 316 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT08 = 0x00000311u, /* tcpwm[0].tr_out0[264] */ 317 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT09 = 0x00000312u, /* tcpwm[0].tr_out0[265] */ 318 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT010 = 0x00000313u, /* tcpwm[0].tr_out0[266] */ 319 TRIG_IN_MUX_3_TCPWM_16M_TR_OUT011 = 0x00000314u, /* tcpwm[0].tr_out0[267] */ 320 TRIG_IN_MUX_3_TCPWM_16_TR_OUT00 = 0x00000315u, /* tcpwm[0].tr_out0[0] */ 321 TRIG_IN_MUX_3_TCPWM_16_TR_OUT01 = 0x00000316u, /* tcpwm[0].tr_out0[1] */ 322 TRIG_IN_MUX_3_TCPWM_16_TR_OUT02 = 0x00000317u, /* tcpwm[0].tr_out0[2] */ 323 TRIG_IN_MUX_3_TCPWM_16_TR_OUT03 = 0x00000318u, /* tcpwm[0].tr_out0[3] */ 324 TRIG_IN_MUX_3_TCPWM_16_TR_OUT04 = 0x00000319u, /* tcpwm[0].tr_out0[4] */ 325 TRIG_IN_MUX_3_TCPWM_16_TR_OUT05 = 0x0000031Au, /* tcpwm[0].tr_out0[5] */ 326 TRIG_IN_MUX_3_TCPWM_16_TR_OUT06 = 0x0000031Bu, /* tcpwm[0].tr_out0[6] */ 327 TRIG_IN_MUX_3_TCPWM_16_TR_OUT07 = 0x0000031Cu, /* tcpwm[0].tr_out0[7] */ 328 TRIG_IN_MUX_3_TCPWM_16_TR_OUT08 = 0x0000031Du, /* tcpwm[0].tr_out0[8] */ 329 TRIG_IN_MUX_3_TCPWM_16_TR_OUT09 = 0x0000031Eu, /* tcpwm[0].tr_out0[9] */ 330 TRIG_IN_MUX_3_TCPWM_16_TR_OUT010 = 0x0000031Fu, /* tcpwm[0].tr_out0[10] */ 331 TRIG_IN_MUX_3_TCPWM_16_TR_OUT011 = 0x00000320u, /* tcpwm[0].tr_out0[11] */ 332 TRIG_IN_MUX_3_TCPWM_16_TR_OUT012 = 0x00000321u, /* tcpwm[0].tr_out0[12] */ 333 TRIG_IN_MUX_3_TCPWM_16_TR_OUT013 = 0x00000322u, /* tcpwm[0].tr_out0[13] */ 334 TRIG_IN_MUX_3_TCPWM_16_TR_OUT014 = 0x00000323u, /* tcpwm[0].tr_out0[14] */ 335 TRIG_IN_MUX_3_TCPWM_16_TR_OUT015 = 0x00000324u, /* tcpwm[0].tr_out0[15] */ 336 TRIG_IN_MUX_3_TCPWM_16_TR_OUT016 = 0x00000325u, /* tcpwm[0].tr_out0[16] */ 337 TRIG_IN_MUX_3_TCPWM_16_TR_OUT017 = 0x00000326u, /* tcpwm[0].tr_out0[17] */ 338 TRIG_IN_MUX_3_TCPWM_16_TR_OUT018 = 0x00000327u, /* tcpwm[0].tr_out0[18] */ 339 TRIG_IN_MUX_3_TCPWM_16_TR_OUT019 = 0x00000328u, /* tcpwm[0].tr_out0[19] */ 340 TRIG_IN_MUX_3_TCPWM_16_TR_OUT020 = 0x00000329u, /* tcpwm[0].tr_out0[20] */ 341 TRIG_IN_MUX_3_TCPWM_16_TR_OUT021 = 0x0000032Au, /* tcpwm[0].tr_out0[21] */ 342 TRIG_IN_MUX_3_TCPWM_16_TR_OUT022 = 0x0000032Bu, /* tcpwm[0].tr_out0[22] */ 343 TRIG_IN_MUX_3_TCPWM_16_TR_OUT023 = 0x0000032Cu, /* tcpwm[0].tr_out0[23] */ 344 TRIG_IN_MUX_3_TCPWM_16_TR_OUT024 = 0x0000032Du, /* tcpwm[0].tr_out0[24] */ 345 TRIG_IN_MUX_3_TCPWM_16_TR_OUT025 = 0x0000032Eu, /* tcpwm[0].tr_out0[25] */ 346 TRIG_IN_MUX_3_TCPWM_16_TR_OUT026 = 0x0000032Fu, /* tcpwm[0].tr_out0[26] */ 347 TRIG_IN_MUX_3_TCPWM_16_TR_OUT027 = 0x00000330u, /* tcpwm[0].tr_out0[27] */ 348 TRIG_IN_MUX_3_TCPWM_16_TR_OUT028 = 0x00000331u, /* tcpwm[0].tr_out0[28] */ 349 TRIG_IN_MUX_3_TCPWM_16_TR_OUT029 = 0x00000332u, /* tcpwm[0].tr_out0[29] */ 350 TRIG_IN_MUX_3_TCPWM_16_TR_OUT030 = 0x00000333u, /* tcpwm[0].tr_out0[30] */ 351 TRIG_IN_MUX_3_TCPWM_16_TR_OUT031 = 0x00000334u, /* tcpwm[0].tr_out0[31] */ 352 TRIG_IN_MUX_3_TCPWM_16_TR_OUT032 = 0x00000335u, /* tcpwm[0].tr_out0[32] */ 353 TRIG_IN_MUX_3_TCPWM_16_TR_OUT033 = 0x00000336u, /* tcpwm[0].tr_out0[33] */ 354 TRIG_IN_MUX_3_TCPWM_16_TR_OUT034 = 0x00000337u, /* tcpwm[0].tr_out0[34] */ 355 TRIG_IN_MUX_3_TCPWM_16_TR_OUT035 = 0x00000338u, /* tcpwm[0].tr_out0[35] */ 356 TRIG_IN_MUX_3_TCPWM_16_TR_OUT036 = 0x00000339u, /* tcpwm[0].tr_out0[36] */ 357 TRIG_IN_MUX_3_TCPWM_16_TR_OUT037 = 0x0000033Au, /* tcpwm[0].tr_out0[37] */ 358 TRIG_IN_MUX_3_TCPWM_16_TR_OUT038 = 0x0000033Bu, /* tcpwm[0].tr_out0[38] */ 359 TRIG_IN_MUX_3_TCPWM_16_TR_OUT039 = 0x0000033Cu, /* tcpwm[0].tr_out0[39] */ 360 TRIG_IN_MUX_3_TCPWM_16_TR_OUT040 = 0x0000033Du, /* tcpwm[0].tr_out0[40] */ 361 TRIG_IN_MUX_3_TCPWM_16_TR_OUT041 = 0x0000033Eu, /* tcpwm[0].tr_out0[41] */ 362 TRIG_IN_MUX_3_TCPWM_16_TR_OUT042 = 0x0000033Fu, /* tcpwm[0].tr_out0[42] */ 363 TRIG_IN_MUX_3_TCPWM_16_TR_OUT043 = 0x00000340u, /* tcpwm[0].tr_out0[43] */ 364 TRIG_IN_MUX_3_TCPWM_16_TR_OUT044 = 0x00000341u, /* tcpwm[0].tr_out0[44] */ 365 TRIG_IN_MUX_3_TCPWM_16_TR_OUT045 = 0x00000342u, /* tcpwm[0].tr_out0[45] */ 366 TRIG_IN_MUX_3_TCPWM_16_TR_OUT046 = 0x00000343u, /* tcpwm[0].tr_out0[46] */ 367 TRIG_IN_MUX_3_TCPWM_16_TR_OUT047 = 0x00000344u, /* tcpwm[0].tr_out0[47] */ 368 TRIG_IN_MUX_3_TCPWM_16_TR_OUT048 = 0x00000345u, /* tcpwm[0].tr_out0[48] */ 369 TRIG_IN_MUX_3_TCPWM_16_TR_OUT049 = 0x00000346u, /* tcpwm[0].tr_out0[49] */ 370 TRIG_IN_MUX_3_TCPWM_16_TR_OUT050 = 0x00000347u, /* tcpwm[0].tr_out0[50] */ 371 TRIG_IN_MUX_3_TCPWM_16_TR_OUT051 = 0x00000348u, /* tcpwm[0].tr_out0[51] */ 372 TRIG_IN_MUX_3_TCPWM_16_TR_OUT052 = 0x00000349u, /* tcpwm[0].tr_out0[52] */ 373 TRIG_IN_MUX_3_TCPWM_16_TR_OUT053 = 0x0000034Au, /* tcpwm[0].tr_out0[53] */ 374 TRIG_IN_MUX_3_TCPWM_16_TR_OUT054 = 0x0000034Bu, /* tcpwm[0].tr_out0[54] */ 375 TRIG_IN_MUX_3_TCPWM_16_TR_OUT055 = 0x0000034Cu, /* tcpwm[0].tr_out0[55] */ 376 TRIG_IN_MUX_3_TCPWM_16_TR_OUT056 = 0x0000034Du, /* tcpwm[0].tr_out0[56] */ 377 TRIG_IN_MUX_3_TCPWM_16_TR_OUT057 = 0x0000034Eu, /* tcpwm[0].tr_out0[57] */ 378 TRIG_IN_MUX_3_TCPWM_16_TR_OUT058 = 0x0000034Fu, /* tcpwm[0].tr_out0[58] */ 379 TRIG_IN_MUX_3_TCPWM_16_TR_OUT059 = 0x00000350u, /* tcpwm[0].tr_out0[59] */ 380 TRIG_IN_MUX_3_TCPWM_16_TR_OUT060 = 0x00000351u, /* tcpwm[0].tr_out0[60] */ 381 TRIG_IN_MUX_3_TCPWM_16_TR_OUT061 = 0x00000352u, /* tcpwm[0].tr_out0[61] */ 382 TRIG_IN_MUX_3_TCPWM_16_TR_OUT062 = 0x00000353u, /* tcpwm[0].tr_out0[62] */ 383 TRIG_IN_MUX_3_CAN0_TT_TR_OUT0 = 0x00000354u, /* canfd[0].tr_tmp_rtp_out[0] */ 384 TRIG_IN_MUX_3_CAN0_TT_TR_OUT1 = 0x00000355u, /* canfd[0].tr_tmp_rtp_out[1] */ 385 TRIG_IN_MUX_3_CAN0_TT_TR_OUT2 = 0x00000356u, /* canfd[0].tr_tmp_rtp_out[2] */ 386 TRIG_IN_MUX_3_CAN0_TT_TR_OUT3 = 0x00000357u, /* canfd[0].tr_tmp_rtp_out[3] */ 387 TRIG_IN_MUX_3_CAN1_TT_TR_OUT0 = 0x00000358u, /* canfd[1].tr_tmp_rtp_out[0] */ 388 TRIG_IN_MUX_3_CAN1_TT_TR_OUT1 = 0x00000359u, /* canfd[1].tr_tmp_rtp_out[1] */ 389 TRIG_IN_MUX_3_CAN1_TT_TR_OUT2 = 0x0000035Au, /* canfd[1].tr_tmp_rtp_out[2] */ 390 TRIG_IN_MUX_3_CAN1_TT_TR_OUT3 = 0x0000035Bu /* canfd[1].tr_tmp_rtp_out[3] */ 391 } en_trig_input_pdma0_tr_1_t; 392 393 /* Trigger Input Group 4 - Reduces tcpwm output triggers to 16 signals, to allow chaining TCPWMs */ 394 typedef enum 395 { 396 TRIG_IN_MUX_4_TCPWM_32_TR_OUT00 = 0x00000401u, /* tcpwm[0].tr_out0[512] */ 397 TRIG_IN_MUX_4_TCPWM_32_TR_OUT01 = 0x00000402u, /* tcpwm[0].tr_out0[513] */ 398 TRIG_IN_MUX_4_TCPWM_32_TR_OUT02 = 0x00000403u, /* tcpwm[0].tr_out0[514] */ 399 TRIG_IN_MUX_4_TCPWM_32_TR_OUT03 = 0x00000404u, /* tcpwm[0].tr_out0[515] */ 400 TRIG_IN_MUX_4_TCPWM_32_TR_OUT04 = 0x00000405u, /* tcpwm[0].tr_out0[516] */ 401 TRIG_IN_MUX_4_TCPWM_32_TR_OUT05 = 0x00000406u, /* tcpwm[0].tr_out0[517] */ 402 TRIG_IN_MUX_4_TCPWM_32_TR_OUT06 = 0x00000407u, /* tcpwm[0].tr_out0[518] */ 403 TRIG_IN_MUX_4_TCPWM_32_TR_OUT07 = 0x00000408u, /* tcpwm[0].tr_out0[519] */ 404 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT00 = 0x00000409u, /* tcpwm[0].tr_out0[256] */ 405 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT01 = 0x0000040Au, /* tcpwm[0].tr_out0[257] */ 406 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT02 = 0x0000040Bu, /* tcpwm[0].tr_out0[258] */ 407 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT03 = 0x0000040Cu, /* tcpwm[0].tr_out0[259] */ 408 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT04 = 0x0000040Du, /* tcpwm[0].tr_out0[260] */ 409 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT05 = 0x0000040Eu, /* tcpwm[0].tr_out0[261] */ 410 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT06 = 0x0000040Fu, /* tcpwm[0].tr_out0[262] */ 411 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT07 = 0x00000410u, /* tcpwm[0].tr_out0[263] */ 412 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT08 = 0x00000411u, /* tcpwm[0].tr_out0[264] */ 413 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT09 = 0x00000412u, /* tcpwm[0].tr_out0[265] */ 414 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT010 = 0x00000413u, /* tcpwm[0].tr_out0[266] */ 415 TRIG_IN_MUX_4_TCPWM_16M_TR_OUT011 = 0x00000414u, /* tcpwm[0].tr_out0[267] */ 416 TRIG_IN_MUX_4_TCPWM_16_TR_OUT00 = 0x00000415u, /* tcpwm[0].tr_out0[0] */ 417 TRIG_IN_MUX_4_TCPWM_16_TR_OUT01 = 0x00000416u, /* tcpwm[0].tr_out0[1] */ 418 TRIG_IN_MUX_4_TCPWM_16_TR_OUT02 = 0x00000417u, /* tcpwm[0].tr_out0[2] */ 419 TRIG_IN_MUX_4_TCPWM_16_TR_OUT03 = 0x00000418u, /* tcpwm[0].tr_out0[3] */ 420 TRIG_IN_MUX_4_TCPWM_16_TR_OUT04 = 0x00000419u, /* tcpwm[0].tr_out0[4] */ 421 TRIG_IN_MUX_4_TCPWM_16_TR_OUT05 = 0x0000041Au, /* tcpwm[0].tr_out0[5] */ 422 TRIG_IN_MUX_4_TCPWM_16_TR_OUT06 = 0x0000041Bu, /* tcpwm[0].tr_out0[6] */ 423 TRIG_IN_MUX_4_TCPWM_16_TR_OUT07 = 0x0000041Cu, /* tcpwm[0].tr_out0[7] */ 424 TRIG_IN_MUX_4_TCPWM_16_TR_OUT08 = 0x0000041Du, /* tcpwm[0].tr_out0[8] */ 425 TRIG_IN_MUX_4_TCPWM_16_TR_OUT09 = 0x0000041Eu, /* tcpwm[0].tr_out0[9] */ 426 TRIG_IN_MUX_4_TCPWM_16_TR_OUT010 = 0x0000041Fu, /* tcpwm[0].tr_out0[10] */ 427 TRIG_IN_MUX_4_TCPWM_16_TR_OUT011 = 0x00000420u, /* tcpwm[0].tr_out0[11] */ 428 TRIG_IN_MUX_4_TCPWM_16_TR_OUT012 = 0x00000421u, /* tcpwm[0].tr_out0[12] */ 429 TRIG_IN_MUX_4_TCPWM_16_TR_OUT013 = 0x00000422u, /* tcpwm[0].tr_out0[13] */ 430 TRIG_IN_MUX_4_TCPWM_16_TR_OUT014 = 0x00000423u, /* tcpwm[0].tr_out0[14] */ 431 TRIG_IN_MUX_4_TCPWM_16_TR_OUT015 = 0x00000424u, /* tcpwm[0].tr_out0[15] */ 432 TRIG_IN_MUX_4_TCPWM_16_TR_OUT016 = 0x00000425u, /* tcpwm[0].tr_out0[16] */ 433 TRIG_IN_MUX_4_TCPWM_16_TR_OUT017 = 0x00000426u, /* tcpwm[0].tr_out0[17] */ 434 TRIG_IN_MUX_4_TCPWM_16_TR_OUT018 = 0x00000427u, /* tcpwm[0].tr_out0[18] */ 435 TRIG_IN_MUX_4_TCPWM_16_TR_OUT019 = 0x00000428u, /* tcpwm[0].tr_out0[19] */ 436 TRIG_IN_MUX_4_TCPWM_16_TR_OUT020 = 0x00000429u, /* tcpwm[0].tr_out0[20] */ 437 TRIG_IN_MUX_4_TCPWM_16_TR_OUT021 = 0x0000042Au, /* tcpwm[0].tr_out0[21] */ 438 TRIG_IN_MUX_4_TCPWM_16_TR_OUT022 = 0x0000042Bu, /* tcpwm[0].tr_out0[22] */ 439 TRIG_IN_MUX_4_TCPWM_16_TR_OUT023 = 0x0000042Cu, /* tcpwm[0].tr_out0[23] */ 440 TRIG_IN_MUX_4_TCPWM_16_TR_OUT024 = 0x0000042Du, /* tcpwm[0].tr_out0[24] */ 441 TRIG_IN_MUX_4_TCPWM_16_TR_OUT025 = 0x0000042Eu, /* tcpwm[0].tr_out0[25] */ 442 TRIG_IN_MUX_4_TCPWM_16_TR_OUT026 = 0x0000042Fu, /* tcpwm[0].tr_out0[26] */ 443 TRIG_IN_MUX_4_TCPWM_16_TR_OUT027 = 0x00000430u, /* tcpwm[0].tr_out0[27] */ 444 TRIG_IN_MUX_4_TCPWM_16_TR_OUT028 = 0x00000431u, /* tcpwm[0].tr_out0[28] */ 445 TRIG_IN_MUX_4_TCPWM_16_TR_OUT029 = 0x00000432u, /* tcpwm[0].tr_out0[29] */ 446 TRIG_IN_MUX_4_TCPWM_16_TR_OUT030 = 0x00000433u, /* tcpwm[0].tr_out0[30] */ 447 TRIG_IN_MUX_4_TCPWM_16_TR_OUT031 = 0x00000434u, /* tcpwm[0].tr_out0[31] */ 448 TRIG_IN_MUX_4_TCPWM_16_TR_OUT032 = 0x00000435u, /* tcpwm[0].tr_out0[32] */ 449 TRIG_IN_MUX_4_TCPWM_16_TR_OUT033 = 0x00000436u, /* tcpwm[0].tr_out0[33] */ 450 TRIG_IN_MUX_4_TCPWM_16_TR_OUT034 = 0x00000437u, /* tcpwm[0].tr_out0[34] */ 451 TRIG_IN_MUX_4_TCPWM_16_TR_OUT035 = 0x00000438u, /* tcpwm[0].tr_out0[35] */ 452 TRIG_IN_MUX_4_TCPWM_16_TR_OUT036 = 0x00000439u, /* tcpwm[0].tr_out0[36] */ 453 TRIG_IN_MUX_4_TCPWM_16_TR_OUT037 = 0x0000043Au, /* tcpwm[0].tr_out0[37] */ 454 TRIG_IN_MUX_4_TCPWM_16_TR_OUT038 = 0x0000043Bu, /* tcpwm[0].tr_out0[38] */ 455 TRIG_IN_MUX_4_TCPWM_16_TR_OUT039 = 0x0000043Cu, /* tcpwm[0].tr_out0[39] */ 456 TRIG_IN_MUX_4_TCPWM_16_TR_OUT040 = 0x0000043Du, /* tcpwm[0].tr_out0[40] */ 457 TRIG_IN_MUX_4_TCPWM_16_TR_OUT041 = 0x0000043Eu, /* tcpwm[0].tr_out0[41] */ 458 TRIG_IN_MUX_4_TCPWM_16_TR_OUT042 = 0x0000043Fu, /* tcpwm[0].tr_out0[42] */ 459 TRIG_IN_MUX_4_TCPWM_16_TR_OUT043 = 0x00000440u, /* tcpwm[0].tr_out0[43] */ 460 TRIG_IN_MUX_4_TCPWM_16_TR_OUT044 = 0x00000441u, /* tcpwm[0].tr_out0[44] */ 461 TRIG_IN_MUX_4_TCPWM_16_TR_OUT045 = 0x00000442u, /* tcpwm[0].tr_out0[45] */ 462 TRIG_IN_MUX_4_TCPWM_16_TR_OUT046 = 0x00000443u, /* tcpwm[0].tr_out0[46] */ 463 TRIG_IN_MUX_4_TCPWM_16_TR_OUT047 = 0x00000444u, /* tcpwm[0].tr_out0[47] */ 464 TRIG_IN_MUX_4_TCPWM_16_TR_OUT048 = 0x00000445u, /* tcpwm[0].tr_out0[48] */ 465 TRIG_IN_MUX_4_TCPWM_16_TR_OUT049 = 0x00000446u, /* tcpwm[0].tr_out0[49] */ 466 TRIG_IN_MUX_4_TCPWM_16_TR_OUT050 = 0x00000447u, /* tcpwm[0].tr_out0[50] */ 467 TRIG_IN_MUX_4_TCPWM_16_TR_OUT051 = 0x00000448u, /* tcpwm[0].tr_out0[51] */ 468 TRIG_IN_MUX_4_TCPWM_16_TR_OUT052 = 0x00000449u, /* tcpwm[0].tr_out0[52] */ 469 TRIG_IN_MUX_4_TCPWM_16_TR_OUT053 = 0x0000044Au, /* tcpwm[0].tr_out0[53] */ 470 TRIG_IN_MUX_4_TCPWM_16_TR_OUT054 = 0x0000044Bu, /* tcpwm[0].tr_out0[54] */ 471 TRIG_IN_MUX_4_TCPWM_16_TR_OUT055 = 0x0000044Cu, /* tcpwm[0].tr_out0[55] */ 472 TRIG_IN_MUX_4_TCPWM_16_TR_OUT056 = 0x0000044Du, /* tcpwm[0].tr_out0[56] */ 473 TRIG_IN_MUX_4_TCPWM_16_TR_OUT057 = 0x0000044Eu, /* tcpwm[0].tr_out0[57] */ 474 TRIG_IN_MUX_4_TCPWM_16_TR_OUT058 = 0x0000044Fu, /* tcpwm[0].tr_out0[58] */ 475 TRIG_IN_MUX_4_TCPWM_16_TR_OUT059 = 0x00000450u, /* tcpwm[0].tr_out0[59] */ 476 TRIG_IN_MUX_4_TCPWM_16_TR_OUT060 = 0x00000451u, /* tcpwm[0].tr_out0[60] */ 477 TRIG_IN_MUX_4_TCPWM_16_TR_OUT061 = 0x00000452u, /* tcpwm[0].tr_out0[61] */ 478 TRIG_IN_MUX_4_TCPWM_16_TR_OUT062 = 0x00000453u, /* tcpwm[0].tr_out0[62] */ 479 TRIG_IN_MUX_4_TCPWM_16_TR_OUT10 = 0x00000454u, /* tcpwm[0].tr_out1[0] */ 480 TRIG_IN_MUX_4_TCPWM_16_TR_OUT11 = 0x00000455u, /* tcpwm[0].tr_out1[1] */ 481 TRIG_IN_MUX_4_TCPWM_16_TR_OUT12 = 0x00000456u, /* tcpwm[0].tr_out1[2] */ 482 TRIG_IN_MUX_4_TCPWM_16_TR_OUT13 = 0x00000457u, /* tcpwm[0].tr_out1[3] */ 483 TRIG_IN_MUX_4_TCPWM_16_TR_OUT14 = 0x00000458u, /* tcpwm[0].tr_out1[4] */ 484 TRIG_IN_MUX_4_TCPWM_16_TR_OUT15 = 0x00000459u, /* tcpwm[0].tr_out1[5] */ 485 TRIG_IN_MUX_4_TCPWM_16_TR_OUT16 = 0x0000045Au, /* tcpwm[0].tr_out1[6] */ 486 TRIG_IN_MUX_4_TCPWM_16_TR_OUT17 = 0x0000045Bu, /* tcpwm[0].tr_out1[7] */ 487 TRIG_IN_MUX_4_CAN0_TT_TR_OUT0 = 0x0000045Cu, /* canfd[0].tr_tmp_rtp_out[0] */ 488 TRIG_IN_MUX_4_CAN0_TT_TR_OUT1 = 0x0000045Du, /* canfd[0].tr_tmp_rtp_out[1] */ 489 TRIG_IN_MUX_4_CAN0_TT_TR_OUT2 = 0x0000045Eu, /* canfd[0].tr_tmp_rtp_out[2] */ 490 TRIG_IN_MUX_4_CAN0_TT_TR_OUT3 = 0x0000045Fu, /* canfd[0].tr_tmp_rtp_out[3] */ 491 TRIG_IN_MUX_4_CAN1_TT_TR_OUT0 = 0x00000460u, /* canfd[1].tr_tmp_rtp_out[0] */ 492 TRIG_IN_MUX_4_CAN1_TT_TR_OUT1 = 0x00000461u, /* canfd[1].tr_tmp_rtp_out[1] */ 493 TRIG_IN_MUX_4_CAN1_TT_TR_OUT2 = 0x00000462u, /* canfd[1].tr_tmp_rtp_out[2] */ 494 TRIG_IN_MUX_4_CAN1_TT_TR_OUT3 = 0x00000463u /* canfd[1].tr_tmp_rtp_out[3] */ 495 } en_trig_input_tcpwm_out_t; 496 497 /* Trigger Input Group 5 - TCPWM trigger inputs */ 498 typedef enum 499 { 500 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ 501 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ 502 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ 503 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ 504 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ 505 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ 506 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ 507 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ 508 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ 509 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ 510 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ 511 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ 512 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ 513 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ 514 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ 515 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ 516 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x00000511u, /* cpuss.dw1_tr_out[0] */ 517 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x00000512u, /* cpuss.dw1_tr_out[1] */ 518 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000513u, /* cpuss.dw1_tr_out[2] */ 519 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000514u, /* cpuss.dw1_tr_out[3] */ 520 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000515u, /* cpuss.dw1_tr_out[4] */ 521 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000516u, /* cpuss.dw1_tr_out[5] */ 522 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000517u, /* cpuss.dw1_tr_out[6] */ 523 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000518u, /* cpuss.dw1_tr_out[7] */ 524 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x00000519u, /* cpuss.dmac_tr_out[0] */ 525 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000051Au, /* cpuss.dmac_tr_out[1] */ 526 TRIG_IN_MUX_5_MDMA_TR_OUT2 = 0x0000051Bu, /* cpuss.dmac_tr_out[2] */ 527 TRIG_IN_MUX_5_MDMA_TR_OUT3 = 0x0000051Cu, /* cpuss.dmac_tr_out[3] */ 528 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x0000051Du, /* cpuss.cti_tr_out[0] */ 529 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x0000051Eu, /* cpuss.cti_tr_out[1] */ 530 TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x0000051Fu, /* cpuss.tr_fault[0] */ 531 TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x00000520u, /* cpuss.tr_fault[1] */ 532 TRIG_IN_MUX_5_FAULT_TR_OUT2 = 0x00000521u, /* cpuss.tr_fault[2] */ 533 TRIG_IN_MUX_5_FAULT_TR_OUT3 = 0x00000522u, /* cpuss.tr_fault[3] */ 534 TRIG_IN_MUX_5_PASS_GEN_TR_OUT0 = 0x00000523u, /* pass[0].tr_sar_gen_out[0] */ 535 TRIG_IN_MUX_5_PASS_GEN_TR_OUT1 = 0x00000524u, /* pass[0].tr_sar_gen_out[1] */ 536 TRIG_IN_MUX_5_PASS_GEN_TR_OUT2 = 0x00000525u, /* pass[0].tr_sar_gen_out[2] */ 537 TRIG_IN_MUX_5_PASS_GEN_TR_OUT3 = 0x00000526u, /* pass[0].tr_sar_gen_out[3] */ 538 TRIG_IN_MUX_5_PASS_GEN_TR_OUT4 = 0x00000527u, /* pass[0].tr_sar_gen_out[4] */ 539 TRIG_IN_MUX_5_PASS_GEN_TR_OUT5 = 0x00000528u, /* pass[0].tr_sar_gen_out[5] */ 540 TRIG_IN_MUX_5_HSIOM_IO_INPUT0 = 0x00000529u, /* peri.tr_io_input[0] */ 541 TRIG_IN_MUX_5_HSIOM_IO_INPUT1 = 0x0000052Au, /* peri.tr_io_input[1] */ 542 TRIG_IN_MUX_5_HSIOM_IO_INPUT2 = 0x0000052Bu, /* peri.tr_io_input[2] */ 543 TRIG_IN_MUX_5_HSIOM_IO_INPUT3 = 0x0000052Cu, /* peri.tr_io_input[3] */ 544 TRIG_IN_MUX_5_HSIOM_IO_INPUT4 = 0x0000052Du, /* peri.tr_io_input[4] */ 545 TRIG_IN_MUX_5_HSIOM_IO_INPUT5 = 0x0000052Eu, /* peri.tr_io_input[5] */ 546 TRIG_IN_MUX_5_HSIOM_IO_INPUT6 = 0x0000052Fu, /* peri.tr_io_input[6] */ 547 TRIG_IN_MUX_5_HSIOM_IO_INPUT7 = 0x00000530u, /* peri.tr_io_input[7] */ 548 TRIG_IN_MUX_5_HSIOM_IO_INPUT8 = 0x00000531u, /* peri.tr_io_input[8] */ 549 TRIG_IN_MUX_5_HSIOM_IO_INPUT9 = 0x00000532u, /* peri.tr_io_input[9] */ 550 TRIG_IN_MUX_5_HSIOM_IO_INPUT10 = 0x00000533u, /* peri.tr_io_input[10] */ 551 TRIG_IN_MUX_5_HSIOM_IO_INPUT11 = 0x00000534u, /* peri.tr_io_input[11] */ 552 TRIG_IN_MUX_5_HSIOM_IO_INPUT12 = 0x00000535u, /* peri.tr_io_input[12] */ 553 TRIG_IN_MUX_5_HSIOM_IO_INPUT13 = 0x00000536u, /* peri.tr_io_input[13] */ 554 TRIG_IN_MUX_5_HSIOM_IO_INPUT14 = 0x00000537u, /* peri.tr_io_input[14] */ 555 TRIG_IN_MUX_5_HSIOM_IO_INPUT15 = 0x00000538u, /* peri.tr_io_input[15] */ 556 TRIG_IN_MUX_5_HSIOM_IO_INPUT16 = 0x00000539u, /* peri.tr_io_input[16] */ 557 TRIG_IN_MUX_5_HSIOM_IO_INPUT17 = 0x0000053Au, /* peri.tr_io_input[17] */ 558 TRIG_IN_MUX_5_HSIOM_IO_INPUT18 = 0x0000053Bu, /* peri.tr_io_input[18] */ 559 TRIG_IN_MUX_5_HSIOM_IO_INPUT19 = 0x0000053Cu, /* peri.tr_io_input[19] */ 560 TRIG_IN_MUX_5_HSIOM_IO_INPUT20 = 0x0000053Du, /* peri.tr_io_input[20] */ 561 TRIG_IN_MUX_5_HSIOM_IO_INPUT21 = 0x0000053Eu, /* peri.tr_io_input[21] */ 562 TRIG_IN_MUX_5_HSIOM_IO_INPUT22 = 0x0000053Fu, /* peri.tr_io_input[22] */ 563 TRIG_IN_MUX_5_HSIOM_IO_INPUT23 = 0x00000540u, /* peri.tr_io_input[23] */ 564 TRIG_IN_MUX_5_HSIOM_IO_INPUT24 = 0x00000541u, /* peri.tr_io_input[24] */ 565 TRIG_IN_MUX_5_HSIOM_IO_INPUT25 = 0x00000542u, /* peri.tr_io_input[25] */ 566 TRIG_IN_MUX_5_HSIOM_IO_INPUT26 = 0x00000543u, /* peri.tr_io_input[26] */ 567 TRIG_IN_MUX_5_HSIOM_IO_INPUT27 = 0x00000544u, /* peri.tr_io_input[27] */ 568 TRIG_IN_MUX_5_HSIOM_IO_INPUT28 = 0x00000545u, /* peri.tr_io_input[28] */ 569 TRIG_IN_MUX_5_HSIOM_IO_INPUT29 = 0x00000546u, /* peri.tr_io_input[29] */ 570 TRIG_IN_MUX_5_HSIOM_IO_INPUT30 = 0x00000547u, /* peri.tr_io_input[30] */ 571 TRIG_IN_MUX_5_HSIOM_IO_INPUT31 = 0x00000548u, /* peri.tr_io_input[31] */ 572 TRIG_IN_MUX_5_SCB_TX_TR_OUT0 = 0x00000549u, /* scb[0].tr_tx_req */ 573 TRIG_IN_MUX_5_SCB_RX_TR_OUT0 = 0x0000054Au, /* scb[0].tr_rx_req */ 574 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT0 = 0x0000054Bu, /* scb[0].tr_i2c_scl_filtered */ 575 TRIG_IN_MUX_5_SCB_TX_TR_OUT1 = 0x0000054Cu, /* scb[1].tr_tx_req */ 576 TRIG_IN_MUX_5_SCB_RX_TR_OUT1 = 0x0000054Du, /* scb[1].tr_rx_req */ 577 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT1 = 0x0000054Eu, /* scb[1].tr_i2c_scl_filtered */ 578 TRIG_IN_MUX_5_SCB_TX_TR_OUT2 = 0x0000054Fu, /* scb[2].tr_tx_req */ 579 TRIG_IN_MUX_5_SCB_RX_TR_OUT2 = 0x00000550u, /* scb[2].tr_rx_req */ 580 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT2 = 0x00000551u, /* scb[2].tr_i2c_scl_filtered */ 581 TRIG_IN_MUX_5_SCB_TX_TR_OUT3 = 0x00000552u, /* scb[3].tr_tx_req */ 582 TRIG_IN_MUX_5_SCB_RX_TR_OUT3 = 0x00000553u, /* scb[3].tr_rx_req */ 583 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT3 = 0x00000554u, /* scb[3].tr_i2c_scl_filtered */ 584 TRIG_IN_MUX_5_SCB_TX_TR_OUT4 = 0x00000555u, /* scb[4].tr_tx_req */ 585 TRIG_IN_MUX_5_SCB_RX_TR_OUT4 = 0x00000556u, /* scb[4].tr_rx_req */ 586 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT4 = 0x00000557u, /* scb[4].tr_i2c_scl_filtered */ 587 TRIG_IN_MUX_5_SCB_TX_TR_OUT5 = 0x00000558u, /* scb[5].tr_tx_req */ 588 TRIG_IN_MUX_5_SCB_RX_TR_OUT5 = 0x00000559u, /* scb[5].tr_rx_req */ 589 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT5 = 0x0000055Au, /* scb[5].tr_i2c_scl_filtered */ 590 TRIG_IN_MUX_5_SCB_TX_TR_OUT6 = 0x0000055Bu, /* scb[6].tr_tx_req */ 591 TRIG_IN_MUX_5_SCB_RX_TR_OUT6 = 0x0000055Cu, /* scb[6].tr_rx_req */ 592 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT6 = 0x0000055Du, /* scb[6].tr_i2c_scl_filtered */ 593 TRIG_IN_MUX_5_SCB_TX_TR_OUT7 = 0x0000055Eu, /* scb[7].tr_tx_req */ 594 TRIG_IN_MUX_5_SCB_RX_TR_OUT7 = 0x0000055Fu, /* scb[7].tr_rx_req */ 595 TRIG_IN_MUX_5_SCB_I2C_SCL_TR_OUT7 = 0x00000560u, /* scb[7].tr_i2c_scl_filtered */ 596 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT0 = 0x00000561u, /* canfd[0].tr_dbg_dma_req[0] */ 597 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT1 = 0x00000562u, /* canfd[0].tr_dbg_dma_req[1] */ 598 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT2 = 0x00000563u, /* canfd[0].tr_dbg_dma_req[2] */ 599 TRIG_IN_MUX_5_CAN0_DBG_TR_OUT3 = 0x00000564u, /* canfd[0].tr_dbg_dma_req[3] */ 600 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT0 = 0x00000565u, /* canfd[0].tr_fifo0[0] */ 601 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT1 = 0x00000566u, /* canfd[0].tr_fifo0[1] */ 602 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT2 = 0x00000567u, /* canfd[0].tr_fifo0[2] */ 603 TRIG_IN_MUX_5_CAN0_FIFO0_TR_OUT3 = 0x00000568u, /* canfd[0].tr_fifo0[3] */ 604 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT0 = 0x00000569u, /* canfd[0].tr_fifo1[0] */ 605 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT1 = 0x0000056Au, /* canfd[0].tr_fifo1[1] */ 606 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT2 = 0x0000056Bu, /* canfd[0].tr_fifo1[2] */ 607 TRIG_IN_MUX_5_CAN0_FIFO1_TR_OUT3 = 0x0000056Cu, /* canfd[0].tr_fifo1[3] */ 608 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT0 = 0x0000056Du, /* canfd[1].tr_dbg_dma_req[0] */ 609 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT1 = 0x0000056Eu, /* canfd[1].tr_dbg_dma_req[1] */ 610 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT2 = 0x0000056Fu, /* canfd[1].tr_dbg_dma_req[2] */ 611 TRIG_IN_MUX_5_CAN1_DBG_TR_OUT3 = 0x00000570u, /* canfd[1].tr_dbg_dma_req[3] */ 612 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT0 = 0x00000571u, /* canfd[1].tr_fifo0[0] */ 613 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT1 = 0x00000572u, /* canfd[1].tr_fifo0[1] */ 614 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT2 = 0x00000573u, /* canfd[1].tr_fifo0[2] */ 615 TRIG_IN_MUX_5_CAN1_FIFO0_TR_OUT3 = 0x00000574u, /* canfd[1].tr_fifo0[3] */ 616 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT0 = 0x00000575u, /* canfd[1].tr_fifo1[0] */ 617 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT1 = 0x00000576u, /* canfd[1].tr_fifo1[1] */ 618 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT2 = 0x00000577u, /* canfd[1].tr_fifo1[2] */ 619 TRIG_IN_MUX_5_CAN1_FIFO1_TR_OUT3 = 0x00000578u, /* canfd[1].tr_fifo1[3] */ 620 TRIG_IN_MUX_5_CXPI_TX_TR_OUT0 = 0x00000579u, /* cxpi[0].tr_tx_req[0] */ 621 TRIG_IN_MUX_5_CXPI_TX_TR_OUT1 = 0x0000057Au, /* cxpi[0].tr_tx_req[1] */ 622 TRIG_IN_MUX_5_CXPI_TX_TR_OUT2 = 0x0000057Bu, /* cxpi[0].tr_tx_req[2] */ 623 TRIG_IN_MUX_5_CXPI_TX_TR_OUT3 = 0x0000057Cu, /* cxpi[0].tr_tx_req[3] */ 624 TRIG_IN_MUX_5_CXPI_RX_TR_OUT0 = 0x0000057Du, /* cxpi[0].tr_rx_req[0] */ 625 TRIG_IN_MUX_5_CXPI_RX_TR_OUT1 = 0x0000057Eu, /* cxpi[0].tr_rx_req[1] */ 626 TRIG_IN_MUX_5_CXPI_RX_TR_OUT2 = 0x0000057Fu, /* cxpi[0].tr_rx_req[2] */ 627 TRIG_IN_MUX_5_CXPI_RX_TR_OUT3 = 0x00000580u, /* cxpi[0].tr_rx_req[3] */ 628 TRIG_IN_MUX_5_EVTGEN_TR_OUT3 = 0x00000581u, /* evtgen[0].tr_out[3] */ 629 TRIG_IN_MUX_5_EVTGEN_TR_OUT4 = 0x00000582u, /* evtgen[0].tr_out[4] */ 630 TRIG_IN_MUX_5_EVTGEN_TR_OUT5 = 0x00000583u, /* evtgen[0].tr_out[5] */ 631 TRIG_IN_MUX_5_EVTGEN_TR_OUT6 = 0x00000584u, /* evtgen[0].tr_out[6] */ 632 TRIG_IN_MUX_5_EVTGEN_TR_OUT7 = 0x00000585u, /* evtgen[0].tr_out[7] */ 633 TRIG_IN_MUX_5_EVTGEN_TR_OUT8 = 0x00000586u, /* evtgen[0].tr_out[8] */ 634 TRIG_IN_MUX_5_EVTGEN_TR_OUT9 = 0x00000587u, /* evtgen[0].tr_out[9] */ 635 TRIG_IN_MUX_5_EVTGEN_TR_OUT10 = 0x00000588u /* evtgen[0].tr_out[10] */ 636 } en_trig_input_tcpwm_in_t; 637 638 /* Trigger Input Group 6 - PASS trigger multiplexer */ 639 typedef enum 640 { 641 TRIG_IN_MUX_6_PDMA0_TR_OUT0 = 0x00000601u, /* cpuss.dw0_tr_out[0] */ 642 TRIG_IN_MUX_6_PDMA0_TR_OUT1 = 0x00000602u, /* cpuss.dw0_tr_out[1] */ 643 TRIG_IN_MUX_6_PDMA0_TR_OUT2 = 0x00000603u, /* cpuss.dw0_tr_out[2] */ 644 TRIG_IN_MUX_6_PDMA0_TR_OUT3 = 0x00000604u, /* cpuss.dw0_tr_out[3] */ 645 TRIG_IN_MUX_6_PDMA0_TR_OUT4 = 0x00000605u, /* cpuss.dw0_tr_out[4] */ 646 TRIG_IN_MUX_6_PDMA0_TR_OUT5 = 0x00000606u, /* cpuss.dw0_tr_out[5] */ 647 TRIG_IN_MUX_6_PDMA0_TR_OUT6 = 0x00000607u, /* cpuss.dw0_tr_out[6] */ 648 TRIG_IN_MUX_6_PDMA0_TR_OUT7 = 0x00000608u, /* cpuss.dw0_tr_out[7] */ 649 TRIG_IN_MUX_6_PDMA0_TR_OUT8 = 0x00000609u, /* cpuss.dw0_tr_out[8] */ 650 TRIG_IN_MUX_6_PDMA0_TR_OUT9 = 0x0000060Au, /* cpuss.dw0_tr_out[9] */ 651 TRIG_IN_MUX_6_PDMA0_TR_OUT10 = 0x0000060Bu, /* cpuss.dw0_tr_out[10] */ 652 TRIG_IN_MUX_6_PDMA0_TR_OUT11 = 0x0000060Cu, /* cpuss.dw0_tr_out[11] */ 653 TRIG_IN_MUX_6_PDMA0_TR_OUT12 = 0x0000060Du, /* cpuss.dw0_tr_out[12] */ 654 TRIG_IN_MUX_6_PDMA0_TR_OUT13 = 0x0000060Eu, /* cpuss.dw0_tr_out[13] */ 655 TRIG_IN_MUX_6_PDMA0_TR_OUT14 = 0x0000060Fu, /* cpuss.dw0_tr_out[14] */ 656 TRIG_IN_MUX_6_PDMA0_TR_OUT15 = 0x00000610u, /* cpuss.dw0_tr_out[15] */ 657 TRIG_IN_MUX_6_CTI_TR_OUT0 = 0x00000611u, /* cpuss.cti_tr_out[0] */ 658 TRIG_IN_MUX_6_CTI_TR_OUT1 = 0x00000612u, /* cpuss.cti_tr_out[1] */ 659 TRIG_IN_MUX_6_FAULT_TR_OUT0 = 0x00000613u, /* cpuss.tr_fault[0] */ 660 TRIG_IN_MUX_6_FAULT_TR_OUT1 = 0x00000614u, /* cpuss.tr_fault[1] */ 661 TRIG_IN_MUX_6_FAULT_TR_OUT2 = 0x00000615u, /* cpuss.tr_fault[2] */ 662 TRIG_IN_MUX_6_FAULT_TR_OUT3 = 0x00000616u, /* cpuss.tr_fault[3] */ 663 TRIG_IN_MUX_6_EVTGEN_TR_OUT0 = 0x00000617u, /* evtgen[0].tr_out[0] */ 664 TRIG_IN_MUX_6_EVTGEN_TR_OUT1 = 0x00000618u, /* evtgen[0].tr_out[1] */ 665 TRIG_IN_MUX_6_EVTGEN_TR_OUT2 = 0x00000619u, /* evtgen[0].tr_out[2] */ 666 TRIG_IN_MUX_6_PASS_GEN_TR_OUT0 = 0x0000061Au, /* pass[0].tr_sar_gen_out[0] */ 667 TRIG_IN_MUX_6_PASS_GEN_TR_OUT1 = 0x0000061Bu, /* pass[0].tr_sar_gen_out[1] */ 668 TRIG_IN_MUX_6_PASS_GEN_TR_OUT2 = 0x0000061Cu, /* pass[0].tr_sar_gen_out[2] */ 669 TRIG_IN_MUX_6_PASS_GEN_TR_OUT3 = 0x0000061Du, /* pass[0].tr_sar_gen_out[3] */ 670 TRIG_IN_MUX_6_PASS_GEN_TR_OUT4 = 0x0000061Eu, /* pass[0].tr_sar_gen_out[4] */ 671 TRIG_IN_MUX_6_PASS_GEN_TR_OUT5 = 0x0000061Fu, /* pass[0].tr_sar_gen_out[5] */ 672 TRIG_IN_MUX_6_HSIOM_IO_INPUT0 = 0x00000620u, /* peri.tr_io_input[0] */ 673 TRIG_IN_MUX_6_HSIOM_IO_INPUT1 = 0x00000621u, /* peri.tr_io_input[1] */ 674 TRIG_IN_MUX_6_HSIOM_IO_INPUT2 = 0x00000622u, /* peri.tr_io_input[2] */ 675 TRIG_IN_MUX_6_HSIOM_IO_INPUT3 = 0x00000623u, /* peri.tr_io_input[3] */ 676 TRIG_IN_MUX_6_HSIOM_IO_INPUT4 = 0x00000624u, /* peri.tr_io_input[4] */ 677 TRIG_IN_MUX_6_HSIOM_IO_INPUT5 = 0x00000625u, /* peri.tr_io_input[5] */ 678 TRIG_IN_MUX_6_HSIOM_IO_INPUT6 = 0x00000626u, /* peri.tr_io_input[6] */ 679 TRIG_IN_MUX_6_HSIOM_IO_INPUT7 = 0x00000627u, /* peri.tr_io_input[7] */ 680 TRIG_IN_MUX_6_HSIOM_IO_INPUT8 = 0x00000628u, /* peri.tr_io_input[8] */ 681 TRIG_IN_MUX_6_HSIOM_IO_INPUT9 = 0x00000629u, /* peri.tr_io_input[9] */ 682 TRIG_IN_MUX_6_HSIOM_IO_INPUT10 = 0x0000062Au, /* peri.tr_io_input[10] */ 683 TRIG_IN_MUX_6_HSIOM_IO_INPUT11 = 0x0000062Bu, /* peri.tr_io_input[11] */ 684 TRIG_IN_MUX_6_HSIOM_IO_INPUT12 = 0x0000062Cu, /* peri.tr_io_input[12] */ 685 TRIG_IN_MUX_6_HSIOM_IO_INPUT13 = 0x0000062Du, /* peri.tr_io_input[13] */ 686 TRIG_IN_MUX_6_HSIOM_IO_INPUT14 = 0x0000062Eu, /* peri.tr_io_input[14] */ 687 TRIG_IN_MUX_6_HSIOM_IO_INPUT15 = 0x0000062Fu, /* peri.tr_io_input[15] */ 688 TRIG_IN_MUX_6_HSIOM_IO_INPUT16 = 0x00000630u, /* peri.tr_io_input[16] */ 689 TRIG_IN_MUX_6_HSIOM_IO_INPUT17 = 0x00000631u, /* peri.tr_io_input[17] */ 690 TRIG_IN_MUX_6_HSIOM_IO_INPUT18 = 0x00000632u, /* peri.tr_io_input[18] */ 691 TRIG_IN_MUX_6_HSIOM_IO_INPUT19 = 0x00000633u, /* peri.tr_io_input[19] */ 692 TRIG_IN_MUX_6_HSIOM_IO_INPUT20 = 0x00000634u, /* peri.tr_io_input[20] */ 693 TRIG_IN_MUX_6_HSIOM_IO_INPUT21 = 0x00000635u, /* peri.tr_io_input[21] */ 694 TRIG_IN_MUX_6_HSIOM_IO_INPUT22 = 0x00000636u, /* peri.tr_io_input[22] */ 695 TRIG_IN_MUX_6_HSIOM_IO_INPUT23 = 0x00000637u, /* peri.tr_io_input[23] */ 696 TRIG_IN_MUX_6_HSIOM_IO_INPUT24 = 0x00000638u, /* peri.tr_io_input[24] */ 697 TRIG_IN_MUX_6_HSIOM_IO_INPUT25 = 0x00000639u, /* peri.tr_io_input[25] */ 698 TRIG_IN_MUX_6_HSIOM_IO_INPUT26 = 0x0000063Au, /* peri.tr_io_input[26] */ 699 TRIG_IN_MUX_6_HSIOM_IO_INPUT27 = 0x0000063Bu, /* peri.tr_io_input[27] */ 700 TRIG_IN_MUX_6_HSIOM_IO_INPUT28 = 0x0000063Cu, /* peri.tr_io_input[28] */ 701 TRIG_IN_MUX_6_HSIOM_IO_INPUT29 = 0x0000063Du, /* peri.tr_io_input[29] */ 702 TRIG_IN_MUX_6_HSIOM_IO_INPUT30 = 0x0000063Eu, /* peri.tr_io_input[30] */ 703 TRIG_IN_MUX_6_HSIOM_IO_INPUT31 = 0x0000063Fu, /* peri.tr_io_input[31] */ 704 TRIG_IN_MUX_6_TCPWM_32_TR_OUT10 = 0x00000640u, /* tcpwm[0].tr_out1[512] */ 705 TRIG_IN_MUX_6_TCPWM_32_TR_OUT11 = 0x00000641u, /* tcpwm[0].tr_out1[513] */ 706 TRIG_IN_MUX_6_TCPWM_32_TR_OUT12 = 0x00000642u, /* tcpwm[0].tr_out1[514] */ 707 TRIG_IN_MUX_6_TCPWM_32_TR_OUT13 = 0x00000643u, /* tcpwm[0].tr_out1[515] */ 708 TRIG_IN_MUX_6_TCPWM_32_TR_OUT14 = 0x00000644u, /* tcpwm[0].tr_out1[516] */ 709 TRIG_IN_MUX_6_TCPWM_32_TR_OUT15 = 0x00000645u, /* tcpwm[0].tr_out1[517] */ 710 TRIG_IN_MUX_6_TCPWM_32_TR_OUT16 = 0x00000646u, /* tcpwm[0].tr_out1[518] */ 711 TRIG_IN_MUX_6_TCPWM_32_TR_OUT17 = 0x00000647u, /* tcpwm[0].tr_out1[519] */ 712 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT10 = 0x00000648u, /* tcpwm[0].tr_out1[256] */ 713 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT11 = 0x00000649u, /* tcpwm[0].tr_out1[257] */ 714 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT12 = 0x0000064Au, /* tcpwm[0].tr_out1[258] */ 715 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT13 = 0x0000064Bu, /* tcpwm[0].tr_out1[259] */ 716 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT14 = 0x0000064Cu, /* tcpwm[0].tr_out1[260] */ 717 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT15 = 0x0000064Du, /* tcpwm[0].tr_out1[261] */ 718 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT16 = 0x0000064Eu, /* tcpwm[0].tr_out1[262] */ 719 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT17 = 0x0000064Fu, /* tcpwm[0].tr_out1[263] */ 720 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT18 = 0x00000650u, /* tcpwm[0].tr_out1[264] */ 721 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT19 = 0x00000651u, /* tcpwm[0].tr_out1[265] */ 722 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT110 = 0x00000652u, /* tcpwm[0].tr_out1[266] */ 723 TRIG_IN_MUX_6_TCPWM_16M_TR_OUT111 = 0x00000653u /* tcpwm[0].tr_out1[267] */ 724 } en_trig_input_pass_t; 725 726 /* Trigger Input Group 7 - CAN TT Synchronization triggers */ 727 typedef enum 728 { 729 TRIG_IN_MUX_7_CAN0_TT_TR_OUT0 = 0x00000701u, /* canfd[0].tr_tmp_rtp_out[0] */ 730 TRIG_IN_MUX_7_CAN0_TT_TR_OUT1 = 0x00000702u, /* canfd[0].tr_tmp_rtp_out[1] */ 731 TRIG_IN_MUX_7_CAN0_TT_TR_OUT2 = 0x00000703u, /* canfd[0].tr_tmp_rtp_out[2] */ 732 TRIG_IN_MUX_7_CAN0_TT_TR_OUT3 = 0x00000704u, /* canfd[0].tr_tmp_rtp_out[3] */ 733 TRIG_IN_MUX_7_CAN1_TT_TR_OUT0 = 0x00000705u, /* canfd[1].tr_tmp_rtp_out[0] */ 734 TRIG_IN_MUX_7_CAN1_TT_TR_OUT1 = 0x00000706u, /* canfd[1].tr_tmp_rtp_out[1] */ 735 TRIG_IN_MUX_7_CAN1_TT_TR_OUT2 = 0x00000707u, /* canfd[1].tr_tmp_rtp_out[2] */ 736 TRIG_IN_MUX_7_CAN1_TT_TR_OUT3 = 0x00000708u /* canfd[1].tr_tmp_rtp_out[3] */ 737 } en_trig_input_cantt_t; 738 739 /* Trigger Input Group 8 - 2nd level MUX using input from MUX_9/10 */ 740 typedef enum 741 { 742 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT0 = 0x00000801u, /* tr_group[9].output[0] */ 743 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT1 = 0x00000802u, /* tr_group[9].output[1] */ 744 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT2 = 0x00000803u, /* tr_group[9].output[2] */ 745 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT3 = 0x00000804u, /* tr_group[9].output[3] */ 746 TRIG_IN_MUX_8_TR_GROUP9_OUTPUT4 = 0x00000805u, /* tr_group[9].output[4] */ 747 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT0 = 0x00000806u, /* tr_group[10].output[0] */ 748 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT1 = 0x00000807u, /* tr_group[10].output[1] */ 749 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT2 = 0x00000808u, /* tr_group[10].output[2] */ 750 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT3 = 0x00000809u, /* tr_group[10].output[3] */ 751 TRIG_IN_MUX_8_TR_GROUP10_OUTPUT4 = 0x0000080Au /* tr_group[10].output[4] */ 752 } en_trig_input_debugmain_t; 753 754 /* Trigger Input Group 9 - Reduces half of all possible triggers for debug purposes */ 755 typedef enum 756 { 757 TRIG_IN_MUX_9_PDMA0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */ 758 TRIG_IN_MUX_9_PDMA0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */ 759 TRIG_IN_MUX_9_PDMA0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */ 760 TRIG_IN_MUX_9_PDMA0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */ 761 TRIG_IN_MUX_9_PDMA0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */ 762 TRIG_IN_MUX_9_PDMA0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */ 763 TRIG_IN_MUX_9_PDMA0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */ 764 TRIG_IN_MUX_9_PDMA0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */ 765 TRIG_IN_MUX_9_PDMA0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */ 766 TRIG_IN_MUX_9_PDMA0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */ 767 TRIG_IN_MUX_9_PDMA0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */ 768 TRIG_IN_MUX_9_PDMA0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */ 769 TRIG_IN_MUX_9_PDMA0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */ 770 TRIG_IN_MUX_9_PDMA0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */ 771 TRIG_IN_MUX_9_PDMA0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */ 772 TRIG_IN_MUX_9_PDMA0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */ 773 TRIG_IN_MUX_9_PDMA0_TR_OUT16 = 0x00000911u, /* cpuss.dw0_tr_out[16] */ 774 TRIG_IN_MUX_9_PDMA0_TR_OUT17 = 0x00000912u, /* cpuss.dw0_tr_out[17] */ 775 TRIG_IN_MUX_9_PDMA0_TR_OUT18 = 0x00000913u, /* cpuss.dw0_tr_out[18] */ 776 TRIG_IN_MUX_9_PDMA0_TR_OUT19 = 0x00000914u, /* cpuss.dw0_tr_out[19] */ 777 TRIG_IN_MUX_9_PDMA0_TR_OUT20 = 0x00000915u, /* cpuss.dw0_tr_out[20] */ 778 TRIG_IN_MUX_9_PDMA0_TR_OUT21 = 0x00000916u, /* cpuss.dw0_tr_out[21] */ 779 TRIG_IN_MUX_9_PDMA0_TR_OUT22 = 0x00000917u, /* cpuss.dw0_tr_out[22] */ 780 TRIG_IN_MUX_9_PDMA0_TR_OUT23 = 0x00000918u, /* cpuss.dw0_tr_out[23] */ 781 TRIG_IN_MUX_9_PDMA0_TR_OUT24 = 0x00000919u, /* cpuss.dw0_tr_out[24] */ 782 TRIG_IN_MUX_9_PDMA0_TR_OUT25 = 0x0000091Au, /* cpuss.dw0_tr_out[25] */ 783 TRIG_IN_MUX_9_PDMA0_TR_OUT26 = 0x0000091Bu, /* cpuss.dw0_tr_out[26] */ 784 TRIG_IN_MUX_9_PDMA0_TR_OUT27 = 0x0000091Cu, /* cpuss.dw0_tr_out[27] */ 785 TRIG_IN_MUX_9_PDMA0_TR_OUT28 = 0x0000091Du, /* cpuss.dw0_tr_out[28] */ 786 TRIG_IN_MUX_9_PDMA0_TR_OUT29 = 0x0000091Eu, /* cpuss.dw0_tr_out[29] */ 787 TRIG_IN_MUX_9_PDMA0_TR_OUT30 = 0x0000091Fu, /* cpuss.dw0_tr_out[30] */ 788 TRIG_IN_MUX_9_PDMA0_TR_OUT31 = 0x00000920u, /* cpuss.dw0_tr_out[31] */ 789 TRIG_IN_MUX_9_PDMA0_TR_OUT32 = 0x00000921u, /* cpuss.dw0_tr_out[32] */ 790 TRIG_IN_MUX_9_PDMA0_TR_OUT33 = 0x00000922u, /* cpuss.dw0_tr_out[33] */ 791 TRIG_IN_MUX_9_PDMA0_TR_OUT34 = 0x00000923u, /* cpuss.dw0_tr_out[34] */ 792 TRIG_IN_MUX_9_PDMA0_TR_OUT35 = 0x00000924u, /* cpuss.dw0_tr_out[35] */ 793 TRIG_IN_MUX_9_PDMA0_TR_OUT36 = 0x00000925u, /* cpuss.dw0_tr_out[36] */ 794 TRIG_IN_MUX_9_PDMA0_TR_OUT37 = 0x00000926u, /* cpuss.dw0_tr_out[37] */ 795 TRIG_IN_MUX_9_PDMA0_TR_OUT38 = 0x00000927u, /* cpuss.dw0_tr_out[38] */ 796 TRIG_IN_MUX_9_PDMA0_TR_OUT39 = 0x00000928u, /* cpuss.dw0_tr_out[39] */ 797 TRIG_IN_MUX_9_PDMA0_TR_OUT40 = 0x00000929u, /* cpuss.dw0_tr_out[40] */ 798 TRIG_IN_MUX_9_PDMA0_TR_OUT41 = 0x0000092Au, /* cpuss.dw0_tr_out[41] */ 799 TRIG_IN_MUX_9_PDMA0_TR_OUT42 = 0x0000092Bu, /* cpuss.dw0_tr_out[42] */ 800 TRIG_IN_MUX_9_PDMA0_TR_OUT43 = 0x0000092Cu, /* cpuss.dw0_tr_out[43] */ 801 TRIG_IN_MUX_9_PDMA0_TR_OUT44 = 0x0000092Du, /* cpuss.dw0_tr_out[44] */ 802 TRIG_IN_MUX_9_PDMA0_TR_OUT45 = 0x0000092Eu, /* cpuss.dw0_tr_out[45] */ 803 TRIG_IN_MUX_9_PDMA0_TR_OUT46 = 0x0000092Fu, /* cpuss.dw0_tr_out[46] */ 804 TRIG_IN_MUX_9_PDMA0_TR_OUT47 = 0x00000930u, /* cpuss.dw0_tr_out[47] */ 805 TRIG_IN_MUX_9_PDMA0_TR_OUT48 = 0x00000931u, /* cpuss.dw0_tr_out[48] */ 806 TRIG_IN_MUX_9_PDMA0_TR_OUT49 = 0x00000932u, /* cpuss.dw0_tr_out[49] */ 807 TRIG_IN_MUX_9_PDMA0_TR_OUT50 = 0x00000933u, /* cpuss.dw0_tr_out[50] */ 808 TRIG_IN_MUX_9_PDMA0_TR_OUT51 = 0x00000934u, /* cpuss.dw0_tr_out[51] */ 809 TRIG_IN_MUX_9_PDMA0_TR_OUT52 = 0x00000935u, /* cpuss.dw0_tr_out[52] */ 810 TRIG_IN_MUX_9_PDMA0_TR_OUT53 = 0x00000936u, /* cpuss.dw0_tr_out[53] */ 811 TRIG_IN_MUX_9_PDMA0_TR_OUT54 = 0x00000937u, /* cpuss.dw0_tr_out[54] */ 812 TRIG_IN_MUX_9_PDMA0_TR_OUT55 = 0x00000938u, /* cpuss.dw0_tr_out[55] */ 813 TRIG_IN_MUX_9_PDMA0_TR_OUT56 = 0x00000939u, /* cpuss.dw0_tr_out[56] */ 814 TRIG_IN_MUX_9_PDMA0_TR_OUT57 = 0x0000093Au, /* cpuss.dw0_tr_out[57] */ 815 TRIG_IN_MUX_9_PDMA0_TR_OUT58 = 0x0000093Bu, /* cpuss.dw0_tr_out[58] */ 816 TRIG_IN_MUX_9_PDMA0_TR_OUT59 = 0x0000093Cu, /* cpuss.dw0_tr_out[59] */ 817 TRIG_IN_MUX_9_PDMA0_TR_OUT60 = 0x0000093Du, /* cpuss.dw0_tr_out[60] */ 818 TRIG_IN_MUX_9_PDMA0_TR_OUT61 = 0x0000093Eu, /* cpuss.dw0_tr_out[61] */ 819 TRIG_IN_MUX_9_PDMA0_TR_OUT62 = 0x0000093Fu, /* cpuss.dw0_tr_out[62] */ 820 TRIG_IN_MUX_9_PDMA0_TR_OUT63 = 0x00000940u, /* cpuss.dw0_tr_out[63] */ 821 TRIG_IN_MUX_9_PDMA0_TR_OUT64 = 0x00000941u, /* cpuss.dw0_tr_out[64] */ 822 TRIG_IN_MUX_9_PDMA0_TR_OUT65 = 0x00000942u, /* cpuss.dw0_tr_out[65] */ 823 TRIG_IN_MUX_9_PDMA0_TR_OUT66 = 0x00000943u, /* cpuss.dw0_tr_out[66] */ 824 TRIG_IN_MUX_9_PDMA0_TR_OUT67 = 0x00000944u, /* cpuss.dw0_tr_out[67] */ 825 TRIG_IN_MUX_9_PDMA0_TR_OUT68 = 0x00000945u, /* cpuss.dw0_tr_out[68] */ 826 TRIG_IN_MUX_9_PDMA0_TR_OUT69 = 0x00000946u, /* cpuss.dw0_tr_out[69] */ 827 TRIG_IN_MUX_9_PDMA0_TR_OUT70 = 0x00000947u, /* cpuss.dw0_tr_out[70] */ 828 TRIG_IN_MUX_9_PDMA0_TR_OUT71 = 0x00000948u, /* cpuss.dw0_tr_out[71] */ 829 TRIG_IN_MUX_9_PDMA0_TR_OUT72 = 0x00000949u, /* cpuss.dw0_tr_out[72] */ 830 TRIG_IN_MUX_9_PDMA0_TR_OUT73 = 0x0000094Au, /* cpuss.dw0_tr_out[73] */ 831 TRIG_IN_MUX_9_PDMA0_TR_OUT74 = 0x0000094Bu, /* cpuss.dw0_tr_out[74] */ 832 TRIG_IN_MUX_9_PDMA0_TR_OUT75 = 0x0000094Cu, /* cpuss.dw0_tr_out[75] */ 833 TRIG_IN_MUX_9_PDMA0_TR_OUT76 = 0x0000094Du, /* cpuss.dw0_tr_out[76] */ 834 TRIG_IN_MUX_9_PDMA0_TR_OUT77 = 0x0000094Eu, /* cpuss.dw0_tr_out[77] */ 835 TRIG_IN_MUX_9_PDMA0_TR_OUT78 = 0x0000094Fu, /* cpuss.dw0_tr_out[78] */ 836 TRIG_IN_MUX_9_PDMA0_TR_OUT79 = 0x00000950u, /* cpuss.dw0_tr_out[79] */ 837 TRIG_IN_MUX_9_PDMA0_TR_OUT80 = 0x00000951u, /* cpuss.dw0_tr_out[80] */ 838 TRIG_IN_MUX_9_PDMA0_TR_OUT81 = 0x00000952u, /* cpuss.dw0_tr_out[81] */ 839 TRIG_IN_MUX_9_PDMA0_TR_OUT82 = 0x00000953u, /* cpuss.dw0_tr_out[82] */ 840 TRIG_IN_MUX_9_PDMA0_TR_OUT83 = 0x00000954u, /* cpuss.dw0_tr_out[83] */ 841 TRIG_IN_MUX_9_PDMA0_TR_OUT84 = 0x00000955u, /* cpuss.dw0_tr_out[84] */ 842 TRIG_IN_MUX_9_PDMA0_TR_OUT85 = 0x00000956u, /* cpuss.dw0_tr_out[85] */ 843 TRIG_IN_MUX_9_PDMA0_TR_OUT86 = 0x00000957u, /* cpuss.dw0_tr_out[86] */ 844 TRIG_IN_MUX_9_PDMA0_TR_OUT87 = 0x00000958u, /* cpuss.dw0_tr_out[87] */ 845 TRIG_IN_MUX_9_PDMA0_TR_OUT88 = 0x00000959u, /* cpuss.dw0_tr_out[88] */ 846 TRIG_IN_MUX_9_PDMA0_TR_OUT89 = 0x0000095Au, /* cpuss.dw0_tr_out[89] */ 847 TRIG_IN_MUX_9_PDMA0_TR_OUT90 = 0x0000095Bu, /* cpuss.dw0_tr_out[90] */ 848 TRIG_IN_MUX_9_PDMA0_TR_OUT91 = 0x0000095Cu, /* cpuss.dw0_tr_out[91] */ 849 TRIG_IN_MUX_9_SCB_TX_TR_OUT0 = 0x0000095Du, /* scb[0].tr_tx_req */ 850 TRIG_IN_MUX_9_SCB_TX_TR_OUT1 = 0x0000095Eu, /* scb[1].tr_tx_req */ 851 TRIG_IN_MUX_9_SCB_TX_TR_OUT2 = 0x0000095Fu, /* scb[2].tr_tx_req */ 852 TRIG_IN_MUX_9_SCB_TX_TR_OUT3 = 0x00000960u, /* scb[3].tr_tx_req */ 853 TRIG_IN_MUX_9_SCB_TX_TR_OUT4 = 0x00000961u, /* scb[4].tr_tx_req */ 854 TRIG_IN_MUX_9_SCB_TX_TR_OUT5 = 0x00000962u, /* scb[5].tr_tx_req */ 855 TRIG_IN_MUX_9_SCB_TX_TR_OUT6 = 0x00000963u, /* scb[6].tr_tx_req */ 856 TRIG_IN_MUX_9_SCB_TX_TR_OUT7 = 0x00000964u, /* scb[7].tr_tx_req */ 857 TRIG_IN_MUX_9_SCB_RX_TR_OUT0 = 0x00000965u, /* scb[0].tr_rx_req */ 858 TRIG_IN_MUX_9_SCB_RX_TR_OUT1 = 0x00000966u, /* scb[1].tr_rx_req */ 859 TRIG_IN_MUX_9_SCB_RX_TR_OUT2 = 0x00000967u, /* scb[2].tr_rx_req */ 860 TRIG_IN_MUX_9_SCB_RX_TR_OUT3 = 0x00000968u, /* scb[3].tr_rx_req */ 861 TRIG_IN_MUX_9_SCB_RX_TR_OUT4 = 0x00000969u, /* scb[4].tr_rx_req */ 862 TRIG_IN_MUX_9_SCB_RX_TR_OUT5 = 0x0000096Au, /* scb[5].tr_rx_req */ 863 TRIG_IN_MUX_9_SCB_RX_TR_OUT6 = 0x0000096Bu, /* scb[6].tr_rx_req */ 864 TRIG_IN_MUX_9_SCB_RX_TR_OUT7 = 0x0000096Cu, /* scb[7].tr_rx_req */ 865 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT0 = 0x0000096Du, /* scb[0].tr_i2c_scl_filtered */ 866 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT1 = 0x0000096Eu, /* scb[1].tr_i2c_scl_filtered */ 867 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT2 = 0x0000096Fu, /* scb[2].tr_i2c_scl_filtered */ 868 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT3 = 0x00000970u, /* scb[3].tr_i2c_scl_filtered */ 869 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT4 = 0x00000971u, /* scb[4].tr_i2c_scl_filtered */ 870 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT5 = 0x00000972u, /* scb[5].tr_i2c_scl_filtered */ 871 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT6 = 0x00000973u, /* scb[6].tr_i2c_scl_filtered */ 872 TRIG_IN_MUX_9_SCB_I2C_SCL_TR_OUT7 = 0x00000974u, /* scb[7].tr_i2c_scl_filtered */ 873 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT0 = 0x00000975u, /* canfd[0].tr_dbg_dma_req[0] */ 874 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT1 = 0x00000976u, /* canfd[0].tr_dbg_dma_req[1] */ 875 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT2 = 0x00000977u, /* canfd[0].tr_dbg_dma_req[2] */ 876 TRIG_IN_MUX_9_CAN0_DBG_TR_OUT3 = 0x00000978u, /* canfd[0].tr_dbg_dma_req[3] */ 877 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT0 = 0x00000979u, /* canfd[0].tr_fifo0[0] */ 878 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT1 = 0x0000097Au, /* canfd[0].tr_fifo0[1] */ 879 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT2 = 0x0000097Bu, /* canfd[0].tr_fifo0[2] */ 880 TRIG_IN_MUX_9_CAN0_FIFO0_TR_OUT3 = 0x0000097Cu, /* canfd[0].tr_fifo0[3] */ 881 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT0 = 0x0000097Du, /* canfd[0].tr_fifo1[0] */ 882 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT1 = 0x0000097Eu, /* canfd[0].tr_fifo1[1] */ 883 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT2 = 0x0000097Fu, /* canfd[0].tr_fifo1[2] */ 884 TRIG_IN_MUX_9_CAN0_FIFO1_TR_OUT3 = 0x00000980u, /* canfd[0].tr_fifo1[3] */ 885 TRIG_IN_MUX_9_CAN0_TT_TR_OUT0 = 0x00000981u, /* canfd[0].tr_tmp_rtp_out[0] */ 886 TRIG_IN_MUX_9_CAN0_TT_TR_OUT1 = 0x00000982u, /* canfd[0].tr_tmp_rtp_out[1] */ 887 TRIG_IN_MUX_9_CAN0_TT_TR_OUT2 = 0x00000983u, /* canfd[0].tr_tmp_rtp_out[2] */ 888 TRIG_IN_MUX_9_CAN0_TT_TR_OUT3 = 0x00000984u, /* canfd[0].tr_tmp_rtp_out[3] */ 889 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT0 = 0x00000985u, /* canfd[1].tr_dbg_dma_req[0] */ 890 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT1 = 0x00000986u, /* canfd[1].tr_dbg_dma_req[1] */ 891 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT2 = 0x00000987u, /* canfd[1].tr_dbg_dma_req[2] */ 892 TRIG_IN_MUX_9_CAN1_DBG_TR_OUT3 = 0x00000988u, /* canfd[1].tr_dbg_dma_req[3] */ 893 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT0 = 0x00000989u, /* canfd[1].tr_fifo0[0] */ 894 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT1 = 0x0000098Au, /* canfd[1].tr_fifo0[1] */ 895 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT2 = 0x0000098Bu, /* canfd[1].tr_fifo0[2] */ 896 TRIG_IN_MUX_9_CAN1_FIFO0_TR_OUT3 = 0x0000098Cu, /* canfd[1].tr_fifo0[3] */ 897 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT0 = 0x0000098Du, /* canfd[1].tr_fifo1[0] */ 898 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT1 = 0x0000098Eu, /* canfd[1].tr_fifo1[1] */ 899 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT2 = 0x0000098Fu, /* canfd[1].tr_fifo1[2] */ 900 TRIG_IN_MUX_9_CAN1_FIFO1_TR_OUT3 = 0x00000990u, /* canfd[1].tr_fifo1[3] */ 901 TRIG_IN_MUX_9_CAN1_TT_TR_OUT0 = 0x00000991u, /* canfd[1].tr_tmp_rtp_out[0] */ 902 TRIG_IN_MUX_9_CAN1_TT_TR_OUT1 = 0x00000992u, /* canfd[1].tr_tmp_rtp_out[1] */ 903 TRIG_IN_MUX_9_CAN1_TT_TR_OUT2 = 0x00000993u, /* canfd[1].tr_tmp_rtp_out[2] */ 904 TRIG_IN_MUX_9_CAN1_TT_TR_OUT3 = 0x00000994u, /* canfd[1].tr_tmp_rtp_out[3] */ 905 TRIG_IN_MUX_9_CTI_TR_OUT0 = 0x00000995u, /* cpuss.cti_tr_out[0] */ 906 TRIG_IN_MUX_9_CTI_TR_OUT1 = 0x00000996u, /* cpuss.cti_tr_out[1] */ 907 TRIG_IN_MUX_9_FAULT_TR_OUT0 = 0x00000997u, /* cpuss.tr_fault[0] */ 908 TRIG_IN_MUX_9_FAULT_TR_OUT1 = 0x00000998u, /* cpuss.tr_fault[1] */ 909 TRIG_IN_MUX_9_FAULT_TR_OUT2 = 0x00000999u, /* cpuss.tr_fault[2] */ 910 TRIG_IN_MUX_9_FAULT_TR_OUT3 = 0x0000099Au, /* cpuss.tr_fault[3] */ 911 TRIG_IN_MUX_9_TCPWM_32_TR_OUT00 = 0x0000099Bu, /* tcpwm[0].tr_out0[512] */ 912 TRIG_IN_MUX_9_TCPWM_32_TR_OUT01 = 0x0000099Cu, /* tcpwm[0].tr_out0[513] */ 913 TRIG_IN_MUX_9_TCPWM_32_TR_OUT02 = 0x0000099Du, /* tcpwm[0].tr_out0[514] */ 914 TRIG_IN_MUX_9_TCPWM_32_TR_OUT03 = 0x0000099Eu, /* tcpwm[0].tr_out0[515] */ 915 TRIG_IN_MUX_9_TCPWM_32_TR_OUT04 = 0x0000099Fu, /* tcpwm[0].tr_out0[516] */ 916 TRIG_IN_MUX_9_TCPWM_32_TR_OUT05 = 0x000009A0u, /* tcpwm[0].tr_out0[517] */ 917 TRIG_IN_MUX_9_TCPWM_32_TR_OUT06 = 0x000009A1u, /* tcpwm[0].tr_out0[518] */ 918 TRIG_IN_MUX_9_TCPWM_32_TR_OUT07 = 0x000009A2u, /* tcpwm[0].tr_out0[519] */ 919 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT00 = 0x000009A3u, /* tcpwm[0].tr_out0[256] */ 920 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT01 = 0x000009A4u, /* tcpwm[0].tr_out0[257] */ 921 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT02 = 0x000009A5u, /* tcpwm[0].tr_out0[258] */ 922 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT03 = 0x000009A6u, /* tcpwm[0].tr_out0[259] */ 923 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT04 = 0x000009A7u, /* tcpwm[0].tr_out0[260] */ 924 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT05 = 0x000009A8u, /* tcpwm[0].tr_out0[261] */ 925 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT06 = 0x000009A9u, /* tcpwm[0].tr_out0[262] */ 926 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT07 = 0x000009AAu, /* tcpwm[0].tr_out0[263] */ 927 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT08 = 0x000009ABu, /* tcpwm[0].tr_out0[264] */ 928 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT09 = 0x000009ACu, /* tcpwm[0].tr_out0[265] */ 929 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT010 = 0x000009ADu, /* tcpwm[0].tr_out0[266] */ 930 TRIG_IN_MUX_9_TCPWM_16M_TR_OUT011 = 0x000009AEu, /* tcpwm[0].tr_out0[267] */ 931 TRIG_IN_MUX_9_TCPWM_16_TR_OUT00 = 0x000009AFu, /* tcpwm[0].tr_out0[0] */ 932 TRIG_IN_MUX_9_TCPWM_16_TR_OUT01 = 0x000009B0u, /* tcpwm[0].tr_out0[1] */ 933 TRIG_IN_MUX_9_TCPWM_16_TR_OUT02 = 0x000009B1u, /* tcpwm[0].tr_out0[2] */ 934 TRIG_IN_MUX_9_TCPWM_16_TR_OUT03 = 0x000009B2u, /* tcpwm[0].tr_out0[3] */ 935 TRIG_IN_MUX_9_TCPWM_16_TR_OUT04 = 0x000009B3u, /* tcpwm[0].tr_out0[4] */ 936 TRIG_IN_MUX_9_TCPWM_16_TR_OUT05 = 0x000009B4u, /* tcpwm[0].tr_out0[5] */ 937 TRIG_IN_MUX_9_TCPWM_16_TR_OUT06 = 0x000009B5u, /* tcpwm[0].tr_out0[6] */ 938 TRIG_IN_MUX_9_TCPWM_16_TR_OUT07 = 0x000009B6u, /* tcpwm[0].tr_out0[7] */ 939 TRIG_IN_MUX_9_TCPWM_16_TR_OUT08 = 0x000009B7u, /* tcpwm[0].tr_out0[8] */ 940 TRIG_IN_MUX_9_TCPWM_16_TR_OUT09 = 0x000009B8u, /* tcpwm[0].tr_out0[9] */ 941 TRIG_IN_MUX_9_TCPWM_16_TR_OUT010 = 0x000009B9u, /* tcpwm[0].tr_out0[10] */ 942 TRIG_IN_MUX_9_TCPWM_16_TR_OUT011 = 0x000009BAu, /* tcpwm[0].tr_out0[11] */ 943 TRIG_IN_MUX_9_TCPWM_16_TR_OUT012 = 0x000009BBu, /* tcpwm[0].tr_out0[12] */ 944 TRIG_IN_MUX_9_TCPWM_16_TR_OUT013 = 0x000009BCu, /* tcpwm[0].tr_out0[13] */ 945 TRIG_IN_MUX_9_TCPWM_16_TR_OUT014 = 0x000009BDu, /* tcpwm[0].tr_out0[14] */ 946 TRIG_IN_MUX_9_TCPWM_16_TR_OUT015 = 0x000009BEu, /* tcpwm[0].tr_out0[15] */ 947 TRIG_IN_MUX_9_TCPWM_16_TR_OUT016 = 0x000009BFu, /* tcpwm[0].tr_out0[16] */ 948 TRIG_IN_MUX_9_TCPWM_16_TR_OUT017 = 0x000009C0u, /* tcpwm[0].tr_out0[17] */ 949 TRIG_IN_MUX_9_TCPWM_16_TR_OUT018 = 0x000009C1u, /* tcpwm[0].tr_out0[18] */ 950 TRIG_IN_MUX_9_TCPWM_16_TR_OUT019 = 0x000009C2u, /* tcpwm[0].tr_out0[19] */ 951 TRIG_IN_MUX_9_TCPWM_16_TR_OUT020 = 0x000009C3u, /* tcpwm[0].tr_out0[20] */ 952 TRIG_IN_MUX_9_TCPWM_16_TR_OUT021 = 0x000009C4u, /* tcpwm[0].tr_out0[21] */ 953 TRIG_IN_MUX_9_TCPWM_16_TR_OUT022 = 0x000009C5u, /* tcpwm[0].tr_out0[22] */ 954 TRIG_IN_MUX_9_TCPWM_16_TR_OUT023 = 0x000009C6u, /* tcpwm[0].tr_out0[23] */ 955 TRIG_IN_MUX_9_TCPWM_16_TR_OUT024 = 0x000009C7u, /* tcpwm[0].tr_out0[24] */ 956 TRIG_IN_MUX_9_TCPWM_16_TR_OUT025 = 0x000009C8u, /* tcpwm[0].tr_out0[25] */ 957 TRIG_IN_MUX_9_TCPWM_16_TR_OUT026 = 0x000009C9u, /* tcpwm[0].tr_out0[26] */ 958 TRIG_IN_MUX_9_TCPWM_16_TR_OUT027 = 0x000009CAu, /* tcpwm[0].tr_out0[27] */ 959 TRIG_IN_MUX_9_TCPWM_16_TR_OUT028 = 0x000009CBu, /* tcpwm[0].tr_out0[28] */ 960 TRIG_IN_MUX_9_TCPWM_16_TR_OUT029 = 0x000009CCu, /* tcpwm[0].tr_out0[29] */ 961 TRIG_IN_MUX_9_TCPWM_16_TR_OUT030 = 0x000009CDu, /* tcpwm[0].tr_out0[30] */ 962 TRIG_IN_MUX_9_TCPWM_16_TR_OUT031 = 0x000009CEu, /* tcpwm[0].tr_out0[31] */ 963 TRIG_IN_MUX_9_TCPWM_16_TR_OUT032 = 0x000009CFu, /* tcpwm[0].tr_out0[32] */ 964 TRIG_IN_MUX_9_TCPWM_16_TR_OUT033 = 0x000009D0u, /* tcpwm[0].tr_out0[33] */ 965 TRIG_IN_MUX_9_TCPWM_16_TR_OUT034 = 0x000009D1u, /* tcpwm[0].tr_out0[34] */ 966 TRIG_IN_MUX_9_TCPWM_16_TR_OUT035 = 0x000009D2u, /* tcpwm[0].tr_out0[35] */ 967 TRIG_IN_MUX_9_TCPWM_16_TR_OUT036 = 0x000009D3u, /* tcpwm[0].tr_out0[36] */ 968 TRIG_IN_MUX_9_TCPWM_16_TR_OUT037 = 0x000009D4u, /* tcpwm[0].tr_out0[37] */ 969 TRIG_IN_MUX_9_TCPWM_16_TR_OUT038 = 0x000009D5u, /* tcpwm[0].tr_out0[38] */ 970 TRIG_IN_MUX_9_TCPWM_16_TR_OUT039 = 0x000009D6u, /* tcpwm[0].tr_out0[39] */ 971 TRIG_IN_MUX_9_TCPWM_16_TR_OUT040 = 0x000009D7u, /* tcpwm[0].tr_out0[40] */ 972 TRIG_IN_MUX_9_TCPWM_16_TR_OUT041 = 0x000009D8u, /* tcpwm[0].tr_out0[41] */ 973 TRIG_IN_MUX_9_TCPWM_16_TR_OUT042 = 0x000009D9u, /* tcpwm[0].tr_out0[42] */ 974 TRIG_IN_MUX_9_TCPWM_16_TR_OUT043 = 0x000009DAu, /* tcpwm[0].tr_out0[43] */ 975 TRIG_IN_MUX_9_TCPWM_16_TR_OUT044 = 0x000009DBu, /* tcpwm[0].tr_out0[44] */ 976 TRIG_IN_MUX_9_TCPWM_16_TR_OUT045 = 0x000009DCu, /* tcpwm[0].tr_out0[45] */ 977 TRIG_IN_MUX_9_TCPWM_16_TR_OUT046 = 0x000009DDu, /* tcpwm[0].tr_out0[46] */ 978 TRIG_IN_MUX_9_TCPWM_16_TR_OUT047 = 0x000009DEu, /* tcpwm[0].tr_out0[47] */ 979 TRIG_IN_MUX_9_TCPWM_16_TR_OUT048 = 0x000009DFu, /* tcpwm[0].tr_out0[48] */ 980 TRIG_IN_MUX_9_TCPWM_16_TR_OUT049 = 0x000009E0u, /* tcpwm[0].tr_out0[49] */ 981 TRIG_IN_MUX_9_TCPWM_16_TR_OUT050 = 0x000009E1u, /* tcpwm[0].tr_out0[50] */ 982 TRIG_IN_MUX_9_TCPWM_16_TR_OUT051 = 0x000009E2u, /* tcpwm[0].tr_out0[51] */ 983 TRIG_IN_MUX_9_TCPWM_16_TR_OUT052 = 0x000009E3u, /* tcpwm[0].tr_out0[52] */ 984 TRIG_IN_MUX_9_TCPWM_16_TR_OUT053 = 0x000009E4u, /* tcpwm[0].tr_out0[53] */ 985 TRIG_IN_MUX_9_TCPWM_16_TR_OUT054 = 0x000009E5u, /* tcpwm[0].tr_out0[54] */ 986 TRIG_IN_MUX_9_TCPWM_16_TR_OUT055 = 0x000009E6u, /* tcpwm[0].tr_out0[55] */ 987 TRIG_IN_MUX_9_TCPWM_16_TR_OUT056 = 0x000009E7u, /* tcpwm[0].tr_out0[56] */ 988 TRIG_IN_MUX_9_TCPWM_16_TR_OUT057 = 0x000009E8u, /* tcpwm[0].tr_out0[57] */ 989 TRIG_IN_MUX_9_TCPWM_16_TR_OUT058 = 0x000009E9u, /* tcpwm[0].tr_out0[58] */ 990 TRIG_IN_MUX_9_TCPWM_16_TR_OUT059 = 0x000009EAu, /* tcpwm[0].tr_out0[59] */ 991 TRIG_IN_MUX_9_TCPWM_16_TR_OUT060 = 0x000009EBu, /* tcpwm[0].tr_out0[60] */ 992 TRIG_IN_MUX_9_TCPWM_16_TR_OUT061 = 0x000009ECu, /* tcpwm[0].tr_out0[61] */ 993 TRIG_IN_MUX_9_TCPWM_16_TR_OUT062 = 0x000009EDu /* tcpwm[0].tr_out0[62] */ 994 } en_trig_input_debugreduction1_t; 995 996 /* Trigger Input Group 10 - Reduces half of all possible triggers for debug purposes */ 997 typedef enum 998 { 999 TRIG_IN_MUX_10_PDMA1_TR_OUT0 = 0x00000A01u, /* cpuss.dw1_tr_out[0] */ 1000 TRIG_IN_MUX_10_PDMA1_TR_OUT1 = 0x00000A02u, /* cpuss.dw1_tr_out[1] */ 1001 TRIG_IN_MUX_10_PDMA1_TR_OUT2 = 0x00000A03u, /* cpuss.dw1_tr_out[2] */ 1002 TRIG_IN_MUX_10_PDMA1_TR_OUT3 = 0x00000A04u, /* cpuss.dw1_tr_out[3] */ 1003 TRIG_IN_MUX_10_PDMA1_TR_OUT4 = 0x00000A05u, /* cpuss.dw1_tr_out[4] */ 1004 TRIG_IN_MUX_10_PDMA1_TR_OUT5 = 0x00000A06u, /* cpuss.dw1_tr_out[5] */ 1005 TRIG_IN_MUX_10_PDMA1_TR_OUT6 = 0x00000A07u, /* cpuss.dw1_tr_out[6] */ 1006 TRIG_IN_MUX_10_PDMA1_TR_OUT7 = 0x00000A08u, /* cpuss.dw1_tr_out[7] */ 1007 TRIG_IN_MUX_10_PDMA1_TR_OUT8 = 0x00000A09u, /* cpuss.dw1_tr_out[8] */ 1008 TRIG_IN_MUX_10_PDMA1_TR_OUT9 = 0x00000A0Au, /* cpuss.dw1_tr_out[9] */ 1009 TRIG_IN_MUX_10_PDMA1_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw1_tr_out[10] */ 1010 TRIG_IN_MUX_10_PDMA1_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw1_tr_out[11] */ 1011 TRIG_IN_MUX_10_PDMA1_TR_OUT12 = 0x00000A0Du, /* cpuss.dw1_tr_out[12] */ 1012 TRIG_IN_MUX_10_PDMA1_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw1_tr_out[13] */ 1013 TRIG_IN_MUX_10_PDMA1_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw1_tr_out[14] */ 1014 TRIG_IN_MUX_10_PDMA1_TR_OUT15 = 0x00000A10u, /* cpuss.dw1_tr_out[15] */ 1015 TRIG_IN_MUX_10_PDMA1_TR_OUT16 = 0x00000A11u, /* cpuss.dw1_tr_out[16] */ 1016 TRIG_IN_MUX_10_PDMA1_TR_OUT17 = 0x00000A12u, /* cpuss.dw1_tr_out[17] */ 1017 TRIG_IN_MUX_10_PDMA1_TR_OUT18 = 0x00000A13u, /* cpuss.dw1_tr_out[18] */ 1018 TRIG_IN_MUX_10_PDMA1_TR_OUT19 = 0x00000A14u, /* cpuss.dw1_tr_out[19] */ 1019 TRIG_IN_MUX_10_PDMA1_TR_OUT20 = 0x00000A15u, /* cpuss.dw1_tr_out[20] */ 1020 TRIG_IN_MUX_10_PDMA1_TR_OUT21 = 0x00000A16u, /* cpuss.dw1_tr_out[21] */ 1021 TRIG_IN_MUX_10_PDMA1_TR_OUT22 = 0x00000A17u, /* cpuss.dw1_tr_out[22] */ 1022 TRIG_IN_MUX_10_PDMA1_TR_OUT23 = 0x00000A18u, /* cpuss.dw1_tr_out[23] */ 1023 TRIG_IN_MUX_10_PDMA1_TR_OUT24 = 0x00000A19u, /* cpuss.dw1_tr_out[24] */ 1024 TRIG_IN_MUX_10_PDMA1_TR_OUT25 = 0x00000A1Au, /* cpuss.dw1_tr_out[25] */ 1025 TRIG_IN_MUX_10_PDMA1_TR_OUT26 = 0x00000A1Bu, /* cpuss.dw1_tr_out[26] */ 1026 TRIG_IN_MUX_10_PDMA1_TR_OUT27 = 0x00000A1Cu, /* cpuss.dw1_tr_out[27] */ 1027 TRIG_IN_MUX_10_PDMA1_TR_OUT28 = 0x00000A1Du, /* cpuss.dw1_tr_out[28] */ 1028 TRIG_IN_MUX_10_PDMA1_TR_OUT29 = 0x00000A1Eu, /* cpuss.dw1_tr_out[29] */ 1029 TRIG_IN_MUX_10_PDMA1_TR_OUT30 = 0x00000A1Fu, /* cpuss.dw1_tr_out[30] */ 1030 TRIG_IN_MUX_10_PDMA1_TR_OUT31 = 0x00000A20u, /* cpuss.dw1_tr_out[31] */ 1031 TRIG_IN_MUX_10_PDMA1_TR_OUT32 = 0x00000A21u, /* cpuss.dw1_tr_out[32] */ 1032 TRIG_IN_MUX_10_PDMA1_TR_OUT33 = 0x00000A22u, /* cpuss.dw1_tr_out[33] */ 1033 TRIG_IN_MUX_10_PDMA1_TR_OUT34 = 0x00000A23u, /* cpuss.dw1_tr_out[34] */ 1034 TRIG_IN_MUX_10_PDMA1_TR_OUT35 = 0x00000A24u, /* cpuss.dw1_tr_out[35] */ 1035 TRIG_IN_MUX_10_PDMA1_TR_OUT36 = 0x00000A25u, /* cpuss.dw1_tr_out[36] */ 1036 TRIG_IN_MUX_10_PDMA1_TR_OUT37 = 0x00000A26u, /* cpuss.dw1_tr_out[37] */ 1037 TRIG_IN_MUX_10_PDMA1_TR_OUT38 = 0x00000A27u, /* cpuss.dw1_tr_out[38] */ 1038 TRIG_IN_MUX_10_PDMA1_TR_OUT39 = 0x00000A28u, /* cpuss.dw1_tr_out[39] */ 1039 TRIG_IN_MUX_10_PDMA1_TR_OUT40 = 0x00000A29u, /* cpuss.dw1_tr_out[40] */ 1040 TRIG_IN_MUX_10_PDMA1_TR_OUT41 = 0x00000A2Au, /* cpuss.dw1_tr_out[41] */ 1041 TRIG_IN_MUX_10_PDMA1_TR_OUT42 = 0x00000A2Bu, /* cpuss.dw1_tr_out[42] */ 1042 TRIG_IN_MUX_10_PDMA1_TR_OUT43 = 0x00000A2Cu, /* cpuss.dw1_tr_out[43] */ 1043 TRIG_IN_MUX_10_MDMA_TR_OUT0 = 0x00000A2Du, /* cpuss.dmac_tr_out[0] */ 1044 TRIG_IN_MUX_10_MDMA_TR_OUT1 = 0x00000A2Eu, /* cpuss.dmac_tr_out[1] */ 1045 TRIG_IN_MUX_10_MDMA_TR_OUT2 = 0x00000A2Fu, /* cpuss.dmac_tr_out[2] */ 1046 TRIG_IN_MUX_10_MDMA_TR_OUT3 = 0x00000A30u, /* cpuss.dmac_tr_out[3] */ 1047 TRIG_IN_MUX_10_TCPWM_32_TR_OUT10 = 0x00000A31u, /* tcpwm[0].tr_out1[512] */ 1048 TRIG_IN_MUX_10_TCPWM_32_TR_OUT11 = 0x00000A32u, /* tcpwm[0].tr_out1[513] */ 1049 TRIG_IN_MUX_10_TCPWM_32_TR_OUT12 = 0x00000A33u, /* tcpwm[0].tr_out1[514] */ 1050 TRIG_IN_MUX_10_TCPWM_32_TR_OUT13 = 0x00000A34u, /* tcpwm[0].tr_out1[515] */ 1051 TRIG_IN_MUX_10_TCPWM_32_TR_OUT14 = 0x00000A35u, /* tcpwm[0].tr_out1[516] */ 1052 TRIG_IN_MUX_10_TCPWM_32_TR_OUT15 = 0x00000A36u, /* tcpwm[0].tr_out1[517] */ 1053 TRIG_IN_MUX_10_TCPWM_32_TR_OUT16 = 0x00000A37u, /* tcpwm[0].tr_out1[518] */ 1054 TRIG_IN_MUX_10_TCPWM_32_TR_OUT17 = 0x00000A38u, /* tcpwm[0].tr_out1[519] */ 1055 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT10 = 0x00000A39u, /* tcpwm[0].tr_out1[256] */ 1056 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT11 = 0x00000A3Au, /* tcpwm[0].tr_out1[257] */ 1057 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT12 = 0x00000A3Bu, /* tcpwm[0].tr_out1[258] */ 1058 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT13 = 0x00000A3Cu, /* tcpwm[0].tr_out1[259] */ 1059 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT14 = 0x00000A3Du, /* tcpwm[0].tr_out1[260] */ 1060 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT15 = 0x00000A3Eu, /* tcpwm[0].tr_out1[261] */ 1061 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT16 = 0x00000A3Fu, /* tcpwm[0].tr_out1[262] */ 1062 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT17 = 0x00000A40u, /* tcpwm[0].tr_out1[263] */ 1063 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT18 = 0x00000A41u, /* tcpwm[0].tr_out1[264] */ 1064 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT19 = 0x00000A42u, /* tcpwm[0].tr_out1[265] */ 1065 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT110 = 0x00000A43u, /* tcpwm[0].tr_out1[266] */ 1066 TRIG_IN_MUX_10_TCPWM_16M_TR_OUT111 = 0x00000A44u, /* tcpwm[0].tr_out1[267] */ 1067 TRIG_IN_MUX_10_TCPWM_16_TR_OUT10 = 0x00000A45u, /* tcpwm[0].tr_out1[0] */ 1068 TRIG_IN_MUX_10_TCPWM_16_TR_OUT11 = 0x00000A46u, /* tcpwm[0].tr_out1[1] */ 1069 TRIG_IN_MUX_10_TCPWM_16_TR_OUT12 = 0x00000A47u, /* tcpwm[0].tr_out1[2] */ 1070 TRIG_IN_MUX_10_TCPWM_16_TR_OUT13 = 0x00000A48u, /* tcpwm[0].tr_out1[3] */ 1071 TRIG_IN_MUX_10_TCPWM_16_TR_OUT14 = 0x00000A49u, /* tcpwm[0].tr_out1[4] */ 1072 TRIG_IN_MUX_10_TCPWM_16_TR_OUT15 = 0x00000A4Au, /* tcpwm[0].tr_out1[5] */ 1073 TRIG_IN_MUX_10_TCPWM_16_TR_OUT16 = 0x00000A4Bu, /* tcpwm[0].tr_out1[6] */ 1074 TRIG_IN_MUX_10_TCPWM_16_TR_OUT17 = 0x00000A4Cu, /* tcpwm[0].tr_out1[7] */ 1075 TRIG_IN_MUX_10_TCPWM_16_TR_OUT18 = 0x00000A4Du, /* tcpwm[0].tr_out1[8] */ 1076 TRIG_IN_MUX_10_TCPWM_16_TR_OUT19 = 0x00000A4Eu, /* tcpwm[0].tr_out1[9] */ 1077 TRIG_IN_MUX_10_TCPWM_16_TR_OUT110 = 0x00000A4Fu, /* tcpwm[0].tr_out1[10] */ 1078 TRIG_IN_MUX_10_TCPWM_16_TR_OUT111 = 0x00000A50u, /* tcpwm[0].tr_out1[11] */ 1079 TRIG_IN_MUX_10_TCPWM_16_TR_OUT112 = 0x00000A51u, /* tcpwm[0].tr_out1[12] */ 1080 TRIG_IN_MUX_10_TCPWM_16_TR_OUT113 = 0x00000A52u, /* tcpwm[0].tr_out1[13] */ 1081 TRIG_IN_MUX_10_TCPWM_16_TR_OUT114 = 0x00000A53u, /* tcpwm[0].tr_out1[14] */ 1082 TRIG_IN_MUX_10_TCPWM_16_TR_OUT115 = 0x00000A54u, /* tcpwm[0].tr_out1[15] */ 1083 TRIG_IN_MUX_10_TCPWM_16_TR_OUT116 = 0x00000A55u, /* tcpwm[0].tr_out1[16] */ 1084 TRIG_IN_MUX_10_TCPWM_16_TR_OUT117 = 0x00000A56u, /* tcpwm[0].tr_out1[17] */ 1085 TRIG_IN_MUX_10_TCPWM_16_TR_OUT118 = 0x00000A57u, /* tcpwm[0].tr_out1[18] */ 1086 TRIG_IN_MUX_10_TCPWM_16_TR_OUT119 = 0x00000A58u, /* tcpwm[0].tr_out1[19] */ 1087 TRIG_IN_MUX_10_TCPWM_16_TR_OUT120 = 0x00000A59u, /* tcpwm[0].tr_out1[20] */ 1088 TRIG_IN_MUX_10_TCPWM_16_TR_OUT121 = 0x00000A5Au, /* tcpwm[0].tr_out1[21] */ 1089 TRIG_IN_MUX_10_TCPWM_16_TR_OUT122 = 0x00000A5Bu, /* tcpwm[0].tr_out1[22] */ 1090 TRIG_IN_MUX_10_TCPWM_16_TR_OUT123 = 0x00000A5Cu, /* tcpwm[0].tr_out1[23] */ 1091 TRIG_IN_MUX_10_TCPWM_16_TR_OUT124 = 0x00000A5Du, /* tcpwm[0].tr_out1[24] */ 1092 TRIG_IN_MUX_10_TCPWM_16_TR_OUT125 = 0x00000A5Eu, /* tcpwm[0].tr_out1[25] */ 1093 TRIG_IN_MUX_10_TCPWM_16_TR_OUT126 = 0x00000A5Fu, /* tcpwm[0].tr_out1[26] */ 1094 TRIG_IN_MUX_10_TCPWM_16_TR_OUT127 = 0x00000A60u, /* tcpwm[0].tr_out1[27] */ 1095 TRIG_IN_MUX_10_TCPWM_16_TR_OUT128 = 0x00000A61u, /* tcpwm[0].tr_out1[28] */ 1096 TRIG_IN_MUX_10_TCPWM_16_TR_OUT129 = 0x00000A62u, /* tcpwm[0].tr_out1[29] */ 1097 TRIG_IN_MUX_10_TCPWM_16_TR_OUT130 = 0x00000A63u, /* tcpwm[0].tr_out1[30] */ 1098 TRIG_IN_MUX_10_TCPWM_16_TR_OUT131 = 0x00000A64u, /* tcpwm[0].tr_out1[31] */ 1099 TRIG_IN_MUX_10_TCPWM_16_TR_OUT132 = 0x00000A65u, /* tcpwm[0].tr_out1[32] */ 1100 TRIG_IN_MUX_10_TCPWM_16_TR_OUT133 = 0x00000A66u, /* tcpwm[0].tr_out1[33] */ 1101 TRIG_IN_MUX_10_TCPWM_16_TR_OUT134 = 0x00000A67u, /* tcpwm[0].tr_out1[34] */ 1102 TRIG_IN_MUX_10_TCPWM_16_TR_OUT135 = 0x00000A68u, /* tcpwm[0].tr_out1[35] */ 1103 TRIG_IN_MUX_10_TCPWM_16_TR_OUT136 = 0x00000A69u, /* tcpwm[0].tr_out1[36] */ 1104 TRIG_IN_MUX_10_TCPWM_16_TR_OUT137 = 0x00000A6Au, /* tcpwm[0].tr_out1[37] */ 1105 TRIG_IN_MUX_10_TCPWM_16_TR_OUT138 = 0x00000A6Bu, /* tcpwm[0].tr_out1[38] */ 1106 TRIG_IN_MUX_10_TCPWM_16_TR_OUT139 = 0x00000A6Cu, /* tcpwm[0].tr_out1[39] */ 1107 TRIG_IN_MUX_10_TCPWM_16_TR_OUT140 = 0x00000A6Du, /* tcpwm[0].tr_out1[40] */ 1108 TRIG_IN_MUX_10_TCPWM_16_TR_OUT141 = 0x00000A6Eu, /* tcpwm[0].tr_out1[41] */ 1109 TRIG_IN_MUX_10_TCPWM_16_TR_OUT142 = 0x00000A6Fu, /* tcpwm[0].tr_out1[42] */ 1110 TRIG_IN_MUX_10_TCPWM_16_TR_OUT143 = 0x00000A70u, /* tcpwm[0].tr_out1[43] */ 1111 TRIG_IN_MUX_10_TCPWM_16_TR_OUT144 = 0x00000A71u, /* tcpwm[0].tr_out1[44] */ 1112 TRIG_IN_MUX_10_TCPWM_16_TR_OUT145 = 0x00000A72u, /* tcpwm[0].tr_out1[45] */ 1113 TRIG_IN_MUX_10_TCPWM_16_TR_OUT146 = 0x00000A73u, /* tcpwm[0].tr_out1[46] */ 1114 TRIG_IN_MUX_10_TCPWM_16_TR_OUT147 = 0x00000A74u, /* tcpwm[0].tr_out1[47] */ 1115 TRIG_IN_MUX_10_TCPWM_16_TR_OUT148 = 0x00000A75u, /* tcpwm[0].tr_out1[48] */ 1116 TRIG_IN_MUX_10_TCPWM_16_TR_OUT149 = 0x00000A76u, /* tcpwm[0].tr_out1[49] */ 1117 TRIG_IN_MUX_10_TCPWM_16_TR_OUT150 = 0x00000A77u, /* tcpwm[0].tr_out1[50] */ 1118 TRIG_IN_MUX_10_TCPWM_16_TR_OUT151 = 0x00000A78u, /* tcpwm[0].tr_out1[51] */ 1119 TRIG_IN_MUX_10_TCPWM_16_TR_OUT152 = 0x00000A79u, /* tcpwm[0].tr_out1[52] */ 1120 TRIG_IN_MUX_10_TCPWM_16_TR_OUT153 = 0x00000A7Au, /* tcpwm[0].tr_out1[53] */ 1121 TRIG_IN_MUX_10_TCPWM_16_TR_OUT154 = 0x00000A7Bu, /* tcpwm[0].tr_out1[54] */ 1122 TRIG_IN_MUX_10_TCPWM_16_TR_OUT155 = 0x00000A7Cu, /* tcpwm[0].tr_out1[55] */ 1123 TRIG_IN_MUX_10_TCPWM_16_TR_OUT156 = 0x00000A7Du, /* tcpwm[0].tr_out1[56] */ 1124 TRIG_IN_MUX_10_TCPWM_16_TR_OUT157 = 0x00000A7Eu, /* tcpwm[0].tr_out1[57] */ 1125 TRIG_IN_MUX_10_TCPWM_16_TR_OUT158 = 0x00000A7Fu, /* tcpwm[0].tr_out1[58] */ 1126 TRIG_IN_MUX_10_TCPWM_16_TR_OUT159 = 0x00000A80u, /* tcpwm[0].tr_out1[59] */ 1127 TRIG_IN_MUX_10_TCPWM_16_TR_OUT160 = 0x00000A81u, /* tcpwm[0].tr_out1[60] */ 1128 TRIG_IN_MUX_10_TCPWM_16_TR_OUT161 = 0x00000A82u, /* tcpwm[0].tr_out1[61] */ 1129 TRIG_IN_MUX_10_TCPWM_16_TR_OUT162 = 0x00000A83u, /* tcpwm[0].tr_out1[62] */ 1130 TRIG_IN_MUX_10_PASS_GEN_TR_OUT0 = 0x00000A84u, /* pass[0].tr_sar_gen_out[0] */ 1131 TRIG_IN_MUX_10_PASS_GEN_TR_OUT1 = 0x00000A85u, /* pass[0].tr_sar_gen_out[1] */ 1132 TRIG_IN_MUX_10_PASS_GEN_TR_OUT2 = 0x00000A86u, /* pass[0].tr_sar_gen_out[2] */ 1133 TRIG_IN_MUX_10_PASS_GEN_TR_OUT3 = 0x00000A87u, /* pass[0].tr_sar_gen_out[3] */ 1134 TRIG_IN_MUX_10_PASS_GEN_TR_OUT4 = 0x00000A88u, /* pass[0].tr_sar_gen_out[4] */ 1135 TRIG_IN_MUX_10_PASS_GEN_TR_OUT5 = 0x00000A89u, /* pass[0].tr_sar_gen_out[5] */ 1136 TRIG_IN_MUX_10_EVTGEN_TR_OUT0 = 0x00000A8Au, /* evtgen[0].tr_out[0] */ 1137 TRIG_IN_MUX_10_EVTGEN_TR_OUT1 = 0x00000A8Bu, /* evtgen[0].tr_out[1] */ 1138 TRIG_IN_MUX_10_EVTGEN_TR_OUT2 = 0x00000A8Cu, /* evtgen[0].tr_out[2] */ 1139 TRIG_IN_MUX_10_EVTGEN_TR_OUT3 = 0x00000A8Du, /* evtgen[0].tr_out[3] */ 1140 TRIG_IN_MUX_10_EVTGEN_TR_OUT4 = 0x00000A8Eu, /* evtgen[0].tr_out[4] */ 1141 TRIG_IN_MUX_10_EVTGEN_TR_OUT5 = 0x00000A8Fu, /* evtgen[0].tr_out[5] */ 1142 TRIG_IN_MUX_10_EVTGEN_TR_OUT6 = 0x00000A90u, /* evtgen[0].tr_out[6] */ 1143 TRIG_IN_MUX_10_EVTGEN_TR_OUT7 = 0x00000A91u, /* evtgen[0].tr_out[7] */ 1144 TRIG_IN_MUX_10_EVTGEN_TR_OUT8 = 0x00000A92u, /* evtgen[0].tr_out[8] */ 1145 TRIG_IN_MUX_10_EVTGEN_TR_OUT9 = 0x00000A93u, /* evtgen[0].tr_out[9] */ 1146 TRIG_IN_MUX_10_EVTGEN_TR_OUT10 = 0x00000A94u, /* evtgen[0].tr_out[10] */ 1147 TRIG_IN_MUX_10_CXPI_TX_TR_OUT0 = 0x00000A95u, /* cxpi[0].tr_tx_req[0] */ 1148 TRIG_IN_MUX_10_CXPI_TX_TR_OUT1 = 0x00000A96u, /* cxpi[0].tr_tx_req[1] */ 1149 TRIG_IN_MUX_10_CXPI_TX_TR_OUT2 = 0x00000A97u, /* cxpi[0].tr_tx_req[2] */ 1150 TRIG_IN_MUX_10_CXPI_TX_TR_OUT3 = 0x00000A98u, /* cxpi[0].tr_tx_req[3] */ 1151 TRIG_IN_MUX_10_CXPI_RX_TR_OUT0 = 0x00000A99u, /* cxpi[0].tr_rx_req[0] */ 1152 TRIG_IN_MUX_10_CXPI_RX_TR_OUT1 = 0x00000A9Au, /* cxpi[0].tr_rx_req[1] */ 1153 TRIG_IN_MUX_10_CXPI_RX_TR_OUT2 = 0x00000A9Bu, /* cxpi[0].tr_rx_req[2] */ 1154 TRIG_IN_MUX_10_CXPI_RX_TR_OUT3 = 0x00000A9Cu, /* cxpi[0].tr_rx_req[3] */ 1155 TRIG_IN_MUX_10_HSIOM_IO_INPUT0 = 0x00000A9Du, /* peri.tr_io_input[0] */ 1156 TRIG_IN_MUX_10_HSIOM_IO_INPUT1 = 0x00000A9Eu, /* peri.tr_io_input[1] */ 1157 TRIG_IN_MUX_10_HSIOM_IO_INPUT2 = 0x00000A9Fu, /* peri.tr_io_input[2] */ 1158 TRIG_IN_MUX_10_HSIOM_IO_INPUT3 = 0x00000AA0u, /* peri.tr_io_input[3] */ 1159 TRIG_IN_MUX_10_HSIOM_IO_INPUT4 = 0x00000AA1u, /* peri.tr_io_input[4] */ 1160 TRIG_IN_MUX_10_HSIOM_IO_INPUT5 = 0x00000AA2u, /* peri.tr_io_input[5] */ 1161 TRIG_IN_MUX_10_HSIOM_IO_INPUT6 = 0x00000AA3u, /* peri.tr_io_input[6] */ 1162 TRIG_IN_MUX_10_HSIOM_IO_INPUT7 = 0x00000AA4u, /* peri.tr_io_input[7] */ 1163 TRIG_IN_MUX_10_HSIOM_IO_INPUT8 = 0x00000AA5u, /* peri.tr_io_input[8] */ 1164 TRIG_IN_MUX_10_HSIOM_IO_INPUT9 = 0x00000AA6u, /* peri.tr_io_input[9] */ 1165 TRIG_IN_MUX_10_HSIOM_IO_INPUT10 = 0x00000AA7u, /* peri.tr_io_input[10] */ 1166 TRIG_IN_MUX_10_HSIOM_IO_INPUT11 = 0x00000AA8u, /* peri.tr_io_input[11] */ 1167 TRIG_IN_MUX_10_HSIOM_IO_INPUT12 = 0x00000AA9u, /* peri.tr_io_input[12] */ 1168 TRIG_IN_MUX_10_HSIOM_IO_INPUT13 = 0x00000AAAu, /* peri.tr_io_input[13] */ 1169 TRIG_IN_MUX_10_HSIOM_IO_INPUT14 = 0x00000AABu, /* peri.tr_io_input[14] */ 1170 TRIG_IN_MUX_10_HSIOM_IO_INPUT15 = 0x00000AACu, /* peri.tr_io_input[15] */ 1171 TRIG_IN_MUX_10_HSIOM_IO_INPUT16 = 0x00000AADu, /* peri.tr_io_input[16] */ 1172 TRIG_IN_MUX_10_HSIOM_IO_INPUT17 = 0x00000AAEu, /* peri.tr_io_input[17] */ 1173 TRIG_IN_MUX_10_HSIOM_IO_INPUT18 = 0x00000AAFu, /* peri.tr_io_input[18] */ 1174 TRIG_IN_MUX_10_HSIOM_IO_INPUT19 = 0x00000AB0u, /* peri.tr_io_input[19] */ 1175 TRIG_IN_MUX_10_HSIOM_IO_INPUT20 = 0x00000AB1u, /* peri.tr_io_input[20] */ 1176 TRIG_IN_MUX_10_HSIOM_IO_INPUT21 = 0x00000AB2u, /* peri.tr_io_input[21] */ 1177 TRIG_IN_MUX_10_HSIOM_IO_INPUT22 = 0x00000AB3u, /* peri.tr_io_input[22] */ 1178 TRIG_IN_MUX_10_HSIOM_IO_INPUT23 = 0x00000AB4u, /* peri.tr_io_input[23] */ 1179 TRIG_IN_MUX_10_HSIOM_IO_INPUT24 = 0x00000AB5u, /* peri.tr_io_input[24] */ 1180 TRIG_IN_MUX_10_HSIOM_IO_INPUT25 = 0x00000AB6u, /* peri.tr_io_input[25] */ 1181 TRIG_IN_MUX_10_HSIOM_IO_INPUT26 = 0x00000AB7u, /* peri.tr_io_input[26] */ 1182 TRIG_IN_MUX_10_HSIOM_IO_INPUT27 = 0x00000AB8u, /* peri.tr_io_input[27] */ 1183 TRIG_IN_MUX_10_HSIOM_IO_INPUT28 = 0x00000AB9u, /* peri.tr_io_input[28] */ 1184 TRIG_IN_MUX_10_HSIOM_IO_INPUT29 = 0x00000ABAu, /* peri.tr_io_input[29] */ 1185 TRIG_IN_MUX_10_HSIOM_IO_INPUT30 = 0x00000ABBu, /* peri.tr_io_input[30] */ 1186 TRIG_IN_MUX_10_HSIOM_IO_INPUT31 = 0x00000ABCu /* peri.tr_io_input[31] */ 1187 } en_trig_input_debugreduction2_t; 1188 1189 /* Trigger Group Outputs */ 1190 /* Trigger Output Group 0 - P-DMA0 Request Assignments */ 1191 typedef enum 1192 { 1193 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1194 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1195 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1196 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1197 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1198 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1199 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1200 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ 1201 } en_trig_output_pdma0_tr_0_t; 1202 1203 /* Trigger Output Group 1 - P-DMA1 Request Assignments */ 1204 typedef enum 1205 { 1206 TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ 1207 TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ 1208 TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ 1209 TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ 1210 TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ 1211 TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ 1212 TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ 1213 TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ 1214 } en_trig_output_pdma1_tr_t; 1215 1216 /* Trigger Output Group 2 - DMA Request Assignments */ 1217 typedef enum 1218 { 1219 TRIG_OUT_MUX_2_MDMA_TR_IN0 = 0x40000200u, /* cpuss.dmac_tr_in[0] */ 1220 TRIG_OUT_MUX_2_MDMA_TR_IN1 = 0x40000201u, /* cpuss.dmac_tr_in[1] */ 1221 TRIG_OUT_MUX_2_MDMA_TR_IN2 = 0x40000202u, /* cpuss.dmac_tr_in[2] */ 1222 TRIG_OUT_MUX_2_MDMA_TR_IN3 = 0x40000203u /* cpuss.dmac_tr_in[3] */ 1223 } en_trig_output_mdma_t; 1224 1225 /* Trigger Output Group 3 - Dedicated mux for TCPWM to P-DMA0 triggers */ 1226 typedef enum 1227 { 1228 TRIG_OUT_MUX_3_PDMA0_TR_IN8 = 0x40000300u, /* cpuss.dw0_tr_in[8] */ 1229 TRIG_OUT_MUX_3_PDMA0_TR_IN9 = 0x40000301u, /* cpuss.dw0_tr_in[9] */ 1230 TRIG_OUT_MUX_3_PDMA0_TR_IN10 = 0x40000302u, /* cpuss.dw0_tr_in[10] */ 1231 TRIG_OUT_MUX_3_PDMA0_TR_IN11 = 0x40000303u, /* cpuss.dw0_tr_in[11] */ 1232 TRIG_OUT_MUX_3_PDMA0_TR_IN12 = 0x40000304u, /* cpuss.dw0_tr_in[12] */ 1233 TRIG_OUT_MUX_3_PDMA0_TR_IN13 = 0x40000305u, /* cpuss.dw0_tr_in[13] */ 1234 TRIG_OUT_MUX_3_PDMA0_TR_IN14 = 0x40000306u, /* cpuss.dw0_tr_in[14] */ 1235 TRIG_OUT_MUX_3_PDMA0_TR_IN15 = 0x40000307u /* cpuss.dw0_tr_in[15] */ 1236 } en_trig_output_pdma0_tr_1_t; 1237 1238 /* Trigger Output Group 4 - Reduces tcpwm output triggers to 16 signals, to allow chaining TCPWMs */ 1239 typedef enum 1240 { 1241 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN0 = 0x40000400u, /* tcpwm[0].tr_all_cnt_in[0] */ 1242 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN1 = 0x40000401u, /* tcpwm[0].tr_all_cnt_in[1] */ 1243 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN2 = 0x40000402u, /* tcpwm[0].tr_all_cnt_in[2] */ 1244 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN3 = 0x40000403u, /* tcpwm[0].tr_all_cnt_in[3] */ 1245 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN4 = 0x40000404u, /* tcpwm[0].tr_all_cnt_in[4] */ 1246 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN5 = 0x40000405u, /* tcpwm[0].tr_all_cnt_in[5] */ 1247 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN6 = 0x40000406u, /* tcpwm[0].tr_all_cnt_in[6] */ 1248 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN7 = 0x40000407u, /* tcpwm[0].tr_all_cnt_in[7] */ 1249 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN8 = 0x40000408u, /* tcpwm[0].tr_all_cnt_in[8] */ 1250 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN9 = 0x40000409u, /* tcpwm[0].tr_all_cnt_in[9] */ 1251 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN10 = 0x4000040Au, /* tcpwm[0].tr_all_cnt_in[10] */ 1252 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN11 = 0x4000040Bu, /* tcpwm[0].tr_all_cnt_in[11] */ 1253 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN12 = 0x4000040Cu, /* tcpwm[0].tr_all_cnt_in[12] */ 1254 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN13 = 0x4000040Du, /* tcpwm[0].tr_all_cnt_in[13] */ 1255 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN14 = 0x4000040Eu, /* tcpwm[0].tr_all_cnt_in[14] */ 1256 TRIG_OUT_MUX_4_TCPWM_ALL_CNT_TR_IN15 = 0x4000040Fu /* tcpwm[0].tr_all_cnt_in[15] */ 1257 } en_trig_output_tcpwm_out_t; 1258 1259 /* Trigger Output Group 5 - TCPWM trigger inputs */ 1260 typedef enum 1261 { 1262 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN16 = 0x40000500u, /* tcpwm[0].tr_all_cnt_in[16] */ 1263 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN17 = 0x40000501u, /* tcpwm[0].tr_all_cnt_in[17] */ 1264 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN18 = 0x40000502u, /* tcpwm[0].tr_all_cnt_in[18] */ 1265 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN19 = 0x40000503u, /* tcpwm[0].tr_all_cnt_in[19] */ 1266 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN20 = 0x40000504u, /* tcpwm[0].tr_all_cnt_in[20] */ 1267 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN21 = 0x40000505u, /* tcpwm[0].tr_all_cnt_in[21] */ 1268 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN22 = 0x40000506u, /* tcpwm[0].tr_all_cnt_in[22] */ 1269 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN23 = 0x40000507u, /* tcpwm[0].tr_all_cnt_in[23] */ 1270 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN24 = 0x40000508u, /* tcpwm[0].tr_all_cnt_in[24] */ 1271 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN25 = 0x40000509u, /* tcpwm[0].tr_all_cnt_in[25] */ 1272 TRIG_OUT_MUX_5_TCPWM_ALL_CNT_TR_IN26 = 0x4000050Au /* tcpwm[0].tr_all_cnt_in[26] */ 1273 } en_trig_output_tcpwm_in_t; 1274 1275 /* Trigger Output Group 6 - PASS trigger multiplexer */ 1276 typedef enum 1277 { 1278 TRIG_OUT_MUX_6_PASS_GEN_TR_IN0 = 0x40000600u, /* pass[0].tr_sar_gen_in[0] */ 1279 TRIG_OUT_MUX_6_PASS_GEN_TR_IN1 = 0x40000601u, /* pass[0].tr_sar_gen_in[1] */ 1280 TRIG_OUT_MUX_6_PASS_GEN_TR_IN2 = 0x40000602u, /* pass[0].tr_sar_gen_in[2] */ 1281 TRIG_OUT_MUX_6_PASS_GEN_TR_IN3 = 0x40000603u, /* pass[0].tr_sar_gen_in[3] */ 1282 TRIG_OUT_MUX_6_PASS_GEN_TR_IN4 = 0x40000604u, /* pass[0].tr_sar_gen_in[4] */ 1283 TRIG_OUT_MUX_6_PASS_GEN_TR_IN5 = 0x40000605u, /* pass[0].tr_sar_gen_in[5] */ 1284 TRIG_OUT_MUX_6_PASS_GEN_TR_IN6 = 0x40000606u, /* pass[0].tr_sar_gen_in[6] */ 1285 TRIG_OUT_MUX_6_PASS_GEN_TR_IN7 = 0x40000607u, /* pass[0].tr_sar_gen_in[7] */ 1286 TRIG_OUT_MUX_6_PASS_GEN_TR_IN8 = 0x40000608u, /* pass[0].tr_sar_gen_in[8] */ 1287 TRIG_OUT_MUX_6_PASS_GEN_TR_IN9 = 0x40000609u, /* pass[0].tr_sar_gen_in[9] */ 1288 TRIG_OUT_MUX_6_PASS_GEN_TR_IN10 = 0x4000060Au, /* pass[0].tr_sar_gen_in[10] */ 1289 TRIG_OUT_MUX_6_PASS_GEN_TR_IN11 = 0x4000060Bu /* pass[0].tr_sar_gen_in[11] */ 1290 } en_trig_output_pass_t; 1291 1292 /* Trigger Output Group 7 - CAN TT Synchronization triggers */ 1293 typedef enum 1294 { 1295 TRIG_OUT_MUX_7_CAN0_TT_TR_IN0 = 0x40000700u, /* canfd[0].tr_evt_swt_in[0] */ 1296 TRIG_OUT_MUX_7_CAN0_TT_TR_IN1 = 0x40000701u, /* canfd[0].tr_evt_swt_in[1] */ 1297 TRIG_OUT_MUX_7_CAN0_TT_TR_IN2 = 0x40000702u, /* canfd[0].tr_evt_swt_in[2] */ 1298 TRIG_OUT_MUX_7_CAN0_TT_TR_IN3 = 0x40000703u, /* canfd[0].tr_evt_swt_in[3] */ 1299 TRIG_OUT_MUX_7_CAN1_TT_TR_IN0 = 0x40000704u, /* canfd[1].tr_evt_swt_in[0] */ 1300 TRIG_OUT_MUX_7_CAN1_TT_TR_IN1 = 0x40000705u, /* canfd[1].tr_evt_swt_in[1] */ 1301 TRIG_OUT_MUX_7_CAN1_TT_TR_IN2 = 0x40000706u, /* canfd[1].tr_evt_swt_in[2] */ 1302 TRIG_OUT_MUX_7_CAN1_TT_TR_IN3 = 0x40000707u /* canfd[1].tr_evt_swt_in[3] */ 1303 } en_trig_output_cantt_t; 1304 1305 /* Trigger Output Group 8 - 2nd level MUX using input from MUX_9/10 */ 1306 typedef enum 1307 { 1308 TRIG_OUT_MUX_8_HSIOM_IO_OUTPUT0 = 0x40000800u, /* peri.tr_io_output[0] */ 1309 TRIG_OUT_MUX_8_HSIOM_IO_OUTPUT1 = 0x40000801u, /* peri.tr_io_output[1] */ 1310 TRIG_OUT_MUX_8_CTI_TR_IN0 = 0x40000802u, /* cpuss.cti_tr_in[0] */ 1311 TRIG_OUT_MUX_8_CTI_TR_IN1 = 0x40000803u, /* cpuss.cti_tr_in[1] */ 1312 TRIG_OUT_MUX_8_PERI_DEBUG_FREEZE_TR_IN = 0x40000804u, /* peri.tr_dbg_freeze */ 1313 TRIG_OUT_MUX_8_PASS_DEBUG_FREEZE_TR_IN = 0x40000805u, /* pass[0].tr_debug_freeze */ 1314 TRIG_OUT_MUX_8_SRSS_WDT_DEBUG_FREEZE_TR_IN = 0x40000806u, /* srss.tr_debug_freeze_wdt */ 1315 TRIG_OUT_MUX_8_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000807u, /* srss.tr_debug_freeze_mcwdt[0] */ 1316 TRIG_OUT_MUX_8_SRSS_MCWDT_DEBUG_FREEZE_TR_IN1 = 0x40000808u, /* srss.tr_debug_freeze_mcwdt[1] */ 1317 TRIG_OUT_MUX_8_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000809u /* tcpwm[0].tr_debug_freeze */ 1318 } en_trig_output_debugmain_t; 1319 1320 /* Trigger Output Group 9 - Reduces half of all possible triggers for debug purposes */ 1321 typedef enum 1322 { 1323 TRIG_OUT_MUX_9_TR_GROUP8_INPUT1 = 0x40000900u, /* tr_group[8].input[1] */ 1324 TRIG_OUT_MUX_9_TR_GROUP8_INPUT2 = 0x40000901u, /* tr_group[8].input[2] */ 1325 TRIG_OUT_MUX_9_TR_GROUP8_INPUT3 = 0x40000902u, /* tr_group[8].input[3] */ 1326 TRIG_OUT_MUX_9_TR_GROUP8_INPUT4 = 0x40000903u, /* tr_group[8].input[4] */ 1327 TRIG_OUT_MUX_9_TR_GROUP8_INPUT5 = 0x40000904u /* tr_group[8].input[5] */ 1328 } en_trig_output_debugreduction1_t; 1329 1330 /* Trigger Output Group 10 - Reduces half of all possible triggers for debug purposes */ 1331 typedef enum 1332 { 1333 TRIG_OUT_MUX_10_TR_GROUP8_INPUT6 = 0x40000A00u, /* tr_group[8].input[6] */ 1334 TRIG_OUT_MUX_10_TR_GROUP8_INPUT7 = 0x40000A01u, /* tr_group[8].input[7] */ 1335 TRIG_OUT_MUX_10_TR_GROUP8_INPUT8 = 0x40000A02u, /* tr_group[8].input[8] */ 1336 TRIG_OUT_MUX_10_TR_GROUP8_INPUT9 = 0x40000A03u, /* tr_group[8].input[9] */ 1337 TRIG_OUT_MUX_10_TR_GROUP8_INPUT10 = 0x40000A04u /* tr_group[8].input[10] */ 1338 } en_trig_output_debugreduction2_t; 1339 1340 /* Trigger Output Group 0 - TCPWM to LIN (OneToOne) */ 1341 typedef enum 1342 { 1343 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR3 = 0x40001000u, /* From tcpwm[0].tr_out0[0] to lin[0].tr_cmd_tx_header[0] */ 1344 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR4 = 0x40001001u, /* From tcpwm[0].tr_out0[1] to lin[0].tr_cmd_tx_header[1] */ 1345 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR5 = 0x40001002u, /* From tcpwm[0].tr_out0[2] to lin[0].tr_cmd_tx_header[2] */ 1346 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR6 = 0x40001003u, /* From tcpwm[0].tr_out0[3] to lin[0].tr_cmd_tx_header[3] */ 1347 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR7 = 0x40001004u, /* From tcpwm[0].tr_out0[4] to lin[0].tr_cmd_tx_header[4] */ 1348 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR8 = 0x40001005u, /* From tcpwm[0].tr_out0[5] to lin[0].tr_cmd_tx_header[5] */ 1349 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR9 = 0x40001006u, /* From tcpwm[0].tr_out0[6] to lin[0].tr_cmd_tx_header[6] */ 1350 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR10 = 0x40001007u, /* From tcpwm[0].tr_out0[7] to lin[0].tr_cmd_tx_header[7] */ 1351 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR11 = 0x40001008u, /* From tcpwm[0].tr_out0[8] to lin[0].tr_cmd_tx_header[8] */ 1352 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR12 = 0x40001009u, /* From tcpwm[0].tr_out0[9] to lin[0].tr_cmd_tx_header[9] */ 1353 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR13 = 0x4000100Au, /* From tcpwm[0].tr_out0[10] to lin[0].tr_cmd_tx_header[10] */ 1354 TRIG_OUT_1TO1_0_TCPWM_TO_LIN_TR14 = 0x4000100Bu /* From tcpwm[0].tr_out0[11] to lin[0].tr_cmd_tx_header[11] */ 1355 } en_trig_output_1to1_tcpwm_to_lin_t; 1356 1357 /* Trigger Output Group 1 - PWM Group 0 to PASS direct connect (OneToOne) */ 1358 typedef enum 1359 { 1360 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR0 = 0x40001100u, /* From tcpwm[0].tr_out1[256] to pass[0].tr_sar_ch_in[0] */ 1361 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR1 = 0x40001101u, /* From tcpwm[0].tr_out1[259] to pass[0].tr_sar_ch_in[1] */ 1362 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR2 = 0x40001102u, /* From tcpwm[0].tr_out1[262] to pass[0].tr_sar_ch_in[2] */ 1363 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR3 = 0x40001103u, /* From tcpwm[0].tr_out1[265] to pass[0].tr_sar_ch_in[3] */ 1364 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR4 = 0x40001104u, /* From tcpwm[0].tr_out1[0] to pass[0].tr_sar_ch_in[4] */ 1365 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR5 = 0x40001105u, /* From tcpwm[0].tr_out1[1] to pass[0].tr_sar_ch_in[5] */ 1366 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR6 = 0x40001106u, /* From tcpwm[0].tr_out1[2] to pass[0].tr_sar_ch_in[6] */ 1367 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR7 = 0x40001107u, /* From tcpwm[0].tr_out1[3] to pass[0].tr_sar_ch_in[7] */ 1368 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR8 = 0x40001108u, /* From tcpwm[0].tr_out1[4] to pass[0].tr_sar_ch_in[8] */ 1369 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR9 = 0x40001109u, /* From tcpwm[0].tr_out1[5] to pass[0].tr_sar_ch_in[9] */ 1370 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR10 = 0x4000110Au, /* From tcpwm[0].tr_out1[6] to pass[0].tr_sar_ch_in[10] */ 1371 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR11 = 0x4000110Bu, /* From tcpwm[0].tr_out1[7] to pass[0].tr_sar_ch_in[11] */ 1372 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR12 = 0x4000110Cu, /* From tcpwm[0].tr_out1[8] to pass[0].tr_sar_ch_in[12] */ 1373 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR13 = 0x4000110Du, /* From tcpwm[0].tr_out1[9] to pass[0].tr_sar_ch_in[13] */ 1374 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR14 = 0x4000110Eu, /* From tcpwm[0].tr_out1[10] to pass[0].tr_sar_ch_in[14] */ 1375 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR15 = 0x4000110Fu, /* From tcpwm[0].tr_out1[11] to pass[0].tr_sar_ch_in[15] */ 1376 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR16 = 0x40001110u, /* From tcpwm[0].tr_out1[12] to pass[0].tr_sar_ch_in[16] */ 1377 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR17 = 0x40001111u, /* From tcpwm[0].tr_out1[13] to pass[0].tr_sar_ch_in[17] */ 1378 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR18 = 0x40001112u, /* From tcpwm[0].tr_out1[14] to pass[0].tr_sar_ch_in[18] */ 1379 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR19 = 0x40001113u, /* From tcpwm[0].tr_out1[15] to pass[0].tr_sar_ch_in[19] */ 1380 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR20 = 0x40001114u, /* From tcpwm[0].tr_out1[16] to pass[0].tr_sar_ch_in[20] */ 1381 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR21 = 0x40001115u, /* From tcpwm[0].tr_out1[17] to pass[0].tr_sar_ch_in[21] */ 1382 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR22 = 0x40001116u, /* From tcpwm[0].tr_out1[18] to pass[0].tr_sar_ch_in[22] */ 1383 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR23 = 0x40001117u, /* From tcpwm[0].tr_out1[19] to pass[0].tr_sar_ch_in[23] */ 1384 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR32 = 0x40001118u, /* From tcpwm[0].tr_out1[257] to pass[0].tr_sar_ch_in[32] */ 1385 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR33 = 0x40001119u, /* From tcpwm[0].tr_out1[260] to pass[0].tr_sar_ch_in[33] */ 1386 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR34 = 0x4000111Au, /* From tcpwm[0].tr_out1[263] to pass[0].tr_sar_ch_in[34] */ 1387 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR35 = 0x4000111Bu, /* From tcpwm[0].tr_out1[266] to pass[0].tr_sar_ch_in[35] */ 1388 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR36 = 0x4000111Cu, /* From tcpwm[0].tr_out1[20] to pass[0].tr_sar_ch_in[36] */ 1389 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR37 = 0x4000111Du, /* From tcpwm[0].tr_out1[21] to pass[0].tr_sar_ch_in[37] */ 1390 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR38 = 0x4000111Eu, /* From tcpwm[0].tr_out1[22] to pass[0].tr_sar_ch_in[38] */ 1391 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR39 = 0x4000111Fu, /* From tcpwm[0].tr_out1[23] to pass[0].tr_sar_ch_in[39] */ 1392 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR40 = 0x40001120u, /* From tcpwm[0].tr_out1[24] to pass[0].tr_sar_ch_in[40] */ 1393 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR41 = 0x40001121u, /* From tcpwm[0].tr_out1[25] to pass[0].tr_sar_ch_in[41] */ 1394 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR42 = 0x40001122u, /* From tcpwm[0].tr_out1[26] to pass[0].tr_sar_ch_in[42] */ 1395 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR43 = 0x40001123u, /* From tcpwm[0].tr_out1[27] to pass[0].tr_sar_ch_in[43] */ 1396 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR44 = 0x40001124u, /* From tcpwm[0].tr_out1[28] to pass[0].tr_sar_ch_in[44] */ 1397 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR45 = 0x40001125u, /* From tcpwm[0].tr_out1[29] to pass[0].tr_sar_ch_in[45] */ 1398 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR46 = 0x40001126u, /* From tcpwm[0].tr_out1[30] to pass[0].tr_sar_ch_in[46] */ 1399 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR47 = 0x40001127u, /* From tcpwm[0].tr_out1[31] to pass[0].tr_sar_ch_in[47] */ 1400 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR48 = 0x40001128u, /* From tcpwm[0].tr_out1[32] to pass[0].tr_sar_ch_in[48] */ 1401 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR49 = 0x40001129u, /* From tcpwm[0].tr_out1[33] to pass[0].tr_sar_ch_in[49] */ 1402 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR50 = 0x4000112Au, /* From tcpwm[0].tr_out1[34] to pass[0].tr_sar_ch_in[50] */ 1403 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR51 = 0x4000112Bu, /* From tcpwm[0].tr_out1[35] to pass[0].tr_sar_ch_in[51] */ 1404 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR52 = 0x4000112Cu, /* From tcpwm[0].tr_out1[36] to pass[0].tr_sar_ch_in[52] */ 1405 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR53 = 0x4000112Du, /* From tcpwm[0].tr_out1[37] to pass[0].tr_sar_ch_in[53] */ 1406 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR54 = 0x4000112Eu, /* From tcpwm[0].tr_out1[38] to pass[0].tr_sar_ch_in[54] */ 1407 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR55 = 0x4000112Fu, /* From tcpwm[0].tr_out1[39] to pass[0].tr_sar_ch_in[55] */ 1408 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR56 = 0x40001130u, /* From tcpwm[0].tr_out1[40] to pass[0].tr_sar_ch_in[56] */ 1409 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR57 = 0x40001131u, /* From tcpwm[0].tr_out1[41] to pass[0].tr_sar_ch_in[57] */ 1410 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR58 = 0x40001132u, /* From tcpwm[0].tr_out1[42] to pass[0].tr_sar_ch_in[58] */ 1411 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR59 = 0x40001133u, /* From tcpwm[0].tr_out1[43] to pass[0].tr_sar_ch_in[59] */ 1412 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR60 = 0x40001134u, /* From tcpwm[0].tr_out1[44] to pass[0].tr_sar_ch_in[60] */ 1413 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR61 = 0x40001135u, /* From tcpwm[0].tr_out1[45] to pass[0].tr_sar_ch_in[61] */ 1414 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR62 = 0x40001136u, /* From tcpwm[0].tr_out1[46] to pass[0].tr_sar_ch_in[62] */ 1415 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR63 = 0x40001137u, /* From tcpwm[0].tr_out1[47] to pass[0].tr_sar_ch_in[63] */ 1416 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR64 = 0x40001138u, /* From tcpwm[0].tr_out1[258] to pass[0].tr_sar_ch_in[64] */ 1417 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR65 = 0x40001139u, /* From tcpwm[0].tr_out1[261] to pass[0].tr_sar_ch_in[65] */ 1418 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR66 = 0x4000113Au, /* From tcpwm[0].tr_out1[264] to pass[0].tr_sar_ch_in[66] */ 1419 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR67 = 0x4000113Bu, /* From tcpwm[0].tr_out1[267] to pass[0].tr_sar_ch_in[67] */ 1420 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR68 = 0x4000113Cu, /* From tcpwm[0].tr_out1[48] to pass[0].tr_sar_ch_in[68] */ 1421 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR69 = 0x4000113Du, /* From tcpwm[0].tr_out1[49] to pass[0].tr_sar_ch_in[69] */ 1422 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR70 = 0x4000113Eu, /* From tcpwm[0].tr_out1[50] to pass[0].tr_sar_ch_in[70] */ 1423 TRIG_OUT_1TO1_1_TCPWM_TO_PASS_CH_TR71 = 0x4000113Fu /* From tcpwm[0].tr_out1[51] to pass[0].tr_sar_ch_in[71] */ 1424 } en_trig_output_1to1_pwm0_to_pass_t; 1425 1426 /* Trigger Output Group 2 - PASS to DW0 direct connect (OneToOne) */ 1427 typedef enum 1428 { 1429 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA00 = 0x40001200u, /* From pass[0].tr_sar_ch_done[0] to cpuss.dw0_tr_in[28] */ 1430 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA01 = 0x40001201u, /* From pass[0].tr_sar_ch_done[1] to cpuss.dw0_tr_in[29] */ 1431 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA02 = 0x40001202u, /* From pass[0].tr_sar_ch_done[2] to cpuss.dw0_tr_in[30] */ 1432 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA03 = 0x40001203u, /* From pass[0].tr_sar_ch_done[3] to cpuss.dw0_tr_in[31] */ 1433 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA04 = 0x40001204u, /* From pass[0].tr_sar_ch_done[4] to cpuss.dw0_tr_in[32] */ 1434 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA05 = 0x40001205u, /* From pass[0].tr_sar_ch_done[5] to cpuss.dw0_tr_in[33] */ 1435 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA06 = 0x40001206u, /* From pass[0].tr_sar_ch_done[6] to cpuss.dw0_tr_in[34] */ 1436 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA07 = 0x40001207u, /* From pass[0].tr_sar_ch_done[7] to cpuss.dw0_tr_in[35] */ 1437 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA08 = 0x40001208u, /* From pass[0].tr_sar_ch_done[8] to cpuss.dw0_tr_in[36] */ 1438 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA09 = 0x40001209u, /* From pass[0].tr_sar_ch_done[9] to cpuss.dw0_tr_in[37] */ 1439 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA010 = 0x4000120Au, /* From pass[0].tr_sar_ch_done[10] to cpuss.dw0_tr_in[38] */ 1440 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA011 = 0x4000120Bu, /* From pass[0].tr_sar_ch_done[11] to cpuss.dw0_tr_in[39] */ 1441 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA012 = 0x4000120Cu, /* From pass[0].tr_sar_ch_done[12] to cpuss.dw0_tr_in[40] */ 1442 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA013 = 0x4000120Du, /* From pass[0].tr_sar_ch_done[13] to cpuss.dw0_tr_in[41] */ 1443 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA014 = 0x4000120Eu, /* From pass[0].tr_sar_ch_done[14] to cpuss.dw0_tr_in[42] */ 1444 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA015 = 0x4000120Fu, /* From pass[0].tr_sar_ch_done[15] to cpuss.dw0_tr_in[43] */ 1445 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA016 = 0x40001210u, /* From pass[0].tr_sar_ch_done[16] to cpuss.dw0_tr_in[44] */ 1446 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA017 = 0x40001211u, /* From pass[0].tr_sar_ch_done[17] to cpuss.dw0_tr_in[45] */ 1447 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA018 = 0x40001212u, /* From pass[0].tr_sar_ch_done[18] to cpuss.dw0_tr_in[46] */ 1448 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA019 = 0x40001213u, /* From pass[0].tr_sar_ch_done[19] to cpuss.dw0_tr_in[47] */ 1449 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA020 = 0x40001214u, /* From pass[0].tr_sar_ch_done[20] to cpuss.dw0_tr_in[48] */ 1450 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA021 = 0x40001215u, /* From pass[0].tr_sar_ch_done[21] to cpuss.dw0_tr_in[49] */ 1451 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA022 = 0x40001216u, /* From pass[0].tr_sar_ch_done[22] to cpuss.dw0_tr_in[50] */ 1452 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA023 = 0x40001217u, /* From pass[0].tr_sar_ch_done[23] to cpuss.dw0_tr_in[51] */ 1453 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA032 = 0x40001218u, /* From pass[0].tr_sar_ch_done[32] to cpuss.dw0_tr_in[52] */ 1454 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA033 = 0x40001219u, /* From pass[0].tr_sar_ch_done[33] to cpuss.dw0_tr_in[53] */ 1455 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA034 = 0x4000121Au, /* From pass[0].tr_sar_ch_done[34] to cpuss.dw0_tr_in[54] */ 1456 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA035 = 0x4000121Bu, /* From pass[0].tr_sar_ch_done[35] to cpuss.dw0_tr_in[55] */ 1457 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA036 = 0x4000121Cu, /* From pass[0].tr_sar_ch_done[36] to cpuss.dw0_tr_in[56] */ 1458 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA037 = 0x4000121Du, /* From pass[0].tr_sar_ch_done[37] to cpuss.dw0_tr_in[57] */ 1459 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA038 = 0x4000121Eu, /* From pass[0].tr_sar_ch_done[38] to cpuss.dw0_tr_in[58] */ 1460 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA039 = 0x4000121Fu, /* From pass[0].tr_sar_ch_done[39] to cpuss.dw0_tr_in[59] */ 1461 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA040 = 0x40001220u, /* From pass[0].tr_sar_ch_done[40] to cpuss.dw0_tr_in[60] */ 1462 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA041 = 0x40001221u, /* From pass[0].tr_sar_ch_done[41] to cpuss.dw0_tr_in[61] */ 1463 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA042 = 0x40001222u, /* From pass[0].tr_sar_ch_done[42] to cpuss.dw0_tr_in[62] */ 1464 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA043 = 0x40001223u, /* From pass[0].tr_sar_ch_done[43] to cpuss.dw0_tr_in[63] */ 1465 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA044 = 0x40001224u, /* From pass[0].tr_sar_ch_done[44] to cpuss.dw0_tr_in[64] */ 1466 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA045 = 0x40001225u, /* From pass[0].tr_sar_ch_done[45] to cpuss.dw0_tr_in[65] */ 1467 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA046 = 0x40001226u, /* From pass[0].tr_sar_ch_done[46] to cpuss.dw0_tr_in[66] */ 1468 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA047 = 0x40001227u, /* From pass[0].tr_sar_ch_done[47] to cpuss.dw0_tr_in[67] */ 1469 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA048 = 0x40001228u, /* From pass[0].tr_sar_ch_done[48] to cpuss.dw0_tr_in[68] */ 1470 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA049 = 0x40001229u, /* From pass[0].tr_sar_ch_done[49] to cpuss.dw0_tr_in[69] */ 1471 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA050 = 0x4000122Au, /* From pass[0].tr_sar_ch_done[50] to cpuss.dw0_tr_in[70] */ 1472 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA051 = 0x4000122Bu, /* From pass[0].tr_sar_ch_done[51] to cpuss.dw0_tr_in[71] */ 1473 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA052 = 0x4000122Cu, /* From pass[0].tr_sar_ch_done[52] to cpuss.dw0_tr_in[72] */ 1474 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA053 = 0x4000122Du, /* From pass[0].tr_sar_ch_done[53] to cpuss.dw0_tr_in[73] */ 1475 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA054 = 0x4000122Eu, /* From pass[0].tr_sar_ch_done[54] to cpuss.dw0_tr_in[74] */ 1476 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA055 = 0x4000122Fu, /* From pass[0].tr_sar_ch_done[55] to cpuss.dw0_tr_in[75] */ 1477 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA056 = 0x40001230u, /* From pass[0].tr_sar_ch_done[56] to cpuss.dw0_tr_in[76] */ 1478 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA057 = 0x40001231u, /* From pass[0].tr_sar_ch_done[57] to cpuss.dw0_tr_in[77] */ 1479 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA058 = 0x40001232u, /* From pass[0].tr_sar_ch_done[58] to cpuss.dw0_tr_in[78] */ 1480 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA059 = 0x40001233u, /* From pass[0].tr_sar_ch_done[59] to cpuss.dw0_tr_in[79] */ 1481 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA060 = 0x40001234u, /* From pass[0].tr_sar_ch_done[60] to cpuss.dw0_tr_in[80] */ 1482 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA061 = 0x40001235u, /* From pass[0].tr_sar_ch_done[61] to cpuss.dw0_tr_in[81] */ 1483 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA062 = 0x40001236u, /* From pass[0].tr_sar_ch_done[62] to cpuss.dw0_tr_in[82] */ 1484 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA063 = 0x40001237u, /* From pass[0].tr_sar_ch_done[63] to cpuss.dw0_tr_in[83] */ 1485 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA064 = 0x40001238u, /* From pass[0].tr_sar_ch_done[64] to cpuss.dw0_tr_in[84] */ 1486 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA065 = 0x40001239u, /* From pass[0].tr_sar_ch_done[65] to cpuss.dw0_tr_in[85] */ 1487 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA066 = 0x4000123Au, /* From pass[0].tr_sar_ch_done[66] to cpuss.dw0_tr_in[86] */ 1488 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA067 = 0x4000123Bu, /* From pass[0].tr_sar_ch_done[67] to cpuss.dw0_tr_in[87] */ 1489 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA068 = 0x4000123Cu, /* From pass[0].tr_sar_ch_done[68] to cpuss.dw0_tr_in[88] */ 1490 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA069 = 0x4000123Du, /* From pass[0].tr_sar_ch_done[69] to cpuss.dw0_tr_in[89] */ 1491 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA070 = 0x4000123Eu, /* From pass[0].tr_sar_ch_done[70] to cpuss.dw0_tr_in[90] */ 1492 TRIG_OUT_1TO1_2_PASS_CH_DONE_TO_PDMA071 = 0x4000123Fu /* From pass[0].tr_sar_ch_done[71] to cpuss.dw0_tr_in[91] */ 1493 } en_trig_output_1to1_pass_to_dw0_t; 1494 1495 /* Trigger Output Group 3 - PASS to PWM direct connect (OneToOne) */ 1496 typedef enum 1497 { 1498 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL0 = 0x40001300u, /* From pass[0].tr_sar_ch_rangevio[0] to tcpwm[0].tr_one_cnt_in[770] */ 1499 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL1 = 0x40001301u, /* From pass[0].tr_sar_ch_rangevio[1] to tcpwm[0].tr_one_cnt_in[779] */ 1500 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL2 = 0x40001302u, /* From pass[0].tr_sar_ch_rangevio[2] to tcpwm[0].tr_one_cnt_in[788] */ 1501 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL3 = 0x40001303u, /* From pass[0].tr_sar_ch_rangevio[3] to tcpwm[0].tr_one_cnt_in[797] */ 1502 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL4 = 0x40001304u, /* From pass[0].tr_sar_ch_rangevio[4] to tcpwm[0].tr_one_cnt_in[2] */ 1503 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL5 = 0x40001305u, /* From pass[0].tr_sar_ch_rangevio[5] to tcpwm[0].tr_one_cnt_in[5] */ 1504 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL6 = 0x40001306u, /* From pass[0].tr_sar_ch_rangevio[6] to tcpwm[0].tr_one_cnt_in[8] */ 1505 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL7 = 0x40001307u, /* From pass[0].tr_sar_ch_rangevio[7] to tcpwm[0].tr_one_cnt_in[11] */ 1506 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL8 = 0x40001308u, /* From pass[0].tr_sar_ch_rangevio[8] to tcpwm[0].tr_one_cnt_in[14] */ 1507 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL9 = 0x40001309u, /* From pass[0].tr_sar_ch_rangevio[9] to tcpwm[0].tr_one_cnt_in[17] */ 1508 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL10 = 0x4000130Au, /* From pass[0].tr_sar_ch_rangevio[10] to tcpwm[0].tr_one_cnt_in[20] */ 1509 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL11 = 0x4000130Bu, /* From pass[0].tr_sar_ch_rangevio[11] to tcpwm[0].tr_one_cnt_in[23] */ 1510 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL12 = 0x4000130Cu, /* From pass[0].tr_sar_ch_rangevio[12] to tcpwm[0].tr_one_cnt_in[26] */ 1511 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL13 = 0x4000130Du, /* From pass[0].tr_sar_ch_rangevio[13] to tcpwm[0].tr_one_cnt_in[29] */ 1512 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL14 = 0x4000130Eu, /* From pass[0].tr_sar_ch_rangevio[14] to tcpwm[0].tr_one_cnt_in[32] */ 1513 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL15 = 0x4000130Fu, /* From pass[0].tr_sar_ch_rangevio[15] to tcpwm[0].tr_one_cnt_in[35] */ 1514 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL16 = 0x40001310u, /* From pass[0].tr_sar_ch_rangevio[16] to tcpwm[0].tr_one_cnt_in[38] */ 1515 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL17 = 0x40001311u, /* From pass[0].tr_sar_ch_rangevio[17] to tcpwm[0].tr_one_cnt_in[41] */ 1516 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL18 = 0x40001312u, /* From pass[0].tr_sar_ch_rangevio[18] to tcpwm[0].tr_one_cnt_in[44] */ 1517 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL19 = 0x40001313u, /* From pass[0].tr_sar_ch_rangevio[19] to tcpwm[0].tr_one_cnt_in[47] */ 1518 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL20 = 0x40001314u, /* From pass[0].tr_sar_ch_rangevio[20] to tcpwm[0].tr_one_cnt_in[50] */ 1519 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL21 = 0x40001315u, /* From pass[0].tr_sar_ch_rangevio[21] to tcpwm[0].tr_one_cnt_in[53] */ 1520 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL22 = 0x40001316u, /* From pass[0].tr_sar_ch_rangevio[22] to tcpwm[0].tr_one_cnt_in[56] */ 1521 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL23 = 0x40001317u, /* From pass[0].tr_sar_ch_rangevio[23] to tcpwm[0].tr_one_cnt_in[59] */ 1522 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL24 = 0x40001318u, /* From pass[0].tr_sar_ch_rangevio[32] to tcpwm[0].tr_one_cnt_in[773] */ 1523 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL25 = 0x40001319u, /* From pass[0].tr_sar_ch_rangevio[33] to tcpwm[0].tr_one_cnt_in[782] */ 1524 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL26 = 0x4000131Au, /* From pass[0].tr_sar_ch_rangevio[34] to tcpwm[0].tr_one_cnt_in[791] */ 1525 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL27 = 0x4000131Bu, /* From pass[0].tr_sar_ch_rangevio[35] to tcpwm[0].tr_one_cnt_in[800] */ 1526 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL28 = 0x4000131Cu, /* From pass[0].tr_sar_ch_rangevio[36] to tcpwm[0].tr_one_cnt_in[62] */ 1527 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL29 = 0x4000131Du, /* From pass[0].tr_sar_ch_rangevio[37] to tcpwm[0].tr_one_cnt_in[65] */ 1528 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL30 = 0x4000131Eu, /* From pass[0].tr_sar_ch_rangevio[38] to tcpwm[0].tr_one_cnt_in[68] */ 1529 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL31 = 0x4000131Fu, /* From pass[0].tr_sar_ch_rangevio[39] to tcpwm[0].tr_one_cnt_in[71] */ 1530 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL32 = 0x40001320u, /* From pass[0].tr_sar_ch_rangevio[40] to tcpwm[0].tr_one_cnt_in[74] */ 1531 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL33 = 0x40001321u, /* From pass[0].tr_sar_ch_rangevio[41] to tcpwm[0].tr_one_cnt_in[77] */ 1532 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL34 = 0x40001322u, /* From pass[0].tr_sar_ch_rangevio[42] to tcpwm[0].tr_one_cnt_in[80] */ 1533 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL35 = 0x40001323u, /* From pass[0].tr_sar_ch_rangevio[43] to tcpwm[0].tr_one_cnt_in[83] */ 1534 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL36 = 0x40001324u, /* From pass[0].tr_sar_ch_rangevio[44] to tcpwm[0].tr_one_cnt_in[86] */ 1535 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL37 = 0x40001325u, /* From pass[0].tr_sar_ch_rangevio[45] to tcpwm[0].tr_one_cnt_in[89] */ 1536 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL38 = 0x40001326u, /* From pass[0].tr_sar_ch_rangevio[46] to tcpwm[0].tr_one_cnt_in[92] */ 1537 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL39 = 0x40001327u, /* From pass[0].tr_sar_ch_rangevio[47] to tcpwm[0].tr_one_cnt_in[95] */ 1538 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL40 = 0x40001328u, /* From pass[0].tr_sar_ch_rangevio[48] to tcpwm[0].tr_one_cnt_in[98] */ 1539 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL41 = 0x40001329u, /* From pass[0].tr_sar_ch_rangevio[49] to tcpwm[0].tr_one_cnt_in[101] */ 1540 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL42 = 0x4000132Au, /* From pass[0].tr_sar_ch_rangevio[50] to tcpwm[0].tr_one_cnt_in[104] */ 1541 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL43 = 0x4000132Bu, /* From pass[0].tr_sar_ch_rangevio[51] to tcpwm[0].tr_one_cnt_in[107] */ 1542 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL44 = 0x4000132Cu, /* From pass[0].tr_sar_ch_rangevio[52] to tcpwm[0].tr_one_cnt_in[110] */ 1543 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL45 = 0x4000132Du, /* From pass[0].tr_sar_ch_rangevio[53] to tcpwm[0].tr_one_cnt_in[113] */ 1544 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL46 = 0x4000132Eu, /* From pass[0].tr_sar_ch_rangevio[54] to tcpwm[0].tr_one_cnt_in[116] */ 1545 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL47 = 0x4000132Fu, /* From pass[0].tr_sar_ch_rangevio[55] to tcpwm[0].tr_one_cnt_in[119] */ 1546 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL48 = 0x40001330u, /* From pass[0].tr_sar_ch_rangevio[56] to tcpwm[0].tr_one_cnt_in[122] */ 1547 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL49 = 0x40001331u, /* From pass[0].tr_sar_ch_rangevio[57] to tcpwm[0].tr_one_cnt_in[125] */ 1548 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL50 = 0x40001332u, /* From pass[0].tr_sar_ch_rangevio[58] to tcpwm[0].tr_one_cnt_in[128] */ 1549 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL51 = 0x40001333u, /* From pass[0].tr_sar_ch_rangevio[59] to tcpwm[0].tr_one_cnt_in[131] */ 1550 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL52 = 0x40001334u, /* From pass[0].tr_sar_ch_rangevio[60] to tcpwm[0].tr_one_cnt_in[134] */ 1551 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL53 = 0x40001335u, /* From pass[0].tr_sar_ch_rangevio[61] to tcpwm[0].tr_one_cnt_in[137] */ 1552 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL54 = 0x40001336u, /* From pass[0].tr_sar_ch_rangevio[62] to tcpwm[0].tr_one_cnt_in[140] */ 1553 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL55 = 0x40001337u, /* From pass[0].tr_sar_ch_rangevio[63] to tcpwm[0].tr_one_cnt_in[143] */ 1554 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL56 = 0x40001338u, /* From pass[0].tr_sar_ch_rangevio[64] to tcpwm[0].tr_one_cnt_in[776] */ 1555 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL57 = 0x40001339u, /* From pass[0].tr_sar_ch_rangevio[65] to tcpwm[0].tr_one_cnt_in[785] */ 1556 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL58 = 0x4000133Au, /* From pass[0].tr_sar_ch_rangevio[66] to tcpwm[0].tr_one_cnt_in[794] */ 1557 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL59 = 0x4000133Bu, /* From pass[0].tr_sar_ch_rangevio[67] to tcpwm[0].tr_one_cnt_in[803] */ 1558 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL60 = 0x4000133Cu, /* From pass[0].tr_sar_ch_rangevio[68] to tcpwm[0].tr_one_cnt_in[146] */ 1559 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL61 = 0x4000133Du, /* From pass[0].tr_sar_ch_rangevio[69] to tcpwm[0].tr_one_cnt_in[149] */ 1560 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL62 = 0x4000133Eu, /* From pass[0].tr_sar_ch_rangevio[70] to tcpwm[0].tr_one_cnt_in[152] */ 1561 TRIG_OUT_1TO1_3_PASS_CH_RANGEVIO_TO_PWM_KILL63 = 0x4000133Fu /* From pass[0].tr_sar_ch_rangevio[71] to tcpwm[0].tr_one_cnt_in[155] */ 1562 } en_trig_output_1to1_pass_to_pwm_t; 1563 1564 /* Trigger Output Group 4 - CAN DW0 Triggers (OneToOne) */ 1565 typedef enum 1566 { 1567 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_0 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw0_tr_in[16] */ 1568 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_0 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw0_tr_in[17] */ 1569 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_0 = 0x40001402u, /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[18] */ 1570 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_1 = 0x40001403u, /* From canfd[0].tr_dbg_dma_req[1] to cpuss.dw0_tr_in[19] */ 1571 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_1 = 0x40001404u, /* From canfd[0].tr_fifo0[1] to cpuss.dw0_tr_in[20] */ 1572 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_1 = 0x40001405u, /* From canfd[0].tr_fifo1[1] to cpuss.dw0_tr_in[21] */ 1573 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_2 = 0x40001406u, /* From canfd[0].tr_dbg_dma_req[2] to cpuss.dw0_tr_in[22] */ 1574 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_2 = 0x40001407u, /* From canfd[0].tr_fifo0[2] to cpuss.dw0_tr_in[23] */ 1575 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_2 = 0x40001408u, /* From canfd[0].tr_fifo1[2] to cpuss.dw0_tr_in[24] */ 1576 TRIG_OUT_1TO1_4_CAN0_DBG_TO_PDMA0_3 = 0x40001409u, /* From canfd[0].tr_dbg_dma_req[3] to cpuss.dw0_tr_in[25] */ 1577 TRIG_OUT_1TO1_4_CAN0_FIFO0_TO_PDMA0_3 = 0x4000140Au, /* From canfd[0].tr_fifo0[3] to cpuss.dw0_tr_in[26] */ 1578 TRIG_OUT_1TO1_4_CAN0_FIFO1_TO_PDMA0_3 = 0x4000140Bu /* From canfd[0].tr_fifo1[3] to cpuss.dw0_tr_in[27] */ 1579 } en_trig_output_1to1_can0_dw_tr_t; 1580 1581 /* Trigger Output Group 5 - CAN DW1 triggers (on DW1 to share BW) (OneToOne) */ 1582 typedef enum 1583 { 1584 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_0 = 0x40001500u, /* From canfd[1].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[24] */ 1585 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_0 = 0x40001501u, /* From canfd[1].tr_fifo0[0] to cpuss.dw1_tr_in[25] */ 1586 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_0 = 0x40001502u, /* From canfd[1].tr_fifo1[0] to cpuss.dw1_tr_in[26] */ 1587 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_1 = 0x40001503u, /* From canfd[1].tr_dbg_dma_req[1] to cpuss.dw1_tr_in[27] */ 1588 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_1 = 0x40001504u, /* From canfd[1].tr_fifo0[1] to cpuss.dw1_tr_in[28] */ 1589 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_1 = 0x40001505u, /* From canfd[1].tr_fifo1[1] to cpuss.dw1_tr_in[29] */ 1590 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_2 = 0x40001506u, /* From canfd[1].tr_dbg_dma_req[2] to cpuss.dw1_tr_in[30] */ 1591 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_2 = 0x40001507u, /* From canfd[1].tr_fifo0[2] to cpuss.dw1_tr_in[31] */ 1592 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_2 = 0x40001508u, /* From canfd[1].tr_fifo1[2] to cpuss.dw1_tr_in[32] */ 1593 TRIG_OUT_1TO1_5_CAN1_DBG_TO_PDMA1_3 = 0x40001509u, /* From canfd[1].tr_dbg_dma_req[3] to cpuss.dw1_tr_in[33] */ 1594 TRIG_OUT_1TO1_5_CAN1_FIFO0_TO_PDMA1_3 = 0x4000150Au, /* From canfd[1].tr_fifo0[3] to cpuss.dw1_tr_in[34] */ 1595 TRIG_OUT_1TO1_5_CAN1_FIFO1_TO_PDMA1_3 = 0x4000150Bu /* From canfd[1].tr_fifo1[3] to cpuss.dw1_tr_in[35] */ 1596 } en_trig_output_1to1_can1_dw_tr_t; 1597 1598 /* Trigger Output Group 6 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ 1599 typedef enum 1600 { 1601 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_0 = 0x40001600u, /* From cpuss.dw0_tr_out[16] to canfd[0].tr_dbg_dma_ack[0] */ 1602 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_1 = 0x40001601u, /* From cpuss.dw0_tr_out[19] to canfd[0].tr_dbg_dma_ack[1] */ 1603 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_2 = 0x40001602u, /* From cpuss.dw0_tr_out[22] to canfd[0].tr_dbg_dma_ack[2] */ 1604 TRIG_OUT_1TO1_6_PDMA0_ACK_TO_CAN0_3 = 0x40001603u /* From cpuss.dw0_tr_out[25] to canfd[0].tr_dbg_dma_ack[3] */ 1605 } en_trig_output_1to1_can0_dw_ack_t; 1606 1607 /* Trigger Output Group 7 - Acknowledge dma request triggers from DW1 to CAN (OneToOne) */ 1608 typedef enum 1609 { 1610 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_0 = 0x40001700u, /* From cpuss.dw1_tr_out[24] to canfd[1].tr_dbg_dma_ack[0] */ 1611 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_1 = 0x40001701u, /* From cpuss.dw1_tr_out[27] to canfd[1].tr_dbg_dma_ack[1] */ 1612 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_2 = 0x40001702u, /* From cpuss.dw1_tr_out[30] to canfd[1].tr_dbg_dma_ack[2] */ 1613 TRIG_OUT_1TO1_7_PDMA1_ACK_TO_CAN1_3 = 0x40001703u /* From cpuss.dw1_tr_out[33] to canfd[1].tr_dbg_dma_ack[3] */ 1614 } en_trig_output_1to1_can1_dw_ack_t; 1615 1616 /* Trigger Output Group 8 - SCB DW Triggers (OneToOne) */ 1617 typedef enum 1618 { 1619 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA10 = 0x40001800u, /* From scb[0].tr_tx_req to cpuss.dw1_tr_in[8] */ 1620 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA10 = 0x40001801u, /* From scb[0].tr_rx_req to cpuss.dw1_tr_in[9] */ 1621 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA11 = 0x40001802u, /* From scb[1].tr_tx_req to cpuss.dw1_tr_in[10] */ 1622 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA11 = 0x40001803u, /* From scb[1].tr_rx_req to cpuss.dw1_tr_in[11] */ 1623 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA12 = 0x40001804u, /* From scb[2].tr_tx_req to cpuss.dw1_tr_in[12] */ 1624 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA12 = 0x40001805u, /* From scb[2].tr_rx_req to cpuss.dw1_tr_in[13] */ 1625 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA13 = 0x40001806u, /* From scb[3].tr_tx_req to cpuss.dw1_tr_in[14] */ 1626 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA13 = 0x40001807u, /* From scb[3].tr_rx_req to cpuss.dw1_tr_in[15] */ 1627 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA14 = 0x40001808u, /* From scb[4].tr_tx_req to cpuss.dw1_tr_in[16] */ 1628 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA14 = 0x40001809u, /* From scb[4].tr_rx_req to cpuss.dw1_tr_in[17] */ 1629 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA15 = 0x4000180Au, /* From scb[5].tr_tx_req to cpuss.dw1_tr_in[18] */ 1630 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA15 = 0x4000180Bu, /* From scb[5].tr_rx_req to cpuss.dw1_tr_in[19] */ 1631 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA16 = 0x4000180Cu, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[20] */ 1632 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA16 = 0x4000180Du, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[21] */ 1633 TRIG_OUT_1TO1_8_SCB_TX_TO_PDMA17 = 0x4000180Eu, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[22] */ 1634 TRIG_OUT_1TO1_8_SCB_RX_TO_PDMA17 = 0x4000180Fu /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[23] */ 1635 } en_trig_output_1to1_scb_dw_tr_t; 1636 1637 /* Trigger Output Group 9 - EVTGEN to CXPI (OneToOne) */ 1638 typedef enum 1639 { 1640 TRIG_OUT_1TO1_9_TCPWM_TO_CXPI_TR0 = 0x40001900u, /* From tcpwm[0].tr_out0[16] to cxpi[0].tr_cmd_tx_header[0] */ 1641 TRIG_OUT_1TO1_9_TCPWM_TO_CXPI_TR1 = 0x40001901u, /* From tcpwm[0].tr_out0[17] to cxpi[0].tr_cmd_tx_header[1] */ 1642 TRIG_OUT_1TO1_9_TCPWM_TO_CXPI_TR2 = 0x40001902u, /* From tcpwm[0].tr_out0[18] to cxpi[0].tr_cmd_tx_header[2] */ 1643 TRIG_OUT_1TO1_9_TCPWM_TO_CXPI_TR3 = 0x40001903u /* From tcpwm[0].tr_out0[19] to cxpi[0].tr_cmd_tx_header[3] */ 1644 } en_trig_output_1to1_evtgen_cxpi_tr_t; 1645 1646 /* Trigger Output Group 10 - CXPI DW Triggers (OneToOne) */ 1647 typedef enum 1648 { 1649 TRIG_OUT_1TO1_10_CXPI_TR_TX_REQ0 = 0x40001A00u, /* From cxpi[0].tr_tx_req[0] to cpuss.dw1_tr_in[36] */ 1650 TRIG_OUT_1TO1_10_CXPI_TR_TX_REQ1 = 0x40001A01u, /* From cxpi[0].tr_tx_req[1] to cpuss.dw1_tr_in[37] */ 1651 TRIG_OUT_1TO1_10_CXPI_TR_TX_REQ2 = 0x40001A02u, /* From cxpi[0].tr_tx_req[2] to cpuss.dw1_tr_in[38] */ 1652 TRIG_OUT_1TO1_10_CXPI_TR_TX_REQ3 = 0x40001A03u, /* From cxpi[0].tr_tx_req[3] to cpuss.dw1_tr_in[39] */ 1653 TRIG_OUT_1TO1_10_CXPI_TR_RX_REQ0 = 0x40001A04u, /* From cxpi[0].tr_rx_req[0] to cpuss.dw1_tr_in[40] */ 1654 TRIG_OUT_1TO1_10_CXPI_TR_RX_REQ1 = 0x40001A05u, /* From cxpi[0].tr_rx_req[1] to cpuss.dw1_tr_in[41] */ 1655 TRIG_OUT_1TO1_10_CXPI_TR_RX_REQ2 = 0x40001A06u, /* From cxpi[0].tr_rx_req[2] to cpuss.dw1_tr_in[42] */ 1656 TRIG_OUT_1TO1_10_CXPI_TR_RX_REQ3 = 0x40001A07u /* From cxpi[0].tr_rx_req[3] to cpuss.dw1_tr_in[43] */ 1657 } en_trig_output_1to1_cxpi_dw_tr_t; 1658 1659 /* Level or edge detection setting for a trigger mux */ 1660 typedef enum 1661 { 1662 /* The trigger is a simple level output */ 1663 TRIGGER_TYPE_LEVEL = 0u, 1664 /* The trigger is synchronized to the consumer blocks clock 1665 and a two cycle pulse is generated on this clock */ 1666 TRIGGER_TYPE_EDGE = 1u 1667 } en_trig_type_t; 1668 1669 /* Trigger Type Defines */ 1670 /* CANFD Trigger Types */ 1671 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 1672 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 1673 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 1674 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 1675 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 1676 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 1677 /* CPUSS Trigger Types */ 1678 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1679 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1680 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1681 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1682 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1683 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1684 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1685 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1686 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1687 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1688 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1689 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1690 /* CXPI Trigger Types */ 1691 #define TRIGGER_TYPE_CXPI_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 1692 #define TRIGGER_TYPE_CXPI_TR_RX_REQ TRIGGER_TYPE_LEVEL 1693 #define TRIGGER_TYPE_CXPI_TR_TX_REQ TRIGGER_TYPE_LEVEL 1694 /* LIN Trigger Types */ 1695 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 1696 /* PASS Trigger Types */ 1697 #define TRIGGER_TYPE_PASS_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1698 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__LEVEL TRIGGER_TYPE_LEVEL 1699 #define TRIGGER_TYPE_PASS_TR_SAR_CH_DONE__EDGE TRIGGER_TYPE_EDGE 1700 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__LEVEL TRIGGER_TYPE_LEVEL 1701 #define TRIGGER_TYPE_PASS_TR_SAR_CH_IN__EDGE TRIGGER_TYPE_EDGE 1702 #define TRIGGER_TYPE_PASS_TR_SAR_CH_RANGEVIO TRIGGER_TYPE_EDGE 1703 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__LEVEL TRIGGER_TYPE_LEVEL 1704 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_IN__EDGE TRIGGER_TYPE_EDGE 1705 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__LEVEL TRIGGER_TYPE_LEVEL 1706 #define TRIGGER_TYPE_PASS_TR_SAR_GEN_OUT__EDGE TRIGGER_TYPE_EDGE 1707 /* PERI Trigger Types */ 1708 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1709 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1710 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1711 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1712 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1713 /* SCB Trigger Types */ 1714 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1715 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1716 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1717 /* SRSS Trigger Types */ 1718 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 1719 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_WDT TRIGGER_TYPE_LEVEL 1720 /* TCPWM Trigger Types */ 1721 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 1722 /* TR_GROUP Trigger Types */ 1723 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1724 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1725 #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1726 #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE 1727 1728 /* Fault connections */ 1729 typedef enum 1730 { 1731 CPUSS_MPU_VIO_0 = 0x0000u, 1732 CPUSS_MPU_VIO_1 = 0x0001u, 1733 CPUSS_MPU_VIO_2 = 0x0002u, 1734 CPUSS_MPU_VIO_3 = 0x0003u, 1735 CPUSS_MPU_VIO_4 = 0x0004u, 1736 CPUSS_MPU_VIO_15 = 0x000Fu, 1737 CPUSS_MPU_VIO_16 = 0x0010u, 1738 CPUSS_MPU_VIO_17 = 0x0011u, 1739 CPUSS_MPU_VIO_18 = 0x0012u, 1740 PERI_PERI_C_ECC = 0x001Au, 1741 PERI_PERI_NC_ECC = 0x001Bu, 1742 PERI_MS_VIO_0 = 0x001Cu, 1743 PERI_MS_VIO_1 = 0x001Du, 1744 PERI_MS_VIO_2 = 0x001Eu, 1745 PERI_MS_VIO_3 = 0x001Fu, 1746 PERI_GROUP_VIO_0 = 0x0020u, 1747 PERI_GROUP_VIO_1 = 0x0021u, 1748 PERI_GROUP_VIO_2 = 0x0022u, 1749 PERI_GROUP_VIO_3 = 0x0023u, 1750 PERI_GROUP_VIO_5 = 0x0025u, 1751 PERI_GROUP_VIO_6 = 0x0026u, 1752 PERI_GROUP_VIO_9 = 0x0029u, 1753 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u, 1754 CPUSS_FLASHC_MAIN_C_ECC = 0x0031u, 1755 CPUSS_FLASHC_MAIN_NC_ECC = 0x0032u, 1756 CPUSS_FLASHC_WORK_BUS_ERR = 0x0033u, 1757 CPUSS_FLASHC_WORK_C_ECC = 0x0034u, 1758 CPUSS_FLASHC_WORK_NC_ECC = 0x0035u, 1759 CPUSS_FLASHC_CM0_CA_C_ECC = 0x0036u, 1760 CPUSS_FLASHC_CM0_CA_NC_ECC = 0x0037u, 1761 CPUSS_FLASHC_CM4_CA_C_ECC = 0x0038u, 1762 CPUSS_FLASHC_CM4_CA_NC_ECC = 0x0039u, 1763 CPUSS_RAMC0_C_ECC = 0x003Au, 1764 CPUSS_RAMC0_NC_ECC = 0x003Bu, 1765 CPUSS_RAMC1_C_ECC = 0x003Cu, 1766 CPUSS_RAMC1_NC_ECC = 0x003Du, 1767 CPUSS_CRYPTO_C_ECC = 0x0040u, 1768 CPUSS_CRYPTO_NC_ECC = 0x0041u, 1769 CPUSS_DW0_C_ECC = 0x0046u, 1770 CPUSS_DW0_NC_ECC = 0x0047u, 1771 CPUSS_DW1_C_ECC = 0x0048u, 1772 CPUSS_DW1_NC_ECC = 0x0049u, 1773 CPUSS_FM_SRAM_C_ECC = 0x004Au, 1774 CPUSS_FM_SRAM_NC_ECC = 0x004Bu, 1775 CANFD_0_CAN_C_ECC = 0x0050u, 1776 CANFD_0_CAN_NC_ECC = 0x0051u, 1777 CANFD_1_CAN_C_ECC = 0x0052u, 1778 CANFD_1_CAN_NC_ECC = 0x0053u, 1779 SRSS_FAULT_CSV = 0x005Au, 1780 SRSS_FAULT_SSV = 0x005Bu, 1781 SRSS_FAULT_MCWDT0 = 0x005Cu, 1782 SRSS_FAULT_MCWDT1 = 0x005Du 1783 } en_sysfault_source_t; 1784 1785 /* Bus masters */ 1786 typedef enum 1787 { 1788 CPUSS_MS_ID_CM0 = 0, 1789 CPUSS_MS_ID_CRYPTO = 1, 1790 CPUSS_MS_ID_DW0 = 2, 1791 CPUSS_MS_ID_DW1 = 3, 1792 CPUSS_MS_ID_DMAC = 4, 1793 CPUSS_MS_ID_SLOW0 = 5, 1794 CPUSS_MS_ID_SLOW1 = 6, 1795 CPUSS_MS_ID_CM4 = 14, 1796 CPUSS_MS_ID_TC = 15 1797 } en_prot_master_t; 1798 1799 /* Pointer to device configuration structure */ 1800 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfgTVIIBE4M) 1801 1802 /* Include IP definitions */ 1803 #include "ip/cyip_sflash_v2_tviibe4m.h" 1804 #include "ip/cyip_peri_v2.h" 1805 #include "ip/cyip_peri_ms_v2.h" 1806 #include "ip/cyip_crypto_v2.h" 1807 #include "ip/cyip_cpuss_v2.h" 1808 #include "ip/cyip_fault_v2.h" 1809 #include "ip/cyip_ipc_v2.h" 1810 #include "ip/cyip_prot_v2.h" 1811 #include "ip/cyip_flashc_v2_ect.h" 1812 #include "ip/cyip_srss_v3.h" 1813 #include "ip/cyip_backup_v3.h" 1814 #include "ip/cyip_dw_v2.h" 1815 #include "ip/cyip_dmac_v2.h" 1816 #include "ip/cyip_efuse_v2.h" 1817 #include "ip/cyip_efuse_data_v2_tviibe4m.h" 1818 #include "ip/cyip_hsiom_v2.h" 1819 #include "ip/cyip_gpio_v2.h" 1820 #include "ip/cyip_smartio_v2.h" 1821 #include "ip/cyip_tcpwm_v2.h" 1822 #include "ip/cyip_evtgen.h" 1823 #include "ip/cyip_lin.h" 1824 #include "ip/cyip_cxpi.h" 1825 #include "ip/cyip_canfd.h" 1826 #include "ip/cyip_scb_v2.h" 1827 #include "ip/cyip_epass.h" 1828 1829 /* IP type definitions */ 1830 typedef SFLASH_V2_Type SFLASH_Type; 1831 typedef PERI_GR_V2_Type PERI_GR_Type; 1832 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 1833 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 1834 typedef PERI_V2_Type PERI_Type; 1835 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 1836 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 1837 typedef PERI_MS_V2_Type PERI_MS_Type; 1838 typedef CRYPTO_V2_Type CRYPTO_Type; 1839 typedef CPUSS_V2_Type CPUSS_Type; 1840 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 1841 typedef FAULT_V2_Type FAULT_Type; 1842 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 1843 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 1844 typedef IPC_V2_Type IPC_Type; 1845 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 1846 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 1847 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 1848 typedef PROT_MPU_V2_Type PROT_MPU_Type; 1849 typedef PROT_V2_Type PROT_Type; 1850 typedef FLASHC_FM_CTL_ECT_V2_Type FLASHC_FM_CTL_ECT_Type; 1851 typedef FLASHC_V2_Type FLASHC_Type; 1852 typedef CSV_HF_CSV_V3_Type CSV_HF_CSV_Type; 1853 typedef CSV_HF_V3_Type CSV_HF_Type; 1854 typedef CSV_REF_CSV_V3_Type CSV_REF_CSV_Type; 1855 typedef CSV_REF_V3_Type CSV_REF_Type; 1856 typedef CSV_LF_CSV_V3_Type CSV_LF_CSV_Type; 1857 typedef CSV_LF_V3_Type CSV_LF_Type; 1858 typedef CSV_ILO_CSV_V3_Type CSV_ILO_CSV_Type; 1859 typedef CSV_ILO_V3_Type CSV_ILO_Type; 1860 typedef CLK_PLL400M_V3_Type CLK_PLL400M_Type; 1861 typedef MCWDT_CTR_V3_Type MCWDT_CTR_Type; 1862 typedef MCWDT_V3_Type MCWDT_Type; 1863 typedef WDT_V3_Type WDT_Type; 1864 typedef SRSS_V3_Type SRSS_Type; 1865 typedef BACKUP_V3_Type BACKUP_Type; 1866 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 1867 typedef DW_V2_Type DW_Type; 1868 typedef DMAC_CH_V2_Type DMAC_CH_Type; 1869 typedef DMAC_V2_Type DMAC_Type; 1870 typedef EFUSE_V2_Type EFUSE_Type; 1871 typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; 1872 typedef HSIOM_V2_Type HSIOM_Type; 1873 typedef GPIO_PRT_V2_Type GPIO_PRT_Type; 1874 typedef GPIO_V2_Type GPIO_Type; 1875 typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; 1876 typedef SMARTIO_V2_Type SMARTIO_Type; 1877 typedef TCPWM_GRP_CNT_V2_Type TCPWM_GRP_CNT_Type; 1878 typedef TCPWM_GRP_V2_Type TCPWM_GRP_Type; 1879 typedef TCPWM_V2_Type TCPWM_Type; 1880 typedef EVTGEN_COMP_STRUCT_V1_Type EVTGEN_COMP_STRUCT_Type; 1881 typedef EVTGEN_V1_Type EVTGEN_Type; 1882 typedef LIN_CH_V1_Type LIN_CH_Type; 1883 typedef LIN_V1_Type LIN_Type; 1884 typedef CXPI_CH_V1_Type CXPI_CH_Type; 1885 typedef CXPI_V1_Type CXPI_Type; 1886 typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; 1887 typedef CANFD_CH_V1_Type CANFD_CH_Type; 1888 typedef CANFD_V1_Type CANFD_Type; 1889 typedef CySCB_V2_Type CySCB_Type; 1890 typedef PASS_SAR_CH_V1_Type PASS_SAR_CH_Type; 1891 typedef PASS_SAR_V1_Type PASS_SAR_Type; 1892 typedef PASS_EPASS_MMIO_V1_Type PASS_EPASS_MMIO_Type; 1893 typedef PASS_V1_Type PASS_Type; 1894 1895 /* Parameter Defines */ 1896 /* Number of TTCAN instances */ 1897 #define CANFD0_CAN_NR 4u 1898 /* ECC logic present or not */ 1899 #define CANFD0_ECC_PRESENT 1u 1900 /* address included in ECC logic or not */ 1901 #define CANFD0_ECC_ADDR_PRESENT 1u 1902 /* Time Stamp counter present or not (required for instance 0, otherwise not 1903 allowed) */ 1904 #define CANFD0_TS_PRESENT 1u 1905 /* Message RAM size in KB */ 1906 #define CANFD0_MRAM_SIZE 32u 1907 /* Message RAM address width */ 1908 #define CANFD0_MRAM_ADDR_WIDTH 13u 1909 /* Number of TTCAN instances */ 1910 #define CANFD1_CAN_NR 4u 1911 /* ECC logic present or not */ 1912 #define CANFD1_ECC_PRESENT 1u 1913 /* address included in ECC logic or not */ 1914 #define CANFD1_ECC_ADDR_PRESENT 1u 1915 /* Time Stamp counter present or not (required for instance 0, otherwise not 1916 allowed) */ 1917 #define CANFD1_TS_PRESENT 0u 1918 /* Message RAM size in KB */ 1919 #define CANFD1_MRAM_SIZE 32u 1920 /* Message RAM address width */ 1921 #define CANFD1_MRAM_ADDR_WIDTH 13u 1922 /* UDB present or not ('0': no, '1': yes) */ 1923 #define CPUSS_UDB_PRESENT 0u 1924 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 1925 chips which doesn't use mxdft. */ 1926 #define CPUSS_MBIST_MMIO_PRESENT 0u 1927 /* System RAM 0 size in KB */ 1928 #define CPUSS_SRAM0_SIZE 256u 1929 /* Number of macros used to implement system RAM 0. Example: 8 if 256 KB system 1930 SRAM 0 is implemented with 8 32KB macros. */ 1931 #define CPUSS_RAMC0_MACRO_NR 8u 1932 /* System RAM 1 present or not ('0': no, '1': yes) */ 1933 #define CPUSS_RAMC1_PRESENT 1u 1934 /* System RAM 1 size in KB */ 1935 #define CPUSS_SRAM1_SIZE 256u 1936 /* Number of macros used to implement system RAM 1. */ 1937 #define CPUSS_RAMC1_MACRO_NR 8u 1938 /* System RAM 2 present or not ('0': no, '1': yes) */ 1939 #define CPUSS_RAMC2_PRESENT 0u 1940 /* System RAM 2 size in KB */ 1941 #define CPUSS_SRAM2_SIZE 1u 1942 /* Number of macros used to implement System RAM 2. */ 1943 #define CPUSS_RAMC2_MACRO_NR 0u 1944 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 1945 #define CPUSS_RAMC_ECC_PRESENT 1u 1946 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 1947 #define CPUSS_RAMC_ECC_ADDR_PRESENT 1u 1948 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 1949 #define CPUSS_ECC_PRESENT 1u 1950 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1951 #define CPUSS_DW_ECC_PRESENT 1u 1952 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 1953 #define CPUSS_DW_ECC_ADDR_PRESENT 1u 1954 /* System ROM size in KB */ 1955 #define CPUSS_ROM_SIZE 32u 1956 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 1957 is implemented with 4 128KB macros. */ 1958 #define CPUSS_ROMC_MACRO_NR 1u 1959 /* Flash memory present or not ('0': no, '1': yes) */ 1960 #define CPUSS_FLASHC_PRESENT 1u 1961 /* Flash memory type ('0' : SONOS, '1': ECT) */ 1962 #define CPUSS_FLASHC_ECT 1u 1963 /* Flash main region size in KB */ 1964 #define CPUSS_FLASH_SIZE 0x00001000u 1965 /* Flash work region size in KB (EEPROM emulation, data) */ 1966 #define CPUSS_WFLASH_SIZE 128u 1967 /* Flash supervisory region size in KB */ 1968 #define CPUSS_SFLASH_SIZE 32u 1969 /* Flash data output word size (in Bytes) */ 1970 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 32u 1971 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 1972 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 1973 Flash, and no Work Flash present. */ 1974 #define CPUSS_FLASHC_SONOS_RWW 0u 1975 /* SONOS Flash, number of main sectors. */ 1976 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 0u 1977 /* SONOS Flash, number of rows per main sector. */ 1978 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 0u 1979 /* SONOS Flash, number of words per row of main sector. */ 1980 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 0u 1981 /* SONOS Flash, number of special sectors. */ 1982 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 0u 1983 /* SONOS Flash, number of rows per special sector. */ 1984 #define CPUSS_FLASHC_SONOS_SPL_ROWS 0u 1985 /* Flash memory ECC present or not ('0': no, '1': yes) */ 1986 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 1u 1987 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 1988 #define CPUSS_FLASHC_RAM_ECC_PRESENT 1u 1989 /* Number of external slaves directly connected to slow AHB-Lite infrastructure. 1990 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1991 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1992 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK 1993 parameters (for the slaves present) should be derived from the Memory Map. */ 1994 #define CPUSS_SLOW_SL_PRESENT 0u 1995 /* Number of external slaves directly connected to fast AHB-Lite infrastructure. 1996 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1997 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1998 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 1999 parameters (for the slaves present) should be derived from the Memory Map. */ 2000 #define CPUSS_FAST_SL_PRESENT 0u 2001 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum 2002 number of masters supported is 2. Width of this parameter is 2-bits. 1-bit 2003 mask for each master indicating present or not. Example: 2'b01 - master 0 is 2004 present. */ 2005 #define CPUSS_SLOW_MS_PRESENT 0u 2006 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 2007 CM0+ PCU, which always uses system interrupt functionality. */ 2008 #define CPUSS_SYSTEM_IRQ_PRESENT 1u 2009 /* Number of system interrupt inputs to CPUSS */ 2010 #define CPUSS_SYSTEM_INT_NR 383u 2011 /* Number of DeepSleep system interrupt inputs to CPUSS */ 2012 #define CPUSS_SYSTEM_DPSLP_INT_NR 45u 2013 /* CM4 CPU present or not ('0': no, '1': yes) */ 2014 #define CPUSS_CM4_PRESENT 1u 2015 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 2016 levels of priority 8 = 256 levels of priority */ 2017 #define CPUSS_CM4_LVL_WIDTH 3u 2018 /* CM4 Floating point unit present or not ('0': no, '1': yes) */ 2019 #define CPUSS_CM4_FPU_PRESENT 1u 2020 /* Debug level. Legal range [0,3] */ 2021 #define CPUSS_DEBUG_LVL 3u 2022 /* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 2023 for trace level is not supported in CPUSS. */ 2024 #define CPUSS_TRACE_LVL 2u 2025 /* Embedded Trace Buffer present or not ('0': no, '1': yes) */ 2026 #define CPUSS_ETB_PRESENT 1u 2027 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2028 #define CPUSS_MTB_SRAM_SIZE 4u 2029 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 2030 #define CPUSS_ETB_SRAM_SIZE 8u 2031 /* PTM interface present (0=No, 1=Yes) */ 2032 #define CPUSS_PTM_PRESENT 0u 2033 /* Width of the PTM interface in bits ([2,32]) */ 2034 #define CPUSS_PTM_WIDTH 1u 2035 /* Width of the TPIU interface in bits ([1,4]) */ 2036 #define CPUSS_TPIU_WIDTH 4u 2037 /* CoreSight Part Identification Number */ 2038 #define CPUSS_JEPID 52u 2039 /* CoreSight Part Identification Number */ 2040 #define CPUSS_JEPCONTINUATION 0u 2041 /* CoreSight Part Identification Number */ 2042 #define CPUSS_FAMILYID 264u 2043 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 2044 #define CPUSS_ROM_TRIM_WIDTH 3u 2045 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002) */ 2046 #define CPUSS_ROM_TRIM_DEFAULT 2u 2047 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 2048 #define CPUSS_RAM_TRIM_WIDTH 8u 2049 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 2050 #define CPUSS_RAM_TRIM_DEFAULT 98u 2051 /* Cryptography IP present or not ('0': no, '1': yes) */ 2052 #define CPUSS_CRYPTO_PRESENT 1u 2053 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2054 #define CPUSS_SW_TR_PRESENT 1u 2055 /* DataWire 0 present or not ('0': no, '1': yes) */ 2056 #define CPUSS_DW0_PRESENT 1u 2057 /* Number of DataWire 0 channels ([1, 1024]) */ 2058 #define CPUSS_DW0_CH_NR 92u 2059 /* DataWire 1 present or not ('0': no, '1': yes) */ 2060 #define CPUSS_DW1_PRESENT 1u 2061 /* Number of DataWire 1 channels ([1, 1024]) */ 2062 #define CPUSS_DW1_CH_NR 44u 2063 /* DMA controller present or not ('0': no, '1': yes) */ 2064 #define CPUSS_DMAC_PRESENT 1u 2065 /* Number of DMA controller channels ([1, 8]) */ 2066 #define CPUSS_DMAC_CH_NR 4u 2067 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 2068 #define CPUSS_CH_SW_TR_PRESENT 1u 2069 /* See MMIO2 instantiation or not */ 2070 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 2071 /* ETAS Calibration support pin out present (automotive only) */ 2072 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 1u 2073 /* TRACE_LVL>0 */ 2074 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 2075 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 2076 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 1u 2077 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 2078 #define CPUSS_CPUSS_DW_DW_NR 2u 2079 /* Number of channels in each DataWire controller */ 2080 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 92u 2081 /* Width of a channel number in bits */ 2082 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 7u 2083 /* Number of channels in each DataWire controller */ 2084 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 44u 2085 /* Width of a channel number in bits */ 2086 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 6u 2087 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 2088 #define CPUSS_CRYPTO_ECC_PRESENT 1u 2089 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 2090 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 1u 2091 /* AES cipher support ('0': no, '1': yes) */ 2092 #define CPUSS_CRYPTO_AES 1u 2093 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 2094 #define CPUSS_CRYPTO_DES 1u 2095 /* Chacha support ('0': no, '1': yes) */ 2096 #define CPUSS_CRYPTO_CHACHA 1u 2097 /* Pseudo random number generation support ('0': no, '1': yes) */ 2098 #define CPUSS_CRYPTO_PR 1u 2099 /* SHA1 hash support ('0': no, '1': yes) */ 2100 #define CPUSS_CRYPTO_SHA1 1u 2101 /* SHA2 hash support ('0': no, '1': yes) */ 2102 #define CPUSS_CRYPTO_SHA2 1u 2103 /* SHA3 hash support ('0': no, '1': yes) */ 2104 #define CPUSS_CRYPTO_SHA3 1u 2105 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 2106 #define CPUSS_CRYPTO_CRC 1u 2107 /* True random number generation support ('0': no, '1': yes) */ 2108 #define CPUSS_CRYPTO_TR 1u 2109 /* Vector unit support ('0': no, '1': yes) */ 2110 #define CPUSS_CRYPTO_VU 1u 2111 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 2112 #define CPUSS_CRYPTO_GCM 1u 2113 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 2114 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 2115 kB and 16 kB memory buffer) */ 2116 #define CPUSS_CRYPTO_BUFF_SIZE 2048u 2117 /* Number of DMA controller channels ([1, 8]) */ 2118 #define CPUSS_DMAC_CH_NR 4u 2119 /* Number of DataWire controllers present (max 2) */ 2120 #define CPUSS_DW_NR 2u 2121 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 2122 #define CPUSS_DW_ECC_PRESENT 1u 2123 /* Number of fault structures. Legal range [1, 4] */ 2124 #define CPUSS_FAULT_FAULT_NR 4u 2125 /* CM4 CPU present or not ('0': no, '1': yes) */ 2126 #define CPUSS_FLASHC_CM4_PRESENT 1u 2127 /* Number of Flash BIST_DATA registers */ 2128 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 8u 2129 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 2130 #define CPUSS_FLASHC_PA_SIZE 128u 2131 /* SONOS Flash is used or not ('0': no, '1': yes) */ 2132 #define CPUSS_FLASHC_FLASHC_IS_SONOS 0u 2133 /* eCT Flash is used or not ('0': no, '1': yes) */ 2134 #define CPUSS_FLASHC_FLASHC_IS_ECT 1u 2135 /* Number of IPC structures. Legal range [1, 16] */ 2136 #define CPUSS_IPC_IPC_NR 8u 2137 /* Number of IPC interrupt structures. Legal range [1, 16] */ 2138 #define CPUSS_IPC_IPC_IRQ_NR 8u 2139 /* Master 0 protect contexts minus one */ 2140 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 2141 /* Master 1 protect contexts minus one */ 2142 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 2143 /* Master 2 protect contexts minus one */ 2144 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 2145 /* Master 3 protect contexts minus one */ 2146 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 2147 /* Master 4 protect contexts minus one */ 2148 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 2149 /* Master 5 protect contexts minus one */ 2150 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u 2151 /* Master 6 protect contexts minus one */ 2152 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u 2153 /* Master 7 protect contexts minus one */ 2154 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 2155 /* Master 8 protect contexts minus one */ 2156 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 2157 /* Master 9 protect contexts minus one */ 2158 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 2159 /* Master 10 protect contexts minus one */ 2160 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 2161 /* Master 11 protect contexts minus one */ 2162 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 2163 /* Master 12 protect contexts minus one */ 2164 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 2165 /* Master 13 protect contexts minus one */ 2166 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u 2167 /* Master 14 protect contexts minus one */ 2168 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2169 /* Master 15 protect contexts minus one */ 2170 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2171 /* Number of SMPU protection structures */ 2172 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2173 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2174 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2175 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2176 #define CXPI_MASTER_WIDTH 8u 2177 /* Number of CXPI channels ([2, 32]). For test functionality (two channels are 2178 connected), the minimal number of CXPI channels is 2. */ 2179 #define CXPI_CH_NR 4u 2180 /* Spare Enable 0=no spare, 1=max, 2=min */ 2181 #define CXPI_SPARE_EN 1u 2182 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 2183 #define DFT_NUM_HFROOT 3u 2184 /* Width of clk_occ_fast output bus (number of external OCCs) */ 2185 #define DFT_EXT_OCC 2u 2186 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 2187 signals. Value defined by CIC during Pass 1 */ 2188 #define DFT_MBIST_C_NUM 6u 2189 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2190 #define EFUSE_EFUSE_NR 4u 2191 /* Number of comparator structures ([1, 32]) */ 2192 #define EVTGEN_COMP_STRUCT_NR 11u 2193 /* Number of GPIO ports in range 0..31 */ 2194 #define IOSS_GPIO_GPIO_PORT_NR_0_31 24u 2195 /* Number of GPIO ports in range 32..63 */ 2196 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 2197 /* Number of GPIO ports in range 64..95 */ 2198 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2199 /* Number of GPIO ports in range 96..127 */ 2200 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2201 /* Number of ports in device */ 2202 #define IOSS_GPIO_GPIO_PORT_NR 24u 2203 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2204 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2205 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2206 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2207 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2208 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 1u 2209 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2210 and ENH cell types) */ 2211 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 2212 /* Indicates that pin #1 exists for this port with slew control feature */ 2213 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 2214 /* Indicates that pin #2 exists for this port with slew control feature */ 2215 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 2216 /* Indicates that pin #3 exists for this port with slew control feature */ 2217 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 2218 /* Indicates that pin #4 exists for this port with slew control feature */ 2219 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 2220 /* Indicates that pin #5 exists for this port with slew control feature */ 2221 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 2222 /* Indicates that pin #6 exists for this port with slew control feature */ 2223 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 2224 /* Indicates that pin #7 exists for this port with slew control feature */ 2225 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 2226 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2227 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 2228 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2229 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 2230 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2231 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 1u 2232 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2233 and ENH cell types) */ 2234 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 2235 /* Indicates that pin #1 exists for this port with slew control feature */ 2236 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 2237 /* Indicates that pin #2 exists for this port with slew control feature */ 2238 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 2239 /* Indicates that pin #3 exists for this port with slew control feature */ 2240 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 2241 /* Indicates that pin #4 exists for this port with slew control feature */ 2242 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 2243 /* Indicates that pin #5 exists for this port with slew control feature */ 2244 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 2245 /* Indicates that pin #6 exists for this port with slew control feature */ 2246 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 2247 /* Indicates that pin #7 exists for this port with slew control feature */ 2248 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 2249 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2250 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 2251 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2252 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 2253 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2254 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 1u 2255 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2256 and ENH cell types) */ 2257 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 2258 /* Indicates that pin #1 exists for this port with slew control feature */ 2259 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 2260 /* Indicates that pin #2 exists for this port with slew control feature */ 2261 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 2262 /* Indicates that pin #3 exists for this port with slew control feature */ 2263 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 2264 /* Indicates that pin #4 exists for this port with slew control feature */ 2265 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 2266 /* Indicates that pin #5 exists for this port with slew control feature */ 2267 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 2268 /* Indicates that pin #6 exists for this port with slew control feature */ 2269 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 2270 /* Indicates that pin #7 exists for this port with slew control feature */ 2271 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 2272 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2273 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 2274 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2275 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 2276 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2277 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 1u 2278 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2279 and ENH cell types) */ 2280 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 2281 /* Indicates that pin #1 exists for this port with slew control feature */ 2282 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 2283 /* Indicates that pin #2 exists for this port with slew control feature */ 2284 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 2285 /* Indicates that pin #3 exists for this port with slew control feature */ 2286 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 2287 /* Indicates that pin #4 exists for this port with slew control feature */ 2288 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 2289 /* Indicates that pin #5 exists for this port with slew control feature */ 2290 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 2291 /* Indicates that pin #6 exists for this port with slew control feature */ 2292 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 2293 /* Indicates that pin #7 exists for this port with slew control feature */ 2294 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 2295 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2296 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 2297 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2298 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 2299 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2300 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 1u 2301 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2302 and ENH cell types) */ 2303 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u 2304 /* Indicates that pin #1 exists for this port with slew control feature */ 2305 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u 2306 /* Indicates that pin #2 exists for this port with slew control feature */ 2307 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 2308 /* Indicates that pin #3 exists for this port with slew control feature */ 2309 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 2310 /* Indicates that pin #4 exists for this port with slew control feature */ 2311 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 2312 /* Indicates that pin #5 exists for this port with slew control feature */ 2313 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 2314 /* Indicates that pin #6 exists for this port with slew control feature */ 2315 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 2316 /* Indicates that pin #7 exists for this port with slew control feature */ 2317 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 2318 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2319 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 2320 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2321 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 2322 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2323 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 1u 2324 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2325 and ENH cell types) */ 2326 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 2327 /* Indicates that pin #1 exists for this port with slew control feature */ 2328 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 2329 /* Indicates that pin #2 exists for this port with slew control feature */ 2330 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 2331 /* Indicates that pin #3 exists for this port with slew control feature */ 2332 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 2333 /* Indicates that pin #4 exists for this port with slew control feature */ 2334 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 2335 /* Indicates that pin #5 exists for this port with slew control feature */ 2336 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 2337 /* Indicates that pin #6 exists for this port with slew control feature */ 2338 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 2339 /* Indicates that pin #7 exists for this port with slew control feature */ 2340 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 2341 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2342 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 2343 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2344 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 2345 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2346 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 1u 2347 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2348 and ENH cell types) */ 2349 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u 2350 /* Indicates that pin #1 exists for this port with slew control feature */ 2351 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u 2352 /* Indicates that pin #2 exists for this port with slew control feature */ 2353 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 0u 2354 /* Indicates that pin #3 exists for this port with slew control feature */ 2355 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 0u 2356 /* Indicates that pin #4 exists for this port with slew control feature */ 2357 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 0u 2358 /* Indicates that pin #5 exists for this port with slew control feature */ 2359 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 0u 2360 /* Indicates that pin #6 exists for this port with slew control feature */ 2361 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 0u 2362 /* Indicates that pin #7 exists for this port with slew control feature */ 2363 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 0u 2364 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2365 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 2366 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2367 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 2368 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2369 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 1u 2370 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2371 and ENH cell types) */ 2372 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 0u 2373 /* Indicates that pin #1 exists for this port with slew control feature */ 2374 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 0u 2375 /* Indicates that pin #2 exists for this port with slew control feature */ 2376 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 0u 2377 /* Indicates that pin #3 exists for this port with slew control feature */ 2378 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 0u 2379 /* Indicates that pin #4 exists for this port with slew control feature */ 2380 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 0u 2381 /* Indicates that pin #5 exists for this port with slew control feature */ 2382 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 0u 2383 /* Indicates that pin #6 exists for this port with slew control feature */ 2384 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u 2385 /* Indicates that pin #7 exists for this port with slew control feature */ 2386 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 0u 2387 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2388 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 2389 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2390 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 2391 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2392 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 1u 2393 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2394 and ENH cell types) */ 2395 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 0u 2396 /* Indicates that pin #1 exists for this port with slew control feature */ 2397 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 0u 2398 /* Indicates that pin #2 exists for this port with slew control feature */ 2399 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u 2400 /* Indicates that pin #3 exists for this port with slew control feature */ 2401 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u 2402 /* Indicates that pin #4 exists for this port with slew control feature */ 2403 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u 2404 /* Indicates that pin #5 exists for this port with slew control feature */ 2405 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u 2406 /* Indicates that pin #6 exists for this port with slew control feature */ 2407 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u 2408 /* Indicates that pin #7 exists for this port with slew control feature */ 2409 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u 2410 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2411 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 2412 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2413 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 2414 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2415 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 1u 2416 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2417 and ENH cell types) */ 2418 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 0u 2419 /* Indicates that pin #1 exists for this port with slew control feature */ 2420 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 0u 2421 /* Indicates that pin #2 exists for this port with slew control feature */ 2422 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 0u 2423 /* Indicates that pin #3 exists for this port with slew control feature */ 2424 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 0u 2425 /* Indicates that pin #4 exists for this port with slew control feature */ 2426 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 0u 2427 /* Indicates that pin #5 exists for this port with slew control feature */ 2428 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 0u 2429 /* Indicates that pin #6 exists for this port with slew control feature */ 2430 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u 2431 /* Indicates that pin #7 exists for this port with slew control feature */ 2432 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u 2433 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2434 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 2435 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2436 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 2437 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2438 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 1u 2439 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2440 and ENH cell types) */ 2441 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 0u 2442 /* Indicates that pin #1 exists for this port with slew control feature */ 2443 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 0u 2444 /* Indicates that pin #2 exists for this port with slew control feature */ 2445 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 0u 2446 /* Indicates that pin #3 exists for this port with slew control feature */ 2447 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 0u 2448 /* Indicates that pin #4 exists for this port with slew control feature */ 2449 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 0u 2450 /* Indicates that pin #5 exists for this port with slew control feature */ 2451 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 0u 2452 /* Indicates that pin #6 exists for this port with slew control feature */ 2453 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 0u 2454 /* Indicates that pin #7 exists for this port with slew control feature */ 2455 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 0u 2456 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2457 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 2458 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2459 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 2460 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2461 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 1u 2462 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2463 and ENH cell types) */ 2464 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u 2465 /* Indicates that pin #1 exists for this port with slew control feature */ 2466 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 0u 2467 /* Indicates that pin #2 exists for this port with slew control feature */ 2468 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 0u 2469 /* Indicates that pin #3 exists for this port with slew control feature */ 2470 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 0u 2471 /* Indicates that pin #4 exists for this port with slew control feature */ 2472 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 0u 2473 /* Indicates that pin #5 exists for this port with slew control feature */ 2474 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 0u 2475 /* Indicates that pin #6 exists for this port with slew control feature */ 2476 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 0u 2477 /* Indicates that pin #7 exists for this port with slew control feature */ 2478 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 0u 2479 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2480 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 2481 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2482 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 2483 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2484 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 1u 2485 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2486 and ENH cell types) */ 2487 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u 2488 /* Indicates that pin #1 exists for this port with slew control feature */ 2489 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u 2490 /* Indicates that pin #2 exists for this port with slew control feature */ 2491 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u 2492 /* Indicates that pin #3 exists for this port with slew control feature */ 2493 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u 2494 /* Indicates that pin #4 exists for this port with slew control feature */ 2495 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u 2496 /* Indicates that pin #5 exists for this port with slew control feature */ 2497 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u 2498 /* Indicates that pin #6 exists for this port with slew control feature */ 2499 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 0u 2500 /* Indicates that pin #7 exists for this port with slew control feature */ 2501 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 0u 2502 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2503 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 2504 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2505 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 2506 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2507 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 1u 2508 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2509 and ENH cell types) */ 2510 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u 2511 /* Indicates that pin #1 exists for this port with slew control feature */ 2512 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u 2513 /* Indicates that pin #2 exists for this port with slew control feature */ 2514 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u 2515 /* Indicates that pin #3 exists for this port with slew control feature */ 2516 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u 2517 /* Indicates that pin #4 exists for this port with slew control feature */ 2518 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u 2519 /* Indicates that pin #5 exists for this port with slew control feature */ 2520 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u 2521 /* Indicates that pin #6 exists for this port with slew control feature */ 2522 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u 2523 /* Indicates that pin #7 exists for this port with slew control feature */ 2524 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u 2525 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2526 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 1u 2527 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2528 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 2529 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2530 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 1u 2531 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2532 and ENH cell types) */ 2533 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 0u 2534 /* Indicates that pin #1 exists for this port with slew control feature */ 2535 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 0u 2536 /* Indicates that pin #2 exists for this port with slew control feature */ 2537 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 2538 /* Indicates that pin #3 exists for this port with slew control feature */ 2539 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 2540 /* Indicates that pin #4 exists for this port with slew control feature */ 2541 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 2542 /* Indicates that pin #5 exists for this port with slew control feature */ 2543 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 2544 /* Indicates that pin #6 exists for this port with slew control feature */ 2545 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 2546 /* Indicates that pin #7 exists for this port with slew control feature */ 2547 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 2548 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2549 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_GPIO 1u 2550 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2551 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SIO 0u 2552 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2553 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_AUTOLVL 1u 2554 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2555 and ENH cell types) */ 2556 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO0 0u 2557 /* Indicates that pin #1 exists for this port with slew control feature */ 2558 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO1 0u 2559 /* Indicates that pin #2 exists for this port with slew control feature */ 2560 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO2 0u 2561 /* Indicates that pin #3 exists for this port with slew control feature */ 2562 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO3 0u 2563 /* Indicates that pin #4 exists for this port with slew control feature */ 2564 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO4 0u 2565 /* Indicates that pin #5 exists for this port with slew control feature */ 2566 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO5 0u 2567 /* Indicates that pin #6 exists for this port with slew control feature */ 2568 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO6 0u 2569 /* Indicates that pin #7 exists for this port with slew control feature */ 2570 #define IOSS_GPIO_GPIO_PORT_NR15_GPIO_PRT_SLOW_IO7 0u 2571 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2572 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_GPIO 1u 2573 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2574 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SIO 0u 2575 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2576 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_AUTOLVL 1u 2577 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2578 and ENH cell types) */ 2579 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO0 0u 2580 /* Indicates that pin #1 exists for this port with slew control feature */ 2581 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO1 0u 2582 /* Indicates that pin #2 exists for this port with slew control feature */ 2583 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO2 0u 2584 /* Indicates that pin #3 exists for this port with slew control feature */ 2585 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO3 0u 2586 /* Indicates that pin #4 exists for this port with slew control feature */ 2587 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO4 0u 2588 /* Indicates that pin #5 exists for this port with slew control feature */ 2589 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO5 0u 2590 /* Indicates that pin #6 exists for this port with slew control feature */ 2591 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO6 0u 2592 /* Indicates that pin #7 exists for this port with slew control feature */ 2593 #define IOSS_GPIO_GPIO_PORT_NR16_GPIO_PRT_SLOW_IO7 0u 2594 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2595 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_GPIO 1u 2596 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2597 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SIO 0u 2598 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2599 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_AUTOLVL 1u 2600 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2601 and ENH cell types) */ 2602 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO0 0u 2603 /* Indicates that pin #1 exists for this port with slew control feature */ 2604 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO1 0u 2605 /* Indicates that pin #2 exists for this port with slew control feature */ 2606 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO2 0u 2607 /* Indicates that pin #3 exists for this port with slew control feature */ 2608 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO3 0u 2609 /* Indicates that pin #4 exists for this port with slew control feature */ 2610 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO4 0u 2611 /* Indicates that pin #5 exists for this port with slew control feature */ 2612 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO5 0u 2613 /* Indicates that pin #6 exists for this port with slew control feature */ 2614 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO6 0u 2615 /* Indicates that pin #7 exists for this port with slew control feature */ 2616 #define IOSS_GPIO_GPIO_PORT_NR17_GPIO_PRT_SLOW_IO7 0u 2617 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2618 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_GPIO 1u 2619 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2620 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SIO 0u 2621 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2622 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_AUTOLVL 1u 2623 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2624 and ENH cell types) */ 2625 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO0 0u 2626 /* Indicates that pin #1 exists for this port with slew control feature */ 2627 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO1 0u 2628 /* Indicates that pin #2 exists for this port with slew control feature */ 2629 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO2 0u 2630 /* Indicates that pin #3 exists for this port with slew control feature */ 2631 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO3 0u 2632 /* Indicates that pin #4 exists for this port with slew control feature */ 2633 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO4 0u 2634 /* Indicates that pin #5 exists for this port with slew control feature */ 2635 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO5 0u 2636 /* Indicates that pin #6 exists for this port with slew control feature */ 2637 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO6 0u 2638 /* Indicates that pin #7 exists for this port with slew control feature */ 2639 #define IOSS_GPIO_GPIO_PORT_NR18_GPIO_PRT_SLOW_IO7 0u 2640 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2641 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_GPIO 1u 2642 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2643 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SIO 0u 2644 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2645 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_AUTOLVL 1u 2646 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2647 and ENH cell types) */ 2648 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO0 0u 2649 /* Indicates that pin #1 exists for this port with slew control feature */ 2650 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO1 0u 2651 /* Indicates that pin #2 exists for this port with slew control feature */ 2652 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO2 0u 2653 /* Indicates that pin #3 exists for this port with slew control feature */ 2654 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO3 0u 2655 /* Indicates that pin #4 exists for this port with slew control feature */ 2656 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO4 0u 2657 /* Indicates that pin #5 exists for this port with slew control feature */ 2658 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO5 0u 2659 /* Indicates that pin #6 exists for this port with slew control feature */ 2660 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO6 0u 2661 /* Indicates that pin #7 exists for this port with slew control feature */ 2662 #define IOSS_GPIO_GPIO_PORT_NR19_GPIO_PRT_SLOW_IO7 0u 2663 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2664 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_GPIO 1u 2665 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2666 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SIO 0u 2667 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2668 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_AUTOLVL 1u 2669 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2670 and ENH cell types) */ 2671 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO0 0u 2672 /* Indicates that pin #1 exists for this port with slew control feature */ 2673 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO1 0u 2674 /* Indicates that pin #2 exists for this port with slew control feature */ 2675 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO2 0u 2676 /* Indicates that pin #3 exists for this port with slew control feature */ 2677 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO3 0u 2678 /* Indicates that pin #4 exists for this port with slew control feature */ 2679 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO4 0u 2680 /* Indicates that pin #5 exists for this port with slew control feature */ 2681 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO5 0u 2682 /* Indicates that pin #6 exists for this port with slew control feature */ 2683 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO6 0u 2684 /* Indicates that pin #7 exists for this port with slew control feature */ 2685 #define IOSS_GPIO_GPIO_PORT_NR20_GPIO_PRT_SLOW_IO7 0u 2686 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2687 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_GPIO 1u 2688 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2689 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SIO 0u 2690 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2691 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_AUTOLVL 1u 2692 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2693 and ENH cell types) */ 2694 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO0 0u 2695 /* Indicates that pin #1 exists for this port with slew control feature */ 2696 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO1 0u 2697 /* Indicates that pin #2 exists for this port with slew control feature */ 2698 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO2 0u 2699 /* Indicates that pin #3 exists for this port with slew control feature */ 2700 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO3 0u 2701 /* Indicates that pin #4 exists for this port with slew control feature */ 2702 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO4 0u 2703 /* Indicates that pin #5 exists for this port with slew control feature */ 2704 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO5 0u 2705 /* Indicates that pin #6 exists for this port with slew control feature */ 2706 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO6 0u 2707 /* Indicates that pin #7 exists for this port with slew control feature */ 2708 #define IOSS_GPIO_GPIO_PORT_NR21_GPIO_PRT_SLOW_IO7 0u 2709 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2710 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_GPIO 1u 2711 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2712 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SIO 0u 2713 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2714 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_AUTOLVL 1u 2715 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2716 and ENH cell types) */ 2717 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO0 0u 2718 /* Indicates that pin #1 exists for this port with slew control feature */ 2719 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO1 0u 2720 /* Indicates that pin #2 exists for this port with slew control feature */ 2721 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO2 0u 2722 /* Indicates that pin #3 exists for this port with slew control feature */ 2723 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO3 0u 2724 /* Indicates that pin #4 exists for this port with slew control feature */ 2725 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO4 0u 2726 /* Indicates that pin #5 exists for this port with slew control feature */ 2727 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO5 0u 2728 /* Indicates that pin #6 exists for this port with slew control feature */ 2729 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO6 0u 2730 /* Indicates that pin #7 exists for this port with slew control feature */ 2731 #define IOSS_GPIO_GPIO_PORT_NR22_GPIO_PRT_SLOW_IO7 0u 2732 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2733 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_GPIO 1u 2734 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2735 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SIO 0u 2736 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2737 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_AUTOLVL 1u 2738 /* Indicates that pin #0 exists for this port with slew control feature (SIO, OVT, 2739 and ENH cell types) */ 2740 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO0 0u 2741 /* Indicates that pin #1 exists for this port with slew control feature */ 2742 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO1 0u 2743 /* Indicates that pin #2 exists for this port with slew control feature */ 2744 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO2 0u 2745 /* Indicates that pin #3 exists for this port with slew control feature */ 2746 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO3 0u 2747 /* Indicates that pin #4 exists for this port with slew control feature */ 2748 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO4 0u 2749 /* Indicates that pin #5 exists for this port with slew control feature */ 2750 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO5 0u 2751 /* Indicates that pin #6 exists for this port with slew control feature */ 2752 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO6 0u 2753 /* Indicates that pin #7 exists for this port with slew control feature */ 2754 #define IOSS_GPIO_GPIO_PORT_NR23_GPIO_PRT_SLOW_IO7 0u 2755 /* Number of AMUX splitter cells */ 2756 #define IOSS_HSIOM_AMUX_SPLIT_NR 3u 2757 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 2758 #define IOSS_HSIOM_HSIOM_PORT_NR 24u 2759 /* Number of PWR/GND MONITOR CELLs in the device */ 2760 #define IOSS_HSIOM_MONITOR_NR 21u 2761 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 2762 #define IOSS_HSIOM_MONITOR_NR_0_31 21u 2763 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 2764 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 2765 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 2766 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 2767 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 2768 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 2769 /* Indicates the presence of alternate JTAG interface */ 2770 #define IOSS_HSIOM_ALTJTAG_PRESENT 1u 2771 /* Mask of SMARTIO instances presence */ 2772 #define IOSS_SMARTIO_SMARTIO_MASK 0x0002F000u 2773 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2774 #define LIN_MASTER_WIDTH 8u 2775 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 2776 connected), the minimal number of LIN channels is 2. */ 2777 #define LIN_CH_NR 12u 2778 /* Platform variant (0=ULL65, 1=MXS40S-ULP, 2=MXS40E, 3=M0S8, 4=MXS40S-HD) */ 2779 #define LIN_CHIP_TOP_PLATFORM_VARIANT 2u 2780 /* Number of SAR blocks */ 2781 #define PASS_SAR_ADC_NR 3u 2782 /* Number of ADC slices. Each slice will contain one SARMUX block and optionally a 2783 SAR and associated sequencer logic. */ 2784 #define PASS_SAR_SLICE_NR 3u 2785 /* Number of SAR sequencer channels (per SAR) */ 2786 #define PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR 24u 2787 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 2788 #define PASS_SAR_SLICE_NR0_SAR_SAR_MUX_IN 24u 2789 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 2790 that lower numbered slices contain the ADCs that are present. */ 2791 #define PASS_SAR_SLICE_NR0_SAR_SAR_ADC_PRESENT 1u 2792 /* Averaging logic present in SAR */ 2793 #define PASS_SAR_SLICE_NR0_SAR_SAR_AVERAGE 1u 2794 /* Range detect logic present in SAR */ 2795 #define PASS_SAR_SLICE_NR0_SAR_SAR_RANGEDET 1u 2796 /* Pulse detect logic present in SAR */ 2797 #define PASS_SAR_SLICE_NR0_SAR_SAR_PULSEDET 1u 2798 /* Number of SAR sequencer channels (per SAR) */ 2799 #define PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR 32u 2800 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 2801 #define PASS_SAR_SLICE_NR1_SAR_SAR_MUX_IN 32u 2802 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 2803 that lower numbered slices contain the ADCs that are present. */ 2804 #define PASS_SAR_SLICE_NR1_SAR_SAR_ADC_PRESENT 1u 2805 /* Averaging logic present in SAR */ 2806 #define PASS_SAR_SLICE_NR1_SAR_SAR_AVERAGE 1u 2807 /* Range detect logic present in SAR */ 2808 #define PASS_SAR_SLICE_NR1_SAR_SAR_RANGEDET 1u 2809 /* Pulse detect logic present in SAR */ 2810 #define PASS_SAR_SLICE_NR1_SAR_SAR_PULSEDET 1u 2811 /* Number of SAR sequencer channels (per SAR) */ 2812 #define PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR 8u 2813 /* Number of MUX inputs (per SAR), must be 8, 16, 24, or 32 */ 2814 #define PASS_SAR_SLICE_NR2_SAR_SAR_MUX_IN 8u 2815 /* Is ADC is present on slice (1 = Yes, 0 = No). Calculated from SAR_ADC_NR such 2816 that lower numbered slices contain the ADCs that are present. */ 2817 #define PASS_SAR_SLICE_NR2_SAR_SAR_ADC_PRESENT 1u 2818 /* Averaging logic present in SAR */ 2819 #define PASS_SAR_SLICE_NR2_SAR_SAR_AVERAGE 1u 2820 /* Range detect logic present in SAR */ 2821 #define PASS_SAR_SLICE_NR2_SAR_SAR_RANGEDET 1u 2822 /* Pulse detect logic present in SAR */ 2823 #define PASS_SAR_SLICE_NR2_SAR_SAR_PULSEDET 1u 2824 /* Parameter that is 1 for ADC0 only if ADC1 exists */ 2825 #define PASS_SAR_SAR_ADC0 1u 2826 /* The number of protection contexts ([2, 16]). */ 2827 #define PERI_PC_NR 8u 2828 /* Master interface presence mask (4 bits) */ 2829 #define PERI_MS_PRESENT 15u 2830 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 2831 #define PERI_ECC_PRESENT 1u 2832 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 2833 #define PERI_ECC_ADDR_PRESENT 1u 2834 /* Clock control functionality present ('0': no, '1': yes) */ 2835 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2836 /* Slave present (0:No, 1:Yes) */ 2837 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2838 /* Slave present (0:No, 1:Yes) */ 2839 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2840 /* Slave present (0:No, 1:Yes) */ 2841 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2842 /* Slave present (0:No, 1:Yes) */ 2843 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2844 /* Slave present (0:No, 1:Yes) */ 2845 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2846 /* Slave present (0:No, 1:Yes) */ 2847 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2848 /* Slave present (0:No, 1:Yes) */ 2849 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2850 /* Slave present (0:No, 1:Yes) */ 2851 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2852 /* Slave present (0:No, 1:Yes) */ 2853 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2854 /* Slave present (0:No, 1:Yes) */ 2855 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2856 /* Slave present (0:No, 1:Yes) */ 2857 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2858 /* Slave present (0:No, 1:Yes) */ 2859 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2860 /* Slave present (0:No, 1:Yes) */ 2861 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2862 /* Slave present (0:No, 1:Yes) */ 2863 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2864 /* Slave present (0:No, 1:Yes) */ 2865 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2866 /* Slave present (0:No, 1:Yes) */ 2867 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2868 /* Clock control functionality present ('0': no, '1': yes) */ 2869 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2870 /* Slave present (0:No, 1:Yes) */ 2871 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2872 /* Slave present (0:No, 1:Yes) */ 2873 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2874 /* Slave present (0:No, 1:Yes) */ 2875 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2876 /* Slave present (0:No, 1:Yes) */ 2877 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2878 /* Slave present (0:No, 1:Yes) */ 2879 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2880 /* Slave present (0:No, 1:Yes) */ 2881 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2882 /* Slave present (0:No, 1:Yes) */ 2883 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2884 /* Slave present (0:No, 1:Yes) */ 2885 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2886 /* Slave present (0:No, 1:Yes) */ 2887 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2888 /* Slave present (0:No, 1:Yes) */ 2889 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2890 /* Slave present (0:No, 1:Yes) */ 2891 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2892 /* Slave present (0:No, 1:Yes) */ 2893 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2894 /* Slave present (0:No, 1:Yes) */ 2895 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2896 /* Slave present (0:No, 1:Yes) */ 2897 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2898 /* Slave present (0:No, 1:Yes) */ 2899 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2900 /* Slave present (0:No, 1:Yes) */ 2901 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2902 /* Clock control functionality present ('0': no, '1': yes) */ 2903 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2904 /* Slave present (0:No, 1:Yes) */ 2905 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2906 /* Slave present (0:No, 1:Yes) */ 2907 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2908 /* Slave present (0:No, 1:Yes) */ 2909 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2910 /* Slave present (0:No, 1:Yes) */ 2911 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2912 /* Slave present (0:No, 1:Yes) */ 2913 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2914 /* Slave present (0:No, 1:Yes) */ 2915 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2916 /* Slave present (0:No, 1:Yes) */ 2917 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2918 /* Slave present (0:No, 1:Yes) */ 2919 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2920 /* Slave present (0:No, 1:Yes) */ 2921 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2922 /* Slave present (0:No, 1:Yes) */ 2923 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2924 /* Slave present (0:No, 1:Yes) */ 2925 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2926 /* Slave present (0:No, 1:Yes) */ 2927 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 1u 2928 /* Slave present (0:No, 1:Yes) */ 2929 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2930 /* Slave present (0:No, 1:Yes) */ 2931 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2932 /* Slave present (0:No, 1:Yes) */ 2933 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2934 /* Slave present (0:No, 1:Yes) */ 2935 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2936 /* Clock control functionality present ('0': no, '1': yes) */ 2937 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2938 /* Slave present (0:No, 1:Yes) */ 2939 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2940 /* Slave present (0:No, 1:Yes) */ 2941 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2942 /* Slave present (0:No, 1:Yes) */ 2943 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2944 /* Slave present (0:No, 1:Yes) */ 2945 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2946 /* Slave present (0:No, 1:Yes) */ 2947 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2948 /* Slave present (0:No, 1:Yes) */ 2949 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2950 /* Slave present (0:No, 1:Yes) */ 2951 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2952 /* Slave present (0:No, 1:Yes) */ 2953 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2954 /* Slave present (0:No, 1:Yes) */ 2955 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2956 /* Slave present (0:No, 1:Yes) */ 2957 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2958 /* Slave present (0:No, 1:Yes) */ 2959 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2960 /* Slave present (0:No, 1:Yes) */ 2961 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2962 /* Slave present (0:No, 1:Yes) */ 2963 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2964 /* Slave present (0:No, 1:Yes) */ 2965 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2966 /* Slave present (0:No, 1:Yes) */ 2967 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2968 /* Slave present (0:No, 1:Yes) */ 2969 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2970 /* Clock control functionality present ('0': no, '1': yes) */ 2971 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2972 /* Slave present (0:No, 1:Yes) */ 2973 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2974 /* Slave present (0:No, 1:Yes) */ 2975 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2976 /* Slave present (0:No, 1:Yes) */ 2977 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2978 /* Slave present (0:No, 1:Yes) */ 2979 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2980 /* Slave present (0:No, 1:Yes) */ 2981 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2982 /* Slave present (0:No, 1:Yes) */ 2983 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2984 /* Slave present (0:No, 1:Yes) */ 2985 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2986 /* Slave present (0:No, 1:Yes) */ 2987 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2988 /* Slave present (0:No, 1:Yes) */ 2989 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2990 /* Slave present (0:No, 1:Yes) */ 2991 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2992 /* Slave present (0:No, 1:Yes) */ 2993 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2994 /* Slave present (0:No, 1:Yes) */ 2995 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2996 /* Slave present (0:No, 1:Yes) */ 2997 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2998 /* Slave present (0:No, 1:Yes) */ 2999 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3000 /* Slave present (0:No, 1:Yes) */ 3001 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3002 /* Slave present (0:No, 1:Yes) */ 3003 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3004 /* Clock control functionality present ('0': no, '1': yes) */ 3005 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3006 /* Slave present (0:No, 1:Yes) */ 3007 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3008 /* Slave present (0:No, 1:Yes) */ 3009 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3010 /* Slave present (0:No, 1:Yes) */ 3011 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3012 /* Slave present (0:No, 1:Yes) */ 3013 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3014 /* Slave present (0:No, 1:Yes) */ 3015 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3016 /* Slave present (0:No, 1:Yes) */ 3017 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3018 /* Slave present (0:No, 1:Yes) */ 3019 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3020 /* Slave present (0:No, 1:Yes) */ 3021 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3022 /* Slave present (0:No, 1:Yes) */ 3023 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3024 /* Slave present (0:No, 1:Yes) */ 3025 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3026 /* Slave present (0:No, 1:Yes) */ 3027 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3028 /* Slave present (0:No, 1:Yes) */ 3029 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3030 /* Slave present (0:No, 1:Yes) */ 3031 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3032 /* Slave present (0:No, 1:Yes) */ 3033 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3034 /* Slave present (0:No, 1:Yes) */ 3035 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3036 /* Slave present (0:No, 1:Yes) */ 3037 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3038 /* Clock control functionality present ('0': no, '1': yes) */ 3039 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3040 /* Slave present (0:No, 1:Yes) */ 3041 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3042 /* Slave present (0:No, 1:Yes) */ 3043 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 3044 /* Slave present (0:No, 1:Yes) */ 3045 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 3046 /* Slave present (0:No, 1:Yes) */ 3047 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 3048 /* Slave present (0:No, 1:Yes) */ 3049 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 3050 /* Slave present (0:No, 1:Yes) */ 3051 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 3052 /* Slave present (0:No, 1:Yes) */ 3053 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 3054 /* Slave present (0:No, 1:Yes) */ 3055 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u 3056 /* Slave present (0:No, 1:Yes) */ 3057 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3058 /* Slave present (0:No, 1:Yes) */ 3059 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3060 /* Slave present (0:No, 1:Yes) */ 3061 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3062 /* Slave present (0:No, 1:Yes) */ 3063 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3064 /* Slave present (0:No, 1:Yes) */ 3065 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3066 /* Slave present (0:No, 1:Yes) */ 3067 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3068 /* Slave present (0:No, 1:Yes) */ 3069 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3070 /* Slave present (0:No, 1:Yes) */ 3071 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3072 /* Clock control functionality present ('0': no, '1': yes) */ 3073 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3074 /* Slave present (0:No, 1:Yes) */ 3075 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3076 /* Slave present (0:No, 1:Yes) */ 3077 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3078 /* Slave present (0:No, 1:Yes) */ 3079 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3080 /* Slave present (0:No, 1:Yes) */ 3081 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3082 /* Slave present (0:No, 1:Yes) */ 3083 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3084 /* Slave present (0:No, 1:Yes) */ 3085 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3086 /* Slave present (0:No, 1:Yes) */ 3087 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3088 /* Slave present (0:No, 1:Yes) */ 3089 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3090 /* Slave present (0:No, 1:Yes) */ 3091 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3092 /* Slave present (0:No, 1:Yes) */ 3093 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3094 /* Slave present (0:No, 1:Yes) */ 3095 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3096 /* Slave present (0:No, 1:Yes) */ 3097 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3098 /* Slave present (0:No, 1:Yes) */ 3099 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3100 /* Slave present (0:No, 1:Yes) */ 3101 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3102 /* Slave present (0:No, 1:Yes) */ 3103 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3104 /* Slave present (0:No, 1:Yes) */ 3105 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3106 /* Clock control functionality present ('0': no, '1': yes) */ 3107 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3108 /* Slave present (0:No, 1:Yes) */ 3109 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3110 /* Slave present (0:No, 1:Yes) */ 3111 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3112 /* Slave present (0:No, 1:Yes) */ 3113 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3114 /* Slave present (0:No, 1:Yes) */ 3115 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3116 /* Slave present (0:No, 1:Yes) */ 3117 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3118 /* Slave present (0:No, 1:Yes) */ 3119 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3120 /* Slave present (0:No, 1:Yes) */ 3121 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3122 /* Slave present (0:No, 1:Yes) */ 3123 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3124 /* Slave present (0:No, 1:Yes) */ 3125 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3126 /* Slave present (0:No, 1:Yes) */ 3127 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3128 /* Slave present (0:No, 1:Yes) */ 3129 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3130 /* Slave present (0:No, 1:Yes) */ 3131 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3132 /* Slave present (0:No, 1:Yes) */ 3133 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3134 /* Slave present (0:No, 1:Yes) */ 3135 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3136 /* Slave present (0:No, 1:Yes) */ 3137 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3138 /* Slave present (0:No, 1:Yes) */ 3139 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3140 /* Clock control functionality present ('0': no, '1': yes) */ 3141 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 3142 /* Slave present (0:No, 1:Yes) */ 3143 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 3144 /* Slave present (0:No, 1:Yes) */ 3145 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3146 /* Slave present (0:No, 1:Yes) */ 3147 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3148 /* Slave present (0:No, 1:Yes) */ 3149 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3150 /* Slave present (0:No, 1:Yes) */ 3151 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3152 /* Slave present (0:No, 1:Yes) */ 3153 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3154 /* Slave present (0:No, 1:Yes) */ 3155 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3156 /* Slave present (0:No, 1:Yes) */ 3157 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3158 /* Slave present (0:No, 1:Yes) */ 3159 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3160 /* Slave present (0:No, 1:Yes) */ 3161 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3162 /* Slave present (0:No, 1:Yes) */ 3163 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3164 /* Slave present (0:No, 1:Yes) */ 3165 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3166 /* Slave present (0:No, 1:Yes) */ 3167 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3168 /* Slave present (0:No, 1:Yes) */ 3169 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3170 /* Slave present (0:No, 1:Yes) */ 3171 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3172 /* Slave present (0:No, 1:Yes) */ 3173 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3174 /* Clock control functionality present ('0': no, '1': yes) */ 3175 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3176 /* Slave present (0:No, 1:Yes) */ 3177 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3178 /* Slave present (0:No, 1:Yes) */ 3179 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3180 /* Slave present (0:No, 1:Yes) */ 3181 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3182 /* Slave present (0:No, 1:Yes) */ 3183 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3184 /* Slave present (0:No, 1:Yes) */ 3185 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3186 /* Slave present (0:No, 1:Yes) */ 3187 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3188 /* Slave present (0:No, 1:Yes) */ 3189 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3190 /* Slave present (0:No, 1:Yes) */ 3191 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3192 /* Slave present (0:No, 1:Yes) */ 3193 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3194 /* Slave present (0:No, 1:Yes) */ 3195 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3196 /* Slave present (0:No, 1:Yes) */ 3197 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3198 /* Slave present (0:No, 1:Yes) */ 3199 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3200 /* Slave present (0:No, 1:Yes) */ 3201 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3202 /* Slave present (0:No, 1:Yes) */ 3203 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3204 /* Slave present (0:No, 1:Yes) */ 3205 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3206 /* Slave present (0:No, 1:Yes) */ 3207 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3208 /* Clock control functionality present ('0': no, '1': yes) */ 3209 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3210 /* Slave present (0:No, 1:Yes) */ 3211 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3212 /* Slave present (0:No, 1:Yes) */ 3213 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3214 /* Slave present (0:No, 1:Yes) */ 3215 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3216 /* Slave present (0:No, 1:Yes) */ 3217 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3218 /* Slave present (0:No, 1:Yes) */ 3219 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3220 /* Slave present (0:No, 1:Yes) */ 3221 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3222 /* Slave present (0:No, 1:Yes) */ 3223 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3224 /* Slave present (0:No, 1:Yes) */ 3225 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3226 /* Slave present (0:No, 1:Yes) */ 3227 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3228 /* Slave present (0:No, 1:Yes) */ 3229 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3230 /* Slave present (0:No, 1:Yes) */ 3231 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3232 /* Slave present (0:No, 1:Yes) */ 3233 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3234 /* Slave present (0:No, 1:Yes) */ 3235 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3236 /* Slave present (0:No, 1:Yes) */ 3237 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3238 /* Slave present (0:No, 1:Yes) */ 3239 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3240 /* Slave present (0:No, 1:Yes) */ 3241 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3242 /* Clock control functionality present ('0': no, '1': yes) */ 3243 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3244 /* Slave present (0:No, 1:Yes) */ 3245 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3246 /* Slave present (0:No, 1:Yes) */ 3247 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3248 /* Slave present (0:No, 1:Yes) */ 3249 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3250 /* Slave present (0:No, 1:Yes) */ 3251 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3252 /* Slave present (0:No, 1:Yes) */ 3253 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3254 /* Slave present (0:No, 1:Yes) */ 3255 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3256 /* Slave present (0:No, 1:Yes) */ 3257 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3258 /* Slave present (0:No, 1:Yes) */ 3259 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3260 /* Slave present (0:No, 1:Yes) */ 3261 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3262 /* Slave present (0:No, 1:Yes) */ 3263 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3264 /* Slave present (0:No, 1:Yes) */ 3265 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3266 /* Slave present (0:No, 1:Yes) */ 3267 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3268 /* Slave present (0:No, 1:Yes) */ 3269 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3270 /* Slave present (0:No, 1:Yes) */ 3271 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3272 /* Slave present (0:No, 1:Yes) */ 3273 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3274 /* Slave present (0:No, 1:Yes) */ 3275 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3276 /* Clock control functionality present ('0': no, '1': yes) */ 3277 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3278 /* Slave present (0:No, 1:Yes) */ 3279 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3280 /* Slave present (0:No, 1:Yes) */ 3281 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3282 /* Slave present (0:No, 1:Yes) */ 3283 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3284 /* Slave present (0:No, 1:Yes) */ 3285 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3286 /* Slave present (0:No, 1:Yes) */ 3287 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3288 /* Slave present (0:No, 1:Yes) */ 3289 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3290 /* Slave present (0:No, 1:Yes) */ 3291 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3292 /* Slave present (0:No, 1:Yes) */ 3293 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3294 /* Slave present (0:No, 1:Yes) */ 3295 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3296 /* Slave present (0:No, 1:Yes) */ 3297 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3298 /* Slave present (0:No, 1:Yes) */ 3299 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3300 /* Slave present (0:No, 1:Yes) */ 3301 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3302 /* Slave present (0:No, 1:Yes) */ 3303 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3304 /* Slave present (0:No, 1:Yes) */ 3305 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3306 /* Slave present (0:No, 1:Yes) */ 3307 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3308 /* Slave present (0:No, 1:Yes) */ 3309 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3310 /* Clock control functionality present ('0': no, '1': yes) */ 3311 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3312 /* Slave present (0:No, 1:Yes) */ 3313 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3314 /* Slave present (0:No, 1:Yes) */ 3315 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3316 /* Slave present (0:No, 1:Yes) */ 3317 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3318 /* Slave present (0:No, 1:Yes) */ 3319 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3320 /* Slave present (0:No, 1:Yes) */ 3321 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3322 /* Slave present (0:No, 1:Yes) */ 3323 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3324 /* Slave present (0:No, 1:Yes) */ 3325 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3326 /* Slave present (0:No, 1:Yes) */ 3327 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3328 /* Slave present (0:No, 1:Yes) */ 3329 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3330 /* Slave present (0:No, 1:Yes) */ 3331 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3332 /* Slave present (0:No, 1:Yes) */ 3333 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3334 /* Slave present (0:No, 1:Yes) */ 3335 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3336 /* Slave present (0:No, 1:Yes) */ 3337 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3338 /* Slave present (0:No, 1:Yes) */ 3339 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3340 /* Slave present (0:No, 1:Yes) */ 3341 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3342 /* Slave present (0:No, 1:Yes) */ 3343 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3344 /* Clock control functionality present ('0': no, '1': yes) */ 3345 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 3346 /* Slave present (0:No, 1:Yes) */ 3347 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 3348 /* Slave present (0:No, 1:Yes) */ 3349 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 3350 /* Slave present (0:No, 1:Yes) */ 3351 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 3352 /* Slave present (0:No, 1:Yes) */ 3353 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 3354 /* Slave present (0:No, 1:Yes) */ 3355 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 3356 /* Slave present (0:No, 1:Yes) */ 3357 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 3358 /* Slave present (0:No, 1:Yes) */ 3359 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 3360 /* Slave present (0:No, 1:Yes) */ 3361 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 3362 /* Slave present (0:No, 1:Yes) */ 3363 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 3364 /* Slave present (0:No, 1:Yes) */ 3365 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 3366 /* Slave present (0:No, 1:Yes) */ 3367 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 3368 /* Slave present (0:No, 1:Yes) */ 3369 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 3370 /* Slave present (0:No, 1:Yes) */ 3371 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 3372 /* Slave present (0:No, 1:Yes) */ 3373 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 3374 /* Slave present (0:No, 1:Yes) */ 3375 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 3376 /* Slave present (0:No, 1:Yes) */ 3377 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 3378 /* Number of programmable clocks (outputs) */ 3379 #define PERI_CLOCK_NR 124u 3380 /* Number of 8.0 dividers */ 3381 #define PERI_DIV_8_NR 32u 3382 /* Number of 16.0 dividers */ 3383 #define PERI_DIV_16_NR 16u 3384 /* Number of 16.5 (fractional) dividers */ 3385 #define PERI_DIV_16_5_NR 0u 3386 /* Number of 24.5 (fractional) dividers */ 3387 #define PERI_DIV_24_5_NR 8u 3388 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 3389 #define PERI_DIV_ADDR_WIDTH 5u 3390 /* Timeout functionality present ('0': no, '1': yes) */ 3391 #define PERI_TIMEOUT_PRESENT 1u 3392 /* Trigger module present (0=No, 1=Yes) */ 3393 #define PERI_TR 1u 3394 /* Number of trigger groups */ 3395 #define PERI_TR_GROUP_NR 11u 3396 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3397 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3398 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3399 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3400 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3401 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3402 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3403 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3404 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3405 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3406 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3407 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3408 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3409 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3410 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3411 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3412 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3413 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3414 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3415 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3416 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3417 #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 0u 3418 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3419 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3420 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3421 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3422 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3423 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3424 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3425 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3426 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3427 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3428 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3429 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3430 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3431 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3432 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3433 #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3434 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3435 #define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3436 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3437 #define PERI_TR_1TO1_GROUP_NR9_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3438 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3439 #define PERI_TR_1TO1_GROUP_NR10_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3440 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3441 #define PERI_MASTER_WIDTH 8u 3442 /* DeepSleep support ('0':no, '1': yes) */ 3443 #define SCB0_DEEPSLEEP 1u 3444 /* I2C master support? ('0': no, '1': yes) */ 3445 #define SCB0_I2C_M 1u 3446 /* I2C slave support? ('0': no, '1': yes) */ 3447 #define SCB0_I2C_S 1u 3448 /* I2C glitch filters present? ('0': no, '1': yes) */ 3449 #define SCB0_I2C_GLITCH 1u 3450 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3451 #define SCB0_I2C_S_EC 1u 3452 /* I2C support? (I2C_M | I2C_S) */ 3453 #define SCB0_I2C 1u 3454 /* I2C externally clocked support? ('0': no, '1': yes) */ 3455 #define SCB0_I2C_EC 1u 3456 /* I2C master and slave support? (I2C_M & I2C_S) */ 3457 #define SCB0_I2C_M_S 1u 3458 /* SPI master support? ('0': no, '1': yes) */ 3459 #define SCB0_SPI_M 1u 3460 /* SPI slave support? ('0': no, '1': yes) */ 3461 #define SCB0_SPI_S 1u 3462 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3463 #define SCB0_SPI_S_EC 1u 3464 /* SPI support? (SPI_M | SPI_S) */ 3465 #define SCB0_SPI 1u 3466 /* SPI externally clocked support? ('0': no, '1': yes) */ 3467 #define SCB0_SPI_EC 1u 3468 /* Externally clocked support? ('0': no, '1': yes) */ 3469 #define SCB0_EC 1u 3470 /* UART support? ('0': no, '1': yes) */ 3471 #define SCB0_UART 1u 3472 /* SPI or UART (SPI | UART) */ 3473 #define SCB0_SPI_UART 1u 3474 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3475 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3476 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3477 #define SCB0_EZ_DATA_NR 256u 3478 /* Command/response mode support? ('0': no, '1': yes) */ 3479 #define SCB0_CMD_RESP 1u 3480 /* EZ mode support? ('0': no, '1': yes) */ 3481 #define SCB0_EZ 1u 3482 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3483 #define SCB0_EZ_CMD_RESP 1u 3484 /* I2C slave with EZ mode (I2C_S & EZ) */ 3485 #define SCB0_I2C_S_EZ 1u 3486 /* SPI slave with EZ mode (SPI_S & EZ) */ 3487 #define SCB0_SPI_S_EZ 1u 3488 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3489 #define SCB0_MASTER_WIDTH 8u 3490 /* Number of used spi_select signals (max 4) */ 3491 #define SCB0_CHIP_TOP_SPI_SEL_NR 4u 3492 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3493 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 3494 /* DeepSleep support ('0':no, '1': yes) */ 3495 #define SCB1_DEEPSLEEP 0u 3496 /* I2C master support? ('0': no, '1': yes) */ 3497 #define SCB1_I2C_M 1u 3498 /* I2C slave support? ('0': no, '1': yes) */ 3499 #define SCB1_I2C_S 1u 3500 /* I2C glitch filters present? ('0': no, '1': yes) */ 3501 #define SCB1_I2C_GLITCH 1u 3502 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3503 #define SCB1_I2C_S_EC 0u 3504 /* I2C support? (I2C_M | I2C_S) */ 3505 #define SCB1_I2C 1u 3506 /* I2C externally clocked support? ('0': no, '1': yes) */ 3507 #define SCB1_I2C_EC 0u 3508 /* I2C master and slave support? (I2C_M & I2C_S) */ 3509 #define SCB1_I2C_M_S 1u 3510 /* SPI master support? ('0': no, '1': yes) */ 3511 #define SCB1_SPI_M 1u 3512 /* SPI slave support? ('0': no, '1': yes) */ 3513 #define SCB1_SPI_S 1u 3514 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3515 #define SCB1_SPI_S_EC 1u 3516 /* SPI support? (SPI_M | SPI_S) */ 3517 #define SCB1_SPI 1u 3518 /* SPI externally clocked support? ('0': no, '1': yes) */ 3519 #define SCB1_SPI_EC 1u 3520 /* Externally clocked support? ('0': no, '1': yes) */ 3521 #define SCB1_EC 1u 3522 /* UART support? ('0': no, '1': yes) */ 3523 #define SCB1_UART 1u 3524 /* SPI or UART (SPI | UART) */ 3525 #define SCB1_SPI_UART 1u 3526 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3527 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3528 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3529 #define SCB1_EZ_DATA_NR 256u 3530 /* Command/response mode support? ('0': no, '1': yes) */ 3531 #define SCB1_CMD_RESP 0u 3532 /* EZ mode support? ('0': no, '1': yes) */ 3533 #define SCB1_EZ 1u 3534 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3535 #define SCB1_EZ_CMD_RESP 1u 3536 /* I2C slave with EZ mode (I2C_S & EZ) */ 3537 #define SCB1_I2C_S_EZ 1u 3538 /* SPI slave with EZ mode (SPI_S & EZ) */ 3539 #define SCB1_SPI_S_EZ 1u 3540 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3541 #define SCB1_MASTER_WIDTH 8u 3542 /* Number of used spi_select signals (max 4) */ 3543 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 3544 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3545 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 3546 /* DeepSleep support ('0':no, '1': yes) */ 3547 #define SCB2_DEEPSLEEP 0u 3548 /* I2C master support? ('0': no, '1': yes) */ 3549 #define SCB2_I2C_M 1u 3550 /* I2C slave support? ('0': no, '1': yes) */ 3551 #define SCB2_I2C_S 1u 3552 /* I2C glitch filters present? ('0': no, '1': yes) */ 3553 #define SCB2_I2C_GLITCH 1u 3554 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3555 #define SCB2_I2C_S_EC 0u 3556 /* I2C support? (I2C_M | I2C_S) */ 3557 #define SCB2_I2C 1u 3558 /* I2C externally clocked support? ('0': no, '1': yes) */ 3559 #define SCB2_I2C_EC 0u 3560 /* I2C master and slave support? (I2C_M & I2C_S) */ 3561 #define SCB2_I2C_M_S 1u 3562 /* SPI master support? ('0': no, '1': yes) */ 3563 #define SCB2_SPI_M 1u 3564 /* SPI slave support? ('0': no, '1': yes) */ 3565 #define SCB2_SPI_S 1u 3566 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3567 #define SCB2_SPI_S_EC 1u 3568 /* SPI support? (SPI_M | SPI_S) */ 3569 #define SCB2_SPI 1u 3570 /* SPI externally clocked support? ('0': no, '1': yes) */ 3571 #define SCB2_SPI_EC 1u 3572 /* Externally clocked support? ('0': no, '1': yes) */ 3573 #define SCB2_EC 1u 3574 /* UART support? ('0': no, '1': yes) */ 3575 #define SCB2_UART 1u 3576 /* SPI or UART (SPI | UART) */ 3577 #define SCB2_SPI_UART 1u 3578 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3579 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3580 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3581 #define SCB2_EZ_DATA_NR 256u 3582 /* Command/response mode support? ('0': no, '1': yes) */ 3583 #define SCB2_CMD_RESP 0u 3584 /* EZ mode support? ('0': no, '1': yes) */ 3585 #define SCB2_EZ 1u 3586 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3587 #define SCB2_EZ_CMD_RESP 1u 3588 /* I2C slave with EZ mode (I2C_S & EZ) */ 3589 #define SCB2_I2C_S_EZ 1u 3590 /* SPI slave with EZ mode (SPI_S & EZ) */ 3591 #define SCB2_SPI_S_EZ 1u 3592 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3593 #define SCB2_MASTER_WIDTH 8u 3594 /* Number of used spi_select signals (max 4) */ 3595 #define SCB2_CHIP_TOP_SPI_SEL_NR 4u 3596 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3597 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 3598 /* DeepSleep support ('0':no, '1': yes) */ 3599 #define SCB3_DEEPSLEEP 0u 3600 /* I2C master support? ('0': no, '1': yes) */ 3601 #define SCB3_I2C_M 1u 3602 /* I2C slave support? ('0': no, '1': yes) */ 3603 #define SCB3_I2C_S 1u 3604 /* I2C glitch filters present? ('0': no, '1': yes) */ 3605 #define SCB3_I2C_GLITCH 1u 3606 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3607 #define SCB3_I2C_S_EC 0u 3608 /* I2C support? (I2C_M | I2C_S) */ 3609 #define SCB3_I2C 1u 3610 /* I2C externally clocked support? ('0': no, '1': yes) */ 3611 #define SCB3_I2C_EC 0u 3612 /* I2C master and slave support? (I2C_M & I2C_S) */ 3613 #define SCB3_I2C_M_S 1u 3614 /* SPI master support? ('0': no, '1': yes) */ 3615 #define SCB3_SPI_M 1u 3616 /* SPI slave support? ('0': no, '1': yes) */ 3617 #define SCB3_SPI_S 1u 3618 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3619 #define SCB3_SPI_S_EC 1u 3620 /* SPI support? (SPI_M | SPI_S) */ 3621 #define SCB3_SPI 1u 3622 /* SPI externally clocked support? ('0': no, '1': yes) */ 3623 #define SCB3_SPI_EC 1u 3624 /* Externally clocked support? ('0': no, '1': yes) */ 3625 #define SCB3_EC 1u 3626 /* UART support? ('0': no, '1': yes) */ 3627 #define SCB3_UART 1u 3628 /* SPI or UART (SPI | UART) */ 3629 #define SCB3_SPI_UART 1u 3630 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3631 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3632 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3633 #define SCB3_EZ_DATA_NR 256u 3634 /* Command/response mode support? ('0': no, '1': yes) */ 3635 #define SCB3_CMD_RESP 0u 3636 /* EZ mode support? ('0': no, '1': yes) */ 3637 #define SCB3_EZ 1u 3638 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3639 #define SCB3_EZ_CMD_RESP 1u 3640 /* I2C slave with EZ mode (I2C_S & EZ) */ 3641 #define SCB3_I2C_S_EZ 1u 3642 /* SPI slave with EZ mode (SPI_S & EZ) */ 3643 #define SCB3_SPI_S_EZ 1u 3644 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3645 #define SCB3_MASTER_WIDTH 8u 3646 /* Number of used spi_select signals (max 4) */ 3647 #define SCB3_CHIP_TOP_SPI_SEL_NR 4u 3648 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3649 #define SCB3_CHIP_TOP_I2C_FAST_PLUS 1u 3650 /* DeepSleep support ('0':no, '1': yes) */ 3651 #define SCB4_DEEPSLEEP 0u 3652 /* I2C master support? ('0': no, '1': yes) */ 3653 #define SCB4_I2C_M 1u 3654 /* I2C slave support? ('0': no, '1': yes) */ 3655 #define SCB4_I2C_S 1u 3656 /* I2C glitch filters present? ('0': no, '1': yes) */ 3657 #define SCB4_I2C_GLITCH 1u 3658 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3659 #define SCB4_I2C_S_EC 0u 3660 /* I2C support? (I2C_M | I2C_S) */ 3661 #define SCB4_I2C 1u 3662 /* I2C externally clocked support? ('0': no, '1': yes) */ 3663 #define SCB4_I2C_EC 0u 3664 /* I2C master and slave support? (I2C_M & I2C_S) */ 3665 #define SCB4_I2C_M_S 1u 3666 /* SPI master support? ('0': no, '1': yes) */ 3667 #define SCB4_SPI_M 1u 3668 /* SPI slave support? ('0': no, '1': yes) */ 3669 #define SCB4_SPI_S 1u 3670 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3671 #define SCB4_SPI_S_EC 1u 3672 /* SPI support? (SPI_M | SPI_S) */ 3673 #define SCB4_SPI 1u 3674 /* SPI externally clocked support? ('0': no, '1': yes) */ 3675 #define SCB4_SPI_EC 1u 3676 /* Externally clocked support? ('0': no, '1': yes) */ 3677 #define SCB4_EC 1u 3678 /* UART support? ('0': no, '1': yes) */ 3679 #define SCB4_UART 1u 3680 /* SPI or UART (SPI | UART) */ 3681 #define SCB4_SPI_UART 1u 3682 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3683 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3684 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3685 #define SCB4_EZ_DATA_NR 256u 3686 /* Command/response mode support? ('0': no, '1': yes) */ 3687 #define SCB4_CMD_RESP 0u 3688 /* EZ mode support? ('0': no, '1': yes) */ 3689 #define SCB4_EZ 1u 3690 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3691 #define SCB4_EZ_CMD_RESP 1u 3692 /* I2C slave with EZ mode (I2C_S & EZ) */ 3693 #define SCB4_I2C_S_EZ 1u 3694 /* SPI slave with EZ mode (SPI_S & EZ) */ 3695 #define SCB4_SPI_S_EZ 1u 3696 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3697 #define SCB4_MASTER_WIDTH 8u 3698 /* Number of used spi_select signals (max 4) */ 3699 #define SCB4_CHIP_TOP_SPI_SEL_NR 4u 3700 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3701 #define SCB4_CHIP_TOP_I2C_FAST_PLUS 1u 3702 /* DeepSleep support ('0':no, '1': yes) */ 3703 #define SCB5_DEEPSLEEP 0u 3704 /* I2C master support? ('0': no, '1': yes) */ 3705 #define SCB5_I2C_M 1u 3706 /* I2C slave support? ('0': no, '1': yes) */ 3707 #define SCB5_I2C_S 1u 3708 /* I2C glitch filters present? ('0': no, '1': yes) */ 3709 #define SCB5_I2C_GLITCH 1u 3710 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3711 #define SCB5_I2C_S_EC 0u 3712 /* I2C support? (I2C_M | I2C_S) */ 3713 #define SCB5_I2C 1u 3714 /* I2C externally clocked support? ('0': no, '1': yes) */ 3715 #define SCB5_I2C_EC 0u 3716 /* I2C master and slave support? (I2C_M & I2C_S) */ 3717 #define SCB5_I2C_M_S 1u 3718 /* SPI master support? ('0': no, '1': yes) */ 3719 #define SCB5_SPI_M 1u 3720 /* SPI slave support? ('0': no, '1': yes) */ 3721 #define SCB5_SPI_S 1u 3722 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3723 #define SCB5_SPI_S_EC 1u 3724 /* SPI support? (SPI_M | SPI_S) */ 3725 #define SCB5_SPI 1u 3726 /* SPI externally clocked support? ('0': no, '1': yes) */ 3727 #define SCB5_SPI_EC 1u 3728 /* Externally clocked support? ('0': no, '1': yes) */ 3729 #define SCB5_EC 1u 3730 /* UART support? ('0': no, '1': yes) */ 3731 #define SCB5_UART 1u 3732 /* SPI or UART (SPI | UART) */ 3733 #define SCB5_SPI_UART 1u 3734 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3735 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3736 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3737 #define SCB5_EZ_DATA_NR 256u 3738 /* Command/response mode support? ('0': no, '1': yes) */ 3739 #define SCB5_CMD_RESP 0u 3740 /* EZ mode support? ('0': no, '1': yes) */ 3741 #define SCB5_EZ 1u 3742 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3743 #define SCB5_EZ_CMD_RESP 1u 3744 /* I2C slave with EZ mode (I2C_S & EZ) */ 3745 #define SCB5_I2C_S_EZ 1u 3746 /* SPI slave with EZ mode (SPI_S & EZ) */ 3747 #define SCB5_SPI_S_EZ 1u 3748 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3749 #define SCB5_MASTER_WIDTH 8u 3750 /* Number of used spi_select signals (max 4) */ 3751 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 3752 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3753 #define SCB5_CHIP_TOP_I2C_FAST_PLUS 1u 3754 /* DeepSleep support ('0':no, '1': yes) */ 3755 #define SCB6_DEEPSLEEP 0u 3756 /* I2C master support? ('0': no, '1': yes) */ 3757 #define SCB6_I2C_M 1u 3758 /* I2C slave support? ('0': no, '1': yes) */ 3759 #define SCB6_I2C_S 1u 3760 /* I2C glitch filters present? ('0': no, '1': yes) */ 3761 #define SCB6_I2C_GLITCH 1u 3762 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3763 #define SCB6_I2C_S_EC 0u 3764 /* I2C support? (I2C_M | I2C_S) */ 3765 #define SCB6_I2C 1u 3766 /* I2C externally clocked support? ('0': no, '1': yes) */ 3767 #define SCB6_I2C_EC 0u 3768 /* I2C master and slave support? (I2C_M & I2C_S) */ 3769 #define SCB6_I2C_M_S 1u 3770 /* SPI master support? ('0': no, '1': yes) */ 3771 #define SCB6_SPI_M 1u 3772 /* SPI slave support? ('0': no, '1': yes) */ 3773 #define SCB6_SPI_S 1u 3774 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3775 #define SCB6_SPI_S_EC 1u 3776 /* SPI support? (SPI_M | SPI_S) */ 3777 #define SCB6_SPI 1u 3778 /* SPI externally clocked support? ('0': no, '1': yes) */ 3779 #define SCB6_SPI_EC 1u 3780 /* Externally clocked support? ('0': no, '1': yes) */ 3781 #define SCB6_EC 1u 3782 /* UART support? ('0': no, '1': yes) */ 3783 #define SCB6_UART 1u 3784 /* SPI or UART (SPI | UART) */ 3785 #define SCB6_SPI_UART 1u 3786 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3787 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3788 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3789 #define SCB6_EZ_DATA_NR 256u 3790 /* Command/response mode support? ('0': no, '1': yes) */ 3791 #define SCB6_CMD_RESP 0u 3792 /* EZ mode support? ('0': no, '1': yes) */ 3793 #define SCB6_EZ 1u 3794 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3795 #define SCB6_EZ_CMD_RESP 1u 3796 /* I2C slave with EZ mode (I2C_S & EZ) */ 3797 #define SCB6_I2C_S_EZ 1u 3798 /* SPI slave with EZ mode (SPI_S & EZ) */ 3799 #define SCB6_SPI_S_EZ 1u 3800 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3801 #define SCB6_MASTER_WIDTH 8u 3802 /* Number of used spi_select signals (max 4) */ 3803 #define SCB6_CHIP_TOP_SPI_SEL_NR 4u 3804 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3805 #define SCB6_CHIP_TOP_I2C_FAST_PLUS 1u 3806 /* DeepSleep support ('0':no, '1': yes) */ 3807 #define SCB7_DEEPSLEEP 0u 3808 /* I2C master support? ('0': no, '1': yes) */ 3809 #define SCB7_I2C_M 1u 3810 /* I2C slave support? ('0': no, '1': yes) */ 3811 #define SCB7_I2C_S 1u 3812 /* I2C glitch filters present? ('0': no, '1': yes) */ 3813 #define SCB7_I2C_GLITCH 1u 3814 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3815 #define SCB7_I2C_S_EC 0u 3816 /* I2C support? (I2C_M | I2C_S) */ 3817 #define SCB7_I2C 1u 3818 /* I2C externally clocked support? ('0': no, '1': yes) */ 3819 #define SCB7_I2C_EC 0u 3820 /* I2C master and slave support? (I2C_M & I2C_S) */ 3821 #define SCB7_I2C_M_S 1u 3822 /* SPI master support? ('0': no, '1': yes) */ 3823 #define SCB7_SPI_M 1u 3824 /* SPI slave support? ('0': no, '1': yes) */ 3825 #define SCB7_SPI_S 1u 3826 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3827 #define SCB7_SPI_S_EC 1u 3828 /* SPI support? (SPI_M | SPI_S) */ 3829 #define SCB7_SPI 1u 3830 /* SPI externally clocked support? ('0': no, '1': yes) */ 3831 #define SCB7_SPI_EC 1u 3832 /* Externally clocked support? ('0': no, '1': yes) */ 3833 #define SCB7_EC 1u 3834 /* UART support? ('0': no, '1': yes) */ 3835 #define SCB7_UART 1u 3836 /* SPI or UART (SPI | UART) */ 3837 #define SCB7_SPI_UART 1u 3838 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3839 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3840 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3841 #define SCB7_EZ_DATA_NR 256u 3842 /* Command/response mode support? ('0': no, '1': yes) */ 3843 #define SCB7_CMD_RESP 0u 3844 /* EZ mode support? ('0': no, '1': yes) */ 3845 #define SCB7_EZ 1u 3846 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3847 #define SCB7_EZ_CMD_RESP 1u 3848 /* I2C slave with EZ mode (I2C_S & EZ) */ 3849 #define SCB7_I2C_S_EZ 1u 3850 /* SPI slave with EZ mode (SPI_S & EZ) */ 3851 #define SCB7_SPI_S_EZ 1u 3852 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3853 #define SCB7_MASTER_WIDTH 8u 3854 /* Number of used spi_select signals (max 4) */ 3855 #define SCB7_CHIP_TOP_SPI_SEL_NR 4u 3856 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3857 #define SCB7_CHIP_TOP_I2C_FAST_PLUS 1u 3858 /* SONOS Flash is used or not ('0': no, '1': yes) */ 3859 #define SFLASH_FLASHC_IS_SONOS 0u 3860 /* WOUND_PRESENT or not ('0': no, '1': yes) */ 3861 #define SFLASH_WOUND_PRESENT 0u 3862 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 3863 #define SRSS_ULP_VARIANT 0u 3864 /* HT variant. Must be 1 when targeting S40E and 0 otherwise. */ 3865 #define SRSS_HT_VARIANT 1u 3866 /* Number of regulator modules instantiated within SRSS. Must be > 0. */ 3867 #define SRSS_NUM_ACTREG_PWRMOD 3u 3868 /* Number of shorting switches between vccd and vccact. Must be > 0. */ 3869 #define SRSS_NUM_ACTIVE_SWITCH 4u 3870 /* ULP linear regulator system is present */ 3871 #define SRSS_ULPLINREG_PRESENT 0u 3872 /* HT linear regulator system is present */ 3873 #define SRSS_HTLINREG_PRESENT 1u 3874 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 3875 system (ULPLINREG_PRESENT==1). */ 3876 #define SRSS_SIMOBUCK_PRESENT 0u 3877 /* Precision ILO (PILO) is present */ 3878 #define SRSS_PILO_PRESENT 0u 3879 /* External Crystal Oscillator is present (high frequency) */ 3880 #define SRSS_ECO_PRESENT 1u 3881 /* System Buck-Boost is present */ 3882 #define SRSS_SYSBB_PRESENT 0u 3883 /* Number of PWR_HIB_DATA registers. Min is zero. */ 3884 #define SRSS_NUM_HIBDATA 1u 3885 /* Number of clock paths. Must be > 0. Recommend 3886 NUM_CLKPATH>=NUM_PLL+CSV_PRESENT+2. CSV and FLL requires special paths, and 3887 one extra is recommended for programming flexibility. */ 3888 #define SRSS_NUM_CLKPATH 4u 3889 /* Number of PLLs present. Must be < NUM_CLKPATH */ 3890 #define SRSS_NUM_PLL 1u 3891 /* Number of HFCLK roots present. Must be > 0. Recommend NUM_HFROOT=<# chipwide 3892 roots>+CSV_PRESENT. */ 3893 #define SRSS_NUM_HFROOT 3u 3894 /* Number of DSI inputs into clock muxes. This is used for logic optimization. 3895 Must be > 0 */ 3896 #define SRSS_NUM_DSI 0u 3897 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 3898 #define SRSS_ALTHF_PRESENT 0u 3899 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 3900 #define SRSS_ALTLF_PRESENT 0u 3901 /* Backup domain is present. See VBCK_PRESENT for whether it is supplied by vddd 3902 or by an independent vbackup supply. */ 3903 #define SRSS_BACKUP_PRESENT 1u 3904 /* CSV present. User must add one NUM_CLKPATH and one NUM_HFROOT to monitor ILO0 3905 with CSV_HF_REF clock. */ 3906 #define SRSS_CSV_PRESENT 1u 3907 /* Number of multi-counter watchdog timers. Min is zero. */ 3908 #define SRSS_NUM_MCWDT 2u 3909 /* Use the hardened clkactfllmux block */ 3910 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 3911 /* Number of clock paths, including direct paths in hardened clkactfllmux block */ 3912 #define SRSS_HARD_CLKPATH 8u 3913 /* Number of clock paths with muxes in hardened clkactfllmux block */ 3914 #define SRSS_HARD_CLKPATHMUX 8u 3915 /* Number of HFCLKS present in hardened clkactfllmux block */ 3916 #define SRSS_HARD_HFROOT 8u 3917 /* ECO mux is present in hardened clkactfllmux block */ 3918 #define SRSS_HARD_ECOMUX_PRESENT 1u 3919 /* ALTHF mux is present in hardened clkactfllmux block */ 3920 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 3921 /* LPECO mux is present in hardened clkactfllmux block */ 3922 #define SRSS_HARD_LPECOMUX_PRESENT 1u 3923 /* POR present. */ 3924 #define SRSS_POR_PRESENT 1u 3925 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 3926 or SIMOBUCK_PRESENT. */ 3927 #define SRSS_BUCKCTL_PRESENT 0u 3928 /* Low-current SISO buck core regulator is present. Only compatible with ULP 3929 linear regulator system (ULPLINREG_PRESENT==1). */ 3930 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 3931 /* HT linear regulator system is present */ 3932 #define SRSS_S40E_HTREGHC_PRESENT 0u 3933 /* PMIC control of vccd is present (without REGHC). */ 3934 #define SRSS_S40E_PMIC_PRESENT 0u 3935 /* Number of 400MHz PLLs present. */ 3936 #define SRSS_NUM_PLL400M 0u 3937 /* Total number of PLLs present. */ 3938 #define SRSS_NUM_TOTAL_PLL 1u 3939 /* Mask of DIRECT_MUX defaults. For each clock root i, if bit[i] is low the 3940 DIRECT_MUX defaults to IMO. If bit[0] is high, the DIRECT_MUX selects the 3941 output of ROOT_MUX. For backward compatibility, M4 systems can have all mask 3942 bits high. BootROM needs either Bit0 high or a code change to pick predivider 3943 output before using the FLL. */ 3944 #define SRSS_MASK_DIRECTMUX_DEF 0x0000FFFFu 3945 /* Mask of which HFCLK roots are enabled when the debugger requests power up 3946 (CDBGPWRUPREQ). For each clock root i, SRSS enables the clock in response to 3947 CDBGPWRUPREQ, if bit[i] of mask is high. SRSS automatically enables clk_hf0, 3948 regardless of setting of mask bit0. */ 3949 #define SRSS_MASK_DEBUG_CLK 0x0000FFFFu 3950 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 3951 #define SRSS_BACKUP_VBCK_PRESENT 0u 3952 /* Alarm1 present in RTC */ 3953 #define SRSS_BACKUP_ALM1_PRESENT 1u 3954 /* Alarm2 present in RTC */ 3955 #define SRSS_BACKUP_ALM2_PRESENT 1u 3956 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 3957 #define SRSS_BACKUP_BMEM_PRESENT 0u 3958 /* Number of Backup registers to include (each is 32b). Only used when 3959 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 3960 #define SRSS_BACKUP_NUM_BREG 4u 3961 /* Low power external crystal oscillator (LPECO) is present. */ 3962 #define SRSS_BACKUP_S40E_LPECO_PRESENT 0u 3963 /* ULP variant. Must be 1 when targeting S40S and 0 otherwise. */ 3964 #define SRSS_CLK_TRIM_PLL400M_ULP_VARIANT 0u 3965 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 3966 mask indicates presence of a CSV. */ 3967 #define SRSS_CSV_HF_MASK_HFCSV 7u 3968 /* Number of input triggers per counter only routed to one counter (0..8) */ 3969 #define TCPWM_TR_ONE_CNT_NR 3u 3970 /* Number of input triggers routed to all counters (0..254), 3971 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 3972 #define TCPWM_TR_ALL_CNT_NR 27u 3973 /* Number of TCPWM counter groups (1..4) */ 3974 #define TCPWM_GRP_NR 3u 3975 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3976 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 16u 3977 /* Second Capture / Compare Unit is present (0, 1) */ 3978 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 1u 3979 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3980 group_CC1_PRESENT = 1 */ 3981 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 3982 /* Stepper Motor Control features are present (0, 1). */ 3983 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 3984 /* Number of counters per TCPWM group (1..256) */ 3985 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 63u 3986 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3987 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 3988 /* Second Capture / Compare Unit is present (0, 1) */ 3989 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 3990 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 3991 group_CC1_PRESENT = 1 */ 3992 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 3993 /* Stepper Motor Control features are present (0, 1). */ 3994 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 1u 3995 /* Number of counters per TCPWM group (1..256) */ 3996 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 12u 3997 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 3998 #define TCPWM_GRP_NR2_CNT_GRP_CNT_WIDTH 32u 3999 /* Second Capture / Compare Unit is present (0, 1) */ 4000 #define TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT 1u 4001 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 4002 group_CC1_PRESENT = 1 */ 4003 #define TCPWM_GRP_NR2_CNT_GRP_AMC_PRESENT 0u 4004 /* Stepper Motor Control features are present (0, 1). */ 4005 #define TCPWM_GRP_NR2_CNT_GRP_SMC_PRESENT 0u 4006 /* Number of counters per TCPWM group (1..256) */ 4007 #define TCPWM_GRP_NR2_GRP_GRP_CNT_NR 8u 4008 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 4009 #define TCPWM_MASTER_WIDTH 8u 4010 4011 /* MMIO Targets Defines */ 4012 /* MMIO1.CRYPTO */ 4013 #define CY_MMIO_CRYPTO_GROUP_NR 1u 4014 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 4015 /* MMIO2.CPUSS */ 4016 #define CY_MMIO_CPUSS_GROUP_NR 2u 4017 #define CY_MMIO_CPUSS_SLAVE_NR 0u 4018 /* MMIO2.FAULT */ 4019 #define CY_MMIO_FAULT_GROUP_NR 2u 4020 #define CY_MMIO_FAULT_SLAVE_NR 1u 4021 /* MMIO2.IPC */ 4022 #define CY_MMIO_IPC_GROUP_NR 2u 4023 #define CY_MMIO_IPC_SLAVE_NR 2u 4024 /* MMIO2.PROT */ 4025 #define CY_MMIO_PROT_GROUP_NR 2u 4026 #define CY_MMIO_PROT_SLAVE_NR 3u 4027 /* MMIO2.FLASHC */ 4028 #define CY_MMIO_FLASHC_GROUP_NR 2u 4029 #define CY_MMIO_FLASHC_SLAVE_NR 4u 4030 /* MMIO2.SRSS */ 4031 #define CY_MMIO_SRSS_GROUP_NR 2u 4032 #define CY_MMIO_SRSS_SLAVE_NR 5u 4033 /* MMIO2.BACKUP */ 4034 #define CY_MMIO_BACKUP_GROUP_NR 2u 4035 #define CY_MMIO_BACKUP_SLAVE_NR 6u 4036 /* MMIO2.DW */ 4037 #define CY_MMIO_DW_GROUP_NR 2u 4038 #define CY_MMIO_DW_SLAVE_NR 7u 4039 /* MMIO2.DMAC */ 4040 #define CY_MMIO_DMAC_GROUP_NR 2u 4041 #define CY_MMIO_DMAC_SLAVE_NR 9u 4042 /* MMIO2.EFUSE */ 4043 #define CY_MMIO_EFUSE_GROUP_NR 2u 4044 #define CY_MMIO_EFUSE_SLAVE_NR 10u 4045 /* MMIO2.DFT */ 4046 #define CY_MMIO_DFT_GROUP_NR 2u 4047 #define CY_MMIO_DFT_SLAVE_NR 11u 4048 /* MMIO3.HSIOM */ 4049 #define CY_MMIO_HSIOM_GROUP_NR 3u 4050 #define CY_MMIO_HSIOM_SLAVE_NR 0u 4051 /* MMIO3.GPIO */ 4052 #define CY_MMIO_GPIO_GROUP_NR 3u 4053 #define CY_MMIO_GPIO_SLAVE_NR 1u 4054 /* MMIO3.SMARTIO */ 4055 #define CY_MMIO_SMARTIO_GROUP_NR 3u 4056 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 4057 /* MMIO3.TCPWM0 */ 4058 #define CY_MMIO_TCPWM0_GROUP_NR 3u 4059 #define CY_MMIO_TCPWM0_SLAVE_NR 3u 4060 /* MMIO3.EVTGEN0 */ 4061 #define CY_MMIO_EVTGEN0_GROUP_NR 3u 4062 #define CY_MMIO_EVTGEN0_SLAVE_NR 4u 4063 /* MMIO5.LIN0 */ 4064 #define CY_MMIO_LIN0_GROUP_NR 5u 4065 #define CY_MMIO_LIN0_SLAVE_NR 0u 4066 /* MMIO5.CXPI0 */ 4067 #define CY_MMIO_CXPI0_GROUP_NR 5u 4068 #define CY_MMIO_CXPI0_SLAVE_NR 1u 4069 /* MMIO5.CANFD0 */ 4070 #define CY_MMIO_CANFD0_GROUP_NR 5u 4071 #define CY_MMIO_CANFD0_SLAVE_NR 2u 4072 /* MMIO5.CANFD1 */ 4073 #define CY_MMIO_CANFD1_GROUP_NR 5u 4074 #define CY_MMIO_CANFD1_SLAVE_NR 3u 4075 /* MMIO6.SCB0 */ 4076 #define CY_MMIO_SCB0_GROUP_NR 6u 4077 #define CY_MMIO_SCB0_SLAVE_NR 0u 4078 /* MMIO6.SCB1 */ 4079 #define CY_MMIO_SCB1_GROUP_NR 6u 4080 #define CY_MMIO_SCB1_SLAVE_NR 1u 4081 /* MMIO6.SCB2 */ 4082 #define CY_MMIO_SCB2_GROUP_NR 6u 4083 #define CY_MMIO_SCB2_SLAVE_NR 2u 4084 /* MMIO6.SCB3 */ 4085 #define CY_MMIO_SCB3_GROUP_NR 6u 4086 #define CY_MMIO_SCB3_SLAVE_NR 3u 4087 /* MMIO6.SCB4 */ 4088 #define CY_MMIO_SCB4_GROUP_NR 6u 4089 #define CY_MMIO_SCB4_SLAVE_NR 4u 4090 /* MMIO6.SCB5 */ 4091 #define CY_MMIO_SCB5_GROUP_NR 6u 4092 #define CY_MMIO_SCB5_SLAVE_NR 5u 4093 /* MMIO6.SCB6 */ 4094 #define CY_MMIO_SCB6_GROUP_NR 6u 4095 #define CY_MMIO_SCB6_SLAVE_NR 6u 4096 /* MMIO6.SCB7 */ 4097 #define CY_MMIO_SCB7_GROUP_NR 6u 4098 #define CY_MMIO_SCB7_SLAVE_NR 7u 4099 /* MMIO9.PASS0 */ 4100 #define CY_MMIO_PASS0_GROUP_NR 9u 4101 #define CY_MMIO_PASS0_SLAVE_NR 0u 4102 4103 /* Backward compatibility definitions */ 4104 #define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR 4105 #define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR 4106 4107 /* Protection regions */ 4108 typedef enum 4109 { 4110 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00002000 */ 4111 PROT_PERI_SECURE = 1, /* Address 0x40002000, size 0x00000004 */ 4112 PROT_PERI_GR0_GROUP = 2, /* Address 0x40004010, size 0x00000004 */ 4113 PROT_PERI_GR1_GROUP = 3, /* Address 0x40004030, size 0x00000004 */ 4114 PROT_PERI_GR2_GROUP = 4, /* Address 0x40004050, size 0x00000004 */ 4115 PROT_PERI_GR3_GROUP = 5, /* Address 0x40004060, size 0x00000020 */ 4116 PROT_PERI_GR5_GROUP = 6, /* Address 0x400040a0, size 0x00000020 */ 4117 PROT_PERI_GR6_GROUP = 7, /* Address 0x400040c0, size 0x00000020 */ 4118 PROT_PERI_GR9_GROUP = 8, /* Address 0x40004120, size 0x00000020 */ 4119 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 4120 PROT_CRYPTO_MAIN = 10, /* Address 0x40100000, size 0x00000400 */ 4121 PROT_CRYPTO_CRYPTO = 11, /* Address 0x40101000, size 0x00000800 */ 4122 PROT_CRYPTO_BOOT = 12, /* Address 0x40102000, size 0x00000100 */ 4123 PROT_CRYPTO_KEY0 = 13, /* Address 0x40102100, size 0x00000004 */ 4124 PROT_CRYPTO_KEY1 = 14, /* Address 0x40102120, size 0x00000004 */ 4125 PROT_CRYPTO_BUF = 15, /* Address 0x40108000, size 0x00002000 */ 4126 PROT_CPUSS_CM4 = 16, /* Address 0x40200000, size 0x00000400 */ 4127 PROT_CPUSS_CM0 = 17, /* Address 0x40201000, size 0x00001000 */ 4128 PROT_CPUSS_BOOT = 18, /* Address 0x40202000, size 0x00000200 */ 4129 PROT_CPUSS_CM0_INT = 19, /* Address 0x40208000, size 0x00000800 */ 4130 PROT_CPUSS_CM4_INT = 20, /* Address 0x4020a000, size 0x00000800 */ 4131 PROT_FAULT_STRUCT0_MAIN = 21, /* Address 0x40210000, size 0x00000100 */ 4132 PROT_FAULT_STRUCT1_MAIN = 22, /* Address 0x40210100, size 0x00000100 */ 4133 PROT_FAULT_STRUCT2_MAIN = 23, /* Address 0x40210200, size 0x00000100 */ 4134 PROT_FAULT_STRUCT3_MAIN = 24, /* Address 0x40210300, size 0x00000100 */ 4135 PROT_IPC_STRUCT0_IPC = 25, /* Address 0x40220000, size 0x00000020 */ 4136 PROT_IPC_STRUCT1_IPC = 26, /* Address 0x40220020, size 0x00000020 */ 4137 PROT_IPC_STRUCT2_IPC = 27, /* Address 0x40220040, size 0x00000020 */ 4138 PROT_IPC_STRUCT3_IPC = 28, /* Address 0x40220060, size 0x00000020 */ 4139 PROT_IPC_STRUCT4_IPC = 29, /* Address 0x40220080, size 0x00000020 */ 4140 PROT_IPC_STRUCT5_IPC = 30, /* Address 0x402200a0, size 0x00000020 */ 4141 PROT_IPC_STRUCT6_IPC = 31, /* Address 0x402200c0, size 0x00000020 */ 4142 PROT_IPC_STRUCT7_IPC = 32, /* Address 0x402200e0, size 0x00000020 */ 4143 PROT_IPC_INTR_STRUCT0_INTR = 33, /* Address 0x40221000, size 0x00000010 */ 4144 PROT_IPC_INTR_STRUCT1_INTR = 34, /* Address 0x40221020, size 0x00000010 */ 4145 PROT_IPC_INTR_STRUCT2_INTR = 35, /* Address 0x40221040, size 0x00000010 */ 4146 PROT_IPC_INTR_STRUCT3_INTR = 36, /* Address 0x40221060, size 0x00000010 */ 4147 PROT_IPC_INTR_STRUCT4_INTR = 37, /* Address 0x40221080, size 0x00000010 */ 4148 PROT_IPC_INTR_STRUCT5_INTR = 38, /* Address 0x402210a0, size 0x00000010 */ 4149 PROT_IPC_INTR_STRUCT6_INTR = 39, /* Address 0x402210c0, size 0x00000010 */ 4150 PROT_IPC_INTR_STRUCT7_INTR = 40, /* Address 0x402210e0, size 0x00000010 */ 4151 PROT_PROT_SMPU_MAIN = 41, /* Address 0x40230000, size 0x00000040 */ 4152 PROT_PROT_MPU0_MAIN = 42, /* Address 0x40234000, size 0x00000004 */ 4153 PROT_PROT_MPU14_MAIN = 43, /* Address 0x40237800, size 0x00000004 */ 4154 PROT_PROT_MPU15_MAIN = 44, /* Address 0x40237c00, size 0x00000400 */ 4155 PROT_FLASHC_MAIN = 45, /* Address 0x40240000, size 0x00000008 */ 4156 PROT_FLASHC_CMD = 46, /* Address 0x40240008, size 0x00000004 */ 4157 PROT_FLASHC_DFT = 47, /* Address 0x40240200, size 0x00000100 */ 4158 PROT_FLASHC_CM0 = 48, /* Address 0x40240400, size 0x00000080 */ 4159 PROT_FLASHC_CM4 = 49, /* Address 0x40240480, size 0x00000080 */ 4160 PROT_FLASHC_CRYPTO = 50, /* Address 0x40240500, size 0x00000004 */ 4161 PROT_FLASHC_DW0 = 51, /* Address 0x40240580, size 0x00000004 */ 4162 PROT_FLASHC_DW1 = 52, /* Address 0x40240600, size 0x00000004 */ 4163 PROT_FLASHC_DMAC = 53, /* Address 0x40240680, size 0x00000004 */ 4164 PROT_FLASHC_FlashMgmt = 54, /* Address 0x4024f000, size 0x00000080 */ 4165 PROT_FLASHC_MainSafety = 55, /* Address 0x4024f400, size 0x00000008 */ 4166 PROT_FLASHC_WorkSafety = 56, /* Address 0x4024f500, size 0x00000004 */ 4167 PROT_SRSS_GENERAL = 57, /* Address 0x40260000, size 0x00000400 */ 4168 PROT_SRSS_MAIN = 58, /* Address 0x40261000, size 0x00001000 */ 4169 PROT_SRSS_SECURE = 59, /* Address 0x40262000, size 0x00002000 */ 4170 PROT_MCWDT0_CONFIG = 60, /* Address 0x40268000, size 0x00000080 */ 4171 PROT_MCWDT1_CONFIG = 61, /* Address 0x40268100, size 0x00000080 */ 4172 PROT_MCWDT0_MAIN = 62, /* Address 0x40268080, size 0x00000040 */ 4173 PROT_MCWDT1_MAIN = 63, /* Address 0x40268180, size 0x00000040 */ 4174 PROT_WDT_CONFIG = 64, /* Address 0x4026c000, size 0x00000020 */ 4175 PROT_WDT_MAIN = 65, /* Address 0x4026c040, size 0x00000020 */ 4176 PROT_BACKUP_BACKUP = 66, /* Address 0x40270000, size 0x00010000 */ 4177 PROT_DW0_DW = 67, /* Address 0x40280000, size 0x00000100 */ 4178 PROT_DW1_DW = 68, /* Address 0x40290000, size 0x00000100 */ 4179 PROT_DW0_DW_CRC = 69, /* Address 0x40280100, size 0x00000080 */ 4180 PROT_DW1_DW_CRC = 70, /* Address 0x40290100, size 0x00000080 */ 4181 PROT_DW0_CH_STRUCT0_CH = 71, /* Address 0x40288000, size 0x00000040 */ 4182 PROT_DW0_CH_STRUCT1_CH = 72, /* Address 0x40288040, size 0x00000040 */ 4183 PROT_DW0_CH_STRUCT2_CH = 73, /* Address 0x40288080, size 0x00000040 */ 4184 PROT_DW0_CH_STRUCT3_CH = 74, /* Address 0x402880c0, size 0x00000040 */ 4185 PROT_DW0_CH_STRUCT4_CH = 75, /* Address 0x40288100, size 0x00000040 */ 4186 PROT_DW0_CH_STRUCT5_CH = 76, /* Address 0x40288140, size 0x00000040 */ 4187 PROT_DW0_CH_STRUCT6_CH = 77, /* Address 0x40288180, size 0x00000040 */ 4188 PROT_DW0_CH_STRUCT7_CH = 78, /* Address 0x402881c0, size 0x00000040 */ 4189 PROT_DW0_CH_STRUCT8_CH = 79, /* Address 0x40288200, size 0x00000040 */ 4190 PROT_DW0_CH_STRUCT9_CH = 80, /* Address 0x40288240, size 0x00000040 */ 4191 PROT_DW0_CH_STRUCT10_CH = 81, /* Address 0x40288280, size 0x00000040 */ 4192 PROT_DW0_CH_STRUCT11_CH = 82, /* Address 0x402882c0, size 0x00000040 */ 4193 PROT_DW0_CH_STRUCT12_CH = 83, /* Address 0x40288300, size 0x00000040 */ 4194 PROT_DW0_CH_STRUCT13_CH = 84, /* Address 0x40288340, size 0x00000040 */ 4195 PROT_DW0_CH_STRUCT14_CH = 85, /* Address 0x40288380, size 0x00000040 */ 4196 PROT_DW0_CH_STRUCT15_CH = 86, /* Address 0x402883c0, size 0x00000040 */ 4197 PROT_DW0_CH_STRUCT16_CH = 87, /* Address 0x40288400, size 0x00000040 */ 4198 PROT_DW0_CH_STRUCT17_CH = 88, /* Address 0x40288440, size 0x00000040 */ 4199 PROT_DW0_CH_STRUCT18_CH = 89, /* Address 0x40288480, size 0x00000040 */ 4200 PROT_DW0_CH_STRUCT19_CH = 90, /* Address 0x402884c0, size 0x00000040 */ 4201 PROT_DW0_CH_STRUCT20_CH = 91, /* Address 0x40288500, size 0x00000040 */ 4202 PROT_DW0_CH_STRUCT21_CH = 92, /* Address 0x40288540, size 0x00000040 */ 4203 PROT_DW0_CH_STRUCT22_CH = 93, /* Address 0x40288580, size 0x00000040 */ 4204 PROT_DW0_CH_STRUCT23_CH = 94, /* Address 0x402885c0, size 0x00000040 */ 4205 PROT_DW0_CH_STRUCT24_CH = 95, /* Address 0x40288600, size 0x00000040 */ 4206 PROT_DW0_CH_STRUCT25_CH = 96, /* Address 0x40288640, size 0x00000040 */ 4207 PROT_DW0_CH_STRUCT26_CH = 97, /* Address 0x40288680, size 0x00000040 */ 4208 PROT_DW0_CH_STRUCT27_CH = 98, /* Address 0x402886c0, size 0x00000040 */ 4209 PROT_DW0_CH_STRUCT28_CH = 99, /* Address 0x40288700, size 0x00000040 */ 4210 PROT_DW0_CH_STRUCT29_CH = 100, /* Address 0x40288740, size 0x00000040 */ 4211 PROT_DW0_CH_STRUCT30_CH = 101, /* Address 0x40288780, size 0x00000040 */ 4212 PROT_DW0_CH_STRUCT31_CH = 102, /* Address 0x402887c0, size 0x00000040 */ 4213 PROT_DW0_CH_STRUCT32_CH = 103, /* Address 0x40288800, size 0x00000040 */ 4214 PROT_DW0_CH_STRUCT33_CH = 104, /* Address 0x40288840, size 0x00000040 */ 4215 PROT_DW0_CH_STRUCT34_CH = 105, /* Address 0x40288880, size 0x00000040 */ 4216 PROT_DW0_CH_STRUCT35_CH = 106, /* Address 0x402888c0, size 0x00000040 */ 4217 PROT_DW0_CH_STRUCT36_CH = 107, /* Address 0x40288900, size 0x00000040 */ 4218 PROT_DW0_CH_STRUCT37_CH = 108, /* Address 0x40288940, size 0x00000040 */ 4219 PROT_DW0_CH_STRUCT38_CH = 109, /* Address 0x40288980, size 0x00000040 */ 4220 PROT_DW0_CH_STRUCT39_CH = 110, /* Address 0x402889c0, size 0x00000040 */ 4221 PROT_DW0_CH_STRUCT40_CH = 111, /* Address 0x40288a00, size 0x00000040 */ 4222 PROT_DW0_CH_STRUCT41_CH = 112, /* Address 0x40288a40, size 0x00000040 */ 4223 PROT_DW0_CH_STRUCT42_CH = 113, /* Address 0x40288a80, size 0x00000040 */ 4224 PROT_DW0_CH_STRUCT43_CH = 114, /* Address 0x40288ac0, size 0x00000040 */ 4225 PROT_DW0_CH_STRUCT44_CH = 115, /* Address 0x40288b00, size 0x00000040 */ 4226 PROT_DW0_CH_STRUCT45_CH = 116, /* Address 0x40288b40, size 0x00000040 */ 4227 PROT_DW0_CH_STRUCT46_CH = 117, /* Address 0x40288b80, size 0x00000040 */ 4228 PROT_DW0_CH_STRUCT47_CH = 118, /* Address 0x40288bc0, size 0x00000040 */ 4229 PROT_DW0_CH_STRUCT48_CH = 119, /* Address 0x40288c00, size 0x00000040 */ 4230 PROT_DW0_CH_STRUCT49_CH = 120, /* Address 0x40288c40, size 0x00000040 */ 4231 PROT_DW0_CH_STRUCT50_CH = 121, /* Address 0x40288c80, size 0x00000040 */ 4232 PROT_DW0_CH_STRUCT51_CH = 122, /* Address 0x40288cc0, size 0x00000040 */ 4233 PROT_DW0_CH_STRUCT52_CH = 123, /* Address 0x40288d00, size 0x00000040 */ 4234 PROT_DW0_CH_STRUCT53_CH = 124, /* Address 0x40288d40, size 0x00000040 */ 4235 PROT_DW0_CH_STRUCT54_CH = 125, /* Address 0x40288d80, size 0x00000040 */ 4236 PROT_DW0_CH_STRUCT55_CH = 126, /* Address 0x40288dc0, size 0x00000040 */ 4237 PROT_DW0_CH_STRUCT56_CH = 127, /* Address 0x40288e00, size 0x00000040 */ 4238 PROT_DW0_CH_STRUCT57_CH = 128, /* Address 0x40288e40, size 0x00000040 */ 4239 PROT_DW0_CH_STRUCT58_CH = 129, /* Address 0x40288e80, size 0x00000040 */ 4240 PROT_DW0_CH_STRUCT59_CH = 130, /* Address 0x40288ec0, size 0x00000040 */ 4241 PROT_DW0_CH_STRUCT60_CH = 131, /* Address 0x40288f00, size 0x00000040 */ 4242 PROT_DW0_CH_STRUCT61_CH = 132, /* Address 0x40288f40, size 0x00000040 */ 4243 PROT_DW0_CH_STRUCT62_CH = 133, /* Address 0x40288f80, size 0x00000040 */ 4244 PROT_DW0_CH_STRUCT63_CH = 134, /* Address 0x40288fc0, size 0x00000040 */ 4245 PROT_DW0_CH_STRUCT64_CH = 135, /* Address 0x40289000, size 0x00000040 */ 4246 PROT_DW0_CH_STRUCT65_CH = 136, /* Address 0x40289040, size 0x00000040 */ 4247 PROT_DW0_CH_STRUCT66_CH = 137, /* Address 0x40289080, size 0x00000040 */ 4248 PROT_DW0_CH_STRUCT67_CH = 138, /* Address 0x402890c0, size 0x00000040 */ 4249 PROT_DW0_CH_STRUCT68_CH = 139, /* Address 0x40289100, size 0x00000040 */ 4250 PROT_DW0_CH_STRUCT69_CH = 140, /* Address 0x40289140, size 0x00000040 */ 4251 PROT_DW0_CH_STRUCT70_CH = 141, /* Address 0x40289180, size 0x00000040 */ 4252 PROT_DW0_CH_STRUCT71_CH = 142, /* Address 0x402891c0, size 0x00000040 */ 4253 PROT_DW0_CH_STRUCT72_CH = 143, /* Address 0x40289200, size 0x00000040 */ 4254 PROT_DW0_CH_STRUCT73_CH = 144, /* Address 0x40289240, size 0x00000040 */ 4255 PROT_DW0_CH_STRUCT74_CH = 145, /* Address 0x40289280, size 0x00000040 */ 4256 PROT_DW0_CH_STRUCT75_CH = 146, /* Address 0x402892c0, size 0x00000040 */ 4257 PROT_DW0_CH_STRUCT76_CH = 147, /* Address 0x40289300, size 0x00000040 */ 4258 PROT_DW0_CH_STRUCT77_CH = 148, /* Address 0x40289340, size 0x00000040 */ 4259 PROT_DW0_CH_STRUCT78_CH = 149, /* Address 0x40289380, size 0x00000040 */ 4260 PROT_DW0_CH_STRUCT79_CH = 150, /* Address 0x402893c0, size 0x00000040 */ 4261 PROT_DW0_CH_STRUCT80_CH = 151, /* Address 0x40289400, size 0x00000040 */ 4262 PROT_DW0_CH_STRUCT81_CH = 152, /* Address 0x40289440, size 0x00000040 */ 4263 PROT_DW0_CH_STRUCT82_CH = 153, /* Address 0x40289480, size 0x00000040 */ 4264 PROT_DW0_CH_STRUCT83_CH = 154, /* Address 0x402894c0, size 0x00000040 */ 4265 PROT_DW0_CH_STRUCT84_CH = 155, /* Address 0x40289500, size 0x00000040 */ 4266 PROT_DW0_CH_STRUCT85_CH = 156, /* Address 0x40289540, size 0x00000040 */ 4267 PROT_DW0_CH_STRUCT86_CH = 157, /* Address 0x40289580, size 0x00000040 */ 4268 PROT_DW0_CH_STRUCT87_CH = 158, /* Address 0x402895c0, size 0x00000040 */ 4269 PROT_DW0_CH_STRUCT88_CH = 159, /* Address 0x40289600, size 0x00000040 */ 4270 PROT_DW0_CH_STRUCT89_CH = 160, /* Address 0x40289640, size 0x00000040 */ 4271 PROT_DW0_CH_STRUCT90_CH = 161, /* Address 0x40289680, size 0x00000040 */ 4272 PROT_DW0_CH_STRUCT91_CH = 162, /* Address 0x402896c0, size 0x00000040 */ 4273 PROT_DW1_CH_STRUCT0_CH = 163, /* Address 0x40298000, size 0x00000040 */ 4274 PROT_DW1_CH_STRUCT1_CH = 164, /* Address 0x40298040, size 0x00000040 */ 4275 PROT_DW1_CH_STRUCT2_CH = 165, /* Address 0x40298080, size 0x00000040 */ 4276 PROT_DW1_CH_STRUCT3_CH = 166, /* Address 0x402980c0, size 0x00000040 */ 4277 PROT_DW1_CH_STRUCT4_CH = 167, /* Address 0x40298100, size 0x00000040 */ 4278 PROT_DW1_CH_STRUCT5_CH = 168, /* Address 0x40298140, size 0x00000040 */ 4279 PROT_DW1_CH_STRUCT6_CH = 169, /* Address 0x40298180, size 0x00000040 */ 4280 PROT_DW1_CH_STRUCT7_CH = 170, /* Address 0x402981c0, size 0x00000040 */ 4281 PROT_DW1_CH_STRUCT8_CH = 171, /* Address 0x40298200, size 0x00000040 */ 4282 PROT_DW1_CH_STRUCT9_CH = 172, /* Address 0x40298240, size 0x00000040 */ 4283 PROT_DW1_CH_STRUCT10_CH = 173, /* Address 0x40298280, size 0x00000040 */ 4284 PROT_DW1_CH_STRUCT11_CH = 174, /* Address 0x402982c0, size 0x00000040 */ 4285 PROT_DW1_CH_STRUCT12_CH = 175, /* Address 0x40298300, size 0x00000040 */ 4286 PROT_DW1_CH_STRUCT13_CH = 176, /* Address 0x40298340, size 0x00000040 */ 4287 PROT_DW1_CH_STRUCT14_CH = 177, /* Address 0x40298380, size 0x00000040 */ 4288 PROT_DW1_CH_STRUCT15_CH = 178, /* Address 0x402983c0, size 0x00000040 */ 4289 PROT_DW1_CH_STRUCT16_CH = 179, /* Address 0x40298400, size 0x00000040 */ 4290 PROT_DW1_CH_STRUCT17_CH = 180, /* Address 0x40298440, size 0x00000040 */ 4291 PROT_DW1_CH_STRUCT18_CH = 181, /* Address 0x40298480, size 0x00000040 */ 4292 PROT_DW1_CH_STRUCT19_CH = 182, /* Address 0x402984c0, size 0x00000040 */ 4293 PROT_DW1_CH_STRUCT20_CH = 183, /* Address 0x40298500, size 0x00000040 */ 4294 PROT_DW1_CH_STRUCT21_CH = 184, /* Address 0x40298540, size 0x00000040 */ 4295 PROT_DW1_CH_STRUCT22_CH = 185, /* Address 0x40298580, size 0x00000040 */ 4296 PROT_DW1_CH_STRUCT23_CH = 186, /* Address 0x402985c0, size 0x00000040 */ 4297 PROT_DW1_CH_STRUCT24_CH = 187, /* Address 0x40298600, size 0x00000040 */ 4298 PROT_DW1_CH_STRUCT25_CH = 188, /* Address 0x40298640, size 0x00000040 */ 4299 PROT_DW1_CH_STRUCT26_CH = 189, /* Address 0x40298680, size 0x00000040 */ 4300 PROT_DW1_CH_STRUCT27_CH = 190, /* Address 0x402986c0, size 0x00000040 */ 4301 PROT_DW1_CH_STRUCT28_CH = 191, /* Address 0x40298700, size 0x00000040 */ 4302 PROT_DW1_CH_STRUCT29_CH = 192, /* Address 0x40298740, size 0x00000040 */ 4303 PROT_DW1_CH_STRUCT30_CH = 193, /* Address 0x40298780, size 0x00000040 */ 4304 PROT_DW1_CH_STRUCT31_CH = 194, /* Address 0x402987c0, size 0x00000040 */ 4305 PROT_DW1_CH_STRUCT32_CH = 195, /* Address 0x40298800, size 0x00000040 */ 4306 PROT_DW1_CH_STRUCT33_CH = 196, /* Address 0x40298840, size 0x00000040 */ 4307 PROT_DW1_CH_STRUCT34_CH = 197, /* Address 0x40298880, size 0x00000040 */ 4308 PROT_DW1_CH_STRUCT35_CH = 198, /* Address 0x402988c0, size 0x00000040 */ 4309 PROT_DW1_CH_STRUCT36_CH = 199, /* Address 0x40298900, size 0x00000040 */ 4310 PROT_DW1_CH_STRUCT37_CH = 200, /* Address 0x40298940, size 0x00000040 */ 4311 PROT_DW1_CH_STRUCT38_CH = 201, /* Address 0x40298980, size 0x00000040 */ 4312 PROT_DW1_CH_STRUCT39_CH = 202, /* Address 0x402989c0, size 0x00000040 */ 4313 PROT_DW1_CH_STRUCT40_CH = 203, /* Address 0x40298a00, size 0x00000040 */ 4314 PROT_DW1_CH_STRUCT41_CH = 204, /* Address 0x40298a40, size 0x00000040 */ 4315 PROT_DW1_CH_STRUCT42_CH = 205, /* Address 0x40298a80, size 0x00000040 */ 4316 PROT_DW1_CH_STRUCT43_CH = 206, /* Address 0x40298ac0, size 0x00000040 */ 4317 PROT_DMAC_TOP = 207, /* Address 0x402a0000, size 0x00000010 */ 4318 PROT_DMAC_CH0_CH = 208, /* Address 0x402a1000, size 0x00000100 */ 4319 PROT_DMAC_CH1_CH = 209, /* Address 0x402a1100, size 0x00000100 */ 4320 PROT_DMAC_CH2_CH = 210, /* Address 0x402a1200, size 0x00000100 */ 4321 PROT_DMAC_CH3_CH = 211, /* Address 0x402a1300, size 0x00000100 */ 4322 PROT_EFUSE_CTL = 212, /* Address 0x402c0000, size 0x00000200 */ 4323 PROT_EFUSE_DATA = 213, /* Address 0x402c0800, size 0x00000200 */ 4324 PROT_BIST = 214, /* Address 0x402f0000, size 0x00001000 */ 4325 PROT_HSIOM_PRT0_PRT = 215, /* Address 0x40300000, size 0x00000008 */ 4326 PROT_HSIOM_PRT1_PRT = 216, /* Address 0x40300010, size 0x00000008 */ 4327 PROT_HSIOM_PRT2_PRT = 217, /* Address 0x40300020, size 0x00000008 */ 4328 PROT_HSIOM_PRT3_PRT = 218, /* Address 0x40300030, size 0x00000008 */ 4329 PROT_HSIOM_PRT4_PRT = 219, /* Address 0x40300040, size 0x00000008 */ 4330 PROT_HSIOM_PRT5_PRT = 220, /* Address 0x40300050, size 0x00000008 */ 4331 PROT_HSIOM_PRT6_PRT = 221, /* Address 0x40300060, size 0x00000008 */ 4332 PROT_HSIOM_PRT7_PRT = 222, /* Address 0x40300070, size 0x00000008 */ 4333 PROT_HSIOM_PRT8_PRT = 223, /* Address 0x40300080, size 0x00000008 */ 4334 PROT_HSIOM_PRT9_PRT = 224, /* Address 0x40300090, size 0x00000008 */ 4335 PROT_HSIOM_PRT10_PRT = 225, /* Address 0x403000a0, size 0x00000008 */ 4336 PROT_HSIOM_PRT11_PRT = 226, /* Address 0x403000b0, size 0x00000008 */ 4337 PROT_HSIOM_PRT12_PRT = 227, /* Address 0x403000c0, size 0x00000008 */ 4338 PROT_HSIOM_PRT13_PRT = 228, /* Address 0x403000d0, size 0x00000008 */ 4339 PROT_HSIOM_PRT14_PRT = 229, /* Address 0x403000e0, size 0x00000008 */ 4340 PROT_HSIOM_PRT15_PRT = 230, /* Address 0x403000f0, size 0x00000008 */ 4341 PROT_HSIOM_PRT16_PRT = 231, /* Address 0x40300100, size 0x00000008 */ 4342 PROT_HSIOM_PRT17_PRT = 232, /* Address 0x40300110, size 0x00000008 */ 4343 PROT_HSIOM_PRT18_PRT = 233, /* Address 0x40300120, size 0x00000008 */ 4344 PROT_HSIOM_PRT19_PRT = 234, /* Address 0x40300130, size 0x00000008 */ 4345 PROT_HSIOM_PRT20_PRT = 235, /* Address 0x40300140, size 0x00000008 */ 4346 PROT_HSIOM_PRT21_PRT = 236, /* Address 0x40300150, size 0x00000008 */ 4347 PROT_HSIOM_PRT22_PRT = 237, /* Address 0x40300160, size 0x00000008 */ 4348 PROT_HSIOM_PRT23_PRT = 238, /* Address 0x40300170, size 0x00000008 */ 4349 PROT_HSIOM_AMUX = 239, /* Address 0x40302000, size 0x00000010 */ 4350 PROT_HSIOM_MON = 240, /* Address 0x40302200, size 0x00000010 */ 4351 PROT_HSIOM_ALTJTAG = 241, /* Address 0x40302240, size 0x00000004 */ 4352 PROT_GPIO_PRT0_PRT = 242, /* Address 0x40310000, size 0x00000040 */ 4353 PROT_GPIO_PRT1_PRT = 243, /* Address 0x40310080, size 0x00000040 */ 4354 PROT_GPIO_PRT2_PRT = 244, /* Address 0x40310100, size 0x00000040 */ 4355 PROT_GPIO_PRT3_PRT = 245, /* Address 0x40310180, size 0x00000040 */ 4356 PROT_GPIO_PRT4_PRT = 246, /* Address 0x40310200, size 0x00000040 */ 4357 PROT_GPIO_PRT5_PRT = 247, /* Address 0x40310280, size 0x00000040 */ 4358 PROT_GPIO_PRT6_PRT = 248, /* Address 0x40310300, size 0x00000040 */ 4359 PROT_GPIO_PRT7_PRT = 249, /* Address 0x40310380, size 0x00000040 */ 4360 PROT_GPIO_PRT8_PRT = 250, /* Address 0x40310400, size 0x00000040 */ 4361 PROT_GPIO_PRT9_PRT = 251, /* Address 0x40310480, size 0x00000040 */ 4362 PROT_GPIO_PRT10_PRT = 252, /* Address 0x40310500, size 0x00000040 */ 4363 PROT_GPIO_PRT11_PRT = 253, /* Address 0x40310580, size 0x00000040 */ 4364 PROT_GPIO_PRT12_PRT = 254, /* Address 0x40310600, size 0x00000040 */ 4365 PROT_GPIO_PRT13_PRT = 255, /* Address 0x40310680, size 0x00000040 */ 4366 PROT_GPIO_PRT14_PRT = 256, /* Address 0x40310700, size 0x00000040 */ 4367 PROT_GPIO_PRT15_PRT = 257, /* Address 0x40310780, size 0x00000040 */ 4368 PROT_GPIO_PRT16_PRT = 258, /* Address 0x40310800, size 0x00000040 */ 4369 PROT_GPIO_PRT17_PRT = 259, /* Address 0x40310880, size 0x00000040 */ 4370 PROT_GPIO_PRT18_PRT = 260, /* Address 0x40310900, size 0x00000040 */ 4371 PROT_GPIO_PRT19_PRT = 261, /* Address 0x40310980, size 0x00000040 */ 4372 PROT_GPIO_PRT20_PRT = 262, /* Address 0x40310a00, size 0x00000040 */ 4373 PROT_GPIO_PRT21_PRT = 263, /* Address 0x40310a80, size 0x00000040 */ 4374 PROT_GPIO_PRT22_PRT = 264, /* Address 0x40310b00, size 0x00000040 */ 4375 PROT_GPIO_PRT23_PRT = 265, /* Address 0x40310b80, size 0x00000040 */ 4376 PROT_GPIO_PRT0_CFG = 266, /* Address 0x40310040, size 0x00000020 */ 4377 PROT_GPIO_PRT1_CFG = 267, /* Address 0x403100c0, size 0x00000020 */ 4378 PROT_GPIO_PRT2_CFG = 268, /* Address 0x40310140, size 0x00000020 */ 4379 PROT_GPIO_PRT3_CFG = 269, /* Address 0x403101c0, size 0x00000020 */ 4380 PROT_GPIO_PRT4_CFG = 270, /* Address 0x40310240, size 0x00000020 */ 4381 PROT_GPIO_PRT5_CFG = 271, /* Address 0x403102c0, size 0x00000020 */ 4382 PROT_GPIO_PRT6_CFG = 272, /* Address 0x40310340, size 0x00000020 */ 4383 PROT_GPIO_PRT7_CFG = 273, /* Address 0x403103c0, size 0x00000020 */ 4384 PROT_GPIO_PRT8_CFG = 274, /* Address 0x40310440, size 0x00000020 */ 4385 PROT_GPIO_PRT9_CFG = 275, /* Address 0x403104c0, size 0x00000020 */ 4386 PROT_GPIO_PRT10_CFG = 276, /* Address 0x40310540, size 0x00000020 */ 4387 PROT_GPIO_PRT11_CFG = 277, /* Address 0x403105c0, size 0x00000020 */ 4388 PROT_GPIO_PRT12_CFG = 278, /* Address 0x40310640, size 0x00000020 */ 4389 PROT_GPIO_PRT13_CFG = 279, /* Address 0x403106c0, size 0x00000020 */ 4390 PROT_GPIO_PRT14_CFG = 280, /* Address 0x40310740, size 0x00000020 */ 4391 PROT_GPIO_PRT15_CFG = 281, /* Address 0x403107c0, size 0x00000020 */ 4392 PROT_GPIO_PRT16_CFG = 282, /* Address 0x40310840, size 0x00000020 */ 4393 PROT_GPIO_PRT17_CFG = 283, /* Address 0x403108c0, size 0x00000020 */ 4394 PROT_GPIO_PRT18_CFG = 284, /* Address 0x40310940, size 0x00000020 */ 4395 PROT_GPIO_PRT19_CFG = 285, /* Address 0x403109c0, size 0x00000020 */ 4396 PROT_GPIO_PRT20_CFG = 286, /* Address 0x40310a40, size 0x00000020 */ 4397 PROT_GPIO_PRT21_CFG = 287, /* Address 0x40310ac0, size 0x00000020 */ 4398 PROT_GPIO_PRT22_CFG = 288, /* Address 0x40310b40, size 0x00000020 */ 4399 PROT_GPIO_PRT23_CFG = 289, /* Address 0x40310bc0, size 0x00000020 */ 4400 PROT_GPIO_GPIO = 290, /* Address 0x40314000, size 0x00000040 */ 4401 PROT_GPIO_TEST = 291, /* Address 0x40315000, size 0x00000008 */ 4402 PROT_SMARTIO_PRT12_PRT = 292, /* Address 0x40320c00, size 0x00000100 */ 4403 PROT_SMARTIO_PRT13_PRT = 293, /* Address 0x40320d00, size 0x00000100 */ 4404 PROT_SMARTIO_PRT14_PRT = 294, /* Address 0x40320e00, size 0x00000100 */ 4405 PROT_SMARTIO_PRT15_PRT = 295, /* Address 0x40320f00, size 0x00000100 */ 4406 PROT_SMARTIO_PRT17_PRT = 296, /* Address 0x40321100, size 0x00000100 */ 4407 PROT_TCPWM0_GRP0_CNT0_CNT = 297, /* Address 0x40380000, size 0x00000080 */ 4408 PROT_TCPWM0_GRP0_CNT1_CNT = 298, /* Address 0x40380080, size 0x00000080 */ 4409 PROT_TCPWM0_GRP0_CNT2_CNT = 299, /* Address 0x40380100, size 0x00000080 */ 4410 PROT_TCPWM0_GRP0_CNT3_CNT = 300, /* Address 0x40380180, size 0x00000080 */ 4411 PROT_TCPWM0_GRP0_CNT4_CNT = 301, /* Address 0x40380200, size 0x00000080 */ 4412 PROT_TCPWM0_GRP0_CNT5_CNT = 302, /* Address 0x40380280, size 0x00000080 */ 4413 PROT_TCPWM0_GRP0_CNT6_CNT = 303, /* Address 0x40380300, size 0x00000080 */ 4414 PROT_TCPWM0_GRP0_CNT7_CNT = 304, /* Address 0x40380380, size 0x00000080 */ 4415 PROT_TCPWM0_GRP0_CNT8_CNT = 305, /* Address 0x40380400, size 0x00000080 */ 4416 PROT_TCPWM0_GRP0_CNT9_CNT = 306, /* Address 0x40380480, size 0x00000080 */ 4417 PROT_TCPWM0_GRP0_CNT10_CNT = 307, /* Address 0x40380500, size 0x00000080 */ 4418 PROT_TCPWM0_GRP0_CNT11_CNT = 308, /* Address 0x40380580, size 0x00000080 */ 4419 PROT_TCPWM0_GRP0_CNT12_CNT = 309, /* Address 0x40380600, size 0x00000080 */ 4420 PROT_TCPWM0_GRP0_CNT13_CNT = 310, /* Address 0x40380680, size 0x00000080 */ 4421 PROT_TCPWM0_GRP0_CNT14_CNT = 311, /* Address 0x40380700, size 0x00000080 */ 4422 PROT_TCPWM0_GRP0_CNT15_CNT = 312, /* Address 0x40380780, size 0x00000080 */ 4423 PROT_TCPWM0_GRP0_CNT16_CNT = 313, /* Address 0x40380800, size 0x00000080 */ 4424 PROT_TCPWM0_GRP0_CNT17_CNT = 314, /* Address 0x40380880, size 0x00000080 */ 4425 PROT_TCPWM0_GRP0_CNT18_CNT = 315, /* Address 0x40380900, size 0x00000080 */ 4426 PROT_TCPWM0_GRP0_CNT19_CNT = 316, /* Address 0x40380980, size 0x00000080 */ 4427 PROT_TCPWM0_GRP0_CNT20_CNT = 317, /* Address 0x40380a00, size 0x00000080 */ 4428 PROT_TCPWM0_GRP0_CNT21_CNT = 318, /* Address 0x40380a80, size 0x00000080 */ 4429 PROT_TCPWM0_GRP0_CNT22_CNT = 319, /* Address 0x40380b00, size 0x00000080 */ 4430 PROT_TCPWM0_GRP0_CNT23_CNT = 320, /* Address 0x40380b80, size 0x00000080 */ 4431 PROT_TCPWM0_GRP0_CNT24_CNT = 321, /* Address 0x40380c00, size 0x00000080 */ 4432 PROT_TCPWM0_GRP0_CNT25_CNT = 322, /* Address 0x40380c80, size 0x00000080 */ 4433 PROT_TCPWM0_GRP0_CNT26_CNT = 323, /* Address 0x40380d00, size 0x00000080 */ 4434 PROT_TCPWM0_GRP0_CNT27_CNT = 324, /* Address 0x40380d80, size 0x00000080 */ 4435 PROT_TCPWM0_GRP0_CNT28_CNT = 325, /* Address 0x40380e00, size 0x00000080 */ 4436 PROT_TCPWM0_GRP0_CNT29_CNT = 326, /* Address 0x40380e80, size 0x00000080 */ 4437 PROT_TCPWM0_GRP0_CNT30_CNT = 327, /* Address 0x40380f00, size 0x00000080 */ 4438 PROT_TCPWM0_GRP0_CNT31_CNT = 328, /* Address 0x40380f80, size 0x00000080 */ 4439 PROT_TCPWM0_GRP0_CNT32_CNT = 329, /* Address 0x40381000, size 0x00000080 */ 4440 PROT_TCPWM0_GRP0_CNT33_CNT = 330, /* Address 0x40381080, size 0x00000080 */ 4441 PROT_TCPWM0_GRP0_CNT34_CNT = 331, /* Address 0x40381100, size 0x00000080 */ 4442 PROT_TCPWM0_GRP0_CNT35_CNT = 332, /* Address 0x40381180, size 0x00000080 */ 4443 PROT_TCPWM0_GRP0_CNT36_CNT = 333, /* Address 0x40381200, size 0x00000080 */ 4444 PROT_TCPWM0_GRP0_CNT37_CNT = 334, /* Address 0x40381280, size 0x00000080 */ 4445 PROT_TCPWM0_GRP0_CNT38_CNT = 335, /* Address 0x40381300, size 0x00000080 */ 4446 PROT_TCPWM0_GRP0_CNT39_CNT = 336, /* Address 0x40381380, size 0x00000080 */ 4447 PROT_TCPWM0_GRP0_CNT40_CNT = 337, /* Address 0x40381400, size 0x00000080 */ 4448 PROT_TCPWM0_GRP0_CNT41_CNT = 338, /* Address 0x40381480, size 0x00000080 */ 4449 PROT_TCPWM0_GRP0_CNT42_CNT = 339, /* Address 0x40381500, size 0x00000080 */ 4450 PROT_TCPWM0_GRP0_CNT43_CNT = 340, /* Address 0x40381580, size 0x00000080 */ 4451 PROT_TCPWM0_GRP0_CNT44_CNT = 341, /* Address 0x40381600, size 0x00000080 */ 4452 PROT_TCPWM0_GRP0_CNT45_CNT = 342, /* Address 0x40381680, size 0x00000080 */ 4453 PROT_TCPWM0_GRP0_CNT46_CNT = 343, /* Address 0x40381700, size 0x00000080 */ 4454 PROT_TCPWM0_GRP0_CNT47_CNT = 344, /* Address 0x40381780, size 0x00000080 */ 4455 PROT_TCPWM0_GRP0_CNT48_CNT = 345, /* Address 0x40381800, size 0x00000080 */ 4456 PROT_TCPWM0_GRP0_CNT49_CNT = 346, /* Address 0x40381880, size 0x00000080 */ 4457 PROT_TCPWM0_GRP0_CNT50_CNT = 347, /* Address 0x40381900, size 0x00000080 */ 4458 PROT_TCPWM0_GRP0_CNT51_CNT = 348, /* Address 0x40381980, size 0x00000080 */ 4459 PROT_TCPWM0_GRP0_CNT52_CNT = 349, /* Address 0x40381a00, size 0x00000080 */ 4460 PROT_TCPWM0_GRP0_CNT53_CNT = 350, /* Address 0x40381a80, size 0x00000080 */ 4461 PROT_TCPWM0_GRP0_CNT54_CNT = 351, /* Address 0x40381b00, size 0x00000080 */ 4462 PROT_TCPWM0_GRP0_CNT55_CNT = 352, /* Address 0x40381b80, size 0x00000080 */ 4463 PROT_TCPWM0_GRP0_CNT56_CNT = 353, /* Address 0x40381c00, size 0x00000080 */ 4464 PROT_TCPWM0_GRP0_CNT57_CNT = 354, /* Address 0x40381c80, size 0x00000080 */ 4465 PROT_TCPWM0_GRP0_CNT58_CNT = 355, /* Address 0x40381d00, size 0x00000080 */ 4466 PROT_TCPWM0_GRP0_CNT59_CNT = 356, /* Address 0x40381d80, size 0x00000080 */ 4467 PROT_TCPWM0_GRP0_CNT60_CNT = 357, /* Address 0x40381e00, size 0x00000080 */ 4468 PROT_TCPWM0_GRP0_CNT61_CNT = 358, /* Address 0x40381e80, size 0x00000080 */ 4469 PROT_TCPWM0_GRP0_CNT62_CNT = 359, /* Address 0x40381f00, size 0x00000080 */ 4470 PROT_TCPWM0_GRP1_CNT0_CNT = 360, /* Address 0x40388000, size 0x00000080 */ 4471 PROT_TCPWM0_GRP1_CNT1_CNT = 361, /* Address 0x40388080, size 0x00000080 */ 4472 PROT_TCPWM0_GRP1_CNT2_CNT = 362, /* Address 0x40388100, size 0x00000080 */ 4473 PROT_TCPWM0_GRP1_CNT3_CNT = 363, /* Address 0x40388180, size 0x00000080 */ 4474 PROT_TCPWM0_GRP1_CNT4_CNT = 364, /* Address 0x40388200, size 0x00000080 */ 4475 PROT_TCPWM0_GRP1_CNT5_CNT = 365, /* Address 0x40388280, size 0x00000080 */ 4476 PROT_TCPWM0_GRP1_CNT6_CNT = 366, /* Address 0x40388300, size 0x00000080 */ 4477 PROT_TCPWM0_GRP1_CNT7_CNT = 367, /* Address 0x40388380, size 0x00000080 */ 4478 PROT_TCPWM0_GRP1_CNT8_CNT = 368, /* Address 0x40388400, size 0x00000080 */ 4479 PROT_TCPWM0_GRP1_CNT9_CNT = 369, /* Address 0x40388480, size 0x00000080 */ 4480 PROT_TCPWM0_GRP1_CNT10_CNT = 370, /* Address 0x40388500, size 0x00000080 */ 4481 PROT_TCPWM0_GRP1_CNT11_CNT = 371, /* Address 0x40388580, size 0x00000080 */ 4482 PROT_TCPWM0_GRP2_CNT0_CNT = 372, /* Address 0x40390000, size 0x00000080 */ 4483 PROT_TCPWM0_GRP2_CNT1_CNT = 373, /* Address 0x40390080, size 0x00000080 */ 4484 PROT_TCPWM0_GRP2_CNT2_CNT = 374, /* Address 0x40390100, size 0x00000080 */ 4485 PROT_TCPWM0_GRP2_CNT3_CNT = 375, /* Address 0x40390180, size 0x00000080 */ 4486 PROT_TCPWM0_GRP2_CNT4_CNT = 376, /* Address 0x40390200, size 0x00000080 */ 4487 PROT_TCPWM0_GRP2_CNT5_CNT = 377, /* Address 0x40390280, size 0x00000080 */ 4488 PROT_TCPWM0_GRP2_CNT6_CNT = 378, /* Address 0x40390300, size 0x00000080 */ 4489 PROT_TCPWM0_GRP2_CNT7_CNT = 379, /* Address 0x40390380, size 0x00000080 */ 4490 PROT_EVTGEN0 = 380, /* Address 0x403f0000, size 0x00001000 */ 4491 PROT_LIN0_MAIN = 381, /* Address 0x40500000, size 0x00000008 */ 4492 PROT_LIN0_CH0_CH = 382, /* Address 0x40508000, size 0x00000100 */ 4493 PROT_LIN0_CH1_CH = 383, /* Address 0x40508100, size 0x00000100 */ 4494 PROT_LIN0_CH2_CH = 384, /* Address 0x40508200, size 0x00000100 */ 4495 PROT_LIN0_CH3_CH = 385, /* Address 0x40508300, size 0x00000100 */ 4496 PROT_LIN0_CH4_CH = 386, /* Address 0x40508400, size 0x00000100 */ 4497 PROT_LIN0_CH5_CH = 387, /* Address 0x40508500, size 0x00000100 */ 4498 PROT_LIN0_CH6_CH = 388, /* Address 0x40508600, size 0x00000100 */ 4499 PROT_LIN0_CH7_CH = 389, /* Address 0x40508700, size 0x00000100 */ 4500 PROT_LIN0_CH8_CH = 390, /* Address 0x40508800, size 0x00000100 */ 4501 PROT_LIN0_CH9_CH = 391, /* Address 0x40508900, size 0x00000100 */ 4502 PROT_LIN0_CH10_CH = 392, /* Address 0x40508a00, size 0x00000100 */ 4503 PROT_LIN0_CH11_CH = 393, /* Address 0x40508b00, size 0x00000100 */ 4504 PROT_CXPI0_MAIN = 394, /* Address 0x40510000, size 0x00000008 */ 4505 PROT_CXPI0_CH0_CH = 395, /* Address 0x40518000, size 0x00000100 */ 4506 PROT_CXPI0_CH1_CH = 396, /* Address 0x40518100, size 0x00000100 */ 4507 PROT_CXPI0_CH2_CH = 397, /* Address 0x40518200, size 0x00000100 */ 4508 PROT_CXPI0_CH3_CH = 398, /* Address 0x40518300, size 0x00000100 */ 4509 PROT_CANFD0_CH0_CH = 399, /* Address 0x40520000, size 0x00000200 */ 4510 PROT_CANFD0_CH1_CH = 400, /* Address 0x40520200, size 0x00000200 */ 4511 PROT_CANFD0_CH2_CH = 401, /* Address 0x40520400, size 0x00000200 */ 4512 PROT_CANFD0_CH3_CH = 402, /* Address 0x40520600, size 0x00000200 */ 4513 PROT_CANFD1_CH0_CH = 403, /* Address 0x40540000, size 0x00000200 */ 4514 PROT_CANFD1_CH1_CH = 404, /* Address 0x40540200, size 0x00000200 */ 4515 PROT_CANFD1_CH2_CH = 405, /* Address 0x40540400, size 0x00000200 */ 4516 PROT_CANFD1_CH3_CH = 406, /* Address 0x40540600, size 0x00000200 */ 4517 PROT_CANFD0_MAIN = 407, /* Address 0x40521000, size 0x00000100 */ 4518 PROT_CANFD1_MAIN = 408, /* Address 0x40541000, size 0x00000100 */ 4519 PROT_CANFD0_BUF = 409, /* Address 0x40530000, size 0x00010000 */ 4520 PROT_CANFD1_BUF = 410, /* Address 0x40550000, size 0x00010000 */ 4521 PROT_SCB0 = 411, /* Address 0x40600000, size 0x00010000 */ 4522 PROT_SCB1 = 412, /* Address 0x40610000, size 0x00010000 */ 4523 PROT_SCB2 = 413, /* Address 0x40620000, size 0x00010000 */ 4524 PROT_SCB3 = 414, /* Address 0x40630000, size 0x00010000 */ 4525 PROT_SCB4 = 415, /* Address 0x40640000, size 0x00010000 */ 4526 PROT_SCB5 = 416, /* Address 0x40650000, size 0x00010000 */ 4527 PROT_SCB6 = 417, /* Address 0x40660000, size 0x00010000 */ 4528 PROT_SCB7 = 418, /* Address 0x40670000, size 0x00010000 */ 4529 PROT_PASS0_SAR0_SAR = 419, /* Address 0x40900000, size 0x00000400 */ 4530 PROT_PASS0_SAR1_SAR = 420, /* Address 0x40901000, size 0x00000400 */ 4531 PROT_PASS0_SAR2_SAR = 421, /* Address 0x40902000, size 0x00000400 */ 4532 PROT_PASS0_SAR0_CH0_CH = 422, /* Address 0x40900800, size 0x00000040 */ 4533 PROT_PASS0_SAR0_CH1_CH = 423, /* Address 0x40900840, size 0x00000040 */ 4534 PROT_PASS0_SAR0_CH2_CH = 424, /* Address 0x40900880, size 0x00000040 */ 4535 PROT_PASS0_SAR0_CH3_CH = 425, /* Address 0x409008c0, size 0x00000040 */ 4536 PROT_PASS0_SAR0_CH4_CH = 426, /* Address 0x40900900, size 0x00000040 */ 4537 PROT_PASS0_SAR0_CH5_CH = 427, /* Address 0x40900940, size 0x00000040 */ 4538 PROT_PASS0_SAR0_CH6_CH = 428, /* Address 0x40900980, size 0x00000040 */ 4539 PROT_PASS0_SAR0_CH7_CH = 429, /* Address 0x409009c0, size 0x00000040 */ 4540 PROT_PASS0_SAR0_CH8_CH = 430, /* Address 0x40900a00, size 0x00000040 */ 4541 PROT_PASS0_SAR0_CH9_CH = 431, /* Address 0x40900a40, size 0x00000040 */ 4542 PROT_PASS0_SAR0_CH10_CH = 432, /* Address 0x40900a80, size 0x00000040 */ 4543 PROT_PASS0_SAR0_CH11_CH = 433, /* Address 0x40900ac0, size 0x00000040 */ 4544 PROT_PASS0_SAR0_CH12_CH = 434, /* Address 0x40900b00, size 0x00000040 */ 4545 PROT_PASS0_SAR0_CH13_CH = 435, /* Address 0x40900b40, size 0x00000040 */ 4546 PROT_PASS0_SAR0_CH14_CH = 436, /* Address 0x40900b80, size 0x00000040 */ 4547 PROT_PASS0_SAR0_CH15_CH = 437, /* Address 0x40900bc0, size 0x00000040 */ 4548 PROT_PASS0_SAR0_CH16_CH = 438, /* Address 0x40900c00, size 0x00000040 */ 4549 PROT_PASS0_SAR0_CH17_CH = 439, /* Address 0x40900c40, size 0x00000040 */ 4550 PROT_PASS0_SAR0_CH18_CH = 440, /* Address 0x40900c80, size 0x00000040 */ 4551 PROT_PASS0_SAR0_CH19_CH = 441, /* Address 0x40900cc0, size 0x00000040 */ 4552 PROT_PASS0_SAR0_CH20_CH = 442, /* Address 0x40900d00, size 0x00000040 */ 4553 PROT_PASS0_SAR0_CH21_CH = 443, /* Address 0x40900d40, size 0x00000040 */ 4554 PROT_PASS0_SAR0_CH22_CH = 444, /* Address 0x40900d80, size 0x00000040 */ 4555 PROT_PASS0_SAR0_CH23_CH = 445, /* Address 0x40900dc0, size 0x00000040 */ 4556 PROT_PASS0_SAR1_CH0_CH = 446, /* Address 0x40901800, size 0x00000040 */ 4557 PROT_PASS0_SAR1_CH1_CH = 447, /* Address 0x40901840, size 0x00000040 */ 4558 PROT_PASS0_SAR1_CH2_CH = 448, /* Address 0x40901880, size 0x00000040 */ 4559 PROT_PASS0_SAR1_CH3_CH = 449, /* Address 0x409018c0, size 0x00000040 */ 4560 PROT_PASS0_SAR1_CH4_CH = 450, /* Address 0x40901900, size 0x00000040 */ 4561 PROT_PASS0_SAR1_CH5_CH = 451, /* Address 0x40901940, size 0x00000040 */ 4562 PROT_PASS0_SAR1_CH6_CH = 452, /* Address 0x40901980, size 0x00000040 */ 4563 PROT_PASS0_SAR1_CH7_CH = 453, /* Address 0x409019c0, size 0x00000040 */ 4564 PROT_PASS0_SAR1_CH8_CH = 454, /* Address 0x40901a00, size 0x00000040 */ 4565 PROT_PASS0_SAR1_CH9_CH = 455, /* Address 0x40901a40, size 0x00000040 */ 4566 PROT_PASS0_SAR1_CH10_CH = 456, /* Address 0x40901a80, size 0x00000040 */ 4567 PROT_PASS0_SAR1_CH11_CH = 457, /* Address 0x40901ac0, size 0x00000040 */ 4568 PROT_PASS0_SAR1_CH12_CH = 458, /* Address 0x40901b00, size 0x00000040 */ 4569 PROT_PASS0_SAR1_CH13_CH = 459, /* Address 0x40901b40, size 0x00000040 */ 4570 PROT_PASS0_SAR1_CH14_CH = 460, /* Address 0x40901b80, size 0x00000040 */ 4571 PROT_PASS0_SAR1_CH15_CH = 461, /* Address 0x40901bc0, size 0x00000040 */ 4572 PROT_PASS0_SAR1_CH16_CH = 462, /* Address 0x40901c00, size 0x00000040 */ 4573 PROT_PASS0_SAR1_CH17_CH = 463, /* Address 0x40901c40, size 0x00000040 */ 4574 PROT_PASS0_SAR1_CH18_CH = 464, /* Address 0x40901c80, size 0x00000040 */ 4575 PROT_PASS0_SAR1_CH19_CH = 465, /* Address 0x40901cc0, size 0x00000040 */ 4576 PROT_PASS0_SAR1_CH20_CH = 466, /* Address 0x40901d00, size 0x00000040 */ 4577 PROT_PASS0_SAR1_CH21_CH = 467, /* Address 0x40901d40, size 0x00000040 */ 4578 PROT_PASS0_SAR1_CH22_CH = 468, /* Address 0x40901d80, size 0x00000040 */ 4579 PROT_PASS0_SAR1_CH23_CH = 469, /* Address 0x40901dc0, size 0x00000040 */ 4580 PROT_PASS0_SAR1_CH24_CH = 470, /* Address 0x40901e00, size 0x00000040 */ 4581 PROT_PASS0_SAR1_CH25_CH = 471, /* Address 0x40901e40, size 0x00000040 */ 4582 PROT_PASS0_SAR1_CH26_CH = 472, /* Address 0x40901e80, size 0x00000040 */ 4583 PROT_PASS0_SAR1_CH27_CH = 473, /* Address 0x40901ec0, size 0x00000040 */ 4584 PROT_PASS0_SAR1_CH28_CH = 474, /* Address 0x40901f00, size 0x00000040 */ 4585 PROT_PASS0_SAR1_CH29_CH = 475, /* Address 0x40901f40, size 0x00000040 */ 4586 PROT_PASS0_SAR1_CH30_CH = 476, /* Address 0x40901f80, size 0x00000040 */ 4587 PROT_PASS0_SAR1_CH31_CH = 477, /* Address 0x40901fc0, size 0x00000040 */ 4588 PROT_PASS0_SAR2_CH0_CH = 478, /* Address 0x40902800, size 0x00000040 */ 4589 PROT_PASS0_SAR2_CH1_CH = 479, /* Address 0x40902840, size 0x00000040 */ 4590 PROT_PASS0_SAR2_CH2_CH = 480, /* Address 0x40902880, size 0x00000040 */ 4591 PROT_PASS0_SAR2_CH3_CH = 481, /* Address 0x409028c0, size 0x00000040 */ 4592 PROT_PASS0_SAR2_CH4_CH = 482, /* Address 0x40902900, size 0x00000040 */ 4593 PROT_PASS0_SAR2_CH5_CH = 483, /* Address 0x40902940, size 0x00000040 */ 4594 PROT_PASS0_SAR2_CH6_CH = 484, /* Address 0x40902980, size 0x00000040 */ 4595 PROT_PASS0_SAR2_CH7_CH = 485, /* Address 0x409029c0, size 0x00000040 */ 4596 PROT_PASS0_TOP = 486 /* Address 0x409f0000, size 0x00001000 */ 4597 } cy_en_prot_region_t; 4598 4599 #endif /* _TVIIBE4M_CONFIG_H_ */ 4600 4601 4602 /* [] END OF FILE */ 4603
