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Searched refs:P23_5_CPUSS_SWJ_SWCLK_TCLK (Results 1 – 25 of 44) sorted by relevance

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/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dgpio_tviibe1m_64_lqfp.h1058 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe2m_64_lqfp.h1073 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe4m_64_lqfp.h1073 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe1m_80_lqfp.h1321 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe2m_80_lqfp.h1350 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe4m_80_lqfp.h1350 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe1m_100_lqfp.h1603 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe2m_100_lqfp.h1641 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe4m_100_lqfp.h1641 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe1m_144_lqfp.h2397 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe2m_144_lqfp.h2461 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_tviibe4m_144_lqfp.h2461 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
/hal_infineon-latest/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/
Dcyhal_tviibe1m_64_lqfp.c77 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe4m_64_lqfp.c77 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe2m_64_lqfp.c77 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe2m_80_lqfp.c82 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe4m_80_lqfp.c82 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe1m_80_lqfp.c80 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe1m_100_lqfp.c82 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe2m_100_lqfp.c86 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe4m_100_lqfp.c86 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
Dcyhal_tviibe1m_144_lqfp.c87 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dgpio_xmc7100_100_teqfp.h1626 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
Dgpio_xmc7100_144_teqfp.h2471 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ enumerator
/hal_infineon-latest/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/
Dcyhal_xmc7100_100_teqfp.c135 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK},

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