1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_100_lqfp.c 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 100-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE1M_100_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe1m_100_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[9] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 39 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 40 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 41 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 42 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 43 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 44 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 45 }; 46 47 /* Connections for: canfd_ttcan_tx */ 48 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[9] = { 49 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 50 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 51 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 52 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 53 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 54 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 55 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 56 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 57 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 58 }; 59 60 /* Connections for: cpuss_cal_sup_nz */ 61 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 62 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 63 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 64 }; 65 66 /* Connections for: cpuss_clk_fm_pump */ 67 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 68 {0u, 0u, NC, HSIOM_SEL_GPIO}, 69 }; 70 71 /* Connections for: cpuss_fault_out */ 72 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5] = { 73 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 74 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 75 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 76 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 77 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 78 }; 79 80 /* Connections for: cpuss_swj_swclk_tclk */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 82 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 83 }; 84 85 /* Connections for: cpuss_swj_swdio_tms */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 87 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 88 }; 89 90 /* Connections for: cpuss_swj_swdoe_tdi */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 92 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 93 }; 94 95 /* Connections for: cpuss_swj_swo_tdo */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 97 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 98 }; 99 100 /* Connections for: cpuss_swj_trstn */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 102 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 103 }; 104 105 /* Connections for: cpuss_trace_clock */ 106 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 107 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 108 }; 109 110 /* Connections for: cpuss_trace_data */ 111 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 112 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 113 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 114 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 115 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 116 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 117 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 118 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 119 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 120 }; 121 122 /* Connections for: lin_lin_en */ 123 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[8] = { 124 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 125 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 126 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 127 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 128 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 129 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 130 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 131 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 132 }; 133 134 /* Connections for: lin_lin_rx */ 135 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[12] = { 136 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 137 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 138 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 139 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 140 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 141 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 142 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 143 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 144 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 145 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 146 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 147 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 148 }; 149 150 /* Connections for: lin_lin_tx */ 151 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[9] = { 152 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 153 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 154 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 155 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 156 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 157 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 158 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 159 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 160 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 161 }; 162 163 /* Connections for: pass_sar_ext_mux_en */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 165 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 166 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 167 }; 168 169 /* Connections for: pass_sar_ext_mux_sel */ 170 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[5] = { 171 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 172 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 173 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 174 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 175 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 176 }; 177 178 /* Connections for: pass_sarmux_pads */ 179 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[39] = { 180 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 181 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 182 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 183 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 184 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 185 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 186 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 187 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 188 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 189 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 190 {0u, 12u, P7_4, HSIOM_SEL_GPIO}, 191 {0u, 13u, P7_5, HSIOM_SEL_GPIO}, 192 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 193 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 194 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 195 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 196 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 197 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 198 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 199 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 200 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 201 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 202 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 203 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 204 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 205 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 206 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 207 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 208 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 209 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 210 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 211 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 212 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 213 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 214 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 215 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 216 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 217 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 218 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 219 }; 220 221 /* Connections for: peri_tr_io_input */ 222 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 223 to know the index of the input or output trigger line. Store that in the channel_num field 224 instead. */ 225 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[14] = { 226 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 227 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 228 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 229 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 230 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 231 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 232 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 233 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 234 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 235 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 236 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 237 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 238 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 239 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 240 }; 241 242 /* Connections for: peri_tr_io_output */ 243 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 244 to know the index of the input or output trigger line. Store that in the channel_num field 245 instead. */ 246 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4] = { 247 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 248 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 249 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 250 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 251 }; 252 253 /* Connections for: scb_i2c_scl */ 254 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10] = { 255 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 256 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 257 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 258 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 259 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 260 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 261 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 262 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 263 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 264 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 265 }; 266 267 /* Connections for: scb_i2c_sda */ 268 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12] = { 269 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 270 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 271 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 272 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 273 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 274 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 275 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 276 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 277 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 278 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 279 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 280 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 281 }; 282 283 /* Connections for: scb_spi_m_clk */ 284 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9] = { 285 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 286 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 287 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 288 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 289 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 290 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 291 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 292 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 293 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 294 }; 295 296 /* Connections for: scb_spi_m_miso */ 297 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11] = { 298 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 299 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 300 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 301 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 302 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 303 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 304 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 305 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 306 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 307 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 308 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 309 }; 310 311 /* Connections for: scb_spi_m_mosi */ 312 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11] = { 313 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 314 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 315 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 316 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 317 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 318 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 319 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 320 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 321 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 322 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 323 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 324 }; 325 326 /* Connections for: scb_spi_m_select0 */ 327 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10] = { 328 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 329 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 330 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 331 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 332 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 333 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 334 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 335 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 336 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 337 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 338 }; 339 340 /* Connections for: scb_spi_m_select1 */ 341 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[6] = { 342 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 343 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 344 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 345 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 346 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 347 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 348 }; 349 350 /* Connections for: scb_spi_m_select2 */ 351 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8] = { 352 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 353 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 354 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 355 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 356 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 357 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 358 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 359 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 360 }; 361 362 /* Connections for: scb_spi_m_select3 */ 363 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3] = { 364 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 365 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 366 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 367 }; 368 369 /* Connections for: scb_spi_s_clk */ 370 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9] = { 371 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 372 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 373 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 374 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 375 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 376 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 377 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 378 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 379 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 380 }; 381 382 /* Connections for: scb_spi_s_miso */ 383 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11] = { 384 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 385 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 386 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 387 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 388 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 389 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 390 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 391 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 392 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 393 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 394 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 395 }; 396 397 /* Connections for: scb_spi_s_mosi */ 398 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11] = { 399 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 400 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 401 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 402 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 403 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 404 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 405 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 406 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 407 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 408 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 409 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 410 }; 411 412 /* Connections for: scb_spi_s_select0 */ 413 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10] = { 414 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 415 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 416 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 417 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 418 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 419 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 420 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 421 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 422 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 423 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 424 }; 425 426 /* Connections for: scb_spi_s_select1 */ 427 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[6] = { 428 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 429 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 430 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 431 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 432 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 433 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 434 }; 435 436 /* Connections for: scb_spi_s_select2 */ 437 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8] = { 438 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 439 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 440 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 441 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 442 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 443 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 444 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 445 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 446 }; 447 448 /* Connections for: scb_spi_s_select3 */ 449 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3] = { 450 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 451 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 452 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 453 }; 454 455 /* Connections for: scb_uart_cts */ 456 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10] = { 457 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 458 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 459 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 460 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 461 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 462 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 463 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 464 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 465 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 466 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 467 }; 468 469 /* Connections for: scb_uart_rts */ 470 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9] = { 471 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 472 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 473 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 474 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 475 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 476 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 477 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 478 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 479 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 480 }; 481 482 /* Connections for: scb_uart_rx */ 483 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11] = { 484 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 485 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 486 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 487 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 488 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 489 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 490 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 491 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 492 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 493 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 494 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 495 }; 496 497 /* Connections for: scb_uart_tx */ 498 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11] = { 499 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 500 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 501 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 502 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 503 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 504 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 505 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 506 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 507 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 508 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 509 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 510 }; 511 512 /* Connections for: tcpwm_line */ 513 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80] = { 514 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 515 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 516 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 517 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 518 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 519 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 520 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 521 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 522 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 523 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 524 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 525 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 526 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 527 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 528 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 529 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 530 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 531 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 532 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 533 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 534 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 535 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 536 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 537 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 538 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 539 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 540 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 541 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 542 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 543 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 544 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 545 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 546 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 547 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 548 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 549 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 550 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 551 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 552 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 553 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 554 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 555 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 556 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 557 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 558 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 559 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 560 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 561 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 562 {2u, 2u, P17_1, P17_1_TCPWM0_LINE514}, 563 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 564 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 565 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 566 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 567 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 568 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 569 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 570 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 571 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 572 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 573 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 574 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 575 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 576 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 577 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 578 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 579 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 580 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 581 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 582 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 583 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 584 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 585 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 586 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 587 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 588 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 589 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 590 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 591 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 592 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 593 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 594 }; 595 596 /* Connections for: tcpwm_line_compl */ 597 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80] = { 598 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 599 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 600 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 601 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 602 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 603 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 604 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 605 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 606 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 607 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 608 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 609 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 610 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 611 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 612 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 613 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 614 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 615 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 616 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 617 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 618 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 619 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 620 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 621 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 622 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 623 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 624 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 625 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 626 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 627 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 628 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 629 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 630 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 631 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 632 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 633 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 634 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 635 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 636 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 637 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 638 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 639 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 640 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 641 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 642 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 643 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 644 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 645 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 646 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 647 {2u, 2u, P17_2, P17_2_TCPWM0_LINE_COMPL514}, 648 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 649 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 650 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 651 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 652 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 653 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 654 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 655 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 656 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 657 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 658 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 659 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 660 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 661 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 662 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 663 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 664 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 665 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 666 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 667 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 668 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 669 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 670 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 671 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 672 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 673 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 674 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 675 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 676 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 677 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 678 }; 679 680 /* Connections for: tcpwm_tr_one_cnt_in */ 681 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[154] = { 682 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 683 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 684 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 685 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 686 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 687 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 688 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 689 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 690 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 691 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 692 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 693 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 694 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 695 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 696 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 697 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 698 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 699 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 700 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 701 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 702 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 703 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 704 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 705 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 706 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 707 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 708 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 709 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 710 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 711 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 712 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 713 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 714 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 715 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 716 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 717 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 718 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 719 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 720 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 721 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 722 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 723 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 724 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 725 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 726 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 727 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 728 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 729 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 730 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 731 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 732 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 733 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 734 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 735 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 736 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 737 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 738 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 739 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 740 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 741 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 742 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 743 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 744 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 745 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 746 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 747 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 748 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 749 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 750 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 751 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 752 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 753 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 754 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 755 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 756 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 757 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 758 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 759 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 760 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 761 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 762 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 763 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 764 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 765 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 766 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 767 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 768 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 769 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 770 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 771 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 772 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 773 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 774 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 775 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 776 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 777 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 778 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 779 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 780 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 781 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 782 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 783 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 784 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 785 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 786 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 787 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 788 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 789 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 790 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 791 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 792 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 793 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 794 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 795 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 796 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 797 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 798 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 799 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 800 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 801 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 802 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 803 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 804 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 805 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 806 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 807 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 808 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 809 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 810 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 811 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 812 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 813 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 814 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 815 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 816 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 817 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 818 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 819 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 820 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 821 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 822 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 823 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 824 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 825 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 826 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 827 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 828 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 829 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 830 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 831 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 832 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 833 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 834 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 835 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 836 }; 837 838 #endif 839
