1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_64_lqfp.c 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 64-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE1M_64_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe1m_64_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[7] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 39 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 40 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 41 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 42 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 43 }; 44 45 /* Connections for: canfd_ttcan_tx */ 46 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[8] = { 47 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 48 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 49 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 50 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 51 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 52 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 53 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 54 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 55 }; 56 57 /* Connections for: cpuss_cal_sup_nz */ 58 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 59 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 60 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 61 }; 62 63 /* Connections for: cpuss_clk_fm_pump */ 64 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 65 {0u, 0u, NC, HSIOM_SEL_GPIO}, 66 }; 67 68 /* Connections for: cpuss_fault_out */ 69 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[3] = { 70 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 71 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 72 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 73 }; 74 75 /* Connections for: cpuss_swj_swclk_tclk */ 76 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 77 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 78 }; 79 80 /* Connections for: cpuss_swj_swdio_tms */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 82 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 83 }; 84 85 /* Connections for: cpuss_swj_swdoe_tdi */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 87 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 88 }; 89 90 /* Connections for: cpuss_swj_swo_tdo */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 92 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 93 }; 94 95 /* Connections for: cpuss_swj_trstn */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 97 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 98 }; 99 100 /* Connections for: cpuss_trace_clock */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 102 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 103 }; 104 105 /* Connections for: cpuss_trace_data */ 106 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[5] = { 107 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 108 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 109 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 110 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 111 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 112 }; 113 114 /* Connections for: lin_lin_en */ 115 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[5] = { 116 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 117 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 118 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 119 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 120 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 121 }; 122 123 /* Connections for: lin_lin_rx */ 124 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[8] = { 125 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 126 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 127 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 128 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 129 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 130 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 131 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 132 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 133 }; 134 135 /* Connections for: lin_lin_tx */ 136 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[7] = { 137 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 138 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 139 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 140 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 141 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 142 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 143 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 144 }; 145 146 /* Connections for: pass_sar_ext_mux_en */ 147 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[1] = { 148 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 149 }; 150 151 /* Connections for: pass_sar_ext_mux_sel */ 152 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[3] = { 153 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 154 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 155 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 156 }; 157 158 /* Connections for: pass_sarmux_pads */ 159 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[27] = { 160 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 161 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 162 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 163 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 164 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 165 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 166 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 167 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 168 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 169 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 170 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 171 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 172 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 173 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 174 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 175 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 176 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 177 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 178 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 179 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 180 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 181 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 182 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 183 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 184 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 185 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 186 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 187 }; 188 189 /* Connections for: peri_tr_io_input */ 190 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 191 to know the index of the input or output trigger line. Store that in the channel_num field 192 instead. */ 193 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8] = { 194 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 195 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 196 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 197 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 198 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 199 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 200 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 201 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 202 }; 203 204 /* Connections for: peri_tr_io_output */ 205 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 206 to know the index of the input or output trigger line. Store that in the channel_num field 207 instead. */ 208 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 209 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 210 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 211 }; 212 213 /* Connections for: scb_i2c_scl */ 214 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6] = { 215 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 216 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 217 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 218 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 219 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 220 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 221 }; 222 223 /* Connections for: scb_i2c_sda */ 224 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[8] = { 225 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 226 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 227 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 228 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 229 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 230 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 231 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 232 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 233 }; 234 235 /* Connections for: scb_spi_m_clk */ 236 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[5] = { 237 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 238 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 239 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 240 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 241 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 242 }; 243 244 /* Connections for: scb_spi_m_miso */ 245 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[8] = { 246 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 247 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 248 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 249 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 250 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 251 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 252 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 253 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 254 }; 255 256 /* Connections for: scb_spi_m_mosi */ 257 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[7] = { 258 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 259 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 260 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 261 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 262 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 263 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 264 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 265 }; 266 267 /* Connections for: scb_spi_m_select0 */ 268 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[5] = { 269 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 270 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 271 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 272 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 273 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 274 }; 275 276 /* Connections for: scb_spi_m_select1 */ 277 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4] = { 278 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 279 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 280 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 281 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 282 }; 283 284 /* Connections for: scb_spi_m_select2 */ 285 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6] = { 286 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 287 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 288 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 289 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 290 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 291 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 292 }; 293 294 /* Connections for: scb_spi_m_select3 */ 295 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2] = { 296 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 297 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 298 }; 299 300 /* Connections for: scb_spi_s_clk */ 301 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[5] = { 302 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 303 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 304 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 305 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 306 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 307 }; 308 309 /* Connections for: scb_spi_s_miso */ 310 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[8] = { 311 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 312 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 313 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 314 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 315 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 316 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 317 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 318 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 319 }; 320 321 /* Connections for: scb_spi_s_mosi */ 322 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[7] = { 323 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 324 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 325 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 326 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 327 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 328 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 329 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 330 }; 331 332 /* Connections for: scb_spi_s_select0 */ 333 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[5] = { 334 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 335 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 336 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 337 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 338 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 339 }; 340 341 /* Connections for: scb_spi_s_select1 */ 342 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4] = { 343 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 344 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 345 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 346 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 347 }; 348 349 /* Connections for: scb_spi_s_select2 */ 350 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6] = { 351 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 352 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 353 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 354 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 355 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 356 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 357 }; 358 359 /* Connections for: scb_spi_s_select3 */ 360 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2] = { 361 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 362 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 363 }; 364 365 /* Connections for: scb_uart_cts */ 366 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[5] = { 367 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 368 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 369 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 370 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 371 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 372 }; 373 374 /* Connections for: scb_uart_rts */ 375 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[5] = { 376 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 377 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 378 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 379 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 380 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 381 }; 382 383 /* Connections for: scb_uart_rx */ 384 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8] = { 385 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 386 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 387 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 388 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 389 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 390 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 391 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 392 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 393 }; 394 395 /* Connections for: scb_uart_tx */ 396 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[7] = { 397 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 398 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 399 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 400 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 401 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 402 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 403 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 404 }; 405 406 /* Connections for: tcpwm_line */ 407 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[49] = { 408 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 409 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 410 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 411 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 412 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 413 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 414 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 415 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 416 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 417 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 418 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 419 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 420 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 421 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 422 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 423 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 424 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 425 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 426 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 427 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 428 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 429 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 430 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 431 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 432 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 433 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 434 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 435 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 436 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 437 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 438 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 439 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 440 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 441 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 442 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 443 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 444 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 445 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 446 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 447 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 448 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 449 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 450 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 451 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 452 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 453 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 454 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 455 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 456 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 457 }; 458 459 /* Connections for: tcpwm_line_compl */ 460 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[50] = { 461 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 462 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 463 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 464 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 465 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 466 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 467 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 468 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 469 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 470 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 471 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 472 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 473 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 474 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 475 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 476 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 477 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 478 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 479 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 480 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 481 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 482 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 483 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 484 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 485 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 486 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 487 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 488 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 489 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 490 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 491 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 492 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 493 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 494 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 495 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 496 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 497 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 498 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 499 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 500 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 501 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 502 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 503 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 504 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 505 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 506 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 507 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 508 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 509 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 510 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 511 }; 512 513 /* Connections for: tcpwm_tr_one_cnt_in */ 514 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[92] = { 515 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 516 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 517 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 518 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 519 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 520 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 521 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 522 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 523 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 524 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 525 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 526 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 527 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 528 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 529 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 530 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 531 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 532 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 533 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 534 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 535 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 536 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 537 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 538 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 539 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 540 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 541 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 542 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 543 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 544 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 545 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 546 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 547 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 548 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 549 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 550 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 551 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 552 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 553 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 554 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 555 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 556 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 557 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 558 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 559 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 560 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 561 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 562 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 563 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 564 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 565 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 566 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 567 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 568 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 569 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 570 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 571 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 572 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 573 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 574 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 575 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 576 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 577 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 578 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 579 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 580 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 581 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 582 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 583 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 584 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 585 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 586 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 587 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 588 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 589 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 590 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 591 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 592 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 593 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 594 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 595 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 596 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 597 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 598 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 599 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 600 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 601 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 602 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 603 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 604 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 605 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 606 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 607 }; 608 609 #endif 610
