1 /***************************************************************************//** 2 * \file gpio_tviibe4m_80_lqfp.h 3 * 4 * \brief 5 * TVIIBE4M device GPIO header for 80-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_TVIIBE4M_80_LQFP_H_ 28 #define _GPIO_TVIIBE4M_80_LQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_LQFP 44 #define CY_GPIO_PIN_COUNT 80u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 2 (GPIO) */ 84 #define P2_0_PORT GPIO_PRT2 85 #define P2_0_PIN 0u 86 #define P2_0_NUM 0u 87 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P2_1_PORT GPIO_PRT2 89 #define P2_1_PIN 1u 90 #define P2_1_NUM 1u 91 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 92 #define P2_2_PORT GPIO_PRT2 93 #define P2_2_PIN 2u 94 #define P2_2_NUM 2u 95 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 96 #define P2_3_PORT GPIO_PRT2 97 #define P2_3_PIN 3u 98 #define P2_3_NUM 3u 99 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 100 101 /* PORT 5 (GPIO) */ 102 #define P5_0_PORT GPIO_PRT5 103 #define P5_0_PIN 0u 104 #define P5_0_NUM 0u 105 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 106 #define P5_1_PORT GPIO_PRT5 107 #define P5_1_PIN 1u 108 #define P5_1_NUM 1u 109 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 110 #define P5_2_PORT GPIO_PRT5 111 #define P5_2_PIN 2u 112 #define P5_2_NUM 2u 113 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 114 #define P5_3_PORT GPIO_PRT5 115 #define P5_3_PIN 3u 116 #define P5_3_NUM 3u 117 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 118 119 /* PORT 6 (GPIO) */ 120 #define P6_0_PORT GPIO_PRT6 121 #define P6_0_PIN 0u 122 #define P6_0_NUM 0u 123 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 124 #define P6_1_PORT GPIO_PRT6 125 #define P6_1_PIN 1u 126 #define P6_1_NUM 1u 127 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 128 #define P6_2_PORT GPIO_PRT6 129 #define P6_2_PIN 2u 130 #define P6_2_NUM 2u 131 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 132 #define P6_3_PORT GPIO_PRT6 133 #define P6_3_PIN 3u 134 #define P6_3_NUM 3u 135 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 136 #define P6_4_PORT GPIO_PRT6 137 #define P6_4_PIN 4u 138 #define P6_4_NUM 4u 139 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 140 #define P6_5_PORT GPIO_PRT6 141 #define P6_5_PIN 5u 142 #define P6_5_NUM 5u 143 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 144 145 /* PORT 7 (GPIO) */ 146 #define P7_0_PORT GPIO_PRT7 147 #define P7_0_PIN 0u 148 #define P7_0_NUM 0u 149 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 150 #define P7_1_PORT GPIO_PRT7 151 #define P7_1_PIN 1u 152 #define P7_1_NUM 1u 153 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 154 #define P7_2_PORT GPIO_PRT7 155 #define P7_2_PIN 2u 156 #define P7_2_NUM 2u 157 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 158 #define P7_3_PORT GPIO_PRT7 159 #define P7_3_PIN 3u 160 #define P7_3_NUM 3u 161 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 162 163 /* PORT 8 (GPIO) */ 164 #define P8_0_PORT GPIO_PRT8 165 #define P8_0_PIN 0u 166 #define P8_0_NUM 0u 167 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 168 #define P8_1_PORT GPIO_PRT8 169 #define P8_1_PIN 1u 170 #define P8_1_NUM 1u 171 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 172 #define P8_2_PORT GPIO_PRT8 173 #define P8_2_PIN 2u 174 #define P8_2_NUM 2u 175 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 176 177 /* PORT 11 (GPIO) */ 178 #define P11_0_PORT GPIO_PRT11 179 #define P11_0_PIN 0u 180 #define P11_0_NUM 0u 181 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 182 #define P11_1_PORT GPIO_PRT11 183 #define P11_1_PIN 1u 184 #define P11_1_NUM 1u 185 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 186 #define P11_2_PORT GPIO_PRT11 187 #define P11_2_PIN 2u 188 #define P11_2_NUM 2u 189 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 190 191 /* PORT 12 (GPIO) */ 192 #define P12_0_PORT GPIO_PRT12 193 #define P12_0_PIN 0u 194 #define P12_0_NUM 0u 195 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 196 #define P12_1_PORT GPIO_PRT12 197 #define P12_1_PIN 1u 198 #define P12_1_NUM 1u 199 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 200 #define P12_2_PORT GPIO_PRT12 201 #define P12_2_PIN 2u 202 #define P12_2_NUM 2u 203 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 204 #define P12_3_PORT GPIO_PRT12 205 #define P12_3_PIN 3u 206 #define P12_3_NUM 3u 207 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 208 209 /* PORT 13 (GPIO) */ 210 #define P13_0_PORT GPIO_PRT13 211 #define P13_0_PIN 0u 212 #define P13_0_NUM 0u 213 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 214 #define P13_1_PORT GPIO_PRT13 215 #define P13_1_PIN 1u 216 #define P13_1_NUM 1u 217 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 218 #define P13_2_PORT GPIO_PRT13 219 #define P13_2_PIN 2u 220 #define P13_2_NUM 2u 221 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 222 #define P13_3_PORT GPIO_PRT13 223 #define P13_3_PIN 3u 224 #define P13_3_NUM 3u 225 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 226 #define P13_4_PORT GPIO_PRT13 227 #define P13_4_PIN 4u 228 #define P13_4_NUM 4u 229 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 230 #define P13_5_PORT GPIO_PRT13 231 #define P13_5_PIN 5u 232 #define P13_5_NUM 5u 233 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 234 #define P13_6_PORT GPIO_PRT13 235 #define P13_6_PIN 6u 236 #define P13_6_NUM 6u 237 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 238 #define P13_7_PORT GPIO_PRT13 239 #define P13_7_PIN 7u 240 #define P13_7_NUM 7u 241 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 242 243 /* PORT 14 (GPIO) */ 244 #define P14_0_PORT GPIO_PRT14 245 #define P14_0_PIN 0u 246 #define P14_0_NUM 0u 247 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 248 #define P14_1_PORT GPIO_PRT14 249 #define P14_1_PIN 1u 250 #define P14_1_NUM 1u 251 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 252 253 /* PORT 18 (GPIO) */ 254 #define P18_0_PORT GPIO_PRT18 255 #define P18_0_PIN 0u 256 #define P18_0_NUM 0u 257 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 258 #define P18_1_PORT GPIO_PRT18 259 #define P18_1_PIN 1u 260 #define P18_1_NUM 1u 261 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 262 #define P18_2_PORT GPIO_PRT18 263 #define P18_2_PIN 2u 264 #define P18_2_NUM 2u 265 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 266 #define P18_3_PORT GPIO_PRT18 267 #define P18_3_PIN 3u 268 #define P18_3_NUM 3u 269 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 270 #define P18_4_PORT GPIO_PRT18 271 #define P18_4_PIN 4u 272 #define P18_4_NUM 4u 273 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 274 #define P18_5_PORT GPIO_PRT18 275 #define P18_5_PIN 5u 276 #define P18_5_NUM 5u 277 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 278 #define P18_6_PORT GPIO_PRT18 279 #define P18_6_PIN 6u 280 #define P18_6_NUM 6u 281 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 282 #define P18_7_PORT GPIO_PRT18 283 #define P18_7_PIN 7u 284 #define P18_7_NUM 7u 285 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 286 287 /* PORT 19 (GPIO) */ 288 #define P19_0_PORT GPIO_PRT19 289 #define P19_0_PIN 0u 290 #define P19_0_NUM 0u 291 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 292 #define P19_1_PORT GPIO_PRT19 293 #define P19_1_PIN 1u 294 #define P19_1_NUM 1u 295 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 296 297 /* PORT 21 (GPIO) */ 298 #define P21_0_PORT GPIO_PRT21 299 #define P21_0_PIN 0u 300 #define P21_0_NUM 0u 301 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 302 #define P21_1_PORT GPIO_PRT21 303 #define P21_1_PIN 1u 304 #define P21_1_NUM 1u 305 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 306 #define P21_2_PORT GPIO_PRT21 307 #define P21_2_PIN 2u 308 #define P21_2_NUM 2u 309 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 310 #define P21_3_PORT GPIO_PRT21 311 #define P21_3_PIN 3u 312 #define P21_3_NUM 3u 313 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 314 315 /* PORT 22 (GPIO) */ 316 #define P22_0_PORT GPIO_PRT22 317 #define P22_0_PIN 0u 318 #define P22_0_NUM 0u 319 #define P22_0_AMUXSEGMENT AMUXBUS_MAIN 320 #define P22_1_PORT GPIO_PRT22 321 #define P22_1_PIN 1u 322 #define P22_1_NUM 1u 323 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 324 325 /* PORT 23 (GPIO) */ 326 #define P23_3_PORT GPIO_PRT23 327 #define P23_3_PIN 3u 328 #define P23_3_NUM 3u 329 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 330 #define P23_4_PORT GPIO_PRT23 331 #define P23_4_PIN 4u 332 #define P23_4_NUM 4u 333 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 334 #define P23_5_PORT GPIO_PRT23 335 #define P23_5_PIN 5u 336 #define P23_5_NUM 5u 337 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 338 #define P23_6_PORT GPIO_PRT23 339 #define P23_6_PIN 6u 340 #define P23_6_NUM 6u 341 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 342 #define P23_7_PORT GPIO_PRT23 343 #define P23_7_PIN 7u 344 #define P23_7_NUM 7u 345 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 346 347 /* Analog Connections */ 348 #define PASS0_I_TEMP_KELVIN_PORT 21u 349 #define PASS0_I_TEMP_KELVIN_PIN 2u 350 #define PASS0_SARMUX_MOTOR0_PORT 11u 351 #define PASS0_SARMUX_MOTOR0_PIN 0u 352 #define PASS0_SARMUX_MOTOR1_PORT 11u 353 #define PASS0_SARMUX_MOTOR1_PIN 1u 354 #define PASS0_SARMUX_MOTOR2_PORT 11u 355 #define PASS0_SARMUX_MOTOR2_PIN 2u 356 #define PASS0_SARMUX_PADS0_PORT 6u 357 #define PASS0_SARMUX_PADS0_PIN 0u 358 #define PASS0_SARMUX_PADS1_PORT 6u 359 #define PASS0_SARMUX_PADS1_PIN 1u 360 #define PASS0_SARMUX_PADS10_PORT 7u 361 #define PASS0_SARMUX_PADS10_PIN 2u 362 #define PASS0_SARMUX_PADS11_PORT 7u 363 #define PASS0_SARMUX_PADS11_PIN 3u 364 #define PASS0_SARMUX_PADS16_PORT 8u 365 #define PASS0_SARMUX_PADS16_PIN 1u 366 #define PASS0_SARMUX_PADS17_PORT 8u 367 #define PASS0_SARMUX_PADS17_PIN 2u 368 #define PASS0_SARMUX_PADS2_PORT 6u 369 #define PASS0_SARMUX_PADS2_PIN 2u 370 #define PASS0_SARMUX_PADS3_PORT 6u 371 #define PASS0_SARMUX_PADS3_PIN 3u 372 #define PASS0_SARMUX_PADS36_PORT 12u 373 #define PASS0_SARMUX_PADS36_PIN 0u 374 #define PASS0_SARMUX_PADS37_PORT 12u 375 #define PASS0_SARMUX_PADS37_PIN 1u 376 #define PASS0_SARMUX_PADS38_PORT 12u 377 #define PASS0_SARMUX_PADS38_PIN 2u 378 #define PASS0_SARMUX_PADS39_PORT 12u 379 #define PASS0_SARMUX_PADS39_PIN 3u 380 #define PASS0_SARMUX_PADS4_PORT 6u 381 #define PASS0_SARMUX_PADS4_PIN 4u 382 #define PASS0_SARMUX_PADS44_PORT 13u 383 #define PASS0_SARMUX_PADS44_PIN 0u 384 #define PASS0_SARMUX_PADS45_PORT 13u 385 #define PASS0_SARMUX_PADS45_PIN 1u 386 #define PASS0_SARMUX_PADS46_PORT 13u 387 #define PASS0_SARMUX_PADS46_PIN 2u 388 #define PASS0_SARMUX_PADS47_PORT 13u 389 #define PASS0_SARMUX_PADS47_PIN 3u 390 #define PASS0_SARMUX_PADS48_PORT 13u 391 #define PASS0_SARMUX_PADS48_PIN 4u 392 #define PASS0_SARMUX_PADS49_PORT 13u 393 #define PASS0_SARMUX_PADS49_PIN 5u 394 #define PASS0_SARMUX_PADS5_PORT 6u 395 #define PASS0_SARMUX_PADS5_PIN 5u 396 #define PASS0_SARMUX_PADS50_PORT 13u 397 #define PASS0_SARMUX_PADS50_PIN 6u 398 #define PASS0_SARMUX_PADS51_PORT 13u 399 #define PASS0_SARMUX_PADS51_PIN 7u 400 #define PASS0_SARMUX_PADS52_PORT 14u 401 #define PASS0_SARMUX_PADS52_PIN 0u 402 #define PASS0_SARMUX_PADS53_PORT 14u 403 #define PASS0_SARMUX_PADS53_PIN 1u 404 #define PASS0_SARMUX_PADS64_PORT 18u 405 #define PASS0_SARMUX_PADS64_PIN 0u 406 #define PASS0_SARMUX_PADS65_PORT 18u 407 #define PASS0_SARMUX_PADS65_PIN 1u 408 #define PASS0_SARMUX_PADS66_PORT 18u 409 #define PASS0_SARMUX_PADS66_PIN 2u 410 #define PASS0_SARMUX_PADS67_PORT 18u 411 #define PASS0_SARMUX_PADS67_PIN 3u 412 #define PASS0_SARMUX_PADS68_PORT 18u 413 #define PASS0_SARMUX_PADS68_PIN 4u 414 #define PASS0_SARMUX_PADS69_PORT 18u 415 #define PASS0_SARMUX_PADS69_PIN 5u 416 #define PASS0_SARMUX_PADS70_PORT 18u 417 #define PASS0_SARMUX_PADS70_PIN 6u 418 #define PASS0_SARMUX_PADS71_PORT 18u 419 #define PASS0_SARMUX_PADS71_PIN 7u 420 #define PASS0_SARMUX_PADS8_PORT 7u 421 #define PASS0_SARMUX_PADS8_PIN 0u 422 #define PASS0_SARMUX_PADS9_PORT 7u 423 #define PASS0_SARMUX_PADS9_PIN 1u 424 #define PASS0_VE_TEMP_KELVIN_PORT 23u 425 #define PASS0_VE_TEMP_KELVIN_PIN 4u 426 #define SRSS_ADFT_PIN0_PORT 23u 427 #define SRSS_ADFT_PIN0_PIN 4u 428 #define SRSS_ADFT_PIN1_PORT 23u 429 #define SRSS_ADFT_PIN1_PIN 3u 430 #define SRSS_ECO_IN_PORT 21u 431 #define SRSS_ECO_IN_PIN 2u 432 #define SRSS_ECO_OUT_PORT 21u 433 #define SRSS_ECO_OUT_PIN 3u 434 #define SRSS_VEXT_REF_REG_PORT 21u 435 #define SRSS_VEXT_REF_REG_PIN 3u 436 #define SRSS_WCO_IN_PORT 21u 437 #define SRSS_WCO_IN_PIN 0u 438 #define SRSS_WCO_OUT_PORT 21u 439 #define SRSS_WCO_OUT_PIN 1u 440 441 /* HSIOM Connections */ 442 typedef enum 443 { 444 /* Generic HSIOM connections */ 445 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 446 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 447 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 448 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 449 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 450 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 451 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 452 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 453 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 454 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 455 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 456 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 457 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 458 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 459 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 460 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 461 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 462 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 463 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 464 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 465 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 466 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 467 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 468 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 469 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 470 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 471 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 472 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 473 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 474 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 475 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 476 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 477 478 /* P0.0 */ 479 P0_0_GPIO = 0, /* GPIO controls 'out' */ 480 P0_0_AMUXA = 4, /* Analog mux bus A */ 481 P0_0_AMUXB = 5, /* Analog mux bus B */ 482 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 483 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 484 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 485 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 486 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 487 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 488 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 489 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 490 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 491 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 492 493 /* P0.1 */ 494 P0_1_GPIO = 0, /* GPIO controls 'out' */ 495 P0_1_AMUXA = 4, /* Analog mux bus A */ 496 P0_1_AMUXB = 5, /* Analog mux bus B */ 497 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 498 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 499 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 500 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 501 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 502 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 503 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 504 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 505 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 506 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 507 508 /* P0.2 */ 509 P0_2_GPIO = 0, /* GPIO controls 'out' */ 510 P0_2_AMUXA = 4, /* Analog mux bus A */ 511 P0_2_AMUXB = 5, /* Analog mux bus B */ 512 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 513 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 514 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 515 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 516 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 517 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 518 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 519 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 520 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 521 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 522 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 523 524 /* P0.3 */ 525 P0_3_GPIO = 0, /* GPIO controls 'out' */ 526 P0_3_AMUXA = 4, /* Analog mux bus A */ 527 P0_3_AMUXB = 5, /* Analog mux bus B */ 528 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 529 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 530 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 531 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 532 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 533 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 534 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 535 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 536 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 537 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 538 539 /* P2.0 */ 540 P2_0_GPIO = 0, /* GPIO controls 'out' */ 541 P2_0_AMUXA = 4, /* Analog mux bus A */ 542 P2_0_AMUXB = 5, /* Analog mux bus B */ 543 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 544 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 545 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 546 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 547 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 548 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 549 P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ 550 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 551 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 552 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 553 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 554 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 555 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 556 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 557 558 /* P2.1 */ 559 P2_1_GPIO = 0, /* GPIO controls 'out' */ 560 P2_1_AMUXA = 4, /* Analog mux bus A */ 561 P2_1_AMUXB = 5, /* Analog mux bus B */ 562 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 563 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 564 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 565 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 566 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 567 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 568 P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ 569 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 570 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 571 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 572 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 573 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 574 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 575 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 576 577 /* P2.2 */ 578 P2_2_GPIO = 0, /* GPIO controls 'out' */ 579 P2_2_AMUXA = 4, /* Analog mux bus A */ 580 P2_2_AMUXB = 5, /* Analog mux bus B */ 581 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 582 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 583 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 584 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 585 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 586 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 587 P2_2_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:0 */ 588 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 589 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 590 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 591 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 592 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 593 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 594 595 /* P2.3 */ 596 P2_3_GPIO = 0, /* GPIO controls 'out' */ 597 P2_3_AMUXA = 4, /* Analog mux bus A */ 598 P2_3_AMUXB = 5, /* Analog mux bus B */ 599 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 600 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 601 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 602 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 603 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 604 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 605 P2_3_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:0 */ 606 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 607 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 608 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 609 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 610 611 /* P5.0 */ 612 P5_0_GPIO = 0, /* GPIO controls 'out' */ 613 P5_0_AMUXA = 4, /* Analog mux bus A */ 614 P5_0_AMUXB = 5, /* Analog mux bus B */ 615 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 616 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 617 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 618 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 619 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 620 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 621 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 622 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 623 624 /* P5.1 */ 625 P5_1_GPIO = 0, /* GPIO controls 'out' */ 626 P5_1_AMUXA = 4, /* Analog mux bus A */ 627 P5_1_AMUXB = 5, /* Analog mux bus B */ 628 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 629 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 630 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 631 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 632 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 633 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 634 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 635 636 /* P5.2 */ 637 P5_2_GPIO = 0, /* GPIO controls 'out' */ 638 P5_2_AMUXA = 4, /* Analog mux bus A */ 639 P5_2_AMUXB = 5, /* Analog mux bus B */ 640 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 641 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 642 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 643 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 644 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 645 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 646 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 647 648 /* P5.3 */ 649 P5_3_GPIO = 0, /* GPIO controls 'out' */ 650 P5_3_AMUXA = 4, /* Analog mux bus A */ 651 P5_3_AMUXB = 5, /* Analog mux bus B */ 652 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 653 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 654 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 655 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 656 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 657 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 658 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 659 660 /* P6.0 */ 661 P6_0_GPIO = 0, /* GPIO controls 'out' */ 662 P6_0_AMUXA = 4, /* Analog mux bus A */ 663 P6_0_AMUXB = 5, /* Analog mux bus B */ 664 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 665 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 666 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 667 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 668 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 669 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 670 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 671 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 672 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 673 674 /* P6.1 */ 675 P6_1_GPIO = 0, /* GPIO controls 'out' */ 676 P6_1_AMUXA = 4, /* Analog mux bus A */ 677 P6_1_AMUXB = 5, /* Analog mux bus B */ 678 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 679 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 680 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 681 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 682 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 683 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 684 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 685 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 686 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 687 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 688 689 /* P6.2 */ 690 P6_2_GPIO = 0, /* GPIO controls 'out' */ 691 P6_2_AMUXA = 4, /* Analog mux bus A */ 692 P6_2_AMUXB = 5, /* Analog mux bus B */ 693 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 694 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 695 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 696 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 697 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 698 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 699 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 700 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 701 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 702 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 703 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 704 705 /* P6.3 */ 706 P6_3_GPIO = 0, /* GPIO controls 'out' */ 707 P6_3_AMUXA = 4, /* Analog mux bus A */ 708 P6_3_AMUXB = 5, /* Analog mux bus B */ 709 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 710 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 711 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 712 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 713 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 714 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 715 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 716 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 717 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 718 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 719 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 720 721 /* P6.4 */ 722 P6_4_GPIO = 0, /* GPIO controls 'out' */ 723 P6_4_AMUXA = 4, /* Analog mux bus A */ 724 P6_4_AMUXB = 5, /* Analog mux bus B */ 725 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 726 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 727 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 728 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 729 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 730 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 731 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 732 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 733 734 /* P6.5 */ 735 P6_5_GPIO = 0, /* GPIO controls 'out' */ 736 P6_5_AMUXA = 4, /* Analog mux bus A */ 737 P6_5_AMUXB = 5, /* Analog mux bus B */ 738 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 739 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 740 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 741 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 742 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 743 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 744 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 745 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 746 747 /* P7.0 */ 748 P7_0_GPIO = 0, /* GPIO controls 'out' */ 749 P7_0_AMUXA = 4, /* Analog mux bus A */ 750 P7_0_AMUXB = 5, /* Analog mux bus B */ 751 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 752 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 753 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 754 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 755 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 756 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 757 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 758 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 759 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 760 P7_0_CXPI0_CXPI_RX0 = 22, /* Digital Active - cxpi[0].cxpi_rx[0]:0 */ 761 762 /* P7.1 */ 763 P7_1_GPIO = 0, /* GPIO controls 'out' */ 764 P7_1_AMUXA = 4, /* Analog mux bus A */ 765 P7_1_AMUXB = 5, /* Analog mux bus B */ 766 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 767 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 768 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 769 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 770 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 771 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 772 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 773 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 774 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 775 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 776 P7_1_CXPI0_CXPI_TX0 = 22, /* Digital Active - cxpi[0].cxpi_tx[0]:0 */ 777 778 /* P7.2 */ 779 P7_2_GPIO = 0, /* GPIO controls 'out' */ 780 P7_2_AMUXA = 4, /* Analog mux bus A */ 781 P7_2_AMUXB = 5, /* Analog mux bus B */ 782 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 783 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 784 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 785 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 786 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 787 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 788 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 789 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 790 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 791 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 792 P7_2_CXPI0_CXPI_EN0 = 22, /* Digital Active - cxpi[0].cxpi_en[0]:0 */ 793 794 /* P7.3 */ 795 P7_3_GPIO = 0, /* GPIO controls 'out' */ 796 P7_3_AMUXA = 4, /* Analog mux bus A */ 797 P7_3_AMUXB = 5, /* Analog mux bus B */ 798 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 799 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 800 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 801 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 802 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 803 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 804 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 805 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 806 807 /* P8.0 */ 808 P8_0_GPIO = 0, /* GPIO controls 'out' */ 809 P8_0_AMUXA = 4, /* Analog mux bus A */ 810 P8_0_AMUXB = 5, /* Analog mux bus B */ 811 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 812 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 813 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 814 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 815 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 816 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 817 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 818 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 819 820 /* P8.1 */ 821 P8_1_GPIO = 0, /* GPIO controls 'out' */ 822 P8_1_AMUXA = 4, /* Analog mux bus A */ 823 P8_1_AMUXB = 5, /* Analog mux bus B */ 824 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 825 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 826 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 827 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 828 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 829 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 830 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 831 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 832 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 833 834 /* P8.2 */ 835 P8_2_GPIO = 0, /* GPIO controls 'out' */ 836 P8_2_AMUXA = 4, /* Analog mux bus A */ 837 P8_2_AMUXB = 5, /* Analog mux bus B */ 838 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 839 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 840 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 841 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 842 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 843 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 844 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 845 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 846 847 /* P11.0 */ 848 P11_0_GPIO = 0, /* GPIO controls 'out' */ 849 P11_0_AMUXA = 4, /* Analog mux bus A */ 850 P11_0_AMUXB = 5, /* Analog mux bus B */ 851 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 852 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 853 854 /* P11.1 */ 855 P11_1_GPIO = 0, /* GPIO controls 'out' */ 856 P11_1_AMUXA = 4, /* Analog mux bus A */ 857 P11_1_AMUXB = 5, /* Analog mux bus B */ 858 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 859 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 860 861 /* P11.2 */ 862 P11_2_GPIO = 0, /* GPIO controls 'out' */ 863 P11_2_AMUXA = 4, /* Analog mux bus A */ 864 P11_2_AMUXB = 5, /* Analog mux bus B */ 865 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 866 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 867 868 /* P12.0 */ 869 P12_0_GPIO = 0, /* GPIO controls 'out' */ 870 P12_0_AMUXA = 4, /* Analog mux bus A */ 871 P12_0_AMUXB = 5, /* Analog mux bus B */ 872 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 873 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 874 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 875 P12_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 876 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 877 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 878 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 879 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 880 881 /* P12.1 */ 882 P12_1_GPIO = 0, /* GPIO controls 'out' */ 883 P12_1_AMUXA = 4, /* Analog mux bus A */ 884 P12_1_AMUXB = 5, /* Analog mux bus B */ 885 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 886 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 887 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 888 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 889 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 890 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 891 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 892 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 893 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 894 895 /* P12.2 */ 896 P12_2_GPIO = 0, /* GPIO controls 'out' */ 897 P12_2_AMUXA = 4, /* Analog mux bus A */ 898 P12_2_AMUXB = 5, /* Analog mux bus B */ 899 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 900 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 901 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 902 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 903 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 904 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 905 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 906 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 907 908 /* P12.3 */ 909 P12_3_GPIO = 0, /* GPIO controls 'out' */ 910 P12_3_AMUXA = 4, /* Analog mux bus A */ 911 P12_3_AMUXB = 5, /* Analog mux bus B */ 912 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 913 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 914 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 915 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 916 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 917 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 918 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 919 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 920 921 /* P13.0 */ 922 P13_0_GPIO = 0, /* GPIO controls 'out' */ 923 P13_0_AMUXA = 4, /* Analog mux bus A */ 924 P13_0_AMUXB = 5, /* Analog mux bus B */ 925 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 926 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 927 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 928 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 929 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 930 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 931 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 932 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 933 P13_0_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:0 */ 934 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 935 P13_0_CXPI0_CXPI_RX1 = 22, /* Digital Active - cxpi[0].cxpi_rx[1]:0 */ 936 937 /* P13.1 */ 938 P13_1_GPIO = 0, /* GPIO controls 'out' */ 939 P13_1_AMUXA = 4, /* Analog mux bus A */ 940 P13_1_AMUXB = 5, /* Analog mux bus B */ 941 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 942 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 943 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 944 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 945 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 946 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 947 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 948 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 949 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 950 P13_1_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:0 */ 951 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 952 P13_1_CXPI0_CXPI_TX1 = 22, /* Digital Active - cxpi[0].cxpi_tx[1]:0 */ 953 954 /* P13.2 */ 955 P13_2_GPIO = 0, /* GPIO controls 'out' */ 956 P13_2_AMUXA = 4, /* Analog mux bus A */ 957 P13_2_AMUXB = 5, /* Analog mux bus B */ 958 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 959 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 960 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 961 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 962 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 963 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 964 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 965 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 966 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 967 P13_2_SCB3_SPI_CLK = 19, /* Digital Active - scb[3].spi_clk:0 */ 968 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 969 P13_2_CXPI0_CXPI_EN1 = 22, /* Digital Active - cxpi[0].cxpi_en[1]:0 */ 970 971 /* P13.3 */ 972 P13_3_GPIO = 0, /* GPIO controls 'out' */ 973 P13_3_AMUXA = 4, /* Analog mux bus A */ 974 P13_3_AMUXB = 5, /* Analog mux bus B */ 975 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 976 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 977 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 978 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 979 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 980 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 981 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 982 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 983 P13_3_SCB3_SPI_SELECT0 = 19, /* Digital Active - scb[3].spi_select0:0 */ 984 985 /* P13.4 */ 986 P13_4_GPIO = 0, /* GPIO controls 'out' */ 987 P13_4_AMUXA = 4, /* Analog mux bus A */ 988 P13_4_AMUXB = 5, /* Analog mux bus B */ 989 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 990 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 991 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 992 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 993 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 994 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 995 P13_4_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:1 */ 996 P13_4_SCB3_SPI_SELECT1 = 19, /* Digital Active - scb[3].spi_select1:0 */ 997 P13_4_LIN0_LIN_RX8 = 20, /* Digital Active - lin[0].lin_rx[8]:0 */ 998 999 /* P13.5 */ 1000 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1001 P13_5_AMUXA = 4, /* Analog mux bus A */ 1002 P13_5_AMUXB = 5, /* Analog mux bus B */ 1003 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1004 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1005 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 1006 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 1007 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 1008 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 1009 P13_5_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:1 */ 1010 P13_5_SCB3_SPI_SELECT2 = 19, /* Digital Active - scb[3].spi_select2:0 */ 1011 P13_5_LIN0_LIN_TX8 = 20, /* Digital Active - lin[0].lin_tx[8]:0 */ 1012 P13_5_CXPI0_CXPI_RX2 = 22, /* Digital Active - cxpi[0].cxpi_rx[2]:0 */ 1013 1014 /* P13.6 */ 1015 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1016 P13_6_AMUXA = 4, /* Analog mux bus A */ 1017 P13_6_AMUXB = 5, /* Analog mux bus B */ 1018 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1019 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1020 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 1021 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 1022 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 1023 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 1024 P13_6_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:1 */ 1025 P13_6_SCB3_SPI_SELECT3 = 19, /* Digital Active - scb[3].spi_select3:0 */ 1026 P13_6_LIN0_LIN_EN8 = 20, /* Digital Active - lin[0].lin_en[8]:0 */ 1027 P13_6_CXPI0_CXPI_TX2 = 22, /* Digital Active - cxpi[0].cxpi_tx[2]:0 */ 1028 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 1029 1030 /* P13.7 */ 1031 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1032 P13_7_AMUXA = 4, /* Analog mux bus A */ 1033 P13_7_AMUXB = 5, /* Analog mux bus B */ 1034 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1035 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1036 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 1037 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 1038 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 1039 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 1040 P13_7_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:1 */ 1041 P13_7_CXPI0_CXPI_EN2 = 22, /* Digital Active - cxpi[0].cxpi_en[2]:0 */ 1042 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 1043 1044 /* P14.0 */ 1045 P14_0_GPIO = 0, /* GPIO controls 'out' */ 1046 P14_0_AMUXA = 4, /* Analog mux bus A */ 1047 P14_0_AMUXB = 5, /* Analog mux bus B */ 1048 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1049 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1050 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 1051 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 1052 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 1053 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 1054 P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ 1055 P14_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:0 */ 1056 P14_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:0 */ 1057 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 1058 1059 /* P14.1 */ 1060 P14_1_GPIO = 0, /* GPIO controls 'out' */ 1061 P14_1_AMUXA = 4, /* Analog mux bus A */ 1062 P14_1_AMUXB = 5, /* Analog mux bus B */ 1063 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1064 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1065 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 1066 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 1067 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 1068 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 1069 P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ 1070 P14_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:0 */ 1071 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 1072 P14_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:0 */ 1073 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 1074 1075 /* P18.0 */ 1076 P18_0_GPIO = 0, /* GPIO controls 'out' */ 1077 P18_0_AMUXA = 4, /* Analog mux bus A */ 1078 P18_0_AMUXB = 5, /* Analog mux bus B */ 1079 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1080 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1081 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 1082 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 1083 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 1084 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 1085 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 1086 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 1087 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 1088 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 1089 1090 /* P18.1 */ 1091 P18_1_GPIO = 0, /* GPIO controls 'out' */ 1092 P18_1_AMUXA = 4, /* Analog mux bus A */ 1093 P18_1_AMUXB = 5, /* Analog mux bus B */ 1094 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1095 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1096 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 1097 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 1098 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 1099 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 1100 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 1101 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 1102 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 1103 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 1104 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 1105 1106 /* P18.2 */ 1107 P18_2_GPIO = 0, /* GPIO controls 'out' */ 1108 P18_2_AMUXA = 4, /* Analog mux bus A */ 1109 P18_2_AMUXB = 5, /* Analog mux bus B */ 1110 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1111 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1112 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 1113 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 1114 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 1115 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 1116 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 1117 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 1118 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 1119 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 1120 1121 /* P18.3 */ 1122 P18_3_GPIO = 0, /* GPIO controls 'out' */ 1123 P18_3_AMUXA = 4, /* Analog mux bus A */ 1124 P18_3_AMUXB = 5, /* Analog mux bus B */ 1125 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1126 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1127 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 1128 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 1129 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 1130 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 1131 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 1132 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 1133 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 1134 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 1135 1136 /* P18.4 */ 1137 P18_4_GPIO = 0, /* GPIO controls 'out' */ 1138 P18_4_AMUXA = 4, /* Analog mux bus A */ 1139 P18_4_AMUXB = 5, /* Analog mux bus B */ 1140 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1141 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1142 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 1143 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 1144 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 1145 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 1146 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 1147 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 1148 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1149 1150 /* P18.5 */ 1151 P18_5_GPIO = 0, /* GPIO controls 'out' */ 1152 P18_5_AMUXA = 4, /* Analog mux bus A */ 1153 P18_5_AMUXB = 5, /* Analog mux bus B */ 1154 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1155 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1156 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 1157 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 1158 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 1159 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 1160 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 1161 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 1162 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1163 1164 /* P18.6 */ 1165 P18_6_GPIO = 0, /* GPIO controls 'out' */ 1166 P18_6_AMUXA = 4, /* Analog mux bus A */ 1167 P18_6_AMUXB = 5, /* Analog mux bus B */ 1168 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1169 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1170 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 1171 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 1172 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 1173 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 1174 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 1175 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 1176 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 1177 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1178 1179 /* P18.7 */ 1180 P18_7_GPIO = 0, /* GPIO controls 'out' */ 1181 P18_7_AMUXA = 4, /* Analog mux bus A */ 1182 P18_7_AMUXB = 5, /* Analog mux bus B */ 1183 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1184 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1185 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 1186 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 1187 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 1188 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 1189 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 1190 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 1191 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1192 1193 /* P19.0 */ 1194 P19_0_GPIO = 0, /* GPIO controls 'out' */ 1195 P19_0_AMUXA = 4, /* Analog mux bus A */ 1196 P19_0_AMUXB = 5, /* Analog mux bus B */ 1197 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1198 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1199 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 1200 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 1201 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 1202 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 1203 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 1204 P19_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:1 */ 1205 P19_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:1 */ 1206 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 1207 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 1208 1209 /* P19.1 */ 1210 P19_1_GPIO = 0, /* GPIO controls 'out' */ 1211 P19_1_AMUXA = 4, /* Analog mux bus A */ 1212 P19_1_AMUXB = 5, /* Analog mux bus B */ 1213 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1214 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1215 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 1216 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 1217 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 1218 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 1219 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 1220 P19_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:1 */ 1221 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 1222 P19_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:1 */ 1223 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 1224 P19_1_CXPI0_CXPI_RX3 = 22, /* Digital Active - cxpi[0].cxpi_rx[3]:0 */ 1225 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 1226 1227 /* P21.0 */ 1228 P21_0_GPIO = 0, /* GPIO controls 'out' */ 1229 P21_0_AMUXA = 4, /* Analog mux bus A */ 1230 P21_0_AMUXB = 5, /* Analog mux bus B */ 1231 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1232 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1233 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 1234 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 1235 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 1236 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 1237 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 1238 1239 /* P21.1 */ 1240 P21_1_GPIO = 0, /* GPIO controls 'out' */ 1241 P21_1_AMUXA = 4, /* Analog mux bus A */ 1242 P21_1_AMUXB = 5, /* Analog mux bus B */ 1243 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1244 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1245 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 1246 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 1247 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 1248 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 1249 1250 /* P21.2 */ 1251 P21_2_GPIO = 0, /* GPIO controls 'out' */ 1252 P21_2_AMUXA = 4, /* Analog mux bus A */ 1253 P21_2_AMUXB = 5, /* Analog mux bus B */ 1254 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1255 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1256 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 1257 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 1258 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 1259 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 1260 P21_2_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:0 */ 1261 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 1262 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1263 1264 /* P21.3 */ 1265 P21_3_GPIO = 0, /* GPIO controls 'out' */ 1266 P21_3_AMUXA = 4, /* Analog mux bus A */ 1267 P21_3_AMUXB = 5, /* Analog mux bus B */ 1268 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1269 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1270 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 1271 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 1272 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 1273 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 1274 1275 /* P22.0 */ 1276 P22_0_GPIO = 0, /* GPIO controls 'out' */ 1277 P22_0_AMUXA = 4, /* Analog mux bus A */ 1278 P22_0_AMUXB = 5, /* Analog mux bus B */ 1279 P22_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1280 P22_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1281 P22_0_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:1 */ 1282 P22_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 1283 P22_0_TCPWM0_TR_ONE_CNT_IN102 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 1284 P22_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 1285 P22_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 1286 P22_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 1287 P22_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 1288 P22_0_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1289 1290 /* P22.1 */ 1291 P22_1_GPIO = 0, /* GPIO controls 'out' */ 1292 P22_1_AMUXA = 4, /* Analog mux bus A */ 1293 P22_1_AMUXB = 5, /* Analog mux bus B */ 1294 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1295 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1296 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 1297 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 1298 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 1299 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 1300 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 1301 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 1302 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 1303 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 1304 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1305 1306 /* P23.3 */ 1307 P23_3_GPIO = 0, /* GPIO controls 'out' */ 1308 P23_3_AMUXA = 4, /* Analog mux bus A */ 1309 P23_3_AMUXB = 5, /* Analog mux bus B */ 1310 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1311 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1312 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 1313 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 1314 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 1315 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 1316 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 1317 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 1318 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 1319 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 1320 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1321 1322 /* P23.4 */ 1323 P23_4_GPIO = 0, /* GPIO controls 'out' */ 1324 P23_4_AMUXA = 4, /* Analog mux bus A */ 1325 P23_4_AMUXB = 5, /* Analog mux bus B */ 1326 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1327 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1328 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 1329 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 1330 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 1331 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 1332 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 1333 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 1334 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 1335 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 1336 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1337 1338 /* P23.5 */ 1339 P23_5_GPIO = 0, /* GPIO controls 'out' */ 1340 P23_5_AMUXA = 4, /* Analog mux bus A */ 1341 P23_5_AMUXB = 5, /* Analog mux bus B */ 1342 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1343 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1344 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 1345 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 1346 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 1347 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 1348 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 1349 P23_5_LIN0_LIN_RX9 = 20, /* Digital Active - lin[0].lin_rx[9]:0 */ 1350 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 1351 1352 /* P23.6 */ 1353 P23_6_GPIO = 0, /* GPIO controls 'out' */ 1354 P23_6_AMUXA = 4, /* Analog mux bus A */ 1355 P23_6_AMUXB = 5, /* Analog mux bus B */ 1356 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1357 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1358 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 1359 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 1360 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 1361 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 1362 P23_6_LIN0_LIN_TX9 = 20, /* Digital Active - lin[0].lin_tx[9]:0 */ 1363 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 1364 1365 /* P23.7 */ 1366 P23_7_GPIO = 0, /* GPIO controls 'out' */ 1367 P23_7_AMUXA = 4, /* Analog mux bus A */ 1368 P23_7_AMUXB = 5, /* Analog mux bus B */ 1369 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1370 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1371 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 1372 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 1373 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 1374 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 1375 P23_7_LIN0_LIN_EN9 = 20, /* Digital Active - lin[0].lin_en[9]:0 */ 1376 P23_7_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:1 */ 1377 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 1378 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 1379 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1380 } en_hsiom_sel_t; 1381 1382 #endif /* _GPIO_TVIIBE4M_80_LQFP_H_ */ 1383 1384 1385 /* [] END OF FILE */ 1386
