1 /***************************************************************************//** 2 * \file gpio_tviibe1m_100_lqfp.h 3 * 4 * \brief 5 * TVIIBE1M device GPIO header for 100-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_TVIIBE1M_100_LQFP_H_ 28 #define _GPIO_TVIIBE1M_100_LQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_LQFP 44 #define CY_GPIO_PIN_COUNT 100u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 2 (GPIO) */ 84 #define P2_0_PORT GPIO_PRT2 85 #define P2_0_PIN 0u 86 #define P2_0_NUM 0u 87 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P2_1_PORT GPIO_PRT2 89 #define P2_1_PIN 1u 90 #define P2_1_NUM 1u 91 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 92 #define P2_2_PORT GPIO_PRT2 93 #define P2_2_PIN 2u 94 #define P2_2_NUM 2u 95 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 96 #define P2_3_PORT GPIO_PRT2 97 #define P2_3_PIN 3u 98 #define P2_3_NUM 3u 99 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 100 101 /* PORT 3 (GPIO) */ 102 #define P3_0_PORT GPIO_PRT3 103 #define P3_0_PIN 0u 104 #define P3_0_NUM 0u 105 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 106 #define P3_1_PORT GPIO_PRT3 107 #define P3_1_PIN 1u 108 #define P3_1_NUM 1u 109 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 110 111 /* PORT 5 (GPIO) */ 112 #define P5_0_PORT GPIO_PRT5 113 #define P5_0_PIN 0u 114 #define P5_0_NUM 0u 115 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 116 #define P5_1_PORT GPIO_PRT5 117 #define P5_1_PIN 1u 118 #define P5_1_NUM 1u 119 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 120 #define P5_2_PORT GPIO_PRT5 121 #define P5_2_PIN 2u 122 #define P5_2_NUM 2u 123 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 124 #define P5_3_PORT GPIO_PRT5 125 #define P5_3_PIN 3u 126 #define P5_3_NUM 3u 127 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 128 129 /* PORT 6 (GPIO) */ 130 #define P6_0_PORT GPIO_PRT6 131 #define P6_0_PIN 0u 132 #define P6_0_NUM 0u 133 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 134 #define P6_1_PORT GPIO_PRT6 135 #define P6_1_PIN 1u 136 #define P6_1_NUM 1u 137 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 138 #define P6_2_PORT GPIO_PRT6 139 #define P6_2_PIN 2u 140 #define P6_2_NUM 2u 141 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 142 #define P6_3_PORT GPIO_PRT6 143 #define P6_3_PIN 3u 144 #define P6_3_NUM 3u 145 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 146 #define P6_4_PORT GPIO_PRT6 147 #define P6_4_PIN 4u 148 #define P6_4_NUM 4u 149 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 150 #define P6_5_PORT GPIO_PRT6 151 #define P6_5_PIN 5u 152 #define P6_5_NUM 5u 153 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 154 155 /* PORT 7 (GPIO) */ 156 #define P7_0_PORT GPIO_PRT7 157 #define P7_0_PIN 0u 158 #define P7_0_NUM 0u 159 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 160 #define P7_1_PORT GPIO_PRT7 161 #define P7_1_PIN 1u 162 #define P7_1_NUM 1u 163 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 164 #define P7_2_PORT GPIO_PRT7 165 #define P7_2_PIN 2u 166 #define P7_2_NUM 2u 167 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 168 #define P7_3_PORT GPIO_PRT7 169 #define P7_3_PIN 3u 170 #define P7_3_NUM 3u 171 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 172 #define P7_4_PORT GPIO_PRT7 173 #define P7_4_PIN 4u 174 #define P7_4_NUM 4u 175 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 176 #define P7_5_PORT GPIO_PRT7 177 #define P7_5_PIN 5u 178 #define P7_5_NUM 5u 179 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 180 181 /* PORT 8 (GPIO) */ 182 #define P8_0_PORT GPIO_PRT8 183 #define P8_0_PIN 0u 184 #define P8_0_NUM 0u 185 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 186 #define P8_1_PORT GPIO_PRT8 187 #define P8_1_PIN 1u 188 #define P8_1_NUM 1u 189 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 190 #define P8_2_PORT GPIO_PRT8 191 #define P8_2_PIN 2u 192 #define P8_2_NUM 2u 193 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 194 195 /* PORT 11 (GPIO) */ 196 #define P11_0_PORT GPIO_PRT11 197 #define P11_0_PIN 0u 198 #define P11_0_NUM 0u 199 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 200 #define P11_1_PORT GPIO_PRT11 201 #define P11_1_PIN 1u 202 #define P11_1_NUM 1u 203 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 204 #define P11_2_PORT GPIO_PRT11 205 #define P11_2_PIN 2u 206 #define P11_2_NUM 2u 207 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 208 209 /* PORT 12 (GPIO) */ 210 #define P12_0_PORT GPIO_PRT12 211 #define P12_0_PIN 0u 212 #define P12_0_NUM 0u 213 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 214 #define P12_1_PORT GPIO_PRT12 215 #define P12_1_PIN 1u 216 #define P12_1_NUM 1u 217 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 218 #define P12_2_PORT GPIO_PRT12 219 #define P12_2_PIN 2u 220 #define P12_2_NUM 2u 221 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 222 #define P12_3_PORT GPIO_PRT12 223 #define P12_3_PIN 3u 224 #define P12_3_NUM 3u 225 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 226 #define P12_4_PORT GPIO_PRT12 227 #define P12_4_PIN 4u 228 #define P12_4_NUM 4u 229 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 230 231 /* PORT 13 (GPIO) */ 232 #define P13_0_PORT GPIO_PRT13 233 #define P13_0_PIN 0u 234 #define P13_0_NUM 0u 235 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 236 #define P13_1_PORT GPIO_PRT13 237 #define P13_1_PIN 1u 238 #define P13_1_NUM 1u 239 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 240 #define P13_2_PORT GPIO_PRT13 241 #define P13_2_PIN 2u 242 #define P13_2_NUM 2u 243 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 244 #define P13_3_PORT GPIO_PRT13 245 #define P13_3_PIN 3u 246 #define P13_3_NUM 3u 247 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 248 #define P13_4_PORT GPIO_PRT13 249 #define P13_4_PIN 4u 250 #define P13_4_NUM 4u 251 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 252 #define P13_5_PORT GPIO_PRT13 253 #define P13_5_PIN 5u 254 #define P13_5_NUM 5u 255 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 256 #define P13_6_PORT GPIO_PRT13 257 #define P13_6_PIN 6u 258 #define P13_6_NUM 6u 259 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 260 #define P13_7_PORT GPIO_PRT13 261 #define P13_7_PIN 7u 262 #define P13_7_NUM 7u 263 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 264 265 /* PORT 14 (GPIO) */ 266 #define P14_0_PORT GPIO_PRT14 267 #define P14_0_PIN 0u 268 #define P14_0_NUM 0u 269 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 270 #define P14_1_PORT GPIO_PRT14 271 #define P14_1_PIN 1u 272 #define P14_1_NUM 1u 273 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 274 #define P14_2_PORT GPIO_PRT14 275 #define P14_2_PIN 2u 276 #define P14_2_NUM 2u 277 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 278 #define P14_3_PORT GPIO_PRT14 279 #define P14_3_PIN 3u 280 #define P14_3_NUM 3u 281 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 282 283 /* PORT 17 (GPIO) */ 284 #define P17_0_PORT GPIO_PRT17 285 #define P17_0_PIN 0u 286 #define P17_0_NUM 0u 287 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 288 #define P17_1_PORT GPIO_PRT17 289 #define P17_1_PIN 1u 290 #define P17_1_NUM 1u 291 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 292 #define P17_2_PORT GPIO_PRT17 293 #define P17_2_PIN 2u 294 #define P17_2_NUM 2u 295 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 296 297 /* PORT 18 (GPIO) */ 298 #define P18_0_PORT GPIO_PRT18 299 #define P18_0_PIN 0u 300 #define P18_0_NUM 0u 301 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 302 #define P18_1_PORT GPIO_PRT18 303 #define P18_1_PIN 1u 304 #define P18_1_NUM 1u 305 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 306 #define P18_2_PORT GPIO_PRT18 307 #define P18_2_PIN 2u 308 #define P18_2_NUM 2u 309 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 310 #define P18_3_PORT GPIO_PRT18 311 #define P18_3_PIN 3u 312 #define P18_3_NUM 3u 313 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 314 #define P18_4_PORT GPIO_PRT18 315 #define P18_4_PIN 4u 316 #define P18_4_NUM 4u 317 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 318 #define P18_5_PORT GPIO_PRT18 319 #define P18_5_PIN 5u 320 #define P18_5_NUM 5u 321 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 322 #define P18_6_PORT GPIO_PRT18 323 #define P18_6_PIN 6u 324 #define P18_6_NUM 6u 325 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 326 #define P18_7_PORT GPIO_PRT18 327 #define P18_7_PIN 7u 328 #define P18_7_NUM 7u 329 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 330 331 /* PORT 19 (GPIO) */ 332 #define P19_0_PORT GPIO_PRT19 333 #define P19_0_PIN 0u 334 #define P19_0_NUM 0u 335 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 336 #define P19_1_PORT GPIO_PRT19 337 #define P19_1_PIN 1u 338 #define P19_1_NUM 1u 339 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 340 #define P19_2_PORT GPIO_PRT19 341 #define P19_2_PIN 2u 342 #define P19_2_NUM 2u 343 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 344 #define P19_3_PORT GPIO_PRT19 345 #define P19_3_PIN 3u 346 #define P19_3_NUM 3u 347 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 348 349 /* PORT 21 (GPIO) */ 350 #define P21_0_PORT GPIO_PRT21 351 #define P21_0_PIN 0u 352 #define P21_0_NUM 0u 353 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 354 #define P21_1_PORT GPIO_PRT21 355 #define P21_1_PIN 1u 356 #define P21_1_NUM 1u 357 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 358 #define P21_2_PORT GPIO_PRT21 359 #define P21_2_PIN 2u 360 #define P21_2_NUM 2u 361 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 362 #define P21_3_PORT GPIO_PRT21 363 #define P21_3_PIN 3u 364 #define P21_3_NUM 3u 365 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 366 #define P21_5_PORT GPIO_PRT21 367 #define P21_5_PIN 5u 368 #define P21_5_NUM 5u 369 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 370 371 /* PORT 22 (GPIO) */ 372 #define P22_0_PORT GPIO_PRT22 373 #define P22_0_PIN 0u 374 #define P22_0_NUM 0u 375 #define P22_0_AMUXSEGMENT AMUXBUS_MAIN 376 #define P22_1_PORT GPIO_PRT22 377 #define P22_1_PIN 1u 378 #define P22_1_NUM 1u 379 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 380 #define P22_2_PORT GPIO_PRT22 381 #define P22_2_PIN 2u 382 #define P22_2_NUM 2u 383 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 384 #define P22_3_PORT GPIO_PRT22 385 #define P22_3_PIN 3u 386 #define P22_3_NUM 3u 387 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 388 389 /* PORT 23 (GPIO) */ 390 #define P23_3_PORT GPIO_PRT23 391 #define P23_3_PIN 3u 392 #define P23_3_NUM 3u 393 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 394 #define P23_4_PORT GPIO_PRT23 395 #define P23_4_PIN 4u 396 #define P23_4_NUM 4u 397 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 398 #define P23_5_PORT GPIO_PRT23 399 #define P23_5_PIN 5u 400 #define P23_5_NUM 5u 401 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 402 #define P23_6_PORT GPIO_PRT23 403 #define P23_6_PIN 6u 404 #define P23_6_NUM 6u 405 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 406 #define P23_7_PORT GPIO_PRT23 407 #define P23_7_PIN 7u 408 #define P23_7_NUM 7u 409 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 410 411 /* Analog Connections */ 412 #define PASS0_I_TEMP_KELVIN_PORT 21u 413 #define PASS0_I_TEMP_KELVIN_PIN 2u 414 #define PASS0_SARMUX_MOTOR0_PORT 11u 415 #define PASS0_SARMUX_MOTOR0_PIN 0u 416 #define PASS0_SARMUX_MOTOR1_PORT 11u 417 #define PASS0_SARMUX_MOTOR1_PIN 1u 418 #define PASS0_SARMUX_MOTOR2_PORT 11u 419 #define PASS0_SARMUX_MOTOR2_PIN 2u 420 #define PASS0_SARMUX_PADS0_PORT 6u 421 #define PASS0_SARMUX_PADS0_PIN 0u 422 #define PASS0_SARMUX_PADS1_PORT 6u 423 #define PASS0_SARMUX_PADS1_PIN 1u 424 #define PASS0_SARMUX_PADS10_PORT 7u 425 #define PASS0_SARMUX_PADS10_PIN 2u 426 #define PASS0_SARMUX_PADS11_PORT 7u 427 #define PASS0_SARMUX_PADS11_PIN 3u 428 #define PASS0_SARMUX_PADS12_PORT 7u 429 #define PASS0_SARMUX_PADS12_PIN 4u 430 #define PASS0_SARMUX_PADS13_PORT 7u 431 #define PASS0_SARMUX_PADS13_PIN 5u 432 #define PASS0_SARMUX_PADS16_PORT 8u 433 #define PASS0_SARMUX_PADS16_PIN 1u 434 #define PASS0_SARMUX_PADS17_PORT 8u 435 #define PASS0_SARMUX_PADS17_PIN 2u 436 #define PASS0_SARMUX_PADS2_PORT 6u 437 #define PASS0_SARMUX_PADS2_PIN 2u 438 #define PASS0_SARMUX_PADS3_PORT 6u 439 #define PASS0_SARMUX_PADS3_PIN 3u 440 #define PASS0_SARMUX_PADS36_PORT 12u 441 #define PASS0_SARMUX_PADS36_PIN 0u 442 #define PASS0_SARMUX_PADS37_PORT 12u 443 #define PASS0_SARMUX_PADS37_PIN 1u 444 #define PASS0_SARMUX_PADS38_PORT 12u 445 #define PASS0_SARMUX_PADS38_PIN 2u 446 #define PASS0_SARMUX_PADS39_PORT 12u 447 #define PASS0_SARMUX_PADS39_PIN 3u 448 #define PASS0_SARMUX_PADS4_PORT 6u 449 #define PASS0_SARMUX_PADS4_PIN 4u 450 #define PASS0_SARMUX_PADS40_PORT 12u 451 #define PASS0_SARMUX_PADS40_PIN 4u 452 #define PASS0_SARMUX_PADS44_PORT 13u 453 #define PASS0_SARMUX_PADS44_PIN 0u 454 #define PASS0_SARMUX_PADS45_PORT 13u 455 #define PASS0_SARMUX_PADS45_PIN 1u 456 #define PASS0_SARMUX_PADS46_PORT 13u 457 #define PASS0_SARMUX_PADS46_PIN 2u 458 #define PASS0_SARMUX_PADS47_PORT 13u 459 #define PASS0_SARMUX_PADS47_PIN 3u 460 #define PASS0_SARMUX_PADS48_PORT 13u 461 #define PASS0_SARMUX_PADS48_PIN 4u 462 #define PASS0_SARMUX_PADS49_PORT 13u 463 #define PASS0_SARMUX_PADS49_PIN 5u 464 #define PASS0_SARMUX_PADS5_PORT 6u 465 #define PASS0_SARMUX_PADS5_PIN 5u 466 #define PASS0_SARMUX_PADS50_PORT 13u 467 #define PASS0_SARMUX_PADS50_PIN 6u 468 #define PASS0_SARMUX_PADS51_PORT 13u 469 #define PASS0_SARMUX_PADS51_PIN 7u 470 #define PASS0_SARMUX_PADS52_PORT 14u 471 #define PASS0_SARMUX_PADS52_PIN 0u 472 #define PASS0_SARMUX_PADS53_PORT 14u 473 #define PASS0_SARMUX_PADS53_PIN 1u 474 #define PASS0_SARMUX_PADS54_PORT 14u 475 #define PASS0_SARMUX_PADS54_PIN 2u 476 #define PASS0_SARMUX_PADS55_PORT 14u 477 #define PASS0_SARMUX_PADS55_PIN 3u 478 #define PASS0_SARMUX_PADS64_PORT 18u 479 #define PASS0_SARMUX_PADS64_PIN 0u 480 #define PASS0_SARMUX_PADS65_PORT 18u 481 #define PASS0_SARMUX_PADS65_PIN 1u 482 #define PASS0_SARMUX_PADS66_PORT 18u 483 #define PASS0_SARMUX_PADS66_PIN 2u 484 #define PASS0_SARMUX_PADS67_PORT 18u 485 #define PASS0_SARMUX_PADS67_PIN 3u 486 #define PASS0_SARMUX_PADS68_PORT 18u 487 #define PASS0_SARMUX_PADS68_PIN 4u 488 #define PASS0_SARMUX_PADS69_PORT 18u 489 #define PASS0_SARMUX_PADS69_PIN 5u 490 #define PASS0_SARMUX_PADS70_PORT 18u 491 #define PASS0_SARMUX_PADS70_PIN 6u 492 #define PASS0_SARMUX_PADS71_PORT 18u 493 #define PASS0_SARMUX_PADS71_PIN 7u 494 #define PASS0_SARMUX_PADS8_PORT 7u 495 #define PASS0_SARMUX_PADS8_PIN 0u 496 #define PASS0_SARMUX_PADS9_PORT 7u 497 #define PASS0_SARMUX_PADS9_PIN 1u 498 #define PASS0_VE_TEMP_KELVIN_PORT 23u 499 #define PASS0_VE_TEMP_KELVIN_PIN 4u 500 #define SRSS_ADFT_PIN0_PORT 23u 501 #define SRSS_ADFT_PIN0_PIN 4u 502 #define SRSS_ADFT_PIN1_PORT 23u 503 #define SRSS_ADFT_PIN1_PIN 3u 504 #define SRSS_ECO_IN_PORT 21u 505 #define SRSS_ECO_IN_PIN 2u 506 #define SRSS_ECO_OUT_PORT 21u 507 #define SRSS_ECO_OUT_PIN 3u 508 #define SRSS_VEXT_REF_REG_PORT 21u 509 #define SRSS_VEXT_REF_REG_PIN 3u 510 #define SRSS_WCO_IN_PORT 21u 511 #define SRSS_WCO_IN_PIN 0u 512 #define SRSS_WCO_OUT_PORT 21u 513 #define SRSS_WCO_OUT_PIN 1u 514 515 /* HSIOM Connections */ 516 typedef enum 517 { 518 /* Generic HSIOM connections */ 519 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 520 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 521 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 522 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 523 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 524 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 525 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 526 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 527 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 528 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 529 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 530 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 531 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 532 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 533 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 534 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 535 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 536 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 537 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 538 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 539 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 540 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 541 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 542 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 543 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 544 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 545 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 546 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 547 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 548 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 549 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 550 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 551 552 /* P0.0 */ 553 P0_0_GPIO = 0, /* GPIO controls 'out' */ 554 P0_0_AMUXA = 4, /* Analog mux bus A */ 555 P0_0_AMUXB = 5, /* Analog mux bus B */ 556 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 557 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 558 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 559 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 560 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 561 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 562 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 563 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 564 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 565 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 566 567 /* P0.1 */ 568 P0_1_GPIO = 0, /* GPIO controls 'out' */ 569 P0_1_AMUXA = 4, /* Analog mux bus A */ 570 P0_1_AMUXB = 5, /* Analog mux bus B */ 571 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 572 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 573 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 574 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 575 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 576 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 577 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 578 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 579 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 580 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 581 582 /* P0.2 */ 583 P0_2_GPIO = 0, /* GPIO controls 'out' */ 584 P0_2_AMUXA = 4, /* Analog mux bus A */ 585 P0_2_AMUXB = 5, /* Analog mux bus B */ 586 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 587 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 588 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 589 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 590 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 591 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 592 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 593 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 594 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 595 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 596 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 597 598 /* P0.3 */ 599 P0_3_GPIO = 0, /* GPIO controls 'out' */ 600 P0_3_AMUXA = 4, /* Analog mux bus A */ 601 P0_3_AMUXB = 5, /* Analog mux bus B */ 602 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 603 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 604 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 605 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 606 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 607 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 608 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 609 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 610 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 611 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 612 613 /* P2.0 */ 614 P2_0_GPIO = 0, /* GPIO controls 'out' */ 615 P2_0_AMUXA = 4, /* Analog mux bus A */ 616 P2_0_AMUXB = 5, /* Analog mux bus B */ 617 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 618 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 619 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 620 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 621 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 622 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 623 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 624 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 625 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 626 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 627 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 628 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 629 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 630 631 /* P2.1 */ 632 P2_1_GPIO = 0, /* GPIO controls 'out' */ 633 P2_1_AMUXA = 4, /* Analog mux bus A */ 634 P2_1_AMUXB = 5, /* Analog mux bus B */ 635 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 636 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 637 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 638 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 639 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 640 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 641 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 642 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 643 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 644 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 645 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 646 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 647 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 648 649 /* P2.2 */ 650 P2_2_GPIO = 0, /* GPIO controls 'out' */ 651 P2_2_AMUXA = 4, /* Analog mux bus A */ 652 P2_2_AMUXB = 5, /* Analog mux bus B */ 653 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 654 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 655 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 656 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 657 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 658 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 659 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 660 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 661 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 662 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 663 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 664 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 665 666 /* P2.3 */ 667 P2_3_GPIO = 0, /* GPIO controls 'out' */ 668 P2_3_AMUXA = 4, /* Analog mux bus A */ 669 P2_3_AMUXB = 5, /* Analog mux bus B */ 670 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 671 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 672 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 673 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 674 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 675 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 676 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 677 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 678 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 679 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 680 681 /* P3.0 */ 682 P3_0_GPIO = 0, /* GPIO controls 'out' */ 683 P3_0_AMUXA = 4, /* Analog mux bus A */ 684 P3_0_AMUXB = 5, /* Analog mux bus B */ 685 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 686 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 687 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 688 P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 689 P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 690 P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ 691 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 692 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 693 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 694 695 /* P3.1 */ 696 P3_1_GPIO = 0, /* GPIO controls 'out' */ 697 P3_1_AMUXA = 4, /* Analog mux bus A */ 698 P3_1_AMUXB = 5, /* Analog mux bus B */ 699 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 700 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 701 P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 702 P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 703 P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 704 P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ 705 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 706 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 707 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 708 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 709 710 /* P5.0 */ 711 P5_0_GPIO = 0, /* GPIO controls 'out' */ 712 P5_0_AMUXA = 4, /* Analog mux bus A */ 713 P5_0_AMUXB = 5, /* Analog mux bus B */ 714 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 715 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 716 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 717 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 718 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 719 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 720 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 721 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 722 723 /* P5.1 */ 724 P5_1_GPIO = 0, /* GPIO controls 'out' */ 725 P5_1_AMUXA = 4, /* Analog mux bus A */ 726 P5_1_AMUXB = 5, /* Analog mux bus B */ 727 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 728 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 729 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 730 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 731 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 732 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 733 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 734 735 /* P5.2 */ 736 P5_2_GPIO = 0, /* GPIO controls 'out' */ 737 P5_2_AMUXA = 4, /* Analog mux bus A */ 738 P5_2_AMUXB = 5, /* Analog mux bus B */ 739 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 740 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 741 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 742 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 743 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 744 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 745 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 746 747 /* P5.3 */ 748 P5_3_GPIO = 0, /* GPIO controls 'out' */ 749 P5_3_AMUXA = 4, /* Analog mux bus A */ 750 P5_3_AMUXB = 5, /* Analog mux bus B */ 751 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 752 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 753 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 754 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 755 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 756 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 757 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 758 759 /* P6.0 */ 760 P6_0_GPIO = 0, /* GPIO controls 'out' */ 761 P6_0_AMUXA = 4, /* Analog mux bus A */ 762 P6_0_AMUXB = 5, /* Analog mux bus B */ 763 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 764 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 765 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 766 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 767 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 768 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 769 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 770 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 771 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 772 773 /* P6.1 */ 774 P6_1_GPIO = 0, /* GPIO controls 'out' */ 775 P6_1_AMUXA = 4, /* Analog mux bus A */ 776 P6_1_AMUXB = 5, /* Analog mux bus B */ 777 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 778 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 779 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 780 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 781 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 782 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 783 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 784 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 785 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 786 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 787 788 /* P6.2 */ 789 P6_2_GPIO = 0, /* GPIO controls 'out' */ 790 P6_2_AMUXA = 4, /* Analog mux bus A */ 791 P6_2_AMUXB = 5, /* Analog mux bus B */ 792 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 793 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 794 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 795 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 796 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 797 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 798 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 799 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 800 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 801 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 802 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 803 804 /* P6.3 */ 805 P6_3_GPIO = 0, /* GPIO controls 'out' */ 806 P6_3_AMUXA = 4, /* Analog mux bus A */ 807 P6_3_AMUXB = 5, /* Analog mux bus B */ 808 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 809 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 810 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 811 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 812 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 813 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 814 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 815 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 816 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 817 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 818 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 819 820 /* P6.4 */ 821 P6_4_GPIO = 0, /* GPIO controls 'out' */ 822 P6_4_AMUXA = 4, /* Analog mux bus A */ 823 P6_4_AMUXB = 5, /* Analog mux bus B */ 824 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 825 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 826 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 827 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 828 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 829 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 830 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 831 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 832 833 /* P6.5 */ 834 P6_5_GPIO = 0, /* GPIO controls 'out' */ 835 P6_5_AMUXA = 4, /* Analog mux bus A */ 836 P6_5_AMUXB = 5, /* Analog mux bus B */ 837 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 838 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 839 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 840 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 841 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 842 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 843 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 844 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 845 846 /* P7.0 */ 847 P7_0_GPIO = 0, /* GPIO controls 'out' */ 848 P7_0_AMUXA = 4, /* Analog mux bus A */ 849 P7_0_AMUXB = 5, /* Analog mux bus B */ 850 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 851 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 852 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 853 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 854 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 855 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 856 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 857 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 858 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 859 860 /* P7.1 */ 861 P7_1_GPIO = 0, /* GPIO controls 'out' */ 862 P7_1_AMUXA = 4, /* Analog mux bus A */ 863 P7_1_AMUXB = 5, /* Analog mux bus B */ 864 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 865 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 866 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 867 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 868 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 869 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 870 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 871 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 872 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 873 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 874 875 /* P7.2 */ 876 P7_2_GPIO = 0, /* GPIO controls 'out' */ 877 P7_2_AMUXA = 4, /* Analog mux bus A */ 878 P7_2_AMUXB = 5, /* Analog mux bus B */ 879 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 880 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 881 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 882 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 883 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 884 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 885 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 886 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 887 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 888 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 889 890 /* P7.3 */ 891 P7_3_GPIO = 0, /* GPIO controls 'out' */ 892 P7_3_AMUXA = 4, /* Analog mux bus A */ 893 P7_3_AMUXB = 5, /* Analog mux bus B */ 894 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 895 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 896 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 897 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 898 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 899 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 900 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 901 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 902 903 /* P7.4 */ 904 P7_4_GPIO = 0, /* GPIO controls 'out' */ 905 P7_4_AMUXA = 4, /* Analog mux bus A */ 906 P7_4_AMUXB = 5, /* Analog mux bus B */ 907 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 908 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 909 P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 910 P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ 911 P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ 912 P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ 913 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 914 915 /* P7.5 */ 916 P7_5_GPIO = 0, /* GPIO controls 'out' */ 917 P7_5_AMUXA = 4, /* Analog mux bus A */ 918 P7_5_AMUXB = 5, /* Analog mux bus B */ 919 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 920 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 921 P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ 922 P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 923 P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ 924 P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ 925 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 926 927 /* P8.0 */ 928 P8_0_GPIO = 0, /* GPIO controls 'out' */ 929 P8_0_AMUXA = 4, /* Analog mux bus A */ 930 P8_0_AMUXB = 5, /* Analog mux bus B */ 931 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 932 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 933 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 934 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 935 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 936 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 937 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 938 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 939 940 /* P8.1 */ 941 P8_1_GPIO = 0, /* GPIO controls 'out' */ 942 P8_1_AMUXA = 4, /* Analog mux bus A */ 943 P8_1_AMUXB = 5, /* Analog mux bus B */ 944 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 945 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 946 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 947 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 948 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 949 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 950 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 951 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 952 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 953 954 /* P8.2 */ 955 P8_2_GPIO = 0, /* GPIO controls 'out' */ 956 P8_2_AMUXA = 4, /* Analog mux bus A */ 957 P8_2_AMUXB = 5, /* Analog mux bus B */ 958 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 959 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 960 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 961 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 962 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 963 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 964 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 965 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 966 967 /* P11.0 */ 968 P11_0_GPIO = 0, /* GPIO controls 'out' */ 969 P11_0_AMUXA = 4, /* Analog mux bus A */ 970 P11_0_AMUXB = 5, /* Analog mux bus B */ 971 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 972 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 973 974 /* P11.1 */ 975 P11_1_GPIO = 0, /* GPIO controls 'out' */ 976 P11_1_AMUXA = 4, /* Analog mux bus A */ 977 P11_1_AMUXB = 5, /* Analog mux bus B */ 978 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 979 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 980 981 /* P11.2 */ 982 P11_2_GPIO = 0, /* GPIO controls 'out' */ 983 P11_2_AMUXA = 4, /* Analog mux bus A */ 984 P11_2_AMUXB = 5, /* Analog mux bus B */ 985 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 986 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 987 988 /* P12.0 */ 989 P12_0_GPIO = 0, /* GPIO controls 'out' */ 990 P12_0_AMUXA = 4, /* Analog mux bus A */ 991 P12_0_AMUXB = 5, /* Analog mux bus B */ 992 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 993 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 994 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 995 P12_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 996 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 997 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 998 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 999 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 1000 1001 /* P12.1 */ 1002 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1003 P12_1_AMUXA = 4, /* Analog mux bus A */ 1004 P12_1_AMUXB = 5, /* Analog mux bus B */ 1005 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1006 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1007 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 1008 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 1009 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 1010 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 1011 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 1012 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 1013 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 1014 1015 /* P12.2 */ 1016 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1017 P12_2_AMUXA = 4, /* Analog mux bus A */ 1018 P12_2_AMUXB = 5, /* Analog mux bus B */ 1019 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1020 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1021 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 1022 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 1023 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 1024 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 1025 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 1026 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 1027 1028 /* P12.3 */ 1029 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1030 P12_3_AMUXA = 4, /* Analog mux bus A */ 1031 P12_3_AMUXB = 5, /* Analog mux bus B */ 1032 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1033 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1034 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 1035 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 1036 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 1037 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 1038 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 1039 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 1040 1041 /* P12.4 */ 1042 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1043 P12_4_AMUXA = 4, /* Analog mux bus A */ 1044 P12_4_AMUXB = 5, /* Analog mux bus B */ 1045 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1046 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1047 P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ 1048 P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ 1049 P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ 1050 P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ 1051 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 1052 1053 /* P13.0 */ 1054 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1055 P13_0_AMUXA = 4, /* Analog mux bus A */ 1056 P13_0_AMUXB = 5, /* Analog mux bus B */ 1057 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1058 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1059 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 1060 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 1061 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 1062 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 1063 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 1064 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 1065 P13_0_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:0 */ 1066 1067 /* P13.1 */ 1068 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1069 P13_1_AMUXA = 4, /* Analog mux bus A */ 1070 P13_1_AMUXB = 5, /* Analog mux bus B */ 1071 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1072 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1073 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 1074 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 1075 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 1076 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 1077 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 1078 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 1079 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 1080 P13_1_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:0 */ 1081 1082 /* P13.2 */ 1083 P13_2_GPIO = 0, /* GPIO controls 'out' */ 1084 P13_2_AMUXA = 4, /* Analog mux bus A */ 1085 P13_2_AMUXB = 5, /* Analog mux bus B */ 1086 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1087 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1088 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 1089 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 1090 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 1091 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 1092 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 1093 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 1094 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 1095 P13_2_SCB3_SPI_CLK = 19, /* Digital Active - scb[3].spi_clk:0 */ 1096 1097 /* P13.3 */ 1098 P13_3_GPIO = 0, /* GPIO controls 'out' */ 1099 P13_3_AMUXA = 4, /* Analog mux bus A */ 1100 P13_3_AMUXB = 5, /* Analog mux bus B */ 1101 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1102 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1103 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 1104 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 1105 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 1106 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 1107 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 1108 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 1109 P13_3_SCB3_SPI_SELECT0 = 19, /* Digital Active - scb[3].spi_select0:0 */ 1110 1111 /* P13.4 */ 1112 P13_4_GPIO = 0, /* GPIO controls 'out' */ 1113 P13_4_AMUXA = 4, /* Analog mux bus A */ 1114 P13_4_AMUXB = 5, /* Analog mux bus B */ 1115 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1116 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1117 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 1118 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 1119 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 1120 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 1121 P13_4_SCB3_SPI_SELECT1 = 19, /* Digital Active - scb[3].spi_select1:0 */ 1122 1123 /* P13.5 */ 1124 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1125 P13_5_AMUXA = 4, /* Analog mux bus A */ 1126 P13_5_AMUXB = 5, /* Analog mux bus B */ 1127 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1128 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1129 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 1130 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 1131 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 1132 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 1133 P13_5_SCB3_SPI_SELECT2 = 19, /* Digital Active - scb[3].spi_select2:0 */ 1134 1135 /* P13.6 */ 1136 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1137 P13_6_AMUXA = 4, /* Analog mux bus A */ 1138 P13_6_AMUXB = 5, /* Analog mux bus B */ 1139 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1140 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1141 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 1142 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 1143 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 1144 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 1145 P13_6_SCB3_SPI_SELECT3 = 19, /* Digital Active - scb[3].spi_select3:0 */ 1146 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 1147 1148 /* P13.7 */ 1149 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1150 P13_7_AMUXA = 4, /* Analog mux bus A */ 1151 P13_7_AMUXB = 5, /* Analog mux bus B */ 1152 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1153 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1154 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 1155 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 1156 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 1157 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 1158 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 1159 1160 /* P14.0 */ 1161 P14_0_GPIO = 0, /* GPIO controls 'out' */ 1162 P14_0_AMUXA = 4, /* Analog mux bus A */ 1163 P14_0_AMUXB = 5, /* Analog mux bus B */ 1164 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1165 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1166 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 1167 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 1168 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 1169 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 1170 P14_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:0 */ 1171 P14_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:0 */ 1172 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 1173 1174 /* P14.1 */ 1175 P14_1_GPIO = 0, /* GPIO controls 'out' */ 1176 P14_1_AMUXA = 4, /* Analog mux bus A */ 1177 P14_1_AMUXB = 5, /* Analog mux bus B */ 1178 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1179 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1180 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 1181 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 1182 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 1183 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 1184 P14_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:0 */ 1185 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 1186 P14_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:0 */ 1187 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 1188 1189 /* P14.2 */ 1190 P14_2_GPIO = 0, /* GPIO controls 'out' */ 1191 P14_2_AMUXA = 4, /* Analog mux bus A */ 1192 P14_2_AMUXB = 5, /* Analog mux bus B */ 1193 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1194 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1195 P14_2_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:0 */ 1196 P14_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:0 */ 1197 P14_2_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:0 */ 1198 P14_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:0 */ 1199 P14_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:0 */ 1200 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 1201 P14_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:0 */ 1202 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 1203 1204 /* P14.3 */ 1205 P14_3_GPIO = 0, /* GPIO controls 'out' */ 1206 P14_3_AMUXA = 4, /* Analog mux bus A */ 1207 P14_3_AMUXB = 5, /* Analog mux bus B */ 1208 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1209 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1210 P14_3_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:0 */ 1211 P14_3_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:0 */ 1212 P14_3_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:0 */ 1213 P14_3_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:0 */ 1214 P14_3_SCB2_UART_CTS = 17, /* Digital Active - scb[2].uart_cts:0 */ 1215 P14_3_SCB2_SPI_SELECT0 = 19, /* Digital Active - scb[2].spi_select0:0 */ 1216 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 1217 1218 /* P17.0 */ 1219 P17_0_GPIO = 0, /* GPIO controls 'out' */ 1220 P17_0_AMUXA = 4, /* Analog mux bus A */ 1221 P17_0_AMUXB = 5, /* Analog mux bus B */ 1222 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1223 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1224 P17_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:1 */ 1225 P17_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:1 */ 1226 P17_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:1 */ 1227 P17_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:1 */ 1228 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 1229 1230 /* P17.1 */ 1231 P17_1_GPIO = 0, /* GPIO controls 'out' */ 1232 P17_1_AMUXA = 4, /* Analog mux bus A */ 1233 P17_1_AMUXB = 5, /* Analog mux bus B */ 1234 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1235 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1236 P17_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:1 */ 1237 P17_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:1 */ 1238 P17_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:1 */ 1239 P17_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:1 */ 1240 P17_1_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:1 */ 1241 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 1242 P17_1_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:1 */ 1243 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 1244 1245 /* P17.2 */ 1246 P17_2_GPIO = 0, /* GPIO controls 'out' */ 1247 P17_2_AMUXA = 4, /* Analog mux bus A */ 1248 P17_2_AMUXB = 5, /* Analog mux bus B */ 1249 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1250 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1251 P17_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:1 */ 1252 P17_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:1 */ 1253 P17_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:1 */ 1254 P17_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:1 */ 1255 P17_2_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:1 */ 1256 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 1257 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 1258 P17_2_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:1 */ 1259 1260 /* P18.0 */ 1261 P18_0_GPIO = 0, /* GPIO controls 'out' */ 1262 P18_0_AMUXA = 4, /* Analog mux bus A */ 1263 P18_0_AMUXB = 5, /* Analog mux bus B */ 1264 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1265 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1266 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 1267 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 1268 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 1269 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 1270 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 1271 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 1272 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 1273 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 1274 1275 /* P18.1 */ 1276 P18_1_GPIO = 0, /* GPIO controls 'out' */ 1277 P18_1_AMUXA = 4, /* Analog mux bus A */ 1278 P18_1_AMUXB = 5, /* Analog mux bus B */ 1279 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1280 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1281 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 1282 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 1283 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 1284 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 1285 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 1286 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 1287 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 1288 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 1289 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 1290 1291 /* P18.2 */ 1292 P18_2_GPIO = 0, /* GPIO controls 'out' */ 1293 P18_2_AMUXA = 4, /* Analog mux bus A */ 1294 P18_2_AMUXB = 5, /* Analog mux bus B */ 1295 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1296 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1297 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 1298 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 1299 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 1300 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 1301 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 1302 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 1303 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 1304 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 1305 1306 /* P18.3 */ 1307 P18_3_GPIO = 0, /* GPIO controls 'out' */ 1308 P18_3_AMUXA = 4, /* Analog mux bus A */ 1309 P18_3_AMUXB = 5, /* Analog mux bus B */ 1310 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1311 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1312 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 1313 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 1314 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 1315 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 1316 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 1317 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 1318 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 1319 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 1320 1321 /* P18.4 */ 1322 P18_4_GPIO = 0, /* GPIO controls 'out' */ 1323 P18_4_AMUXA = 4, /* Analog mux bus A */ 1324 P18_4_AMUXB = 5, /* Analog mux bus B */ 1325 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1326 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1327 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 1328 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 1329 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 1330 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 1331 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 1332 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 1333 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1334 1335 /* P18.5 */ 1336 P18_5_GPIO = 0, /* GPIO controls 'out' */ 1337 P18_5_AMUXA = 4, /* Analog mux bus A */ 1338 P18_5_AMUXB = 5, /* Analog mux bus B */ 1339 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1340 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1341 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 1342 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 1343 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 1344 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 1345 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 1346 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 1347 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1348 1349 /* P18.6 */ 1350 P18_6_GPIO = 0, /* GPIO controls 'out' */ 1351 P18_6_AMUXA = 4, /* Analog mux bus A */ 1352 P18_6_AMUXB = 5, /* Analog mux bus B */ 1353 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1354 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1355 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 1356 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 1357 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 1358 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 1359 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 1360 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 1361 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 1362 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1363 1364 /* P18.7 */ 1365 P18_7_GPIO = 0, /* GPIO controls 'out' */ 1366 P18_7_AMUXA = 4, /* Analog mux bus A */ 1367 P18_7_AMUXB = 5, /* Analog mux bus B */ 1368 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1369 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1370 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 1371 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 1372 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 1373 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 1374 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 1375 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 1376 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1377 1378 /* P19.0 */ 1379 P19_0_GPIO = 0, /* GPIO controls 'out' */ 1380 P19_0_AMUXA = 4, /* Analog mux bus A */ 1381 P19_0_AMUXB = 5, /* Analog mux bus B */ 1382 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1383 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1384 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 1385 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 1386 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 1387 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 1388 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 1389 P19_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:1 */ 1390 P19_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:1 */ 1391 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 1392 1393 /* P19.1 */ 1394 P19_1_GPIO = 0, /* GPIO controls 'out' */ 1395 P19_1_AMUXA = 4, /* Analog mux bus A */ 1396 P19_1_AMUXB = 5, /* Analog mux bus B */ 1397 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1398 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1399 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 1400 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 1401 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 1402 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 1403 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 1404 P19_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:1 */ 1405 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 1406 P19_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:1 */ 1407 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 1408 1409 /* P19.2 */ 1410 P19_2_GPIO = 0, /* GPIO controls 'out' */ 1411 P19_2_AMUXA = 4, /* Analog mux bus A */ 1412 P19_2_AMUXB = 5, /* Analog mux bus B */ 1413 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1414 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1415 P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 1416 P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 1417 P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ 1418 P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ 1419 P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ 1420 P19_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:1 */ 1421 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 1422 P19_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:1 */ 1423 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 1424 1425 /* P19.3 */ 1426 P19_3_GPIO = 0, /* GPIO controls 'out' */ 1427 P19_3_AMUXA = 4, /* Analog mux bus A */ 1428 P19_3_AMUXB = 5, /* Analog mux bus B */ 1429 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1430 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1431 P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 1432 P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 1433 P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ 1434 P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ 1435 P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ 1436 P19_3_SCB2_UART_CTS = 17, /* Digital Active - scb[2].uart_cts:1 */ 1437 P19_3_SCB2_SPI_SELECT0 = 19, /* Digital Active - scb[2].spi_select0:1 */ 1438 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 1439 1440 /* P21.0 */ 1441 P21_0_GPIO = 0, /* GPIO controls 'out' */ 1442 P21_0_AMUXA = 4, /* Analog mux bus A */ 1443 P21_0_AMUXB = 5, /* Analog mux bus B */ 1444 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1445 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1446 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 1447 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 1448 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 1449 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 1450 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 1451 1452 /* P21.1 */ 1453 P21_1_GPIO = 0, /* GPIO controls 'out' */ 1454 P21_1_AMUXA = 4, /* Analog mux bus A */ 1455 P21_1_AMUXB = 5, /* Analog mux bus B */ 1456 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1457 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1458 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 1459 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 1460 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 1461 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 1462 1463 /* P21.2 */ 1464 P21_2_GPIO = 0, /* GPIO controls 'out' */ 1465 P21_2_AMUXA = 4, /* Analog mux bus A */ 1466 P21_2_AMUXB = 5, /* Analog mux bus B */ 1467 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1468 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1469 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 1470 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 1471 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 1472 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 1473 P21_2_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:0 */ 1474 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 1475 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1476 1477 /* P21.3 */ 1478 P21_3_GPIO = 0, /* GPIO controls 'out' */ 1479 P21_3_AMUXA = 4, /* Analog mux bus A */ 1480 P21_3_AMUXB = 5, /* Analog mux bus B */ 1481 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1482 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1483 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 1484 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 1485 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 1486 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 1487 1488 /* P21.5 */ 1489 P21_5_GPIO = 0, /* GPIO controls 'out' */ 1490 P21_5_AMUXA = 4, /* Analog mux bus A */ 1491 P21_5_AMUXB = 5, /* Analog mux bus B */ 1492 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1493 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1494 P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 1495 P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ 1496 P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ 1497 P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ 1498 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 1499 1500 /* P22.0 */ 1501 P22_0_GPIO = 0, /* GPIO controls 'out' */ 1502 P22_0_AMUXA = 4, /* Analog mux bus A */ 1503 P22_0_AMUXB = 5, /* Analog mux bus B */ 1504 P22_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1505 P22_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1506 P22_0_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:1 */ 1507 P22_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 1508 P22_0_TCPWM0_TR_ONE_CNT_IN102 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 1509 P22_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 1510 P22_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 1511 P22_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 1512 P22_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 1513 P22_0_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1514 1515 /* P22.1 */ 1516 P22_1_GPIO = 0, /* GPIO controls 'out' */ 1517 P22_1_AMUXA = 4, /* Analog mux bus A */ 1518 P22_1_AMUXB = 5, /* Analog mux bus B */ 1519 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1520 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1521 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 1522 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 1523 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 1524 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 1525 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 1526 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 1527 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 1528 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 1529 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1530 1531 /* P22.2 */ 1532 P22_2_GPIO = 0, /* GPIO controls 'out' */ 1533 P22_2_AMUXA = 4, /* Analog mux bus A */ 1534 P22_2_AMUXB = 5, /* Analog mux bus B */ 1535 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1536 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1537 P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 1538 P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 1539 P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ 1540 P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ 1541 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 1542 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 1543 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 1544 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1545 1546 /* P22.3 */ 1547 P22_3_GPIO = 0, /* GPIO controls 'out' */ 1548 P22_3_AMUXA = 4, /* Analog mux bus A */ 1549 P22_3_AMUXB = 5, /* Analog mux bus B */ 1550 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1551 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1552 P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 1553 P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 1554 P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ 1555 P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ 1556 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 1557 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 1558 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1559 1560 /* P23.3 */ 1561 P23_3_GPIO = 0, /* GPIO controls 'out' */ 1562 P23_3_AMUXA = 4, /* Analog mux bus A */ 1563 P23_3_AMUXB = 5, /* Analog mux bus B */ 1564 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1565 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1566 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 1567 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 1568 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 1569 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 1570 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 1571 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 1572 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 1573 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 1574 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1575 1576 /* P23.4 */ 1577 P23_4_GPIO = 0, /* GPIO controls 'out' */ 1578 P23_4_AMUXA = 4, /* Analog mux bus A */ 1579 P23_4_AMUXB = 5, /* Analog mux bus B */ 1580 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1581 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1582 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 1583 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 1584 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 1585 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 1586 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 1587 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 1588 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 1589 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 1590 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1591 1592 /* P23.5 */ 1593 P23_5_GPIO = 0, /* GPIO controls 'out' */ 1594 P23_5_AMUXA = 4, /* Analog mux bus A */ 1595 P23_5_AMUXB = 5, /* Analog mux bus B */ 1596 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1597 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1598 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 1599 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 1600 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 1601 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 1602 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 1603 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 1604 1605 /* P23.6 */ 1606 P23_6_GPIO = 0, /* GPIO controls 'out' */ 1607 P23_6_AMUXA = 4, /* Analog mux bus A */ 1608 P23_6_AMUXB = 5, /* Analog mux bus B */ 1609 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1610 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1611 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 1612 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 1613 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 1614 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 1615 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 1616 1617 /* P23.7 */ 1618 P23_7_GPIO = 0, /* GPIO controls 'out' */ 1619 P23_7_AMUXA = 4, /* Analog mux bus A */ 1620 P23_7_AMUXB = 5, /* Analog mux bus B */ 1621 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1622 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1623 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 1624 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 1625 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 1626 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 1627 P23_7_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:1 */ 1628 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 1629 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 1630 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1631 } en_hsiom_sel_t; 1632 1633 #endif /* _GPIO_TVIIBE1M_100_LQFP_H_ */ 1634 1635 1636 /* [] END OF FILE */ 1637
