1 /***************************************************************************//** 2 * \file cyhal_tviibe4m_64_lqfp.c 3 * 4 * \brief 5 * TVIIBE4M device GPIO HAL header for 64-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE4M_64_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe4m_64_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[7] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 39 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 40 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 41 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 42 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 43 }; 44 45 /* Connections for: canfd_ttcan_tx */ 46 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[8] = { 47 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 48 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 49 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 50 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 51 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 52 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 53 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 54 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 55 }; 56 57 /* Connections for: cpuss_cal_sup_nz */ 58 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 59 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 60 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 61 }; 62 63 /* Connections for: cpuss_clk_fm_pump */ 64 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 65 {0u, 0u, NC, HSIOM_SEL_GPIO}, 66 }; 67 68 /* Connections for: cpuss_fault_out */ 69 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[3] = { 70 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 71 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 72 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 73 }; 74 75 /* Connections for: cpuss_swj_swclk_tclk */ 76 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 77 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 78 }; 79 80 /* Connections for: cpuss_swj_swdio_tms */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 82 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 83 }; 84 85 /* Connections for: cpuss_swj_swdoe_tdi */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 87 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 88 }; 89 90 /* Connections for: cpuss_swj_swo_tdo */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 92 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 93 }; 94 95 /* Connections for: cpuss_swj_trstn */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 97 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 98 }; 99 100 /* Connections for: cpuss_trace_clock */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 102 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 103 }; 104 105 /* Connections for: cpuss_trace_data */ 106 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[5] = { 107 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 108 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 109 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 110 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 111 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 112 }; 113 114 /* Connections for: cxpi_cxpi_en */ 115 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[2] = { 116 {0u, 0u, P7_2, P7_2_CXPI0_CXPI_EN0}, 117 {0u, 1u, P13_2, P13_2_CXPI0_CXPI_EN1}, 118 }; 119 120 /* Connections for: cxpi_cxpi_rx */ 121 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[2] = { 122 {0u, 0u, P7_0, P7_0_CXPI0_CXPI_RX0}, 123 {0u, 1u, P13_0, P13_0_CXPI0_CXPI_RX1}, 124 }; 125 126 /* Connections for: cxpi_cxpi_tx */ 127 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[2] = { 128 {0u, 0u, P7_1, P7_1_CXPI0_CXPI_TX0}, 129 {0u, 1u, P13_1, P13_1_CXPI0_CXPI_TX1}, 130 }; 131 132 /* Connections for: lin_lin_en */ 133 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[7] = { 134 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 135 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 136 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 137 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 138 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 139 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 140 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 141 }; 142 143 /* Connections for: lin_lin_rx */ 144 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[10] = { 145 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 146 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 147 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 148 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 149 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 150 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 151 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 152 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 153 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 154 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 155 }; 156 157 /* Connections for: lin_lin_tx */ 158 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[9] = { 159 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 160 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 161 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 162 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 163 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 164 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 165 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 166 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 167 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 168 }; 169 170 /* Connections for: pass_sar_ext_mux_en */ 171 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[1] = { 172 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 173 }; 174 175 /* Connections for: pass_sar_ext_mux_sel */ 176 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[3] = { 177 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 178 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 179 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 180 }; 181 182 /* Connections for: pass_sarmux_pads */ 183 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[27] = { 184 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 185 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 186 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 187 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 188 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 189 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 190 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 191 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 192 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 193 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 194 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 195 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 196 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 197 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 198 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 199 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 200 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 201 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 202 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 203 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 204 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 205 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 206 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 207 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 208 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 209 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 210 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 211 }; 212 213 /* Connections for: peri_tr_io_input */ 214 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 215 to know the index of the input or output trigger line. Store that in the channel_num field 216 instead. */ 217 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8] = { 218 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 219 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 220 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 221 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 222 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 223 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 224 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 225 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 226 }; 227 228 /* Connections for: peri_tr_io_output */ 229 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 230 to know the index of the input or output trigger line. Store that in the channel_num field 231 instead. */ 232 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 233 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 234 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 235 }; 236 237 /* Connections for: scb_i2c_scl */ 238 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6] = { 239 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 240 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 241 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 242 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 243 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 244 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 245 }; 246 247 /* Connections for: scb_i2c_sda */ 248 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[8] = { 249 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 250 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 251 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 252 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 253 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 254 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 255 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 256 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 257 }; 258 259 /* Connections for: scb_spi_m_clk */ 260 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[5] = { 261 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 262 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 263 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 264 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 265 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 266 }; 267 268 /* Connections for: scb_spi_m_miso */ 269 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[8] = { 270 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 271 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 272 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 273 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 274 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 275 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 276 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 277 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 278 }; 279 280 /* Connections for: scb_spi_m_mosi */ 281 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[7] = { 282 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 283 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 284 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 285 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 286 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 287 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 288 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 289 }; 290 291 /* Connections for: scb_spi_m_select0 */ 292 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[5] = { 293 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 294 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 295 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 296 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 297 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 298 }; 299 300 /* Connections for: scb_spi_m_select1 */ 301 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4] = { 302 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 303 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 304 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 305 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 306 }; 307 308 /* Connections for: scb_spi_m_select2 */ 309 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6] = { 310 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 311 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 312 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 313 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 314 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 315 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 316 }; 317 318 /* Connections for: scb_spi_m_select3 */ 319 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2] = { 320 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 321 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 322 }; 323 324 /* Connections for: scb_spi_s_clk */ 325 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[5] = { 326 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 327 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 328 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 329 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 330 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 331 }; 332 333 /* Connections for: scb_spi_s_miso */ 334 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[8] = { 335 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 336 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 337 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 338 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 339 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 340 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 341 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 342 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 343 }; 344 345 /* Connections for: scb_spi_s_mosi */ 346 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[7] = { 347 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 348 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 349 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 350 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 351 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 352 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 353 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 354 }; 355 356 /* Connections for: scb_spi_s_select0 */ 357 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[5] = { 358 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 359 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 360 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 361 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 362 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 363 }; 364 365 /* Connections for: scb_spi_s_select1 */ 366 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4] = { 367 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 368 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 369 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 370 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 371 }; 372 373 /* Connections for: scb_spi_s_select2 */ 374 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6] = { 375 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 376 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 377 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 378 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 379 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 380 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 381 }; 382 383 /* Connections for: scb_spi_s_select3 */ 384 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2] = { 385 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 386 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 387 }; 388 389 /* Connections for: scb_uart_cts */ 390 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[5] = { 391 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 392 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 393 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 394 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 395 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 396 }; 397 398 /* Connections for: scb_uart_rts */ 399 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[5] = { 400 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 401 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 402 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 403 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 404 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 405 }; 406 407 /* Connections for: scb_uart_rx */ 408 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8] = { 409 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 410 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 411 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 412 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 413 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 414 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 415 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 416 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 417 }; 418 419 /* Connections for: scb_uart_tx */ 420 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[7] = { 421 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 422 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 423 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 424 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 425 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 426 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 427 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 428 }; 429 430 /* Connections for: tcpwm_line */ 431 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[51] = { 432 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 433 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 434 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 435 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 436 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 437 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 438 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 439 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 440 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 441 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 442 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 443 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 444 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 445 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 446 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 447 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 448 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 449 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 450 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 451 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 452 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 453 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 454 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 455 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 456 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 457 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 458 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 459 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 460 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 461 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 462 {2u, 7u, P14_2, P14_2_TCPWM0_LINE519}, 463 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 464 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 465 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 466 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 467 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 468 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 469 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 470 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 471 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 472 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 473 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 474 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 475 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 476 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 477 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 478 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 479 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 480 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 481 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 482 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 483 }; 484 485 /* Connections for: tcpwm_line_compl */ 486 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[51] = { 487 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 488 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 489 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 490 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 491 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 492 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 493 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 494 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 495 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 496 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 497 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 498 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 499 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 500 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 501 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 502 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 503 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 504 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 505 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 506 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 507 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 508 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 509 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 510 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 511 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 512 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 513 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 514 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 515 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 516 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 517 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 518 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 519 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 520 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 521 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 522 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 523 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 524 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 525 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 526 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 527 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 528 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 529 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 530 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 531 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 532 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 533 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 534 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 535 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 536 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 537 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 538 }; 539 540 /* Connections for: tcpwm_tr_one_cnt_in */ 541 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[94] = { 542 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 543 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 544 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 545 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 546 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 547 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 548 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 549 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 550 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 551 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 552 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 553 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 554 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 555 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 556 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 557 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 558 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 559 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 560 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 561 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 562 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 563 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 564 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 565 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 566 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 567 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 568 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 569 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 570 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 571 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 572 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 573 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 574 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 575 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 576 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 577 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 578 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 579 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 580 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 581 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 582 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 583 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 584 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 585 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 586 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 587 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 588 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 589 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 590 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 591 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 592 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 593 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 594 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 595 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 596 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 597 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 598 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 599 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 600 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 601 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 602 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 603 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 604 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 605 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 606 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 607 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 608 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 609 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 610 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 611 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 612 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 613 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 614 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 615 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 616 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 617 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 618 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 619 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 620 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 621 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 622 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 623 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 624 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 625 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 626 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 627 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 628 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 629 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 630 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 631 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 632 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 633 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 634 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 635 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 636 }; 637 638 #endif 639
