1 /***************************************************************************//** 2 * \file cyhal_tviibe4m_80_lqfp.c 3 * 4 * \brief 5 * TVIIBE4M device GPIO HAL header for 80-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE4M_80_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe4m_80_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[9] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 39 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 40 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 41 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 42 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 43 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 44 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 45 }; 46 47 /* Connections for: canfd_ttcan_tx */ 48 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[9] = { 49 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 50 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 51 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 52 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 53 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 54 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 55 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 56 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 57 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 58 }; 59 60 /* Connections for: cpuss_cal_sup_nz */ 61 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 62 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 63 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 64 }; 65 66 /* Connections for: cpuss_clk_fm_pump */ 67 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 68 {0u, 0u, NC, HSIOM_SEL_GPIO}, 69 }; 70 71 /* Connections for: cpuss_fault_out */ 72 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5] = { 73 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 74 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 75 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 76 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 77 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 78 }; 79 80 /* Connections for: cpuss_swj_swclk_tclk */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 82 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 83 }; 84 85 /* Connections for: cpuss_swj_swdio_tms */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 87 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 88 }; 89 90 /* Connections for: cpuss_swj_swdoe_tdi */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 92 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 93 }; 94 95 /* Connections for: cpuss_swj_swo_tdo */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 97 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 98 }; 99 100 /* Connections for: cpuss_swj_trstn */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 102 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 103 }; 104 105 /* Connections for: cpuss_trace_clock */ 106 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 107 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 108 }; 109 110 /* Connections for: cpuss_trace_data */ 111 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[6] = { 112 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 113 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 114 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 115 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 116 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 117 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 118 }; 119 120 /* Connections for: cxpi_cxpi_en */ 121 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[3] = { 122 {0u, 0u, P7_2, P7_2_CXPI0_CXPI_EN0}, 123 {0u, 1u, P13_2, P13_2_CXPI0_CXPI_EN1}, 124 {0u, 2u, P13_7, P13_7_CXPI0_CXPI_EN2}, 125 }; 126 127 /* Connections for: cxpi_cxpi_rx */ 128 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[4] = { 129 {0u, 0u, P7_0, P7_0_CXPI0_CXPI_RX0}, 130 {0u, 1u, P13_0, P13_0_CXPI0_CXPI_RX1}, 131 {0u, 2u, P13_5, P13_5_CXPI0_CXPI_RX2}, 132 {0u, 3u, P19_1, P19_1_CXPI0_CXPI_RX3}, 133 }; 134 135 /* Connections for: cxpi_cxpi_tx */ 136 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[3] = { 137 {0u, 0u, P7_1, P7_1_CXPI0_CXPI_TX0}, 138 {0u, 1u, P13_1, P13_1_CXPI0_CXPI_TX1}, 139 {0u, 2u, P13_6, P13_6_CXPI0_CXPI_TX2}, 140 }; 141 142 /* Connections for: lin_lin_en */ 143 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[11] = { 144 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 145 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 146 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 147 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 148 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 149 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 150 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 151 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 152 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 153 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 154 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 155 }; 156 157 /* Connections for: lin_lin_rx */ 158 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[13] = { 159 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 160 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 161 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 162 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 163 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 164 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 165 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 166 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 167 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 168 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 169 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 170 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 171 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 172 }; 173 174 /* Connections for: lin_lin_tx */ 175 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[11] = { 176 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 177 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 178 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 179 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 180 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 181 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 182 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 183 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 184 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 185 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 186 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 187 }; 188 189 /* Connections for: pass_sar_ext_mux_en */ 190 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 191 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 192 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 193 }; 194 195 /* Connections for: pass_sar_ext_mux_sel */ 196 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[4] = { 197 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 198 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 199 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 200 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 201 }; 202 203 /* Connections for: pass_sarmux_pads */ 204 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[34] = { 205 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 206 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 207 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 208 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 209 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 210 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 211 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 212 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 213 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 214 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 215 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 216 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 217 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 218 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 219 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 220 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 221 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 222 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 223 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 224 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 225 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 226 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 227 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 228 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 229 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 230 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 231 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 232 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 233 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 234 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 235 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 236 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 237 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 238 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 239 }; 240 241 /* Connections for: peri_tr_io_input */ 242 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 243 to know the index of the input or output trigger line. Store that in the channel_num field 244 instead. */ 245 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[12] = { 246 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 247 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 248 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 249 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 250 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 251 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 252 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 253 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 254 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 255 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 256 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 257 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 258 }; 259 260 /* Connections for: peri_tr_io_output */ 261 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 262 to know the index of the input or output trigger line. Store that in the channel_num field 263 instead. */ 264 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 265 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 266 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 267 }; 268 269 /* Connections for: scb_i2c_scl */ 270 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[7] = { 271 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 272 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 273 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 274 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 275 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 276 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 277 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 278 }; 279 280 /* Connections for: scb_i2c_sda */ 281 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10] = { 282 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 283 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 284 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 285 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 286 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 287 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 288 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 289 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 290 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 291 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 292 }; 293 294 /* Connections for: scb_spi_m_clk */ 295 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6] = { 296 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 297 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 298 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 299 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 300 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 301 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 302 }; 303 304 /* Connections for: scb_spi_m_miso */ 305 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[9] = { 306 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 307 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 308 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 309 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 310 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 311 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 312 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 313 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 314 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 315 }; 316 317 /* Connections for: scb_spi_m_mosi */ 318 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[9] = { 319 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 320 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 321 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 322 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 323 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 324 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 325 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 326 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 327 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 328 }; 329 330 /* Connections for: scb_spi_m_select0 */ 331 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7] = { 332 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 333 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 334 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 335 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 336 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 337 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 338 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 339 }; 340 341 /* Connections for: scb_spi_m_select1 */ 342 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5] = { 343 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 344 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 345 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 346 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 347 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 348 }; 349 350 /* Connections for: scb_spi_m_select2 */ 351 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[7] = { 352 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 353 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 354 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 355 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 356 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 357 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 358 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 359 }; 360 361 /* Connections for: scb_spi_m_select3 */ 362 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3] = { 363 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 364 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 365 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 366 }; 367 368 /* Connections for: scb_spi_s_clk */ 369 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6] = { 370 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 371 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 372 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 373 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 374 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 375 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 376 }; 377 378 /* Connections for: scb_spi_s_miso */ 379 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[9] = { 380 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 381 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 382 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 383 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 384 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 385 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 386 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 387 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 388 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 389 }; 390 391 /* Connections for: scb_spi_s_mosi */ 392 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[9] = { 393 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 394 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 395 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 396 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 397 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 398 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 399 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 400 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 401 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 402 }; 403 404 /* Connections for: scb_spi_s_select0 */ 405 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7] = { 406 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 407 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 408 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 409 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 410 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 411 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 412 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 413 }; 414 415 /* Connections for: scb_spi_s_select1 */ 416 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5] = { 417 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 418 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 419 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 420 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 421 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 422 }; 423 424 /* Connections for: scb_spi_s_select2 */ 425 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[7] = { 426 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 427 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 428 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 429 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 430 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 431 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 432 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 433 }; 434 435 /* Connections for: scb_spi_s_select3 */ 436 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3] = { 437 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 438 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 439 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 440 }; 441 442 /* Connections for: scb_uart_cts */ 443 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7] = { 444 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 445 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 446 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 447 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 448 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 449 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 450 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 451 }; 452 453 /* Connections for: scb_uart_rts */ 454 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6] = { 455 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 456 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 457 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 458 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 459 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 460 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 461 }; 462 463 /* Connections for: scb_uart_rx */ 464 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9] = { 465 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 466 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 467 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 468 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 469 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 470 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 471 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 472 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 473 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 474 }; 475 476 /* Connections for: scb_uart_tx */ 477 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9] = { 478 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 479 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 480 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 481 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 482 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 483 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 484 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 485 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 486 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 487 }; 488 489 /* Connections for: tcpwm_line */ 490 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[67] = { 491 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 492 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 493 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 494 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 495 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 496 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 497 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 498 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 499 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 500 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 501 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 502 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 503 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 504 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 505 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 506 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 507 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 508 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 509 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 510 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 511 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 512 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 513 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 514 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 515 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 516 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 517 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 518 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 519 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 520 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 521 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 522 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 523 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 524 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 525 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 526 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 527 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 528 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 529 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 530 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 531 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 532 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 533 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 534 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 535 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 536 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 537 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 538 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 539 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 540 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 541 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 542 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 543 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 544 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 545 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 546 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 547 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 548 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 549 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 550 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 551 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 552 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 553 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 554 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 555 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 556 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 557 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 558 }; 559 560 /* Connections for: tcpwm_line_compl */ 561 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[67] = { 562 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 563 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 564 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 565 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 566 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 567 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 568 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 569 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 570 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 571 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 572 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 573 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 574 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 575 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 576 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 577 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 578 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 579 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 580 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 581 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 582 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 583 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 584 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 585 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 586 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 587 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 588 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 589 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 590 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 591 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 592 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 593 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 594 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 595 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 596 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 597 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 598 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 599 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 600 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 601 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 602 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 603 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 604 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 605 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 606 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 607 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 608 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 609 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 610 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 611 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 612 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 613 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 614 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 615 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 616 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 617 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 618 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 619 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 620 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 621 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 622 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 623 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 624 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 625 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 626 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 627 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 628 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 629 }; 630 631 /* Connections for: tcpwm_tr_one_cnt_in */ 632 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[126] = { 633 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 634 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 635 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 636 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 637 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 638 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 639 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 640 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 641 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 642 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 643 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 644 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 645 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 646 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 647 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 648 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 649 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 650 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 651 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 652 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 653 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 654 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 655 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 656 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 657 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 658 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 659 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 660 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 661 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 662 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 663 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 664 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 665 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 666 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 667 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 668 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 669 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 670 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 671 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 672 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 673 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 674 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 675 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 676 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 677 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 678 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 679 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 680 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 681 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 682 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 683 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 684 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 685 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 686 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 687 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 688 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 689 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 690 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 691 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 692 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 693 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 694 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 695 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 696 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 697 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 698 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 699 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 700 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 701 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 702 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 703 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 704 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 705 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 706 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 707 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 708 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 709 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 710 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 711 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 712 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 713 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 714 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 715 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 716 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 717 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 718 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 719 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 720 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 721 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 722 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 723 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 724 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 725 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 726 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 727 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 728 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 729 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 730 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 731 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 732 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 733 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 734 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 735 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 736 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 737 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 738 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 739 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 740 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 741 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 742 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 743 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 744 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 745 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 746 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 747 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 748 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 749 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 750 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 751 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 752 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 753 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 754 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 755 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 756 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 757 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 758 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 759 }; 760 761 #endif 762
