1 /***************************************************************************//** 2 * \file cyhal_tviibe4m_100_lqfp.c 3 * 4 * \brief 5 * TVIIBE4M device GPIO HAL header for 100-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE4M_100_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe4m_100_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[11] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 39 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 40 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 41 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 42 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 43 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 44 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 45 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 46 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 47 }; 48 49 /* Connections for: canfd_ttcan_tx */ 50 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[11] = { 51 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 52 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 53 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 54 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 55 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 56 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 57 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 58 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 59 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 60 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 61 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 62 }; 63 64 /* Connections for: cpuss_cal_sup_nz */ 65 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 66 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 67 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 68 }; 69 70 /* Connections for: cpuss_clk_fm_pump */ 71 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 72 {0u, 0u, NC, HSIOM_SEL_GPIO}, 73 }; 74 75 /* Connections for: cpuss_fault_out */ 76 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5] = { 77 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 78 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 79 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 80 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 81 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 82 }; 83 84 /* Connections for: cpuss_swj_swclk_tclk */ 85 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 86 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 87 }; 88 89 /* Connections for: cpuss_swj_swdio_tms */ 90 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 91 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 92 }; 93 94 /* Connections for: cpuss_swj_swdoe_tdi */ 95 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 96 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 97 }; 98 99 /* Connections for: cpuss_swj_swo_tdo */ 100 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 101 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 102 }; 103 104 /* Connections for: cpuss_swj_trstn */ 105 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 106 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 107 }; 108 109 /* Connections for: cpuss_trace_clock */ 110 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 111 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 112 }; 113 114 /* Connections for: cpuss_trace_data */ 115 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 116 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 117 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 118 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 119 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 120 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 121 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 122 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 123 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 124 }; 125 126 /* Connections for: cxpi_cxpi_en */ 127 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[4] = { 128 {0u, 0u, P7_2, P7_2_CXPI0_CXPI_EN0}, 129 {0u, 1u, P13_2, P13_2_CXPI0_CXPI_EN1}, 130 {0u, 2u, P13_7, P13_7_CXPI0_CXPI_EN2}, 131 {0u, 3u, P19_3, P19_3_CXPI0_CXPI_EN3}, 132 }; 133 134 /* Connections for: cxpi_cxpi_rx */ 135 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[4] = { 136 {0u, 0u, P7_0, P7_0_CXPI0_CXPI_RX0}, 137 {0u, 1u, P13_0, P13_0_CXPI0_CXPI_RX1}, 138 {0u, 2u, P13_5, P13_5_CXPI0_CXPI_RX2}, 139 {0u, 3u, P19_1, P19_1_CXPI0_CXPI_RX3}, 140 }; 141 142 /* Connections for: cxpi_cxpi_tx */ 143 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[4] = { 144 {0u, 0u, P7_1, P7_1_CXPI0_CXPI_TX0}, 145 {0u, 1u, P13_1, P13_1_CXPI0_CXPI_TX1}, 146 {0u, 2u, P13_6, P13_6_CXPI0_CXPI_TX2}, 147 {0u, 3u, P19_2, P19_2_CXPI0_CXPI_TX3}, 148 }; 149 150 /* Connections for: lin_lin_en */ 151 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[11] = { 152 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 153 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 154 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 155 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 156 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 157 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 158 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 159 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 160 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 161 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 162 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 163 }; 164 165 /* Connections for: lin_lin_rx */ 166 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[16] = { 167 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 168 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 169 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 170 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 171 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 172 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 173 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 174 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 175 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 176 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 177 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 178 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 179 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 180 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 181 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 182 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 183 }; 184 185 /* Connections for: lin_lin_tx */ 186 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[12] = { 187 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 188 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 189 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 190 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 191 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 192 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 193 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 194 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 195 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 196 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 197 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 198 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 199 }; 200 201 /* Connections for: pass_sar_ext_mux_en */ 202 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 203 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 204 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 205 }; 206 207 /* Connections for: pass_sar_ext_mux_sel */ 208 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[5] = { 209 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 210 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 211 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 212 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 213 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 214 }; 215 216 /* Connections for: pass_sarmux_pads */ 217 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[39] = { 218 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 219 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 220 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 221 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 222 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 223 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 224 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 225 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 226 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 227 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 228 {0u, 12u, P7_4, HSIOM_SEL_GPIO}, 229 {0u, 13u, P7_5, HSIOM_SEL_GPIO}, 230 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 231 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 232 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 233 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 234 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 235 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 236 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 237 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 238 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 239 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 240 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 241 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 242 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 243 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 244 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 245 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 246 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 247 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 248 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 249 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 250 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 251 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 252 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 253 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 254 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 255 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 256 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 257 }; 258 259 /* Connections for: peri_tr_io_input */ 260 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 261 to know the index of the input or output trigger line. Store that in the channel_num field 262 instead. */ 263 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[14] = { 264 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 265 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 266 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 267 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 268 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 269 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 270 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 271 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 272 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 273 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 274 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 275 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 276 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 277 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 278 }; 279 280 /* Connections for: peri_tr_io_output */ 281 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 282 to know the index of the input or output trigger line. Store that in the channel_num field 283 instead. */ 284 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4] = { 285 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 286 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 287 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 288 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 289 }; 290 291 /* Connections for: scb_i2c_scl */ 292 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10] = { 293 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 294 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 295 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 296 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 297 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 298 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 299 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 300 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 301 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 302 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 303 }; 304 305 /* Connections for: scb_i2c_sda */ 306 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12] = { 307 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 308 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 309 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 310 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 311 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 312 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 313 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 314 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 315 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 316 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 317 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 318 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 319 }; 320 321 /* Connections for: scb_spi_m_clk */ 322 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9] = { 323 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 324 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 325 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 326 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 327 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 328 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 329 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 330 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 331 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 332 }; 333 334 /* Connections for: scb_spi_m_miso */ 335 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11] = { 336 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 337 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 338 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 339 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 340 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 341 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 342 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 343 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 344 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 345 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 346 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 347 }; 348 349 /* Connections for: scb_spi_m_mosi */ 350 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11] = { 351 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 352 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 353 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 354 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 355 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 356 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 357 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 358 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 359 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 360 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 361 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 362 }; 363 364 /* Connections for: scb_spi_m_select0 */ 365 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10] = { 366 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 367 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 368 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 369 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 370 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 371 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 372 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 373 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 374 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 375 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 376 }; 377 378 /* Connections for: scb_spi_m_select1 */ 379 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[6] = { 380 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 381 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 382 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 383 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 384 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 385 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 386 }; 387 388 /* Connections for: scb_spi_m_select2 */ 389 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8] = { 390 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 391 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 392 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 393 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 394 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 395 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 396 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 397 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 398 }; 399 400 /* Connections for: scb_spi_m_select3 */ 401 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3] = { 402 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 403 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 404 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 405 }; 406 407 /* Connections for: scb_spi_s_clk */ 408 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9] = { 409 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 410 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 411 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 412 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 413 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 414 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 415 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 416 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 417 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 418 }; 419 420 /* Connections for: scb_spi_s_miso */ 421 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11] = { 422 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 423 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 424 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 425 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 426 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 427 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 428 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 429 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 430 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 431 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 432 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 433 }; 434 435 /* Connections for: scb_spi_s_mosi */ 436 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11] = { 437 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 438 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 439 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 440 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 441 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 442 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 443 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 444 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 445 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 446 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 447 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 448 }; 449 450 /* Connections for: scb_spi_s_select0 */ 451 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10] = { 452 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 453 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 454 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 455 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 456 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 457 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 458 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 459 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 460 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 461 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 462 }; 463 464 /* Connections for: scb_spi_s_select1 */ 465 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[6] = { 466 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 467 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 468 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 469 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 470 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 471 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 472 }; 473 474 /* Connections for: scb_spi_s_select2 */ 475 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8] = { 476 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 477 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 478 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 479 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 480 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 481 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 482 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 483 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 484 }; 485 486 /* Connections for: scb_spi_s_select3 */ 487 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3] = { 488 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 489 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 490 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 491 }; 492 493 /* Connections for: scb_uart_cts */ 494 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10] = { 495 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 496 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 497 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 498 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 499 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 500 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 501 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 502 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 503 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 504 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 505 }; 506 507 /* Connections for: scb_uart_rts */ 508 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9] = { 509 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 510 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 511 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 512 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 513 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 514 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 515 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 516 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 517 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 518 }; 519 520 /* Connections for: scb_uart_rx */ 521 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11] = { 522 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 523 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 524 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 525 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 526 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 527 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 528 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 529 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 530 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 531 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 532 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 533 }; 534 535 /* Connections for: scb_uart_tx */ 536 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11] = { 537 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 538 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 539 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 540 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 541 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 542 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 543 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 544 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 545 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 546 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 547 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 548 }; 549 550 /* Connections for: tcpwm_line */ 551 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[84] = { 552 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 553 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 554 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 555 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 556 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 557 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 558 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 559 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 560 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 561 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 562 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 563 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 564 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 565 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 566 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 567 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 568 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 569 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 570 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 571 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 572 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 573 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 574 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 575 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 576 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 577 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 578 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 579 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 580 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 581 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 582 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 583 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 584 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 585 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 586 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 587 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 588 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 589 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 590 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 591 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 592 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 593 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 594 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 595 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 596 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 597 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 598 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 599 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 600 {2u, 7u, P14_2, P14_2_TCPWM0_LINE519}, 601 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 602 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 603 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 604 {2u, 2u, P17_1, P17_1_TCPWM0_LINE514}, 605 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 606 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 607 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 608 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 609 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 610 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 611 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 612 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 613 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 614 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 615 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 616 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 617 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 618 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 619 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 620 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 621 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 622 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 623 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 624 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 625 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 626 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 627 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 628 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 629 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 630 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 631 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 632 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 633 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 634 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 635 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 636 }; 637 638 /* Connections for: tcpwm_line_compl */ 639 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[86] = { 640 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 641 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 642 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 643 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 644 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 645 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 646 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 647 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 648 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 649 {2u, 6u, P3_0, P3_0_TCPWM0_LINE_COMPL518}, 650 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 651 {2u, 7u, P3_1, P3_1_TCPWM0_LINE_COMPL519}, 652 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 653 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 654 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 655 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 656 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 657 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 658 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 659 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 660 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 661 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 662 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 663 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 664 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 665 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 666 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 667 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 668 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 669 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 670 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 671 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 672 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 673 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 674 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 675 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 676 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 677 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 678 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 679 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 680 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 681 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 682 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 683 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 684 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 685 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 686 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 687 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 688 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 689 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 690 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 691 {2u, 7u, P14_3, P14_3_TCPWM0_LINE_COMPL519}, 692 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 693 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 694 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 695 {2u, 2u, P17_2, P17_2_TCPWM0_LINE_COMPL514}, 696 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 697 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 698 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 699 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 700 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 701 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 702 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 703 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 704 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 705 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 706 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 707 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 708 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 709 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 710 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 711 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 712 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 713 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 714 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 715 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 716 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 717 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 718 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 719 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 720 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 721 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 722 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 723 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 724 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 725 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 726 }; 727 728 /* Connections for: tcpwm_tr_one_cnt_in */ 729 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[158] = { 730 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 731 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 732 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 733 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 734 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 735 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 736 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 737 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 738 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 739 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 740 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 741 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 742 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 743 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 744 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 745 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 746 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 747 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 748 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 749 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 750 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 751 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 752 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 753 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 754 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 755 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 756 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 757 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 758 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 759 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 760 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 761 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 762 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 763 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 764 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 765 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 766 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 767 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 768 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 769 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 770 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 771 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 772 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 773 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 774 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 775 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 776 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 777 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 778 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 779 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 780 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 781 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 782 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 783 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 784 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 785 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 786 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 787 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 788 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 789 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 790 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 791 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 792 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 793 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 794 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 795 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 796 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 797 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 798 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 799 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 800 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 801 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 802 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 803 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 804 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 805 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 806 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 807 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 808 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 809 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 810 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 811 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 812 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 813 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 814 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 815 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 816 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 817 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 818 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 819 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 820 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 821 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 822 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 823 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 824 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 825 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 826 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 827 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 828 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 829 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 830 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 831 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 832 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 833 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 834 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 835 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 836 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 837 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 838 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 839 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 840 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 841 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 842 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 843 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 844 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 845 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 846 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 847 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 848 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 849 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 850 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 851 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 852 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 853 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 854 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 855 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 856 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 857 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 858 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 859 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 860 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 861 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 862 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 863 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 864 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 865 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 866 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 867 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 868 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 869 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 870 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 871 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 872 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 873 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 874 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 875 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 876 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 877 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 878 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 879 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 880 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 881 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 882 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 883 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 884 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 885 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 886 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 887 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 888 }; 889 890 #endif 891
