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Searched refs:CPUSS_RAMC0_MACRO_NR (Results 1 – 17 of 17) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_syspm.c2092 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_SetSRAMMacroPwrMode()
2093 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR) in Cy_SysPm_SetSRAMMacroPwrMode()
2134 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_GetSRAMMacroPwrMode()
2135 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR) in Cy_SysPm_GetSRAMMacroPwrMode()
2175 for(idx = 0UL; idx < CPUSS_RAMC0_MACRO_NR; idx++) in Cy_SysPm_SetSRAMPwrMode()
Dcy_syspm_v3.c1502 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_SetSRAMMacroPwrMode()
1503 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR) in Cy_SysPm_SetSRAMMacroPwrMode()
1545 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR ); in Cy_SysPm_GetSRAMMacroPwrMode()
1546 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR) in Cy_SysPm_GetSRAMMacroPwrMode()
1578 for(idx = 0UL; idx < CPUSS_RAMC0_MACRO_NR; idx++) in Cy_SysPm_SetSRAMPwrMode()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device_common.h414 #define CPUSS_RAMC0_MACRO_NR 9u macro
Dpsoc6_01_config.h1668 #define CPUSS_RAMC0_MACRO_NR 9u macro
Dpsoc6_03_config.h1319 #define CPUSS_RAMC0_MACRO_NR 8u macro
Dpsoc6_04_config.h1281 #define CPUSS_RAMC0_MACRO_NR 4u macro
Dpsoc6_02_config.h1794 #define CPUSS_RAMC0_MACRO_NR 16u macro
Dfx3g2_config.h1951 #define CPUSS_RAMC0_MACRO_NR 4u macro
Dtviibe1m_config.h1771 #define CPUSS_RAMC0_MACRO_NR 2u macro
Dtviibe2m_config.h1930 #define CPUSS_RAMC0_MACRO_NR 4u macro
Dtviibe4m_config.h1931 #define CPUSS_RAMC0_MACRO_NR 8u macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcyw20829B0_config.h632 #define CPUSS_RAMC0_MACRO_NR 4u macro
Dcyw20829_config.h632 #define CPUSS_RAMC0_MACRO_NR 4u macro
Dcy_device.h2523 #define CY_CPUSS_RAMC0_MACRO_NR CPUSS_RAMC0_MACRO_NR
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h2014 #define CPUSS_RAMC0_MACRO_NR 16u macro
Dtviic2d6m_config.h2166 #define CPUSS_RAMC0_MACRO_NR 8u macro
Dxmc7200_config.h2599 #define CPUSS_RAMC0_MACRO_NR 16u macro