1 /***************************************************************************//** 2 * \file cy_device_common.h 3 * \version 2.91 4 * 5 * \brief 6 * This file provides types and IP block definitions common for all PSoC 6 7 * devices. 8 * 9 ******************************************************************************** 10 * \copyright 11 * Copyright 2018-2021 Cypress Semiconductor Corporation 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CY_DEVICE_COMMON_H_ 28 #define _CY_DEVICE_COMMON_H_ 29 30 #include <stdint.h> 31 32 /******************************************************************************* 33 * CPU Core Interrupts 34 *******************************************************************************/ 35 36 typedef enum { 37 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 38 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 39 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ 40 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 41 /* ARM Cortex-M0+ Core Interrupt Numbers */ 42 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 43 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 44 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 45 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 46 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 47 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 48 cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ 49 unconnected_IRQn = 240 50 #else 51 /* ARM Cortex-M4 Core Interrupt Numbers */ 52 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 53 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 54 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 55 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 56 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 57 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 58 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 59 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 60 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 61 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 62 cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ 63 unconnected_IRQn = 240 64 #endif 65 } IRQn_Type; 66 67 68 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 69 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 70 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ 71 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 72 73 typedef enum { 74 disconnected_IRQn = 1023 /*!< 1023 Disconnected */ 75 } cy_en_intr_t; 76 77 #endif 78 79 /******************************************************************************* 80 * Processor and Core Peripheral Section 81 *******************************************************************************/ 82 83 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 84 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 85 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ 86 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 87 88 /* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ 89 #define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ 90 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 91 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 92 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 93 #define __MPU_PRESENT 1 /*!< MPU present or not */ 94 95 /** \} Configuration_of_CMSIS */ 96 97 #include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ 98 99 #else 100 101 /* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ 102 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 103 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 104 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 105 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 106 #define __MPU_PRESENT 1 /*!< MPU present or not */ 107 #define __FPU_PRESENT 1 /*!< FPU present or not */ 108 #define __CM0P_PRESENT 1 /*!< CM0P present or not */ 109 110 /** \} Configuration_of_CMSIS */ 111 112 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 113 114 #endif 115 116 /******************************************************************************* 117 * Product-Specific Enumeration Types 118 *******************************************************************************/ 119 /* For the target device these enums are defined in product-specific 120 * configuration files. 121 * For the library these enums define the max value or a set of values used by 122 * the library that are common across all target devices, so the compiler can 123 * determine the enum width to hold the biggest number in the enum. 124 */ 125 126 typedef enum 127 { 128 PCLK_PASS_CLOCK_CTDAC = 55, 129 PCLK_CLOCK_NR_MINUS_ONE = 255 130 } en_clk_dst_t; 131 132 typedef enum 133 { 134 PRFL_MONITOR_NR_MINUS_ONE = 127 135 } en_ep_mon_sel_t; 136 137 typedef enum 138 { 139 AMUX_SPLIT_NR_MINUS_ONE = 63 140 } cy_en_amux_split_t; 141 142 typedef enum 143 { 144 TRIGGER_TYPE_LEVEL = 0u, 145 TRIGGER_TYPE_EDGE = 1u 146 } en_trig_type_t; 147 148 typedef enum 149 { 150 CPUSS_MS_ID_CM0 = 0, 151 CPUSS_MS_ID_CM4 = 14, 152 } en_prot_master_t; 153 154 typedef enum 155 { 156 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 157 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 158 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 159 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 160 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 161 } en_hsiom_sel_t; 162 163 /******************************************************************************* 164 * Platform and Peripheral Definitions 165 *******************************************************************************/ 166 167 #define CY_IP_MXTCPWM 1u 168 #define CY_IP_MXTCPWM_INSTANCES 1u 169 #define CY_IP_MXTCPWM_VERSION 1u 170 #define CY_IP_MXCSDV2 1u 171 #define CY_IP_MXLCD 1u 172 #define CY_IP_MXS40SRSS 1u 173 #define CY_IP_MXS40SRSS_RTC 1u 174 #define CY_IP_MXS40SRSS_MCWDT 1u 175 #define CY_IP_MXSCB 1u 176 #define CY_IP_MXSCB_VERSION 1u 177 #define CY_IP_MXPERI 1u 178 #define CY_IP_MXPERI_TR 1u 179 #define CY_IP_M4CPUSS 1u 180 #define CY_IP_M4CPUSS_DMAC 1u 181 #define CY_IP_M4CPUSS_DMA 1u 182 #define CY_IP_MXCRYPTO 1u 183 #define CY_IP_MXCRYPTO_VERSION 2u 184 #define CY_IP_MXBLESS 1u 185 #define CY_IP_MXSDHC 1u 186 #define CY_IP_MXTTCANFD 1u 187 #define CY_IP_MXAUDIOSS 1u 188 #define CY_IP_MXLPCOMP 1u 189 #define CY_IP_MXS40PASS 1u 190 #define CY_IP_MXS40PASS_SAR 1u 191 #define CY_IP_MXS40PASS_CTDAC 1u 192 #define CY_IP_MXS40PASS_CTB 1u 193 #define CY_IP_MXSMIF 1u 194 #define CY_IP_MXSMIF_VERSION 1u 195 #define CY_IP_MXUSBFS 1u 196 #define CY_IP_MXS40IOSS 1u 197 #define CY_IP_MXEFUSE 1u 198 #define CY_IP_MXUDB 1u 199 #define CY_IP_MXPROFILE 1u 200 201 202 /******************************************************************************* 203 * Include IP Block Definitions 204 *******************************************************************************/ 205 #include "ip/cyip_sflash_psoc6_01.h" 206 #include "ip/cyip_peri.h" 207 #include "ip/cyip_peri_v2.h" 208 #include "ip/cyip_peri_ms_v2.h" 209 #include "ip/cyip_crypto.h" 210 #include "ip/cyip_crypto_v2.h" 211 #include "ip/cyip_cpuss.h" 212 #include "ip/cyip_cpuss_v2.h" 213 #include "ip/cyip_fault.h" 214 #include "ip/cyip_fault_v2.h" 215 #include "ip/cyip_ipc.h" 216 #include "ip/cyip_ipc_v2.h" 217 #include "ip/cyip_prot.h" 218 #include "ip/cyip_prot_v2.h" 219 #include "ip/cyip_flashc.h" 220 #include "ip/cyip_flashc_v2.h" 221 #include "ip/cyip_srss.h" 222 #include "ip/cyip_backup.h" 223 #include "ip/cyip_dw.h" 224 #include "ip/cyip_dw_v2.h" 225 #include "ip/cyip_dmac_v2.h" 226 #include "ip/cyip_efuse.h" 227 #include "ip/cyip_profile.h" 228 #include "ip/cyip_hsiom.h" 229 #include "ip/cyip_hsiom_v2.h" 230 #include "ip/cyip_gpio.h" 231 #include "ip/cyip_gpio_v2.h" 232 #include "ip/cyip_smartio.h" 233 #include "ip/cyip_smartio_v2.h" 234 #include "ip/cyip_udb.h" 235 #include "ip/cyip_lpcomp.h" 236 #include "ip/cyip_csd.h" 237 #include "ip/cyip_tcpwm.h" 238 #include "ip/cyip_lcd.h" 239 #include "ip/cyip_ble.h" 240 #include "ip/cyip_usbfs.h" 241 #include "ip/cyip_smif.h" 242 #include "ip/cyip_sdhc.h" 243 #include "ip/cyip_scb.h" 244 #include "ip/cyip_ctbm.h" 245 #include "ip/cyip_ctdac.h" 246 #include "ip/cyip_sar.h" 247 #include "ip/cyip_pass.h" 248 #include "ip/cyip_pass_v2.h" 249 #include "ip/cyip_i2s.h" 250 #include "ip/cyip_pdm.h" 251 #include "ip/cyip_canfd.h" 252 253 /******************************************************************************* 254 * IP Type Definitions 255 *******************************************************************************/ 256 typedef SFLASH_V1_Type SFLASH_Type; 257 typedef PERI_GR_V2_Type PERI_GR_Type; 258 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 259 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 260 typedef PERI_PPU_PR_V1_Type PERI_PPU_PR_Type; 261 typedef PERI_PPU_GR_V1_Type PERI_PPU_GR_Type; 262 typedef PERI_GR_PPU_SL_V1_Type PERI_GR_PPU_SL_Type; 263 typedef PERI_GR_PPU_RG_V1_Type PERI_GR_PPU_RG_Type; 264 typedef PERI_V2_Type PERI_Type; 265 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 266 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 267 typedef PERI_MS_V2_Type PERI_MS_Type; 268 typedef CRYPTO_V2_Type CRYPTO_Type; 269 typedef CPUSS_V2_Type CPUSS_Type; 270 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 271 typedef FAULT_V2_Type FAULT_Type; 272 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 273 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 274 typedef IPC_V2_Type IPC_Type; 275 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 276 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 277 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 278 typedef PROT_MPU_V2_Type PROT_MPU_Type; 279 typedef PROT_V2_Type PROT_Type; 280 typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; 281 typedef FLASHC_V2_Type FLASHC_Type; 282 typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; 283 typedef SRSS_V1_Type SRSS_Type; 284 typedef BACKUP_V1_Type BACKUP_Type; 285 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 286 typedef DW_V2_Type DW_Type; 287 typedef DMAC_CH_V2_Type DMAC_CH_Type; 288 typedef DMAC_V2_Type DMAC_Type; 289 typedef EFUSE_V1_Type EFUSE_Type; 290 typedef PROFILE_CNT_STRUCT_V1_Type PROFILE_CNT_STRUCT_Type; 291 typedef PROFILE_V1_Type PROFILE_Type; 292 typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; 293 typedef HSIOM_V2_Type HSIOM_Type; 294 typedef GPIO_PRT_V2_Type GPIO_PRT_Type; 295 typedef GPIO_V2_Type GPIO_Type; 296 typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; 297 typedef SMARTIO_V2_Type SMARTIO_Type; 298 typedef UDB_WRKONE_V1_Type UDB_WRKONE_Type; 299 typedef UDB_WRKMULT_V1_Type UDB_WRKMULT_Type; 300 typedef UDB_UDBPAIR_UDBSNG_V1_Type UDB_UDBPAIR_UDBSNG_Type; 301 typedef UDB_UDBPAIR_ROUTE_V1_Type UDB_UDBPAIR_ROUTE_Type; 302 typedef UDB_UDBPAIR_V1_Type UDB_UDBPAIR_Type; 303 typedef UDB_DSI_V1_Type UDB_DSI_Type; 304 typedef UDB_PA_V1_Type UDB_PA_Type; 305 typedef UDB_BCTL_V1_Type UDB_BCTL_Type; 306 typedef UDB_UDBIF_V1_Type UDB_UDBIF_Type; 307 typedef UDB_V1_Type UDB_Type; 308 typedef LPCOMP_V1_Type LPCOMP_Type; 309 typedef CSD_V1_Type CSD_Type; 310 typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type; 311 typedef TCPWM_V1_Type TCPWM_Type; 312 typedef LCD_V1_Type LCD_Type; 313 typedef BLE_RCB_RCBLL_V1_Type BLE_RCB_RCBLL_Type; 314 typedef BLE_RCB_V1_Type BLE_RCB_Type; 315 typedef BLE_BLELL_V1_Type BLE_BLELL_Type; 316 typedef BLE_BLESS_V1_Type BLE_BLESS_Type; 317 typedef BLE_V1_Type BLE_Type; 318 typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; 319 typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; 320 typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; 321 typedef USBFS_V1_Type USBFS_Type; 322 typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; 323 typedef SMIF_V1_Type SMIF_Type; 324 typedef SDHC_WRAP_V1_Type SDHC_WRAP_Type; 325 typedef SDHC_CORE_V1_Type SDHC_CORE_Type; 326 typedef SDHC_V1_Type SDHC_Type; 327 typedef CySCB_V1_Type CySCB_Type; 328 typedef CTBM_V1_Type CTBM_Type; 329 typedef CTDAC_V1_Type CTDAC_Type; 330 typedef SAR_V1_Type SAR_Type; 331 typedef PASS_AREF_V1_Type PASS_AREF_Type; 332 typedef PASS_V1_Type PASS_Type; 333 typedef PDM_V1_Type PDM_Type; 334 typedef I2S_V1_Type I2S_Type; 335 typedef CANFD_V1_Type CANFD_Type; 336 typedef CANFD_CH_V1_Type CANFD_CH_Type; 337 typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; 338 339 /******************************************************************************* 340 * Symbols with External Linkage 341 *******************************************************************************/ 342 343 extern uint32_t cy_PeriClkFreqHz; 344 extern uint32_t cy_BleEcoClockFreqHz; 345 extern uint32_t cy_Hfclk0FreqHz; 346 extern uint32_t cy_delayFreqKhz; 347 extern uint8_t cy_delayFreqMhz; 348 extern uint32_t cy_AhbFreqHz; 349 350 extern void SystemCoreClockUpdate(void); 351 extern uint32_t Cy_SysGetCM4Status(void); 352 353 /******************************************************************************* 354 * Platform and Peripheral Parameters 355 *******************************************************************************/ 356 357 /* Flash Start Address and Size */ 358 #define CY_FLASH_BASE 0x10000000UL 359 #define CY_FLASH_SIZE 0x00100000UL 360 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 361 #define CPUSS_FLASHC_PA_SIZE 128u 362 /* EEPROM Start Address and Size */ 363 #define CY_EM_EEPROM_BASE 0x14000000UL 364 #define CY_EM_EEPROM_SIZE 0x00008000UL 365 /* Number of 8.0 dividers */ 366 #define PERI_DIV_8_NR 8u 367 /* Number of 16.0 dividers */ 368 #define PERI_DIV_16_NR 16u 369 /* Number of 16.5 (fractional) dividers */ 370 #define PERI_DIV_16_5_NR 4u 371 /* Number of 24.5 (fractional) dividers */ 372 #define PERI_DIV_24_5_NR 1u 373 /* The number of protection contexts ([2, 16]). */ 374 #define PERI_PC_NR 8u 375 /* Number of external devices supported ([1,4]) */ 376 #define SMIF_DEVICE_NR 4u 377 /* Number of ports in device */ 378 #define IOSS_GPIO_GPIO_PORT_NR 15u 379 /* Number of SAR channels */ 380 #define PASS_SAR_SAR_CHANNELS 16u 381 /* CM4 Enabled State */ 382 #define CY_SYS_CM4_STATUS_ENABLED 3U 383 /* Cryptography IP present or not (0=No, 1=Yes) */ 384 #define CPUSS_CRYPTO_PRESENT 1u 385 /* AES cipher support (0 = no support, 1 = support */ 386 #define CPUSS_CRYPTO_AES 1u 387 /* (Tripple) DES cipher support (0 = no support, 1 = support */ 388 #define CPUSS_CRYPTO_DES 1u 389 /* Pseudo random number generation support (0 = no support, 1 = support) */ 390 #define CPUSS_CRYPTO_PR 1u 391 /* SHA support included */ 392 #define CPUSS_CRYPTO_SHA 1u 393 /* SHA1 hash support (0 = no support, 1 = support) */ 394 #define CPUSS_CRYPTO_SHA1 1u 395 /* SHA256 hash support (0 = no support, 1 = support) */ 396 #define CPUSS_CRYPTO_SHA256 1u 397 /* SHA512 hash support (0 = no support, 1 = support) */ 398 #define CPUSS_CRYPTO_SHA512 1u 399 /* Cyclic Redundancy Check support (0 = no support, 1 = support) */ 400 #define CPUSS_CRYPTO_CRC 1u 401 /* Vector unit support (0 = no support, 1 = support) */ 402 #define CPUSS_CRYPTO_VU 1u 403 /* True random number generation support (0 = no support, 1 = support) */ 404 #define CPUSS_CRYPTO_TR 1u 405 /* String support (0 = no support, 1 = support) */ 406 #define CPUSS_CRYPTO_STR 1u 407 /* Number of ports supoprting up to 4 COMs */ 408 #define LCD_NUMPORTS 8u 409 /* Number of ports supporting up to 8 COMs */ 410 #define LCD_NUMPORTS8 8u 411 /* Number of ports supporting up to 16 COMs */ 412 #define LCD_NUMPORTS16 0u 413 /* SRAM0 is implemented with 8 32KB macros. */ 414 #define CPUSS_RAMC0_MACRO_NR 9u 415 /* System RAM 1 present or not (0=No, 1=Yes) */ 416 #define CPUSS_RAMC1_PRESENT 0u 417 /* System RAM 1 size in kilobytes */ 418 #define CPUSS_SRAM1_SIZE 32u 419 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 420 RAM 1 is implemented with 8 32KB macros. */ 421 #define CPUSS_RAMC1_MACRO_NR 1u 422 /* System RAM 2 present or not (0=No, 1=Yes) */ 423 #define CPUSS_RAMC2_PRESENT 0u 424 /* System RAM 2 size in kilobytes */ 425 #define CPUSS_SRAM2_SIZE 256u 426 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 427 RAM 2 is implemented with 8 32KB macros. */ 428 #define CPUSS_RAMC2_MACRO_NR 16u 429 /* System ROM size in KB */ 430 #define CPUSS_ROM_SIZE 128u 431 /* Number of DMAC channels */ 432 #define CPUSS_DMAC_CH_NR 4u 433 434 /******************************************************************************* 435 * Access Definitions for IP Blocks 436 *******************************************************************************/ 437 438 #define SFLASH_BASE 0x16000000UL 439 #define SFLASH ((SFLASH_Type*) SFLASH_BASE) 440 #define SRSS_BASE 0x40260000UL 441 #define SRSS ((SRSS_Type*) SRSS_BASE) 442 #define BACKUP_BASE 0x40270000UL 443 #define BACKUP ((BACKUP_Type*) BACKUP_BASE) 444 #define PROFILE_BASE 0x402D0000UL 445 #define PROFILE ((PROFILE_Type*) PROFILE_BASE) 446 #define BLE_BASE 0x403C0000UL 447 #define BLE ((BLE_Type*) BLE_BASE) 448 #define CRYPTO_BASE 0x40110000UL 449 #define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ 450 #define CTBM0_BASE 0x40900000UL /* for the PASS_v2 only */ 451 #define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ 452 #endif /* _CY_DEVICE_COMMON_H_ */ 453 454 455 /* [] END OF FILE */ 456
