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Searched refs:en1_clr (Results 1 – 20 of 20) sorted by relevance

/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/GPIO/
Dgpio_reva.c153 port->en1_clr = mask; in MXC_GPIO_RevA_SetAF()
161 port->en1_clr = mask; in MXC_GPIO_RevA_SetAF()
169 port->en1_clr = mask; in MXC_GPIO_RevA_SetAF()
184 port->en1_clr = mask; in MXC_GPIO_RevA_SetAF()
199 port->en1_clr = mask; in MXC_GPIO_RevA_SetAF()
Dgpio_revb.c39 gpio->en1_clr = cfg->mask; in MXC_GPIO_RevB_Config()
46 gpio->en1_clr = cfg->mask; in MXC_GPIO_RevB_Config()
52 gpio->en1_clr = cfg->mask; in MXC_GPIO_RevB_Config()
Dgpio_me11.c76 gpio->en1_clr = cfg->mask; in MXC_GPIO_Config()
83 gpio->en1_clr = cfg->mask; in MXC_GPIO_Config()
89 gpio->en1_clr = cfg->mask; in MXC_GPIO_Config()
Dgpio_reva_regs.h103 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO_REVA EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Include/
Dgpio_regs.h104 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Include/
Dgpio_regs.h105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ member
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SPIXF/
Dspixf_me55.c65 port->en1_clr = cfg->mask; in MXC_GPIO_Config_SPIXF()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/AFE/
Dhart_uart.c741 HART_CLK_GPIO_PORT->en1_clr = HART_CLK_GPIO_PIN; in idle_hart_clock_pin()