1 /** 2 * @file gpio_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup gpio_reva 65 * @defgroup gpio_reva_registers GPIO_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the GPIO_REVA Peripheral Module. 67 * @details Individual I/O for each GPIO 68 */ 69 70 /** 71 * @ingroup gpio_reva_registers 72 * Structure type to access the GPIO_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO_REVA EN0 Register */ 76 __IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO_REVA EN0_SET Register */ 77 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO_REVA EN0_CLR Register */ 78 __IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO_REVA OUTEN Register */ 79 __IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO_REVA OUTEN_SET Register */ 80 __IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO_REVA OUTEN_CLR Register */ 81 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO_REVA OUT Register */ 82 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO_REVA OUT_SET Register */ 83 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO_REVA OUT_CLR Register */ 84 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO_REVA IN Register */ 85 __IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO_REVA INTMODE Register */ 86 __IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO_REVA INTPOL Register */ 87 __IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO_REVA INEN Register */ 88 __IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO_REVA INTEN Register */ 89 __IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO_REVA INTEN_SET Register */ 90 __IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO_REVA INTEN_CLR Register */ 91 __I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO_REVA INTFL Register */ 92 __R uint32_t rsv_0x44; 93 __IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO_REVA INTFL_CLR Register */ 94 __IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO_REVA WKEN Register */ 95 __IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO_REVA WKEN_SET Register */ 96 __IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO_REVA WKEN_CLR Register */ 97 __R uint32_t rsv_0x58; 98 __IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO_REVA DUALEDGE Register */ 99 __IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO_REVA PADCTRL0 Register */ 100 __IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO_REVA PADCTRL1 Register */ 101 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO_REVA EN1 Register */ 102 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO_REVA EN1_SET Register */ 103 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO_REVA EN1_CLR Register */ 104 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO_REVA EN2 Register */ 105 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO_REVA EN2_SET Register */ 106 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO_REVA EN2_CLR Register */ 107 __IO uint32_t en3; /**< <tt>\b 0x80:</tt> GPIO_REVA EN3 Register */ 108 __IO uint32_t en3_set; /**< <tt>\b 0x84:</tt> GPIO_REVA EN3_SET Register */ 109 __IO uint32_t en3_clr; /**< <tt>\b 0x88:</tt> GPIO_REVA EN3_CLR Register */ 110 __R uint32_t rsv_0x8c_0xa7[7]; 111 __IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO_REVA HYSEN Register */ 112 __IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO_REVA SRSEL Register */ 113 __IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO_REVA DS0 Register */ 114 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO_REVA DS1 Register */ 115 __IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO_REVA PS Register */ 116 __R uint32_t rsv_0xbc; 117 __IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO_REVA VSSEL Register */ 118 } mxc_gpio_reva_regs_t; 119 120 /* Register offsets for module GPIO_REVA */ 121 /** 122 * @ingroup gpio_reva_registers 123 * @defgroup GPIO_REVA_Register_Offsets Register Offsets 124 * @brief GPIO_REVA Peripheral Register Offsets from the GPIO_REVA Base Peripheral Address. 125 * @{ 126 */ 127 #define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0000</tt> */ 128 #define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0004</tt> */ 129 #define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0008</tt> */ 130 #define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x000C</tt> */ 131 #define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0010</tt> */ 132 #define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0014</tt> */ 133 #define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0018</tt> */ 134 #define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x001C</tt> */ 135 #define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0020</tt> */ 136 #define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0024</tt> */ 137 #define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0028</tt> */ 138 #define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x002C</tt> */ 139 #define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0030</tt> */ 140 #define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0034</tt> */ 141 #define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0038</tt> */ 142 #define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x003C</tt> */ 143 #define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0040</tt> */ 144 #define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0048</tt> */ 145 #define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x004C</tt> */ 146 #define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0050</tt> */ 147 #define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0054</tt> */ 148 #define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x005C</tt> */ 149 #define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0060</tt> */ 150 #define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0064</tt> */ 151 #define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0068</tt> */ 152 #define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x006C</tt> */ 153 #define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0070</tt> */ 154 #define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0074</tt> */ 155 #define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0078</tt> */ 156 #define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x007C</tt> */ 157 #define MXC_R_GPIO_REVA_EN3 ((uint32_t)0x00000080UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0080</tt> */ 158 #define MXC_R_GPIO_REVA_EN3_SET ((uint32_t)0x00000084UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0084</tt> */ 159 #define MXC_R_GPIO_REVA_EN3_CLR ((uint32_t)0x00000088UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x0088</tt> */ 160 #define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00A8</tt> */ 161 #define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00AC</tt> */ 162 #define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00B0</tt> */ 163 #define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00B4</tt> */ 164 #define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00B8</tt> */ 165 #define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO_REVA Base Address: <tt> 0x00C0</tt> */ 166 /**@} end of group gpio_reva_registers */ 167 168 /** 169 * @ingroup gpio_reva_registers 170 * @defgroup GPIO_REVA_EN0 GPIO_REVA_EN0 171 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one 172 * GPIO pin on the associated port. 173 * @{ 174 */ 175 #define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ 176 #define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ 177 #define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ 178 #define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ 179 #define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ 180 #define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ 181 182 /**@} end of group GPIO_REVA_EN0_Register */ 183 184 /** 185 * @ingroup gpio_reva_registers 186 * @defgroup GPIO_REVA_EN0_SET GPIO_REVA_EN0_SET 187 * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this 188 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 189 * other bits in that register. 190 * @{ 191 */ 192 #define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ 193 #define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ 194 195 /**@} end of group GPIO_REVA_EN0_SET_Register */ 196 197 /** 198 * @ingroup gpio_reva_registers 199 * @defgroup GPIO_REVA_EN0_CLR GPIO_REVA_EN0_CLR 200 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 201 * register clears the bits in the same positions in GPIO_EN to 0, without 202 * affecting other bits in that register. 203 * @{ 204 */ 205 #define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ 206 #define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ 207 208 /**@} end of group GPIO_REVA_EN0_CLR_Register */ 209 210 /** 211 * @ingroup gpio_reva_registers 212 * @defgroup GPIO_REVA_OUTEN GPIO_REVA_OUTEN 213 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 214 * GPIO pin in the associated port. 215 * @{ 216 */ 217 #define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ 218 #define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ 219 #define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ 220 #define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ 221 #define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ 222 #define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ 223 224 /**@} end of group GPIO_REVA_OUTEN_Register */ 225 226 /** 227 * @ingroup gpio_reva_registers 228 * @defgroup GPIO_REVA_OUTEN_SET GPIO_REVA_OUTEN_SET 229 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 230 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 231 * without affecting other bits in that register. 232 * @{ 233 */ 234 #define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ 235 #define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ 236 237 /**@} end of group GPIO_REVA_OUTEN_SET_Register */ 238 239 /** 240 * @ingroup gpio_reva_registers 241 * @defgroup GPIO_REVA_OUTEN_CLR GPIO_REVA_OUTEN_CLR 242 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 243 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 244 * without affecting other bits in that register. 245 * @{ 246 */ 247 #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ 248 #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ 249 250 /**@} end of group GPIO_REVA_OUTEN_CLR_Register */ 251 252 /** 253 * @ingroup gpio_reva_registers 254 * @defgroup GPIO_REVA_OUT GPIO_REVA_OUT 255 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 256 * associated port. This register can be written either directly, or by using the 257 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 258 * @{ 259 */ 260 #define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ 261 #define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ 262 #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ 263 #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ 264 #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ 265 #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ 266 267 /**@} end of group GPIO_REVA_OUT_Register */ 268 269 /** 270 * @ingroup gpio_reva_registers 271 * @defgroup GPIO_REVA_OUT_SET GPIO_REVA_OUT_SET 272 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 273 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 274 * register. 275 * @{ 276 */ 277 #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ 278 #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ 279 #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ 280 #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ 281 #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ 282 #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ 283 284 /**@} end of group GPIO_REVA_OUT_SET_Register */ 285 286 /** 287 * @ingroup gpio_reva_registers 288 * @defgroup GPIO_REVA_OUT_CLR GPIO_REVA_OUT_CLR 289 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 290 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 291 * that register. 292 * @{ 293 */ 294 #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ 295 #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ 296 297 /**@} end of group GPIO_REVA_OUT_CLR_Register */ 298 299 /** 300 * @ingroup gpio_reva_registers 301 * @defgroup GPIO_REVA_IN GPIO_REVA_IN 302 * @brief GPIO Input Register. Read-only register to read from the logic states of the 303 * GPIO pins on this port. 304 * @{ 305 */ 306 #define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ 307 #define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ 308 309 /**@} end of group GPIO_REVA_IN_Register */ 310 311 /** 312 * @ingroup gpio_reva_registers 313 * @defgroup GPIO_REVA_INTMODE GPIO_REVA_INTMODE 314 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 315 * mode setting for the associated GPIO pin on this port. 316 * @{ 317 */ 318 #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ 319 #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ 320 #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ 321 #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ 322 #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ 323 #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ 324 325 /**@} end of group GPIO_REVA_INTMODE_Register */ 326 327 /** 328 * @ingroup gpio_reva_registers 329 * @defgroup GPIO_REVA_INTPOL GPIO_REVA_INTPOL 330 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 331 * interrupt polarity setting for one GPIO pin in the associated port. 332 * @{ 333 */ 334 #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ 335 #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ 336 #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ 337 #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ 338 #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ 339 #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ 340 341 /**@} end of group GPIO_REVA_INTPOL_Register */ 342 343 /** 344 * @ingroup gpio_reva_registers 345 * @defgroup GPIO_REVA_INTEN GPIO_REVA_INTEN 346 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 347 * interrupt enable for the associated pin on the GPIO port. 348 * @{ 349 */ 350 #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ 351 #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ 352 #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ 353 #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ 354 #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ 355 #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ 356 357 /**@} end of group GPIO_REVA_INTEN_Register */ 358 359 /** 360 * @ingroup gpio_reva_registers 361 * @defgroup GPIO_REVA_INTEN_SET GPIO_REVA_INTEN_SET 362 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 363 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 364 * in that register. 365 * @{ 366 */ 367 #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ 368 #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ 369 #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ 370 #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ 371 #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ 372 #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ 373 374 /**@} end of group GPIO_REVA_INTEN_SET_Register */ 375 376 /** 377 * @ingroup gpio_reva_registers 378 * @defgroup GPIO_REVA_INTEN_CLR GPIO_REVA_INTEN_CLR 379 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 380 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 381 * other bits in that register. 382 * @{ 383 */ 384 #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ 385 #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ 386 #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ 387 #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ 388 #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ 389 #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ 390 391 /**@} end of group GPIO_REVA_INTEN_CLR_Register */ 392 393 /** 394 * @ingroup gpio_reva_registers 395 * @defgroup GPIO_REVA_INTFL GPIO_REVA_INTFL 396 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 397 * interrupt status for the associated GPIO pin in this port. 398 * @{ 399 */ 400 #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ 401 #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ 402 #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ 403 #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ 404 #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ 405 #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ 406 407 /**@} end of group GPIO_REVA_INTFL_Register */ 408 409 /** 410 * @ingroup gpio_reva_registers 411 * @defgroup GPIO_REVA_INTFL_CLR GPIO_REVA_INTFL_CLR 412 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 413 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 414 * in that register. 415 * @{ 416 */ 417 #define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ 418 #define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ 419 420 /**@} end of group GPIO_REVA_INTFL_CLR_Register */ 421 422 /** 423 * @ingroup gpio_reva_registers 424 * @defgroup GPIO_REVA_WKEN GPIO_REVA_WKEN 425 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 426 * enable for the associated GPIO pin in this port. 427 * @{ 428 */ 429 #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ 430 #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ 431 #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ 432 #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ 433 #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ 434 #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ 435 436 /**@} end of group GPIO_REVA_WKEN_Register */ 437 438 /** 439 * @ingroup gpio_reva_registers 440 * @defgroup GPIO_REVA_WKEN_SET GPIO_REVA_WKEN_SET 441 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 442 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 443 * that register. 444 * @{ 445 */ 446 #define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ 447 #define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ 448 449 /**@} end of group GPIO_REVA_WKEN_SET_Register */ 450 451 /** 452 * @ingroup gpio_reva_registers 453 * @defgroup GPIO_REVA_WKEN_CLR GPIO_REVA_WKEN_CLR 454 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 455 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 456 * bits in that register. 457 * @{ 458 */ 459 #define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ 460 #define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ 461 462 /**@} end of group GPIO_REVA_WKEN_CLR_Register */ 463 464 /** 465 * @ingroup gpio_reva_registers 466 * @defgroup GPIO_REVA_DUALEDGE GPIO_REVA_DUALEDGE 467 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 468 * edge mode for the associated GPIO pin in this port. 469 * @{ 470 */ 471 #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ 472 #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ 473 #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ 474 #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ 475 #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ 476 #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ 477 478 /**@} end of group GPIO_REVA_DUALEDGE_Register */ 479 480 /** 481 * @ingroup gpio_reva_registers 482 * @defgroup GPIO_REVA_PADCTRL0 GPIO_REVA_PADCTRL0 483 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 484 * the associated GPIO pin in this port. 485 * @{ 486 */ 487 #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ 488 #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ 489 #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ 490 #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ 491 #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ 492 #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ 493 #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ 494 #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ 495 496 /**@} end of group GPIO_REVA_PADCTRL0_Register */ 497 498 /** 499 * @ingroup gpio_reva_registers 500 * @defgroup GPIO_REVA_PADCTRL1 GPIO_REVA_PADCTRL1 501 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for 502 * the associated GPIO pin in this port. 503 * @{ 504 */ 505 #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ 506 #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ 507 #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ 508 #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ 509 #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ 510 #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ 511 #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ 512 #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ 513 514 /**@} end of group GPIO_REVA_PADCTRL1_Register */ 515 516 /** 517 * @ingroup gpio_reva_registers 518 * @defgroup GPIO_REVA_EN1 GPIO_REVA_EN1 519 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 520 * between primary/secondary functions for the associated GPIO pin in this port. 521 * @{ 522 */ 523 #define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ 524 #define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ 525 #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ 526 #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ 527 #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ 528 #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ 529 530 /**@} end of group GPIO_REVA_EN1_Register */ 531 532 /** 533 * @ingroup gpio_reva_registers 534 * @defgroup GPIO_REVA_EN1_SET GPIO_REVA_EN1_SET 535 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 536 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 537 * bits in that register. 538 * @{ 539 */ 540 #define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 541 #define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 542 543 /**@} end of group GPIO_REVA_EN1_SET_Register */ 544 545 /** 546 * @ingroup gpio_reva_registers 547 * @defgroup GPIO_REVA_EN1_CLR GPIO_REVA_EN1_CLR 548 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 549 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 550 * bits in that register. 551 * @{ 552 */ 553 #define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 554 #define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 555 556 /**@} end of group GPIO_REVA_EN1_CLR_Register */ 557 558 /** 559 * @ingroup gpio_reva_registers 560 * @defgroup GPIO_REVA_EN2 GPIO_REVA_EN2 561 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 562 * between primary/secondary functions for the associated GPIO pin in this port. 563 * @{ 564 */ 565 #define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ 566 #define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ 567 #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ 568 #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ 569 #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ 570 #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ 571 572 /**@} end of group GPIO_REVA_EN2_Register */ 573 574 /** 575 * @ingroup gpio_reva_registers 576 * @defgroup GPIO_REVA_EN2_SET GPIO_REVA_EN2_SET 577 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 578 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 579 * bits in that register. 580 * @{ 581 */ 582 #define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 583 #define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 584 585 /**@} end of group GPIO_REVA_EN2_SET_Register */ 586 587 /** 588 * @ingroup gpio_reva_registers 589 * @defgroup GPIO_REVA_EN2_CLR GPIO_REVA_EN2_CLR 590 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 591 * register clears the bits in the same positions in GPIO_EN2 to 0, without 592 * affecting other bits in that register. 593 * @{ 594 */ 595 #define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 596 #define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 597 598 /**@} end of group GPIO_REVA_EN2_CLR_Register */ 599 600 /** 601 * @ingroup gpio_reva_registers 602 * @defgroup GPIO_REVA_EN3 GPIO_REVA_EN3 603 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 604 * between primary/secondary functions for the associated GPIO pin in this port. 605 * @{ 606 */ 607 #define MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS 0 /**< EN3_GPIO_EN3 Position */ 608 #define MXC_F_GPIO_REVA_EN3_GPIO_EN3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS)) /**< EN3_GPIO_EN3 Mask */ 609 #define MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY ((uint32_t)0x0UL) /**< EN3_GPIO_EN3_PRIMARY Value */ 610 #define MXC_S_GPIO_REVA_EN3_GPIO_EN3_PRIMARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_PRIMARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_PRIMARY Setting */ 611 #define MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY ((uint32_t)0x1UL) /**< EN3_GPIO_EN3_SECONDARY Value */ 612 #define MXC_S_GPIO_REVA_EN3_GPIO_EN3_SECONDARY (MXC_V_GPIO_REVA_EN3_GPIO_EN3_SECONDARY << MXC_F_GPIO_REVA_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_SECONDARY Setting */ 613 614 /**@} end of group GPIO_REVA_EN3_Register */ 615 616 /** 617 * @ingroup gpio_reva_registers 618 * @defgroup GPIO_REVA_EN3_SET GPIO_REVA_EN3_SET 619 * @brief GPIO Alternate Function 3 Set. Writing a 1 to one or more bits in this register 620 * sets the bits in the same positions in GPIO_EN3 to 1, without affecting other 621 * bits in that register. 622 * @{ 623 */ 624 #define MXC_F_GPIO_REVA_EN3_SET_ALL_POS 0 /**< EN3_SET_ALL Position */ 625 #define MXC_F_GPIO_REVA_EN3_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_SET_ALL_POS)) /**< EN3_SET_ALL Mask */ 626 627 /**@} end of group GPIO_REVA_EN3_SET_Register */ 628 629 /** 630 * @ingroup gpio_reva_registers 631 * @defgroup GPIO_REVA_EN3_CLR GPIO_REVA_EN3_CLR 632 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 633 * register clears the bits in the same positions in GPIO_EN3 to 0, without 634 * affecting other bits in that register. 635 * @{ 636 */ 637 #define MXC_F_GPIO_REVA_EN3_CLR_ALL_POS 0 /**< EN3_CLR_ALL Position */ 638 #define MXC_F_GPIO_REVA_EN3_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN3_CLR_ALL_POS)) /**< EN3_CLR_ALL Mask */ 639 640 /**@} end of group GPIO_REVA_EN3_CLR_Register */ 641 642 /** 643 * @ingroup gpio_reva_registers 644 * @defgroup GPIO_REVA_HYSEN GPIO_REVA_HYSEN 645 * @brief GPIO Input Hysteresis Enable. 646 * @{ 647 */ 648 #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ 649 #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ 650 651 /**@} end of group GPIO_REVA_HYSEN_Register */ 652 653 /** 654 * @ingroup gpio_reva_registers 655 * @defgroup GPIO_REVA_SRSEL GPIO_REVA_SRSEL 656 * @brief GPIO Slew Rate Enable Register. 657 * @{ 658 */ 659 #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ 660 #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ 661 #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ 662 #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ 663 #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ 664 #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ 665 666 /**@} end of group GPIO_REVA_SRSEL_Register */ 667 668 /** 669 * @ingroup gpio_reva_registers 670 * @defgroup GPIO_REVA_DS0 GPIO_REVA_DS0 671 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive 672 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 673 * sink/source current of GPIO pins in each mode. 674 * @{ 675 */ 676 #define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ 677 #define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ 678 #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ 679 #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ 680 #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ 681 #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ 682 683 /**@} end of group GPIO_REVA_DS0_Register */ 684 685 /** 686 * @ingroup gpio_reva_registers 687 * @defgroup GPIO_REVA_DS1 GPIO_REVA_DS1 688 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 689 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 690 * sink/source current of GPIO pins in each mode. 691 * @{ 692 */ 693 #define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ 694 #define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ 695 696 /**@} end of group GPIO_REVA_DS1_Register */ 697 698 /** 699 * @ingroup gpio_reva_registers 700 * @defgroup GPIO_REVA_PS GPIO_REVA_PS 701 * @brief GPIO Pull Select Mode. 702 * @{ 703 */ 704 #define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */ 705 #define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */ 706 707 /**@} end of group GPIO_REVA_PS_Register */ 708 709 /** 710 * @ingroup gpio_reva_registers 711 * @defgroup GPIO_REVA_VSSEL GPIO_REVA_VSSEL 712 * @brief GPIO Voltage Select. 713 * @{ 714 */ 715 #define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ 716 #define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ 717 718 /**@} end of group GPIO_REVA_VSSEL_Register */ 719 720 #ifdef __cplusplus 721 } 722 #endif 723 724 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_GPIO_GPIO_REVA_REGS_H_ 725 726
