1 /** 2 * @file gpio_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_GPIO_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_GPIO_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup gpio 66 * @defgroup gpio_registers GPIO_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 68 * @details Individual I/O for each GPIO 69 */ 70 71 /** 72 * @ingroup gpio_registers 73 * Structure type to access the GPIO Registers. 74 */ 75 typedef struct { 76 __IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */ 77 __IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */ 78 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ 79 __IO uint32_t out_en; /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */ 80 __IO uint32_t out_en_set; /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */ 81 __IO uint32_t out_en_clr; /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */ 82 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */ 83 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */ 84 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */ 85 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */ 86 __IO uint32_t int_mode; /**< <tt>\b 0x28:</tt> GPIO INT_MODE Register */ 87 __IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */ 88 __IO uint32_t in_en; /**< <tt>\b 0x30:</tt> GPIO IN_EN Register */ 89 __IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */ 90 __IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */ 91 __IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */ 92 __I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */ 93 __R uint32_t rsv_0x44; 94 __IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */ 95 __IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */ 96 __IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */ 97 __IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */ 98 __R uint32_t rsv_0x58; 99 __IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */ 100 __IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */ 101 __IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */ 102 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */ 103 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */ 104 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ 105 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */ 106 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */ 107 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */ 108 __R uint32_t rsv_0x80_0xaf[12]; 109 __IO uint32_t ds; /**< <tt>\b 0xB0:</tt> GPIO DS Register */ 110 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */ 111 __IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */ 112 __R uint32_t rsv_0xbc; 113 __IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */ 114 } mxc_gpio_regs_t; 115 116 /* Register offsets for module GPIO */ 117 /** 118 * @ingroup gpio_registers 119 * @defgroup GPIO_Register_Offsets Register Offsets 120 * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 121 * @{ 122 */ 123 #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 124 #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 125 #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 126 #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 127 #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 128 #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 129 #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 130 #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 131 #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 132 #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 133 #define MXC_R_GPIO_INT_MODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 134 #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 135 #define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ 136 #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 137 #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 138 #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 139 #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 140 #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 141 #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 142 #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 143 #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 144 #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 145 #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 146 #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 147 #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 148 #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 149 #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 150 #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 151 #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 152 #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 153 #define MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 154 #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 155 #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 156 #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */ 157 /**@} end of group gpio_registers */ 158 159 /** 160 * @ingroup gpio_registers 161 * @defgroup GPIO_EN0 GPIO_EN0 162 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one 163 * GPIO pin on the associated port. 164 * @{ 165 */ 166 #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ 167 #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ 168 #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ 169 #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ 170 #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ 171 #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ 172 173 /**@} end of group GPIO_EN0_Register */ 174 175 /** 176 * @ingroup gpio_registers 177 * @defgroup GPIO_EN0_SET GPIO_EN0_SET 178 * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this 179 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 180 * other bits in that register. 181 * @{ 182 */ 183 #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ 184 #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ 185 186 /**@} end of group GPIO_EN0_SET_Register */ 187 188 /** 189 * @ingroup gpio_registers 190 * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR 191 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 192 * register clears the bits in the same positions in GPIO_EN to 0, without 193 * affecting other bits in that register. 194 * @{ 195 */ 196 #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ 197 #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ 198 199 /**@} end of group GPIO_EN0_CLR_Register */ 200 201 /** 202 * @ingroup gpio_registers 203 * @defgroup GPIO_OUT_EN GPIO_OUT_EN 204 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 205 * GPIO pin in the associated port. 206 * @{ 207 */ 208 #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ 209 #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ 210 #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ 211 #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ 212 #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ 213 #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ 214 215 /**@} end of group GPIO_OUT_EN_Register */ 216 217 /** 218 * @ingroup gpio_registers 219 * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET 220 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 221 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 222 * without affecting other bits in that register. 223 * @{ 224 */ 225 #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ 226 #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ 227 228 /**@} end of group GPIO_OUT_EN_SET_Register */ 229 230 /** 231 * @ingroup gpio_registers 232 * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR 233 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 234 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 235 * without affecting other bits in that register. 236 * @{ 237 */ 238 #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ 239 #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ 240 241 /**@} end of group GPIO_OUT_EN_CLR_Register */ 242 243 /** 244 * @ingroup gpio_registers 245 * @defgroup GPIO_OUT GPIO_OUT 246 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 247 * associated port. This register can be written either directly, or by using the 248 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 249 * @{ 250 */ 251 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ 252 #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ 253 #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ 254 #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ 255 #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ 256 #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ 257 258 /**@} end of group GPIO_OUT_Register */ 259 260 /** 261 * @ingroup gpio_registers 262 * @defgroup GPIO_OUT_SET GPIO_OUT_SET 263 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 264 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 265 * register. 266 * @{ 267 */ 268 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ 269 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ 270 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ 271 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ 272 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ 273 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ 274 275 /**@} end of group GPIO_OUT_SET_Register */ 276 277 /** 278 * @ingroup gpio_registers 279 * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR 280 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 281 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 282 * that register. 283 * @{ 284 */ 285 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ 286 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ 287 288 /**@} end of group GPIO_OUT_CLR_Register */ 289 290 /** 291 * @ingroup gpio_registers 292 * @defgroup GPIO_IN GPIO_IN 293 * @brief GPIO Input Register. Read-only register to read from the logic states of the 294 * GPIO pins on this port. 295 * @{ 296 */ 297 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ 298 #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ 299 300 /**@} end of group GPIO_IN_Register */ 301 302 /** 303 * @ingroup gpio_registers 304 * @defgroup GPIO_INT_MODE GPIO_INT_MODE 305 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 306 * mode setting for the associated GPIO pin on this port. 307 * @{ 308 */ 309 #define MXC_F_GPIO_INT_MODE_GPIO_INT_MODE_POS 0 /**< INT_MODE_GPIO_INT_MODE Position */ 310 #define MXC_F_GPIO_INT_MODE_GPIO_INT_MODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MODE_GPIO_INT_MODE_POS)) /**< INT_MODE_GPIO_INT_MODE Mask */ 311 #define MXC_V_GPIO_INT_MODE_GPIO_INT_MODE_LEVEL ((uint32_t)0x0UL) /**< INT_MODE_GPIO_INT_MODE_LEVEL Value */ 312 #define MXC_S_GPIO_INT_MODE_GPIO_INT_MODE_LEVEL (MXC_V_GPIO_INT_MODE_GPIO_INT_MODE_LEVEL << MXC_F_GPIO_INT_MODE_GPIO_INT_MODE_POS) /**< INT_MODE_GPIO_INT_MODE_LEVEL Setting */ 313 #define MXC_V_GPIO_INT_MODE_GPIO_INT_MODE_EDGE ((uint32_t)0x1UL) /**< INT_MODE_GPIO_INT_MODE_EDGE Value */ 314 #define MXC_S_GPIO_INT_MODE_GPIO_INT_MODE_EDGE (MXC_V_GPIO_INT_MODE_GPIO_INT_MODE_EDGE << MXC_F_GPIO_INT_MODE_GPIO_INT_MODE_POS) /**< INT_MODE_GPIO_INT_MODE_EDGE Setting */ 315 316 /**@} end of group GPIO_INT_MODE_Register */ 317 318 /** 319 * @ingroup gpio_registers 320 * @defgroup GPIO_INT_POL GPIO_INT_POL 321 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 322 * interrupt polarity setting for one GPIO pin in the associated port. 323 * @{ 324 */ 325 #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ 326 #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ 327 #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ 328 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ 329 #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ 330 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ 331 332 /**@} end of group GPIO_INT_POL_Register */ 333 334 /** 335 * @ingroup gpio_registers 336 * @defgroup GPIO_INT_EN GPIO_INT_EN 337 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 338 * interrupt enable for the associated pin on the GPIO port. 339 * @{ 340 */ 341 #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ 342 #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ 343 #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ 344 #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ 345 #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ 346 #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ 347 348 /**@} end of group GPIO_INT_EN_Register */ 349 350 /** 351 * @ingroup gpio_registers 352 * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET 353 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 354 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 355 * in that register. 356 * @{ 357 */ 358 #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ 359 #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ 360 #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ 361 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ 362 #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ 363 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ 364 365 /**@} end of group GPIO_INT_EN_SET_Register */ 366 367 /** 368 * @ingroup gpio_registers 369 * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR 370 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 371 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 372 * other bits in that register. 373 * @{ 374 */ 375 #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ 376 #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ 377 #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ 378 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ 379 #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ 380 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ 381 382 /**@} end of group GPIO_INT_EN_CLR_Register */ 383 384 /** 385 * @ingroup gpio_registers 386 * @defgroup GPIO_INT_STAT GPIO_INT_STAT 387 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 388 * interrupt status for the associated GPIO pin in this port. 389 * @{ 390 */ 391 #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ 392 #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ 393 #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ 394 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ 395 #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ 396 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ 397 398 /**@} end of group GPIO_INT_STAT_Register */ 399 400 /** 401 * @ingroup gpio_registers 402 * @defgroup GPIO_INT_CLR GPIO_INT_CLR 403 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 404 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 405 * in that register. 406 * @{ 407 */ 408 #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ 409 #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ 410 411 /**@} end of group GPIO_INT_CLR_Register */ 412 413 /** 414 * @ingroup gpio_registers 415 * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN 416 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 417 * enable for the associated GPIO pin in this port. 418 * @{ 419 */ 420 #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ 421 #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ 422 #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ 423 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ 424 #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ 425 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ 426 427 /**@} end of group GPIO_WAKE_EN_Register */ 428 429 /** 430 * @ingroup gpio_registers 431 * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET 432 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 433 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 434 * that register. 435 * @{ 436 */ 437 #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ 438 #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ 439 440 /**@} end of group GPIO_WAKE_EN_SET_Register */ 441 442 /** 443 * @ingroup gpio_registers 444 * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR 445 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 446 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 447 * bits in that register. 448 * @{ 449 */ 450 #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ 451 #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ 452 453 /**@} end of group GPIO_WAKE_EN_CLR_Register */ 454 455 /** 456 * @ingroup gpio_registers 457 * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE 458 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 459 * edge mode for the associated GPIO pin in this port. 460 * @{ 461 */ 462 #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ 463 #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ 464 #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ 465 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ 466 #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ 467 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ 468 469 /**@} end of group GPIO_INT_DUAL_EDGE_Register */ 470 471 /** 472 * @ingroup gpio_registers 473 * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1 474 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 475 * the associated GPIO pin in this port. 476 * @{ 477 */ 478 #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ 479 #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ 480 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ 481 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ 482 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ 483 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ 484 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ 485 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ 486 487 /**@} end of group GPIO_PAD_CFG1_Register */ 488 489 /** 490 * @ingroup gpio_registers 491 * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2 492 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for 493 * the associated GPIO pin in this port. 494 * @{ 495 */ 496 #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ 497 #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ 498 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ 499 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ 500 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ 501 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ 502 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ 503 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ 504 505 /**@} end of group GPIO_PAD_CFG2_Register */ 506 507 /** 508 * @ingroup gpio_registers 509 * @defgroup GPIO_EN1 GPIO_EN1 510 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 511 * between primary/secondary functions for the associated GPIO pin in this port. 512 * @{ 513 */ 514 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ 515 #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ 516 #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ 517 #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ 518 #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ 519 #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ 520 521 /**@} end of group GPIO_EN1_Register */ 522 523 /** 524 * @ingroup gpio_registers 525 * @defgroup GPIO_EN1_SET GPIO_EN1_SET 526 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 527 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 528 * bits in that register. 529 * @{ 530 */ 531 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 532 #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 533 534 /**@} end of group GPIO_EN1_SET_Register */ 535 536 /** 537 * @ingroup gpio_registers 538 * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR 539 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 540 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 541 * bits in that register. 542 * @{ 543 */ 544 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 545 #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 546 547 /**@} end of group GPIO_EN1_CLR_Register */ 548 549 /** 550 * @ingroup gpio_registers 551 * @defgroup GPIO_EN2 GPIO_EN2 552 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 553 * between primary/secondary functions for the associated GPIO pin in this port. 554 * @{ 555 */ 556 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ 557 #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ 558 #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ 559 #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ 560 #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ 561 #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ 562 563 /**@} end of group GPIO_EN2_Register */ 564 565 /** 566 * @ingroup gpio_registers 567 * @defgroup GPIO_EN2_SET GPIO_EN2_SET 568 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 569 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 570 * bits in that register. 571 * @{ 572 */ 573 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 574 #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 575 576 /**@} end of group GPIO_EN2_SET_Register */ 577 578 /** 579 * @ingroup gpio_registers 580 * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR 581 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 582 * register clears the bits in the same positions in GPIO_EN2 to 0, without 583 * affecting other bits in that register. 584 * @{ 585 */ 586 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 587 #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 588 589 /**@} end of group GPIO_EN2_CLR_Register */ 590 591 /** 592 * @ingroup gpio_registers 593 * @defgroup GPIO_DS GPIO_DS 594 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive 595 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 596 * sink/source current of GPIO pins in each mode. 597 * @{ 598 */ 599 #define MXC_F_GPIO_DS_GPIO_DS_POS 0 /**< DS_GPIO_DS Position */ 600 #define MXC_F_GPIO_DS_GPIO_DS ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_GPIO_DS_POS)) /**< DS_GPIO_DS Mask */ 601 #define MXC_V_GPIO_DS_GPIO_DS_LD ((uint32_t)0x0UL) /**< DS_GPIO_DS_LD Value */ 602 #define MXC_S_GPIO_DS_GPIO_DS_LD (MXC_V_GPIO_DS_GPIO_DS_LD << MXC_F_GPIO_DS_GPIO_DS_POS) /**< DS_GPIO_DS_LD Setting */ 603 #define MXC_V_GPIO_DS_GPIO_DS_HD ((uint32_t)0x1UL) /**< DS_GPIO_DS_HD Value */ 604 #define MXC_S_GPIO_DS_GPIO_DS_HD (MXC_V_GPIO_DS_GPIO_DS_HD << MXC_F_GPIO_DS_GPIO_DS_POS) /**< DS_GPIO_DS_HD Setting */ 605 606 /**@} end of group GPIO_DS_Register */ 607 608 /** 609 * @ingroup gpio_registers 610 * @defgroup GPIO_DS1 GPIO_DS1 611 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 612 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 613 * sink/source current of GPIO pins in each mode. 614 * @{ 615 */ 616 #define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ 617 #define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ 618 619 /**@} end of group GPIO_DS1_Register */ 620 621 /** 622 * @ingroup gpio_registers 623 * @defgroup GPIO_PS GPIO_PS 624 * @brief GPIO Pull Select Mode. 625 * @{ 626 */ 627 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ 628 #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ 629 630 /**@} end of group GPIO_PS_Register */ 631 632 /** 633 * @ingroup gpio_registers 634 * @defgroup GPIO_VSSEL GPIO_VSSEL 635 * @brief GPIO Voltage Select. 636 * @{ 637 */ 638 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ 639 #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ 640 641 /**@} end of group GPIO_VSSEL_Register */ 642 643 #ifdef __cplusplus 644 } 645 #endif 646 647 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_GPIO_REGS_H_ 648
