1 /** 2 * @file gpio_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gpio_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gpio 67 * @defgroup gpio_registers GPIO_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 69 * @details Individual I/O for each GPIO 70 */ 71 72 /** 73 * @ingroup gpio_registers 74 * Structure type to access the GPIO Registers. 75 */ 76 typedef struct { 77 __IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */ 78 __IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */ 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ 80 __IO uint32_t out_en; /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */ 81 __IO uint32_t out_en_set; /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */ 82 __IO uint32_t out_en_clr; /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */ 83 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */ 84 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */ 85 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */ 86 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */ 87 __IO uint32_t int_mod; /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */ 88 __IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */ 89 __IO uint32_t in_en; /**< <tt>\b 0x30:</tt> GPIO IN_EN Register */ 90 __IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */ 91 __IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */ 92 __IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */ 93 __I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */ 96 __IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */ 97 __IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */ 98 __IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */ 99 __R uint32_t rsv_0x58; 100 __IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */ 101 __IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */ 102 __IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */ 103 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */ 104 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */ 105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ 106 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */ 107 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */ 108 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */ 109 __R uint32_t rsv_0x80_0xa7[10]; 110 __IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */ 111 __IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */ 112 __IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */ 113 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */ 114 __IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */ 115 __R uint32_t rsv_0xbc; 116 __IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */ 117 } mxc_gpio_regs_t; 118 119 /* Register offsets for module GPIO */ 120 /** 121 * @ingroup gpio_registers 122 * @defgroup GPIO_Register_Offsets Register Offsets 123 * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 124 * @{ 125 */ 126 #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 127 #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 128 #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 129 #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 130 #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 131 #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 132 #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 133 #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 134 #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 135 #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 136 #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 137 #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 138 #define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ 139 #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 140 #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 141 #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 142 #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 143 #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 144 #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 145 #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 146 #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 147 #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 148 #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 149 #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 150 #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 151 #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 152 #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 153 #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 154 #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 155 #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 156 #define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 157 #define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 158 #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 159 #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 160 #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 161 #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */ 162 /**@} end of group gpio_registers */ 163 164 /** 165 * @ingroup gpio_registers 166 * @defgroup GPIO_EN0 GPIO_EN0 167 * @brief GPIO Function Enable 0 Register. Each bit controls the GPIO_EN setting for one 168 * GPIO pin on the associated port. 169 * @{ 170 */ 171 #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ 172 #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ 173 #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ 174 #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ 175 #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ 176 #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ 177 178 /**@} end of group GPIO_EN0_Register */ 179 180 /** 181 * @ingroup gpio_registers 182 * @defgroup GPIO_EN0_SET GPIO_EN0_SET 183 * @brief GPIO Set Function Enable 0 Register. Writing a 1 to one or more bits in this 184 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 185 * other bits in that register. 186 * @{ 187 */ 188 #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ 189 #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ 190 191 /**@} end of group GPIO_EN0_SET_Register */ 192 193 /** 194 * @ingroup gpio_registers 195 * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR 196 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 197 * register clears the bits in the same positions in GPIO_EN to 0, without 198 * affecting other bits in that register. 199 * @{ 200 */ 201 #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ 202 #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ 203 204 /**@} end of group GPIO_EN0_CLR_Register */ 205 206 /** 207 * @ingroup gpio_registers 208 * @defgroup GPIO_OUT_EN GPIO_OUT_EN 209 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 210 * GPIO pin in the associated port. 211 * @{ 212 */ 213 #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ 214 #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ 215 #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ 216 #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ 217 #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ 218 #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ 219 220 /**@} end of group GPIO_OUT_EN_Register */ 221 222 /** 223 * @ingroup gpio_registers 224 * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET 225 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 226 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 227 * without affecting other bits in that register. 228 * @{ 229 */ 230 #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ 231 #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ 232 233 /**@} end of group GPIO_OUT_EN_SET_Register */ 234 235 /** 236 * @ingroup gpio_registers 237 * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR 238 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 239 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 240 * without affecting other bits in that register. 241 * @{ 242 */ 243 #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ 244 #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ 245 246 /**@} end of group GPIO_OUT_EN_CLR_Register */ 247 248 /** 249 * @ingroup gpio_registers 250 * @defgroup GPIO_OUT GPIO_OUT 251 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 252 * associated port. This register can be written either directly, or by using the 253 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 254 * @{ 255 */ 256 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ 257 #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ 258 #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ 259 #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ 260 #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ 261 #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ 262 263 /**@} end of group GPIO_OUT_Register */ 264 265 /** 266 * @ingroup gpio_registers 267 * @defgroup GPIO_OUT_SET GPIO_OUT_SET 268 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 269 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 270 * register. 271 * @{ 272 */ 273 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ 274 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ 275 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ 276 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ 277 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ 278 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ 279 280 /**@} end of group GPIO_OUT_SET_Register */ 281 282 /** 283 * @ingroup gpio_registers 284 * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR 285 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 286 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 287 * that register. 288 * @{ 289 */ 290 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ 291 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ 292 293 /**@} end of group GPIO_OUT_CLR_Register */ 294 295 /** 296 * @ingroup gpio_registers 297 * @defgroup GPIO_IN GPIO_IN 298 * @brief GPIO Input Register. Read-only register to read from the logic states of the 299 * GPIO pins on this port. 300 * @{ 301 */ 302 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ 303 #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ 304 305 /**@} end of group GPIO_IN_Register */ 306 307 /** 308 * @ingroup gpio_registers 309 * @defgroup GPIO_INT_MOD GPIO_INT_MOD 310 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 311 * mode setting for the associated GPIO pin on this port. 312 * @{ 313 */ 314 #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ 315 #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ 316 #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ 317 #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ 318 #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ 319 #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ 320 321 /**@} end of group GPIO_INT_MOD_Register */ 322 323 /** 324 * @ingroup gpio_registers 325 * @defgroup GPIO_INT_POL GPIO_INT_POL 326 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 327 * interrupt polarity setting for one GPIO pin in the associated port. 328 * @{ 329 */ 330 #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ 331 #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ 332 #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ 333 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ 334 #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ 335 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ 336 337 /**@} end of group GPIO_INT_POL_Register */ 338 339 /** 340 * @ingroup gpio_registers 341 * @defgroup GPIO_IN_EN GPIO_IN_EN 342 * @brief GPIO Port Input Enable. 343 * @{ 344 */ 345 #define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */ 346 #define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */ 347 #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */ 348 #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */ 349 #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */ 350 #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */ 351 352 /**@} end of group GPIO_IN_EN_Register */ 353 354 /** 355 * @ingroup gpio_registers 356 * @defgroup GPIO_INT_EN GPIO_INT_EN 357 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 358 * interrupt enable for the associated pin on the GPIO port. 359 * @{ 360 */ 361 #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ 362 #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ 363 #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ 364 #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ 365 #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ 366 #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ 367 368 /**@} end of group GPIO_INT_EN_Register */ 369 370 /** 371 * @ingroup gpio_registers 372 * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET 373 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 374 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 375 * in that register. 376 * @{ 377 */ 378 #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ 379 #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ 380 #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ 381 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ 382 #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ 383 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ 384 385 /**@} end of group GPIO_INT_EN_SET_Register */ 386 387 /** 388 * @ingroup gpio_registers 389 * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR 390 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 391 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 392 * other bits in that register. 393 * @{ 394 */ 395 #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ 396 #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ 397 #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ 398 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ 399 #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ 400 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ 401 402 /**@} end of group GPIO_INT_EN_CLR_Register */ 403 404 /** 405 * @ingroup gpio_registers 406 * @defgroup GPIO_INT_STAT GPIO_INT_STAT 407 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 408 * interrupt status for the associated GPIO pin in this port. 409 * @{ 410 */ 411 #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ 412 #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ 413 #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ 414 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ 415 #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ 416 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ 417 418 /**@} end of group GPIO_INT_STAT_Register */ 419 420 /** 421 * @ingroup gpio_registers 422 * @defgroup GPIO_INT_CLR GPIO_INT_CLR 423 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 424 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 425 * in that register. 426 * @{ 427 */ 428 #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ 429 #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ 430 431 /**@} end of group GPIO_INT_CLR_Register */ 432 433 /** 434 * @ingroup gpio_registers 435 * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN 436 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 437 * enable for the associated GPIO pin in this port. 438 * @{ 439 */ 440 #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ 441 #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ 442 #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ 443 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ 444 #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ 445 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ 446 447 /**@} end of group GPIO_WAKE_EN_Register */ 448 449 /** 450 * @ingroup gpio_registers 451 * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET 452 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 453 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 454 * that register. 455 * @{ 456 */ 457 #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ 458 #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ 459 460 /**@} end of group GPIO_WAKE_EN_SET_Register */ 461 462 /** 463 * @ingroup gpio_registers 464 * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR 465 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 466 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 467 * bits in that register. 468 * @{ 469 */ 470 #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ 471 #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ 472 473 /**@} end of group GPIO_WAKE_EN_CLR_Register */ 474 475 /** 476 * @ingroup gpio_registers 477 * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE 478 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 479 * edge mode for the associated GPIO pin in this port. 480 * @{ 481 */ 482 #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ 483 #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ 484 #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ 485 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ 486 #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ 487 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ 488 489 /**@} end of group GPIO_INT_DUAL_EDGE_Register */ 490 491 /** 492 * @ingroup gpio_registers 493 * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1 494 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 495 * the associated GPIO pin in this port. 496 * @{ 497 */ 498 #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ 499 #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ 500 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ 501 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ 502 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ 503 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ 504 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ 505 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ 506 507 /**@} end of group GPIO_PAD_CFG1_Register */ 508 509 /** 510 * @ingroup gpio_registers 511 * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2 512 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for 513 * the associated GPIO pin in this port. 514 * @{ 515 */ 516 #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ 517 #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ 518 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ 519 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ 520 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ 521 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ 522 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ 523 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ 524 525 /**@} end of group GPIO_PAD_CFG2_Register */ 526 527 /** 528 * @ingroup gpio_registers 529 * @defgroup GPIO_EN1 GPIO_EN1 530 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 531 * between primary/secondary functions for the associated GPIO pin in this port. 532 * @{ 533 */ 534 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ 535 #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ 536 #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ 537 #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ 538 #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ 539 #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ 540 541 /**@} end of group GPIO_EN1_Register */ 542 543 /** 544 * @ingroup gpio_registers 545 * @defgroup GPIO_EN1_SET GPIO_EN1_SET 546 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 547 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 548 * bits in that register. 549 * @{ 550 */ 551 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 552 #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 553 554 /**@} end of group GPIO_EN1_SET_Register */ 555 556 /** 557 * @ingroup gpio_registers 558 * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR 559 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 560 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 561 * bits in that register. 562 * @{ 563 */ 564 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 565 #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 566 567 /**@} end of group GPIO_EN1_CLR_Register */ 568 569 /** 570 * @ingroup gpio_registers 571 * @defgroup GPIO_EN2 GPIO_EN2 572 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 573 * between primary/secondary functions for the associated GPIO pin in this port. 574 * @{ 575 */ 576 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ 577 #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ 578 #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ 579 #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ 580 #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ 581 #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ 582 583 /**@} end of group GPIO_EN2_Register */ 584 585 /** 586 * @ingroup gpio_registers 587 * @defgroup GPIO_EN2_SET GPIO_EN2_SET 588 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 589 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 590 * bits in that register. 591 * @{ 592 */ 593 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 594 #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 595 596 /**@} end of group GPIO_EN2_SET_Register */ 597 598 /** 599 * @ingroup gpio_registers 600 * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR 601 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 602 * register clears the bits in the same positions in GPIO_EN2 to 0, without 603 * affecting other bits in that register. 604 * @{ 605 */ 606 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 607 #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 608 609 /**@} end of group GPIO_EN2_CLR_Register */ 610 611 /** 612 * @ingroup gpio_registers 613 * @defgroup GPIO_IS GPIO_IS 614 * @brief GPIO Input Hysteresis Enable. 615 * @{ 616 */ 617 #define MXC_F_GPIO_IS_ALL_POS 0 /**< IS_ALL Position */ 618 #define MXC_F_GPIO_IS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IS_ALL_POS)) /**< IS_ALL Mask */ 619 620 /**@} end of group GPIO_IS_Register */ 621 622 /** 623 * @ingroup gpio_registers 624 * @defgroup GPIO_SR GPIO_SR 625 * @brief GPIO Slew Rate Enable Register. 626 * @{ 627 */ 628 #define MXC_F_GPIO_SR_ALL_POS 0 /**< SR_ALL Position */ 629 #define MXC_F_GPIO_SR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SR_ALL_POS)) /**< SR_ALL Mask */ 630 #define MXC_V_GPIO_SR_ALL_FAST ((uint32_t)0x0UL) /**< SR_ALL_FAST Value */ 631 #define MXC_S_GPIO_SR_ALL_FAST (MXC_V_GPIO_SR_ALL_FAST << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_FAST Setting */ 632 #define MXC_V_GPIO_SR_ALL_SLOW ((uint32_t)0x1UL) /**< SR_ALL_SLOW Value */ 633 #define MXC_S_GPIO_SR_ALL_SLOW (MXC_V_GPIO_SR_ALL_SLOW << MXC_F_GPIO_SR_ALL_POS) /**< SR_ALL_SLOW Setting */ 634 635 /**@} end of group GPIO_SR_Register */ 636 637 /** 638 * @ingroup gpio_registers 639 * @defgroup GPIO_DS0 GPIO_DS0 640 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive 641 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 642 * sink/source current of GPIO pins in each mode. 643 * @{ 644 */ 645 #define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ 646 #define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ 647 #define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ 648 #define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ 649 #define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ 650 #define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ 651 652 /**@} end of group GPIO_DS0_Register */ 653 654 /** 655 * @ingroup gpio_registers 656 * @defgroup GPIO_DS1 GPIO_DS1 657 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 658 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 659 * sink/source current of GPIO pins in each mode. 660 * @{ 661 */ 662 #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ 663 #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ 664 665 /**@} end of group GPIO_DS1_Register */ 666 667 /** 668 * @ingroup gpio_registers 669 * @defgroup GPIO_PS GPIO_PS 670 * @brief GPIO Pull Select Mode. 671 * @{ 672 */ 673 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ 674 #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ 675 676 /**@} end of group GPIO_PS_Register */ 677 678 /** 679 * @ingroup gpio_registers 680 * @defgroup GPIO_VSSEL GPIO_VSSEL 681 * @brief GPIO Voltage Select. 682 * @{ 683 */ 684 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ 685 #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ 686 687 /**@} end of group GPIO_VSSEL_Register */ 688 689 #ifdef __cplusplus 690 } 691 #endif 692 693 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GPIO_REGS_H_ 694
