1 /** 2 * @file gpio_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gpio_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GPIO_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GPIO_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gpio 67 * @defgroup gpio_registers GPIO_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 69 * @details Individual I/O for each GPIO 70 */ 71 72 /** 73 * @ingroup gpio_registers 74 * Structure type to access the GPIO Registers. 75 */ 76 typedef struct { 77 __IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */ 78 __IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */ 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ 80 __IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */ 81 __IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */ 82 __IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */ 83 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */ 84 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */ 85 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */ 86 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */ 87 __IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */ 88 __IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */ 89 __IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO INEN Register */ 90 __IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO INTEN Register */ 91 __IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */ 92 __IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */ 93 __I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO INTFL Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */ 96 __IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */ 97 __IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */ 98 __IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */ 99 __R uint32_t rsv_0x58; 100 __IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */ 101 __IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */ 102 __IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */ 103 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */ 104 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */ 105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ 106 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */ 107 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */ 108 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */ 109 __R uint32_t rsv_0x80_0xa7[10]; 110 __IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */ 111 __IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */ 112 __IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */ 113 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */ 114 __IO uint32_t pssel; /**< <tt>\b 0xB8:</tt> GPIO PSSEL Register */ 115 __R uint32_t rsv_0xbc; 116 __IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */ 117 } mxc_gpio_regs_t; 118 119 /* Register offsets for module GPIO */ 120 /** 121 * @ingroup gpio_registers 122 * @defgroup GPIO_Register_Offsets Register Offsets 123 * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 124 * @{ 125 */ 126 #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 127 #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 128 #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 129 #define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 130 #define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 131 #define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 132 #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 133 #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 134 #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 135 #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 136 #define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 137 #define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 138 #define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ 139 #define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 140 #define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 141 #define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 142 #define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 143 #define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 144 #define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 145 #define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 146 #define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 147 #define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 148 #define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 149 #define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 150 #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 151 #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 152 #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 153 #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 154 #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 155 #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 156 #define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 157 #define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 158 #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 159 #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 160 #define MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 161 #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */ 162 /**@} end of group gpio_registers */ 163 164 /** 165 * @ingroup gpio_registers 166 * @defgroup GPIO_EN0 GPIO_EN0 167 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one 168 * GPIO pin on the associated port. 169 * @{ 170 */ 171 #define MXC_F_GPIO_EN0_ALL_POS 0 /**< EN0_ALL Position */ 172 #define MXC_F_GPIO_EN0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_ALL_POS)) /**< EN0_ALL Mask */ 173 #define MXC_V_GPIO_EN0_ALL_ALTERNATE ((uint32_t)0x0UL) /**< EN0_ALL_ALTERNATE Value */ 174 #define MXC_S_GPIO_EN0_ALL_ALTERNATE (MXC_V_GPIO_EN0_ALL_ALTERNATE << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_ALTERNATE Setting */ 175 #define MXC_V_GPIO_EN0_ALL_GPIO ((uint32_t)0x1UL) /**< EN0_ALL_GPIO Value */ 176 #define MXC_S_GPIO_EN0_ALL_GPIO (MXC_V_GPIO_EN0_ALL_GPIO << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_GPIO Setting */ 177 178 /**@} end of group GPIO_EN0_Register */ 179 180 /** 181 * @ingroup gpio_registers 182 * @defgroup GPIO_EN0_SET GPIO_EN0_SET 183 * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this 184 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 185 * other bits in that register. 186 * @{ 187 */ 188 #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ 189 #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ 190 191 /**@} end of group GPIO_EN0_SET_Register */ 192 193 /** 194 * @ingroup gpio_registers 195 * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR 196 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 197 * register clears the bits in the same positions in GPIO_EN to 0, without 198 * affecting other bits in that register. 199 * @{ 200 */ 201 #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ 202 #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ 203 204 /**@} end of group GPIO_EN0_CLR_Register */ 205 206 /** 207 * @ingroup gpio_registers 208 * @defgroup GPIO_OUTEN GPIO_OUTEN 209 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 210 * GPIO pin in the associated port. 211 * @{ 212 */ 213 #define MXC_F_GPIO_OUTEN_ALL_POS 0 /**< OUTEN_ALL Position */ 214 #define MXC_F_GPIO_OUTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_ALL_POS)) /**< OUTEN_ALL Mask */ 215 #define MXC_V_GPIO_OUTEN_ALL_DIS ((uint32_t)0x0UL) /**< OUTEN_ALL_DIS Value */ 216 #define MXC_S_GPIO_OUTEN_ALL_DIS (MXC_V_GPIO_OUTEN_ALL_DIS << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_DIS Setting */ 217 #define MXC_V_GPIO_OUTEN_ALL_EN ((uint32_t)0x1UL) /**< OUTEN_ALL_EN Value */ 218 #define MXC_S_GPIO_OUTEN_ALL_EN (MXC_V_GPIO_OUTEN_ALL_EN << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_EN Setting */ 219 220 /**@} end of group GPIO_OUTEN_Register */ 221 222 /** 223 * @ingroup gpio_registers 224 * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET 225 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 226 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 227 * without affecting other bits in that register. 228 * @{ 229 */ 230 #define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ 231 #define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ 232 233 /**@} end of group GPIO_OUTEN_SET_Register */ 234 235 /** 236 * @ingroup gpio_registers 237 * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR 238 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 239 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 240 * without affecting other bits in that register. 241 * @{ 242 */ 243 #define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ 244 #define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ 245 246 /**@} end of group GPIO_OUTEN_CLR_Register */ 247 248 /** 249 * @ingroup gpio_registers 250 * @defgroup GPIO_OUT GPIO_OUT 251 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 252 * associated port. This register can be written either directly, or by using the 253 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 254 * @{ 255 */ 256 #define MXC_F_GPIO_OUT_ALL_POS 0 /**< OUT_ALL Position */ 257 #define MXC_F_GPIO_OUT_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_ALL_POS)) /**< OUT_ALL Mask */ 258 #define MXC_V_GPIO_OUT_ALL_LOW ((uint32_t)0x0UL) /**< OUT_ALL_LOW Value */ 259 #define MXC_S_GPIO_OUT_ALL_LOW (MXC_V_GPIO_OUT_ALL_LOW << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_LOW Setting */ 260 #define MXC_V_GPIO_OUT_ALL_HIGH ((uint32_t)0x1UL) /**< OUT_ALL_HIGH Value */ 261 #define MXC_S_GPIO_OUT_ALL_HIGH (MXC_V_GPIO_OUT_ALL_HIGH << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_HIGH Setting */ 262 263 /**@} end of group GPIO_OUT_Register */ 264 265 /** 266 * @ingroup gpio_registers 267 * @defgroup GPIO_OUT_SET GPIO_OUT_SET 268 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 269 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 270 * register. 271 * @{ 272 */ 273 #define MXC_F_GPIO_OUT_SET_ALL_POS 0 /**< OUT_SET_ALL Position */ 274 #define MXC_F_GPIO_OUT_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_ALL_POS)) /**< OUT_SET_ALL Mask */ 275 #define MXC_V_GPIO_OUT_SET_ALL_NO ((uint32_t)0x0UL) /**< OUT_SET_ALL_NO Value */ 276 #define MXC_S_GPIO_OUT_SET_ALL_NO (MXC_V_GPIO_OUT_SET_ALL_NO << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_NO Setting */ 277 #define MXC_V_GPIO_OUT_SET_ALL_SET ((uint32_t)0x1UL) /**< OUT_SET_ALL_SET Value */ 278 #define MXC_S_GPIO_OUT_SET_ALL_SET (MXC_V_GPIO_OUT_SET_ALL_SET << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_SET Setting */ 279 280 /**@} end of group GPIO_OUT_SET_Register */ 281 282 /** 283 * @ingroup gpio_registers 284 * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR 285 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 286 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 287 * that register. 288 * @{ 289 */ 290 #define MXC_F_GPIO_OUT_CLR_ALL_POS 0 /**< OUT_CLR_ALL Position */ 291 #define MXC_F_GPIO_OUT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_ALL_POS)) /**< OUT_CLR_ALL Mask */ 292 293 /**@} end of group GPIO_OUT_CLR_Register */ 294 295 /** 296 * @ingroup gpio_registers 297 * @defgroup GPIO_IN GPIO_IN 298 * @brief GPIO Input Register. Read-only register to read from the logic states of the 299 * GPIO pins on this port. 300 * @{ 301 */ 302 #define MXC_F_GPIO_IN_ALL_POS 0 /**< IN_ALL Position */ 303 #define MXC_F_GPIO_IN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_ALL_POS)) /**< IN_ALL Mask */ 304 305 /**@} end of group GPIO_IN_Register */ 306 307 /** 308 * @ingroup gpio_registers 309 * @defgroup GPIO_INTMODE GPIO_INTMODE 310 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 311 * mode setting for the associated GPIO pin on this port. 312 * @{ 313 */ 314 #define MXC_F_GPIO_INTMODE_ALL_POS 0 /**< INTMODE_ALL Position */ 315 #define MXC_F_GPIO_INTMODE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_ALL_POS)) /**< INTMODE_ALL Mask */ 316 #define MXC_V_GPIO_INTMODE_ALL_LEVEL ((uint32_t)0x0UL) /**< INTMODE_ALL_LEVEL Value */ 317 #define MXC_S_GPIO_INTMODE_ALL_LEVEL (MXC_V_GPIO_INTMODE_ALL_LEVEL << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_LEVEL Setting */ 318 #define MXC_V_GPIO_INTMODE_ALL_EDGE ((uint32_t)0x1UL) /**< INTMODE_ALL_EDGE Value */ 319 #define MXC_S_GPIO_INTMODE_ALL_EDGE (MXC_V_GPIO_INTMODE_ALL_EDGE << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_EDGE Setting */ 320 321 /**@} end of group GPIO_INTMODE_Register */ 322 323 /** 324 * @ingroup gpio_registers 325 * @defgroup GPIO_INTPOL GPIO_INTPOL 326 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 327 * interrupt polarity setting for one GPIO pin in the associated port. 328 * @{ 329 */ 330 #define MXC_F_GPIO_INTPOL_ALL_POS 0 /**< INTPOL_ALL Position */ 331 #define MXC_F_GPIO_INTPOL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_ALL_POS)) /**< INTPOL_ALL Mask */ 332 #define MXC_V_GPIO_INTPOL_ALL_FALLING ((uint32_t)0x0UL) /**< INTPOL_ALL_FALLING Value */ 333 #define MXC_S_GPIO_INTPOL_ALL_FALLING (MXC_V_GPIO_INTPOL_ALL_FALLING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_FALLING Setting */ 334 #define MXC_V_GPIO_INTPOL_ALL_RISING ((uint32_t)0x1UL) /**< INTPOL_ALL_RISING Value */ 335 #define MXC_S_GPIO_INTPOL_ALL_RISING (MXC_V_GPIO_INTPOL_ALL_RISING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_RISING Setting */ 336 337 /**@} end of group GPIO_INTPOL_Register */ 338 339 /** 340 * @ingroup gpio_registers 341 * @defgroup GPIO_INTEN GPIO_INTEN 342 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 343 * interrupt enable for the associated pin on the GPIO port. 344 * @{ 345 */ 346 #define MXC_F_GPIO_INTEN_ALL_POS 0 /**< INTEN_ALL Position */ 347 #define MXC_F_GPIO_INTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_ALL_POS)) /**< INTEN_ALL Mask */ 348 #define MXC_V_GPIO_INTEN_ALL_DIS ((uint32_t)0x0UL) /**< INTEN_ALL_DIS Value */ 349 #define MXC_S_GPIO_INTEN_ALL_DIS (MXC_V_GPIO_INTEN_ALL_DIS << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_DIS Setting */ 350 #define MXC_V_GPIO_INTEN_ALL_EN ((uint32_t)0x1UL) /**< INTEN_ALL_EN Value */ 351 #define MXC_S_GPIO_INTEN_ALL_EN (MXC_V_GPIO_INTEN_ALL_EN << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_EN Setting */ 352 353 /**@} end of group GPIO_INTEN_Register */ 354 355 /** 356 * @ingroup gpio_registers 357 * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET 358 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 359 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 360 * in that register. 361 * @{ 362 */ 363 #define MXC_F_GPIO_INTEN_SET_ALL_POS 0 /**< INTEN_SET_ALL Position */ 364 #define MXC_F_GPIO_INTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_ALL_POS)) /**< INTEN_SET_ALL Mask */ 365 #define MXC_V_GPIO_INTEN_SET_ALL_NO ((uint32_t)0x0UL) /**< INTEN_SET_ALL_NO Value */ 366 #define MXC_S_GPIO_INTEN_SET_ALL_NO (MXC_V_GPIO_INTEN_SET_ALL_NO << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_NO Setting */ 367 #define MXC_V_GPIO_INTEN_SET_ALL_SET ((uint32_t)0x1UL) /**< INTEN_SET_ALL_SET Value */ 368 #define MXC_S_GPIO_INTEN_SET_ALL_SET (MXC_V_GPIO_INTEN_SET_ALL_SET << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_SET Setting */ 369 370 /**@} end of group GPIO_INTEN_SET_Register */ 371 372 /** 373 * @ingroup gpio_registers 374 * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR 375 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 376 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 377 * other bits in that register. 378 * @{ 379 */ 380 #define MXC_F_GPIO_INTEN_CLR_ALL_POS 0 /**< INTEN_CLR_ALL Position */ 381 #define MXC_F_GPIO_INTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_ALL_POS)) /**< INTEN_CLR_ALL Mask */ 382 #define MXC_V_GPIO_INTEN_CLR_ALL_NO ((uint32_t)0x0UL) /**< INTEN_CLR_ALL_NO Value */ 383 #define MXC_S_GPIO_INTEN_CLR_ALL_NO (MXC_V_GPIO_INTEN_CLR_ALL_NO << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_NO Setting */ 384 #define MXC_V_GPIO_INTEN_CLR_ALL_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_ALL_CLEAR Value */ 385 #define MXC_S_GPIO_INTEN_CLR_ALL_CLEAR (MXC_V_GPIO_INTEN_CLR_ALL_CLEAR << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_CLEAR Setting */ 386 387 /**@} end of group GPIO_INTEN_CLR_Register */ 388 389 /** 390 * @ingroup gpio_registers 391 * @defgroup GPIO_INTFL GPIO_INTFL 392 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 393 * interrupt status for the associated GPIO pin in this port. 394 * @{ 395 */ 396 #define MXC_F_GPIO_INTFL_ALL_POS 0 /**< INTFL_ALL Position */ 397 #define MXC_F_GPIO_INTFL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_ALL_POS)) /**< INTFL_ALL Mask */ 398 #define MXC_V_GPIO_INTFL_ALL_NO ((uint32_t)0x0UL) /**< INTFL_ALL_NO Value */ 399 #define MXC_S_GPIO_INTFL_ALL_NO (MXC_V_GPIO_INTFL_ALL_NO << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_NO Setting */ 400 #define MXC_V_GPIO_INTFL_ALL_PENDING ((uint32_t)0x1UL) /**< INTFL_ALL_PENDING Value */ 401 #define MXC_S_GPIO_INTFL_ALL_PENDING (MXC_V_GPIO_INTFL_ALL_PENDING << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_PENDING Setting */ 402 403 /**@} end of group GPIO_INTFL_Register */ 404 405 /** 406 * @ingroup gpio_registers 407 * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR 408 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 409 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 410 * in that register. 411 * @{ 412 */ 413 #define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ 414 #define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ 415 416 /**@} end of group GPIO_INTFL_CLR_Register */ 417 418 /** 419 * @ingroup gpio_registers 420 * @defgroup GPIO_WKEN GPIO_WKEN 421 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 422 * enable for the associated GPIO pin in this port. 423 * @{ 424 */ 425 #define MXC_F_GPIO_WKEN_ALL_POS 0 /**< WKEN_ALL Position */ 426 #define MXC_F_GPIO_WKEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_ALL_POS)) /**< WKEN_ALL Mask */ 427 #define MXC_V_GPIO_WKEN_ALL_DIS ((uint32_t)0x0UL) /**< WKEN_ALL_DIS Value */ 428 #define MXC_S_GPIO_WKEN_ALL_DIS (MXC_V_GPIO_WKEN_ALL_DIS << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_DIS Setting */ 429 #define MXC_V_GPIO_WKEN_ALL_EN ((uint32_t)0x1UL) /**< WKEN_ALL_EN Value */ 430 #define MXC_S_GPIO_WKEN_ALL_EN (MXC_V_GPIO_WKEN_ALL_EN << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_EN Setting */ 431 432 /**@} end of group GPIO_WKEN_Register */ 433 434 /** 435 * @ingroup gpio_registers 436 * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET 437 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 438 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 439 * that register. 440 * @{ 441 */ 442 #define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ 443 #define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ 444 445 /**@} end of group GPIO_WKEN_SET_Register */ 446 447 /** 448 * @ingroup gpio_registers 449 * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR 450 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 451 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 452 * bits in that register. 453 * @{ 454 */ 455 #define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ 456 #define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ 457 458 /**@} end of group GPIO_WKEN_CLR_Register */ 459 460 /** 461 * @ingroup gpio_registers 462 * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE 463 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 464 * edge mode for the associated GPIO pin in this port. 465 * @{ 466 */ 467 #define MXC_F_GPIO_DUALEDGE_ALL_POS 0 /**< DUALEDGE_ALL Position */ 468 #define MXC_F_GPIO_DUALEDGE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_ALL_POS)) /**< DUALEDGE_ALL Mask */ 469 #define MXC_V_GPIO_DUALEDGE_ALL_NO ((uint32_t)0x0UL) /**< DUALEDGE_ALL_NO Value */ 470 #define MXC_S_GPIO_DUALEDGE_ALL_NO (MXC_V_GPIO_DUALEDGE_ALL_NO << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_NO Setting */ 471 #define MXC_V_GPIO_DUALEDGE_ALL_EN ((uint32_t)0x1UL) /**< DUALEDGE_ALL_EN Value */ 472 #define MXC_S_GPIO_DUALEDGE_ALL_EN (MXC_V_GPIO_DUALEDGE_ALL_EN << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_EN Setting */ 473 474 /**@} end of group GPIO_DUALEDGE_Register */ 475 476 /** 477 * @ingroup gpio_registers 478 * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 479 * @brief GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for 480 * the associated GPIO pin in this port. 481 * @{ 482 */ 483 #define MXC_F_GPIO_PADCTRL0_ALL_POS 0 /**< PADCTRL0_ALL Position */ 484 #define MXC_F_GPIO_PADCTRL0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_ALL_POS)) /**< PADCTRL0_ALL Mask */ 485 #define MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_ALL_IMPEDANCE Value */ 486 #define MXC_S_GPIO_PADCTRL0_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_IMPEDANCE Setting */ 487 #define MXC_V_GPIO_PADCTRL0_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL0_ALL_PU Value */ 488 #define MXC_S_GPIO_PADCTRL0_ALL_PU (MXC_V_GPIO_PADCTRL0_ALL_PU << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PU Setting */ 489 #define MXC_V_GPIO_PADCTRL0_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL0_ALL_PD Value */ 490 #define MXC_S_GPIO_PADCTRL0_ALL_PD (MXC_V_GPIO_PADCTRL0_ALL_PD << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PD Setting */ 491 492 /**@} end of group GPIO_PADCTRL0_Register */ 493 494 /** 495 * @ingroup gpio_registers 496 * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 497 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 498 * the associated GPIO pin in this port. 499 * @{ 500 */ 501 #define MXC_F_GPIO_PADCTRL1_ALL_POS 0 /**< PADCTRL1_ALL Position */ 502 #define MXC_F_GPIO_PADCTRL1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_ALL_POS)) /**< PADCTRL1_ALL Mask */ 503 #define MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_ALL_IMPEDANCE Value */ 504 #define MXC_S_GPIO_PADCTRL1_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_IMPEDANCE Setting */ 505 #define MXC_V_GPIO_PADCTRL1_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL1_ALL_PU Value */ 506 #define MXC_S_GPIO_PADCTRL1_ALL_PU (MXC_V_GPIO_PADCTRL1_ALL_PU << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PU Setting */ 507 #define MXC_V_GPIO_PADCTRL1_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL1_ALL_PD Value */ 508 #define MXC_S_GPIO_PADCTRL1_ALL_PD (MXC_V_GPIO_PADCTRL1_ALL_PD << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PD Setting */ 509 510 /**@} end of group GPIO_PADCTRL1_Register */ 511 512 /** 513 * @ingroup gpio_registers 514 * @defgroup GPIO_EN1 GPIO_EN1 515 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 516 * between primary/secondary functions for the associated GPIO pin in this port. 517 * @{ 518 */ 519 #define MXC_F_GPIO_EN1_ALL_POS 0 /**< EN1_ALL Position */ 520 #define MXC_F_GPIO_EN1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_ALL_POS)) /**< EN1_ALL Mask */ 521 #define MXC_V_GPIO_EN1_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN1_ALL_PRIMARY Value */ 522 #define MXC_S_GPIO_EN1_ALL_PRIMARY (MXC_V_GPIO_EN1_ALL_PRIMARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_PRIMARY Setting */ 523 #define MXC_V_GPIO_EN1_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN1_ALL_SECONDARY Value */ 524 #define MXC_S_GPIO_EN1_ALL_SECONDARY (MXC_V_GPIO_EN1_ALL_SECONDARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_SECONDARY Setting */ 525 526 /**@} end of group GPIO_EN1_Register */ 527 528 /** 529 * @ingroup gpio_registers 530 * @defgroup GPIO_EN1_SET GPIO_EN1_SET 531 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 532 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 533 * bits in that register. 534 * @{ 535 */ 536 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 537 #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 538 539 /**@} end of group GPIO_EN1_SET_Register */ 540 541 /** 542 * @ingroup gpio_registers 543 * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR 544 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 545 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 546 * bits in that register. 547 * @{ 548 */ 549 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 550 #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 551 552 /**@} end of group GPIO_EN1_CLR_Register */ 553 554 /** 555 * @ingroup gpio_registers 556 * @defgroup GPIO_EN2 GPIO_EN2 557 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 558 * between primary/secondary functions for the associated GPIO pin in this port. 559 * @{ 560 */ 561 #define MXC_F_GPIO_EN2_ALL_POS 0 /**< EN2_ALL Position */ 562 #define MXC_F_GPIO_EN2_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_ALL_POS)) /**< EN2_ALL Mask */ 563 #define MXC_V_GPIO_EN2_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN2_ALL_PRIMARY Value */ 564 #define MXC_S_GPIO_EN2_ALL_PRIMARY (MXC_V_GPIO_EN2_ALL_PRIMARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_PRIMARY Setting */ 565 #define MXC_V_GPIO_EN2_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN2_ALL_SECONDARY Value */ 566 #define MXC_S_GPIO_EN2_ALL_SECONDARY (MXC_V_GPIO_EN2_ALL_SECONDARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_SECONDARY Setting */ 567 568 /**@} end of group GPIO_EN2_Register */ 569 570 /** 571 * @ingroup gpio_registers 572 * @defgroup GPIO_EN2_SET GPIO_EN2_SET 573 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 574 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 575 * bits in that register. 576 * @{ 577 */ 578 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 579 #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 580 581 /**@} end of group GPIO_EN2_SET_Register */ 582 583 /** 584 * @ingroup gpio_registers 585 * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR 586 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 587 * register clears the bits in the same positions in GPIO_EN2 to 0, without 588 * affecting other bits in that register. 589 * @{ 590 */ 591 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 592 #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 593 594 /**@} end of group GPIO_EN2_CLR_Register */ 595 596 /** 597 * @ingroup gpio_registers 598 * @defgroup GPIO_HYSEN GPIO_HYSEN 599 * @brief GPIO Input Hysteresis Enable. 600 * @{ 601 */ 602 #define MXC_F_GPIO_HYSEN_ALL_POS 0 /**< HYSEN_ALL Position */ 603 #define MXC_F_GPIO_HYSEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_ALL_POS)) /**< HYSEN_ALL Mask */ 604 605 /**@} end of group GPIO_HYSEN_Register */ 606 607 /** 608 * @ingroup gpio_registers 609 * @defgroup GPIO_SRSEL GPIO_SRSEL 610 * @brief GPIO Slew Rate Enable Register. 611 * @{ 612 */ 613 #define MXC_F_GPIO_SRSEL_ALL_POS 0 /**< SRSEL_ALL Position */ 614 #define MXC_F_GPIO_SRSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_ALL_POS)) /**< SRSEL_ALL Mask */ 615 #define MXC_V_GPIO_SRSEL_ALL_FAST ((uint32_t)0x0UL) /**< SRSEL_ALL_FAST Value */ 616 #define MXC_S_GPIO_SRSEL_ALL_FAST (MXC_V_GPIO_SRSEL_ALL_FAST << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_FAST Setting */ 617 #define MXC_V_GPIO_SRSEL_ALL_SLOW ((uint32_t)0x1UL) /**< SRSEL_ALL_SLOW Value */ 618 #define MXC_S_GPIO_SRSEL_ALL_SLOW (MXC_V_GPIO_SRSEL_ALL_SLOW << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_SLOW Setting */ 619 620 /**@} end of group GPIO_SRSEL_Register */ 621 622 /** 623 * @ingroup gpio_registers 624 * @defgroup GPIO_DS0 GPIO_DS0 625 * @brief GPIO Drive Strength 0 Register. Each bit in this register selects the drive 626 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 627 * sink/source current of GPIO pins in each mode. 628 * @{ 629 */ 630 #define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ 631 #define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ 632 #define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ 633 #define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ 634 #define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ 635 #define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ 636 637 /**@} end of group GPIO_DS0_Register */ 638 639 /** 640 * @ingroup gpio_registers 641 * @defgroup GPIO_DS1 GPIO_DS1 642 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 643 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 644 * sink/source current of GPIO pins in each mode. 645 * @{ 646 */ 647 #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ 648 #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ 649 650 /**@} end of group GPIO_DS1_Register */ 651 652 /** 653 * @ingroup gpio_registers 654 * @defgroup GPIO_PSSEL GPIO_PSSEL 655 * @brief GPIO Pull Select Mode. 656 * @{ 657 */ 658 #define MXC_F_GPIO_PSSEL_ALL_POS 0 /**< PSSEL_ALL Position */ 659 #define MXC_F_GPIO_PSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PSSEL_ALL_POS)) /**< PSSEL_ALL Mask */ 660 661 /**@} end of group GPIO_PSSEL_Register */ 662 663 /** 664 * @ingroup gpio_registers 665 * @defgroup GPIO_VSSEL GPIO_VSSEL 666 * @brief GPIO Voltage Select. 667 * @{ 668 */ 669 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ 670 #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ 671 672 /**@} end of group GPIO_VSSEL_Register */ 673 674 #ifdef __cplusplus 675 } 676 #endif 677 678 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GPIO_REGS_H_ 679
