1 /** 2 * @file gpio_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gpio_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_GPIO_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_GPIO_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gpio 67 * @defgroup gpio_registers GPIO_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 69 * @details Individual I/O for each GPIO 70 */ 71 72 /** 73 * @ingroup gpio_registers 74 * Structure type to access the GPIO Registers. 75 */ 76 typedef struct { 77 __IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */ 78 __IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */ 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ 80 __IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */ 81 __IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */ 82 __IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */ 83 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */ 84 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */ 85 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */ 86 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */ 87 __IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */ 88 __IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */ 89 __IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO INEN Register */ 90 __IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO INTEN Register */ 91 __IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */ 92 __IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */ 93 __I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO INTFL Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */ 96 __IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */ 97 __IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */ 98 __IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */ 99 __R uint32_t rsv_0x58; 100 __IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */ 101 __IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */ 102 __IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */ 103 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */ 104 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */ 105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ 106 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */ 107 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */ 108 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */ 109 __R uint32_t rsv_0x80_0xa7[10]; 110 __IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */ 111 __IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */ 112 __IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */ 113 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */ 114 __IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */ 115 } mxc_gpio_regs_t; 116 117 /* Register offsets for module GPIO */ 118 /** 119 * @ingroup gpio_registers 120 * @defgroup GPIO_Register_Offsets Register Offsets 121 * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 122 * @{ 123 */ 124 #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 125 #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 126 #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 127 #define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 128 #define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 129 #define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 130 #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 131 #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 132 #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 133 #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 134 #define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 135 #define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 136 #define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ 137 #define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 138 #define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 139 #define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 140 #define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 141 #define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 142 #define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 143 #define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 144 #define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 145 #define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 146 #define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 147 #define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 148 #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 149 #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 150 #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 151 #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 152 #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 153 #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 154 #define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 155 #define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 156 #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 157 #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 158 #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 159 /**@} end of group gpio_registers */ 160 161 /** 162 * @ingroup gpio_registers 163 * @defgroup GPIO_EN0 GPIO_EN0 164 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one 165 * GPIO pin on the associated port. 166 * @{ 167 */ 168 #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ 169 #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ 170 #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ 171 #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ 172 #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ 173 #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ 174 175 /**@} end of group GPIO_EN0_Register */ 176 177 /** 178 * @ingroup gpio_registers 179 * @defgroup GPIO_EN0_SET GPIO_EN0_SET 180 * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this 181 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 182 * other bits in that register. 183 * @{ 184 */ 185 #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ 186 #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ 187 188 /**@} end of group GPIO_EN0_SET_Register */ 189 190 /** 191 * @ingroup gpio_registers 192 * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR 193 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 194 * register clears the bits in the same positions in GPIO_EN to 0, without 195 * affecting other bits in that register. 196 * @{ 197 */ 198 #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ 199 #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ 200 201 /**@} end of group GPIO_EN0_CLR_Register */ 202 203 /** 204 * @ingroup gpio_registers 205 * @defgroup GPIO_OUTEN GPIO_OUTEN 206 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 207 * GPIO pin in the associated port. 208 * @{ 209 */ 210 #define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ 211 #define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ 212 #define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ 213 #define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ 214 #define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ 215 #define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ 216 217 /**@} end of group GPIO_OUTEN_Register */ 218 219 /** 220 * @ingroup gpio_registers 221 * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET 222 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 223 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 224 * without affecting other bits in that register. 225 * @{ 226 */ 227 #define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ 228 #define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ 229 230 /**@} end of group GPIO_OUTEN_SET_Register */ 231 232 /** 233 * @ingroup gpio_registers 234 * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR 235 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 236 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 237 * without affecting other bits in that register. 238 * @{ 239 */ 240 #define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ 241 #define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ 242 243 /**@} end of group GPIO_OUTEN_CLR_Register */ 244 245 /** 246 * @ingroup gpio_registers 247 * @defgroup GPIO_OUT GPIO_OUT 248 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 249 * associated port. This register can be written either directly, or by using the 250 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 251 * @{ 252 */ 253 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ 254 #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ 255 #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ 256 #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ 257 #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ 258 #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ 259 260 /**@} end of group GPIO_OUT_Register */ 261 262 /** 263 * @ingroup gpio_registers 264 * @defgroup GPIO_OUT_SET GPIO_OUT_SET 265 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 266 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 267 * register. 268 * @{ 269 */ 270 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ 271 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ 272 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ 273 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ 274 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ 275 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ 276 277 /**@} end of group GPIO_OUT_SET_Register */ 278 279 /** 280 * @ingroup gpio_registers 281 * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR 282 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 283 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 284 * that register. 285 * @{ 286 */ 287 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ 288 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ 289 290 /**@} end of group GPIO_OUT_CLR_Register */ 291 292 /** 293 * @ingroup gpio_registers 294 * @defgroup GPIO_IN GPIO_IN 295 * @brief GPIO Input Register. Read-only register to read from the logic states of the 296 * GPIO pins on this port. 297 * @{ 298 */ 299 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ 300 #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ 301 302 /**@} end of group GPIO_IN_Register */ 303 304 /** 305 * @ingroup gpio_registers 306 * @defgroup GPIO_INTMODE GPIO_INTMODE 307 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 308 * mode setting for the associated GPIO pin on this port. 309 * @{ 310 */ 311 #define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ 312 #define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ 313 #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ 314 #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ 315 #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ 316 #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ 317 318 /**@} end of group GPIO_INTMODE_Register */ 319 320 /** 321 * @ingroup gpio_registers 322 * @defgroup GPIO_INTPOL GPIO_INTPOL 323 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 324 * interrupt polarity setting for one GPIO pin in the associated port. 325 * @{ 326 */ 327 #define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ 328 #define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ 329 #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ 330 #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ 331 #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ 332 #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ 333 334 /**@} end of group GPIO_INTPOL_Register */ 335 336 /** 337 * @ingroup gpio_registers 338 * @defgroup GPIO_INTEN GPIO_INTEN 339 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 340 * interrupt enable for the associated pin on the GPIO port. 341 * @{ 342 */ 343 #define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ 344 #define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ 345 #define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ 346 #define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ 347 #define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ 348 #define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ 349 350 /**@} end of group GPIO_INTEN_Register */ 351 352 /** 353 * @ingroup gpio_registers 354 * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET 355 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 356 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 357 * in that register. 358 * @{ 359 */ 360 #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ 361 #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ 362 #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ 363 #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ 364 #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ 365 #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ 366 367 /**@} end of group GPIO_INTEN_SET_Register */ 368 369 /** 370 * @ingroup gpio_registers 371 * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR 372 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 373 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 374 * other bits in that register. 375 * @{ 376 */ 377 #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ 378 #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ 379 #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ 380 #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ 381 #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ 382 #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ 383 384 /**@} end of group GPIO_INTEN_CLR_Register */ 385 386 /** 387 * @ingroup gpio_registers 388 * @defgroup GPIO_INTFL GPIO_INTFL 389 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 390 * interrupt status for the associated GPIO pin in this port. 391 * @{ 392 */ 393 #define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ 394 #define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ 395 #define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ 396 #define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ 397 #define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ 398 #define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ 399 400 /**@} end of group GPIO_INTFL_Register */ 401 402 /** 403 * @ingroup gpio_registers 404 * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR 405 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 406 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 407 * in that register. 408 * @{ 409 */ 410 #define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ 411 #define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ 412 413 /**@} end of group GPIO_INTFL_CLR_Register */ 414 415 /** 416 * @ingroup gpio_registers 417 * @defgroup GPIO_WKEN GPIO_WKEN 418 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 419 * enable for the associated GPIO pin in this port. 420 * @{ 421 */ 422 #define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ 423 #define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ 424 #define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ 425 #define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ 426 #define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ 427 #define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ 428 429 /**@} end of group GPIO_WKEN_Register */ 430 431 /** 432 * @ingroup gpio_registers 433 * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET 434 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 435 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 436 * that register. 437 * @{ 438 */ 439 #define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ 440 #define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ 441 442 /**@} end of group GPIO_WKEN_SET_Register */ 443 444 /** 445 * @ingroup gpio_registers 446 * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR 447 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 448 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 449 * bits in that register. 450 * @{ 451 */ 452 #define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ 453 #define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ 454 455 /**@} end of group GPIO_WKEN_CLR_Register */ 456 457 /** 458 * @ingroup gpio_registers 459 * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE 460 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 461 * edge mode for the associated GPIO pin in this port. 462 * @{ 463 */ 464 #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ 465 #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ 466 #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ 467 #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ 468 #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ 469 #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ 470 471 /**@} end of group GPIO_DUALEDGE_Register */ 472 473 /** 474 * @ingroup gpio_registers 475 * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 476 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 477 * the associated GPIO pin in this port. 478 * @{ 479 */ 480 #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ 481 #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ 482 #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ 483 #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ 484 #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ 485 #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ 486 #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ 487 #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ 488 489 /**@} end of group GPIO_PADCTRL0_Register */ 490 491 /** 492 * @ingroup gpio_registers 493 * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 494 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for 495 * the associated GPIO pin in this port. 496 * @{ 497 */ 498 #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ 499 #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ 500 #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ 501 #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ 502 #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ 503 #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ 504 #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ 505 #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ 506 507 /**@} end of group GPIO_PADCTRL1_Register */ 508 509 /** 510 * @ingroup gpio_registers 511 * @defgroup GPIO_EN1 GPIO_EN1 512 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 513 * between primary/secondary functions for the associated GPIO pin in this port. 514 * @{ 515 */ 516 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ 517 #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ 518 #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ 519 #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ 520 #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ 521 #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ 522 523 /**@} end of group GPIO_EN1_Register */ 524 525 /** 526 * @ingroup gpio_registers 527 * @defgroup GPIO_EN1_SET GPIO_EN1_SET 528 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 529 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 530 * bits in that register. 531 * @{ 532 */ 533 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 534 #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 535 536 /**@} end of group GPIO_EN1_SET_Register */ 537 538 /** 539 * @ingroup gpio_registers 540 * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR 541 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 542 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 543 * bits in that register. 544 * @{ 545 */ 546 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 547 #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 548 549 /**@} end of group GPIO_EN1_CLR_Register */ 550 551 /** 552 * @ingroup gpio_registers 553 * @defgroup GPIO_EN2 GPIO_EN2 554 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 555 * between primary/secondary functions for the associated GPIO pin in this port. 556 * @{ 557 */ 558 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ 559 #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ 560 #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ 561 #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ 562 #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ 563 #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ 564 565 /**@} end of group GPIO_EN2_Register */ 566 567 /** 568 * @ingroup gpio_registers 569 * @defgroup GPIO_EN2_SET GPIO_EN2_SET 570 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 571 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 572 * bits in that register. 573 * @{ 574 */ 575 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 576 #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 577 578 /**@} end of group GPIO_EN2_SET_Register */ 579 580 /** 581 * @ingroup gpio_registers 582 * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR 583 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 584 * register clears the bits in the same positions in GPIO_EN2 to 0, without 585 * affecting other bits in that register. 586 * @{ 587 */ 588 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 589 #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 590 591 /**@} end of group GPIO_EN2_CLR_Register */ 592 593 /** 594 * @ingroup gpio_registers 595 * @defgroup GPIO_HYSEN GPIO_HYSEN 596 * @brief GPIO Input Hysteresis Enable. 597 * @{ 598 */ 599 #define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ 600 #define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ 601 602 /**@} end of group GPIO_HYSEN_Register */ 603 604 /** 605 * @ingroup gpio_registers 606 * @defgroup GPIO_SRSEL GPIO_SRSEL 607 * @brief GPIO Slew Rate Enable Register. 608 * @{ 609 */ 610 #define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ 611 #define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ 612 #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ 613 #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ 614 #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ 615 #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ 616 617 /**@} end of group GPIO_SRSEL_Register */ 618 619 /** 620 * @ingroup gpio_registers 621 * @defgroup GPIO_DS0 GPIO_DS0 622 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive 623 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 624 * sink/source current of GPIO pins in each mode. 625 * @{ 626 */ 627 #define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ 628 #define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ 629 #define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ 630 #define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ 631 #define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ 632 #define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ 633 634 /**@} end of group GPIO_DS0_Register */ 635 636 /** 637 * @ingroup gpio_registers 638 * @defgroup GPIO_DS1 GPIO_DS1 639 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 640 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 641 * sink/source current of GPIO pins in each mode. 642 * @{ 643 */ 644 #define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ 645 #define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ 646 647 /**@} end of group GPIO_DS1_Register */ 648 649 /** 650 * @ingroup gpio_registers 651 * @defgroup GPIO_PS GPIO_PS 652 * @brief GPIO Pull Select Mode. 653 * @{ 654 */ 655 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ 656 #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ 657 658 /**@} end of group GPIO_PS_Register */ 659 660 #ifdef __cplusplus 661 } 662 #endif 663 664 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_GPIO_REGS_H_ 665
