1 /** 2 * @file gpio_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gpio_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_GPIO_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_GPIO_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gpio 67 * @defgroup gpio_registers GPIO_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 69 * @details Individual I/O for each GPIO 70 */ 71 72 /** 73 * @ingroup gpio_registers 74 * Structure type to access the GPIO Registers. 75 */ 76 typedef struct { 77 __IO uint32_t en0; /**< <tt>\b 0x00:</tt> GPIO EN0 Register */ 78 __IO uint32_t en0_set; /**< <tt>\b 0x04:</tt> GPIO EN0_SET Register */ 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ 80 __IO uint32_t outen; /**< <tt>\b 0x0C:</tt> GPIO OUTEN Register */ 81 __IO uint32_t outen_set; /**< <tt>\b 0x10:</tt> GPIO OUTEN_SET Register */ 82 __IO uint32_t outen_clr; /**< <tt>\b 0x14:</tt> GPIO OUTEN_CLR Register */ 83 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */ 84 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */ 85 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */ 86 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */ 87 __IO uint32_t intmode; /**< <tt>\b 0x28:</tt> GPIO INTMODE Register */ 88 __IO uint32_t intpol; /**< <tt>\b 0x2C:</tt> GPIO INTPOL Register */ 89 __IO uint32_t inen; /**< <tt>\b 0x30:</tt> GPIO INEN Register */ 90 __IO uint32_t inten; /**< <tt>\b 0x34:</tt> GPIO INTEN Register */ 91 __IO uint32_t inten_set; /**< <tt>\b 0x38:</tt> GPIO INTEN_SET Register */ 92 __IO uint32_t inten_clr; /**< <tt>\b 0x3C:</tt> GPIO INTEN_CLR Register */ 93 __I uint32_t intfl; /**< <tt>\b 0x40:</tt> GPIO INTFL Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t intfl_clr; /**< <tt>\b 0x48:</tt> GPIO INTFL_CLR Register */ 96 __IO uint32_t wken; /**< <tt>\b 0x4C:</tt> GPIO WKEN Register */ 97 __IO uint32_t wken_set; /**< <tt>\b 0x50:</tt> GPIO WKEN_SET Register */ 98 __IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */ 99 __R uint32_t rsv_0x58; 100 __IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */ 101 __IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */ 102 __IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */ 103 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */ 104 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */ 105 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ 106 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */ 107 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */ 108 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */ 109 __IO uint32_t en3; /**< <tt>\b 0x80:</tt> GPIO EN3 Register */ 110 __IO uint32_t en3_set; /**< <tt>\b 0x84:</tt> GPIO EN3_SET Register */ 111 __IO uint32_t en3_clr; /**< <tt>\b 0x88:</tt> GPIO EN3_CLR Register */ 112 __R uint32_t rsv_0x8c_0xa7[7]; 113 __IO uint32_t hysen; /**< <tt>\b 0xA8:</tt> GPIO HYSEN Register */ 114 __IO uint32_t srsel; /**< <tt>\b 0xAC:</tt> GPIO SRSEL Register */ 115 __IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */ 116 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */ 117 __IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */ 118 __R uint32_t rsv_0xbc; 119 __IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */ 120 } mxc_gpio_regs_t; 121 122 /* Register offsets for module GPIO */ 123 /** 124 * @ingroup gpio_registers 125 * @defgroup GPIO_Register_Offsets Register Offsets 126 * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 127 * @{ 128 */ 129 #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 130 #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 131 #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 132 #define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 133 #define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 134 #define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 135 #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 136 #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 137 #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 138 #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 139 #define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 140 #define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 141 #define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */ 142 #define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 143 #define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 144 #define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 145 #define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 146 #define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 147 #define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 148 #define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 149 #define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 150 #define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 151 #define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 152 #define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 153 #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 154 #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 155 #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 156 #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 157 #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 158 #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 159 #define MXC_R_GPIO_EN3 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt> 0x0080</tt> */ 160 #define MXC_R_GPIO_EN3_SET ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt> 0x0084</tt> */ 161 #define MXC_R_GPIO_EN3_CLR ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt> 0x0088</tt> */ 162 #define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 163 #define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 164 #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 165 #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 166 #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 167 #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */ 168 /**@} end of group gpio_registers */ 169 170 /** 171 * @ingroup gpio_registers 172 * @defgroup GPIO_EN0 GPIO_EN0 173 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one 174 * GPIO pin on the associated port. 175 * @{ 176 */ 177 #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ 178 #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ 179 #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ 180 #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ 181 #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ 182 #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ 183 184 /**@} end of group GPIO_EN0_Register */ 185 186 /** 187 * @ingroup gpio_registers 188 * @defgroup GPIO_EN0_SET GPIO_EN0_SET 189 * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this 190 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 191 * other bits in that register. 192 * @{ 193 */ 194 #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ 195 #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ 196 197 /**@} end of group GPIO_EN0_SET_Register */ 198 199 /** 200 * @ingroup gpio_registers 201 * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR 202 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 203 * register clears the bits in the same positions in GPIO_EN to 0, without 204 * affecting other bits in that register. 205 * @{ 206 */ 207 #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ 208 #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ 209 210 /**@} end of group GPIO_EN0_CLR_Register */ 211 212 /** 213 * @ingroup gpio_registers 214 * @defgroup GPIO_OUTEN GPIO_OUTEN 215 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 216 * GPIO pin in the associated port. 217 * @{ 218 */ 219 #define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ 220 #define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ 221 #define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ 222 #define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ 223 #define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ 224 #define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ 225 226 /**@} end of group GPIO_OUTEN_Register */ 227 228 /** 229 * @ingroup gpio_registers 230 * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET 231 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 232 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 233 * without affecting other bits in that register. 234 * @{ 235 */ 236 #define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ 237 #define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ 238 239 /**@} end of group GPIO_OUTEN_SET_Register */ 240 241 /** 242 * @ingroup gpio_registers 243 * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR 244 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 245 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 246 * without affecting other bits in that register. 247 * @{ 248 */ 249 #define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ 250 #define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ 251 252 /**@} end of group GPIO_OUTEN_CLR_Register */ 253 254 /** 255 * @ingroup gpio_registers 256 * @defgroup GPIO_OUT GPIO_OUT 257 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 258 * associated port. This register can be written either directly, or by using the 259 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 260 * @{ 261 */ 262 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ 263 #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ 264 #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ 265 #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ 266 #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ 267 #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ 268 269 /**@} end of group GPIO_OUT_Register */ 270 271 /** 272 * @ingroup gpio_registers 273 * @defgroup GPIO_OUT_SET GPIO_OUT_SET 274 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 275 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 276 * register. 277 * @{ 278 */ 279 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ 280 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ 281 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ 282 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ 283 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ 284 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ 285 286 /**@} end of group GPIO_OUT_SET_Register */ 287 288 /** 289 * @ingroup gpio_registers 290 * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR 291 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 292 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 293 * that register. 294 * @{ 295 */ 296 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ 297 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ 298 299 /**@} end of group GPIO_OUT_CLR_Register */ 300 301 /** 302 * @ingroup gpio_registers 303 * @defgroup GPIO_IN GPIO_IN 304 * @brief GPIO Input Register. Read-only register to read from the logic states of the 305 * GPIO pins on this port. 306 * @{ 307 */ 308 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ 309 #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ 310 311 /**@} end of group GPIO_IN_Register */ 312 313 /** 314 * @ingroup gpio_registers 315 * @defgroup GPIO_INTMODE GPIO_INTMODE 316 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 317 * mode setting for the associated GPIO pin on this port. 318 * @{ 319 */ 320 #define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ 321 #define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ 322 #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ 323 #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ 324 #define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ 325 #define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ 326 327 /**@} end of group GPIO_INTMODE_Register */ 328 329 /** 330 * @ingroup gpio_registers 331 * @defgroup GPIO_INTPOL GPIO_INTPOL 332 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 333 * interrupt polarity setting for one GPIO pin in the associated port. 334 * @{ 335 */ 336 #define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ 337 #define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ 338 #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ 339 #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ 340 #define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ 341 #define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ 342 343 /**@} end of group GPIO_INTPOL_Register */ 344 345 /** 346 * @ingroup gpio_registers 347 * @defgroup GPIO_INTEN GPIO_INTEN 348 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 349 * interrupt enable for the associated pin on the GPIO port. 350 * @{ 351 */ 352 #define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ 353 #define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ 354 #define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ 355 #define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ 356 #define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ 357 #define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ 358 359 /**@} end of group GPIO_INTEN_Register */ 360 361 /** 362 * @ingroup gpio_registers 363 * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET 364 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 365 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 366 * in that register. 367 * @{ 368 */ 369 #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ 370 #define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ 371 #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ 372 #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ 373 #define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ 374 #define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ 375 376 /**@} end of group GPIO_INTEN_SET_Register */ 377 378 /** 379 * @ingroup gpio_registers 380 * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR 381 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 382 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 383 * other bits in that register. 384 * @{ 385 */ 386 #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ 387 #define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ 388 #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ 389 #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ 390 #define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ 391 #define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ 392 393 /**@} end of group GPIO_INTEN_CLR_Register */ 394 395 /** 396 * @ingroup gpio_registers 397 * @defgroup GPIO_INTFL GPIO_INTFL 398 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 399 * interrupt status for the associated GPIO pin in this port. 400 * @{ 401 */ 402 #define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ 403 #define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ 404 #define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ 405 #define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ 406 #define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ 407 #define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ 408 409 /**@} end of group GPIO_INTFL_Register */ 410 411 /** 412 * @ingroup gpio_registers 413 * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR 414 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 415 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 416 * in that register. 417 * @{ 418 */ 419 #define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ 420 #define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ 421 422 /**@} end of group GPIO_INTFL_CLR_Register */ 423 424 /** 425 * @ingroup gpio_registers 426 * @defgroup GPIO_WKEN GPIO_WKEN 427 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 428 * enable for the associated GPIO pin in this port. 429 * @{ 430 */ 431 #define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ 432 #define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ 433 #define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ 434 #define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ 435 #define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ 436 #define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ 437 438 /**@} end of group GPIO_WKEN_Register */ 439 440 /** 441 * @ingroup gpio_registers 442 * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET 443 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 444 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 445 * that register. 446 * @{ 447 */ 448 #define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ 449 #define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ 450 451 /**@} end of group GPIO_WKEN_SET_Register */ 452 453 /** 454 * @ingroup gpio_registers 455 * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR 456 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 457 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 458 * bits in that register. 459 * @{ 460 */ 461 #define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ 462 #define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ 463 464 /**@} end of group GPIO_WKEN_CLR_Register */ 465 466 /** 467 * @ingroup gpio_registers 468 * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE 469 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 470 * edge mode for the associated GPIO pin in this port. 471 * @{ 472 */ 473 #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ 474 #define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ 475 #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ 476 #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ 477 #define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ 478 #define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ 479 480 /**@} end of group GPIO_DUALEDGE_Register */ 481 482 /** 483 * @ingroup gpio_registers 484 * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 485 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 486 * the associated GPIO pin in this port. 487 * @{ 488 */ 489 #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ 490 #define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ 491 #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ 492 #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ 493 #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ 494 #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ 495 #define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ 496 #define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ 497 498 /**@} end of group GPIO_PADCTRL0_Register */ 499 500 /** 501 * @ingroup gpio_registers 502 * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 503 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for 504 * the associated GPIO pin in this port. 505 * @{ 506 */ 507 #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ 508 #define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ 509 #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ 510 #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ 511 #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ 512 #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ 513 #define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ 514 #define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ 515 516 /**@} end of group GPIO_PADCTRL1_Register */ 517 518 /** 519 * @ingroup gpio_registers 520 * @defgroup GPIO_EN1 GPIO_EN1 521 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 522 * between primary/secondary functions for the associated GPIO pin in this port. 523 * @{ 524 */ 525 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ 526 #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ 527 #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ 528 #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ 529 #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ 530 #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ 531 532 /**@} end of group GPIO_EN1_Register */ 533 534 /** 535 * @ingroup gpio_registers 536 * @defgroup GPIO_EN1_SET GPIO_EN1_SET 537 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 538 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 539 * bits in that register. 540 * @{ 541 */ 542 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 543 #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 544 545 /**@} end of group GPIO_EN1_SET_Register */ 546 547 /** 548 * @ingroup gpio_registers 549 * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR 550 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 551 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 552 * bits in that register. 553 * @{ 554 */ 555 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 556 #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 557 558 /**@} end of group GPIO_EN1_CLR_Register */ 559 560 /** 561 * @ingroup gpio_registers 562 * @defgroup GPIO_EN2 GPIO_EN2 563 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 564 * between primary/secondary functions for the associated GPIO pin in this port. 565 * @{ 566 */ 567 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ 568 #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ 569 #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ 570 #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ 571 #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ 572 #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ 573 574 /**@} end of group GPIO_EN2_Register */ 575 576 /** 577 * @ingroup gpio_registers 578 * @defgroup GPIO_EN2_SET GPIO_EN2_SET 579 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 580 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 581 * bits in that register. 582 * @{ 583 */ 584 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 585 #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 586 587 /**@} end of group GPIO_EN2_SET_Register */ 588 589 /** 590 * @ingroup gpio_registers 591 * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR 592 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 593 * register clears the bits in the same positions in GPIO_EN2 to 0, without 594 * affecting other bits in that register. 595 * @{ 596 */ 597 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 598 #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 599 600 /**@} end of group GPIO_EN2_CLR_Register */ 601 602 /** 603 * @ingroup gpio_registers 604 * @defgroup GPIO_EN3 GPIO_EN3 605 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 606 * between primary/secondary functions for the associated GPIO pin in this port. 607 * @{ 608 */ 609 #define MXC_F_GPIO_EN3_GPIO_EN3_POS 0 /**< EN3_GPIO_EN3 Position */ 610 #define MXC_F_GPIO_EN3_GPIO_EN3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN3_GPIO_EN3_POS)) /**< EN3_GPIO_EN3 Mask */ 611 #define MXC_V_GPIO_EN3_GPIO_EN3_PRIMARY ((uint32_t)0x0UL) /**< EN3_GPIO_EN3_PRIMARY Value */ 612 #define MXC_S_GPIO_EN3_GPIO_EN3_PRIMARY (MXC_V_GPIO_EN3_GPIO_EN3_PRIMARY << MXC_F_GPIO_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_PRIMARY Setting */ 613 #define MXC_V_GPIO_EN3_GPIO_EN3_SECONDARY ((uint32_t)0x1UL) /**< EN3_GPIO_EN3_SECONDARY Value */ 614 #define MXC_S_GPIO_EN3_GPIO_EN3_SECONDARY (MXC_V_GPIO_EN3_GPIO_EN3_SECONDARY << MXC_F_GPIO_EN3_GPIO_EN3_POS) /**< EN3_GPIO_EN3_SECONDARY Setting */ 615 616 /**@} end of group GPIO_EN3_Register */ 617 618 /** 619 * @ingroup gpio_registers 620 * @defgroup GPIO_EN3_SET GPIO_EN3_SET 621 * @brief GPIO Alternate Function 3 Set. Writing a 1 to one or more bits in this register 622 * sets the bits in the same positions in GPIO_EN3 to 1, without affecting other 623 * bits in that register. 624 * @{ 625 */ 626 #define MXC_F_GPIO_EN3_SET_ALL_POS 0 /**< EN3_SET_ALL Position */ 627 #define MXC_F_GPIO_EN3_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN3_SET_ALL_POS)) /**< EN3_SET_ALL Mask */ 628 629 /**@} end of group GPIO_EN3_SET_Register */ 630 631 /** 632 * @ingroup gpio_registers 633 * @defgroup GPIO_EN3_CLR GPIO_EN3_CLR 634 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 635 * register clears the bits in the same positions in GPIO_EN3 to 0, without 636 * affecting other bits in that register. 637 * @{ 638 */ 639 #define MXC_F_GPIO_EN3_CLR_ALL_POS 0 /**< EN3_CLR_ALL Position */ 640 #define MXC_F_GPIO_EN3_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN3_CLR_ALL_POS)) /**< EN3_CLR_ALL Mask */ 641 642 /**@} end of group GPIO_EN3_CLR_Register */ 643 644 /** 645 * @ingroup gpio_registers 646 * @defgroup GPIO_HYSEN GPIO_HYSEN 647 * @brief GPIO Input Hysteresis Enable. 648 * @{ 649 */ 650 #define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ 651 #define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ 652 653 /**@} end of group GPIO_HYSEN_Register */ 654 655 /** 656 * @ingroup gpio_registers 657 * @defgroup GPIO_SRSEL GPIO_SRSEL 658 * @brief GPIO Slew Rate Enable Register. 659 * @{ 660 */ 661 #define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ 662 #define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ 663 #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ 664 #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ 665 #define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ 666 #define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ 667 668 /**@} end of group GPIO_SRSEL_Register */ 669 670 /** 671 * @ingroup gpio_registers 672 * @defgroup GPIO_DS0 GPIO_DS0 673 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive 674 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 675 * sink/source current of GPIO pins in each mode. 676 * @{ 677 */ 678 #define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ 679 #define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ 680 #define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ 681 #define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ 682 #define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ 683 #define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ 684 685 /**@} end of group GPIO_DS0_Register */ 686 687 /** 688 * @ingroup gpio_registers 689 * @defgroup GPIO_DS1 GPIO_DS1 690 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 691 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 692 * sink/source current of GPIO pins in each mode. 693 * @{ 694 */ 695 #define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ 696 #define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ 697 698 /**@} end of group GPIO_DS1_Register */ 699 700 /** 701 * @ingroup gpio_registers 702 * @defgroup GPIO_PS GPIO_PS 703 * @brief GPIO Pull Select Mode. 704 * @{ 705 */ 706 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ 707 #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ 708 709 /**@} end of group GPIO_PS_Register */ 710 711 /** 712 * @ingroup gpio_registers 713 * @defgroup GPIO_VSSEL GPIO_VSSEL 714 * @brief GPIO Voltage Select. 715 * @{ 716 */ 717 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ 718 #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ 719 720 /**@} end of group GPIO_VSSEL_Register */ 721 722 #ifdef __cplusplus 723 } 724 #endif 725 726 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_GPIO_REGS_H_ 727
