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Searched refs:cipher_ctrl (Results 1 – 13 of 13) sorted by relevance

/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/CTB/
Dctb_reva.c188 if (ctb_regs->cipher_ctrl) { // set flag if only configured in MXC_CTB_RevA_Done()
926 MXC_SETFIELD(ctb_regs->cipher_ctrl, MXC_F_CTB_REVA_CIPHER_CTRL_MODE, in MXC_CTB_RevA_Cipher_SetMode()
932 return (mxc_ctb_reva_cipher_mode_t)((ctb_regs->cipher_ctrl & MXC_F_CTB_REVA_CIPHER_CTRL_MODE) >> in MXC_CTB_RevA_Cipher_GetMode()
938 MXC_SETFIELD(ctb_regs->cipher_ctrl, MXC_F_CTB_REVA_CIPHER_CTRL_CIPHER, in MXC_CTB_RevA_Cipher_SetCipher()
944 return (mxc_ctb_reva_cipher_t)((ctb_regs->cipher_ctrl & MXC_F_CTB_REVA_CIPHER_CTRL_CIPHER) >> in MXC_CTB_RevA_Cipher_GetCipher()
951 MXC_SETFIELD(ctb_regs->cipher_ctrl, MXC_F_CTB_REVA_CIPHER_CTRL_SRC, in MXC_CTB_RevA_Cipher_SetKeySource()
957 return (mxc_ctb_reva_cipher_key_t)((ctb_regs->cipher_ctrl & MXC_F_CTB_REVA_CIPHER_CTRL_SRC) >> in MXC_CTB_RevA_Cipher_GetKeySource()
968 ctb_regs->cipher_ctrl |= MXC_F_CTB_REVA_CIPHER_CTRL_KEY; in MXC_CTB_RevA_Cipher_LoadKey()
974 MXC_SETFIELD(ctb_regs->cipher_ctrl, MXC_F_CTB_REVA_CIPHER_CTRL_ENC, in MXC_CTB_RevA_Cipher_SetOperation()
Dctb_reva_regs.h76 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/TPU/
Dtpu_reva.c238 tpu->cipher_ctrl &= ~MXC_F_TPU_REVA_CIPHER_CTRL_ENC; in MXC_TPU_RevA_Cipher_EncDecSelect()
240 tpu->cipher_ctrl |= MXC_F_TPU_REVA_CIPHER_CTRL_ENC; in MXC_TPU_RevA_Cipher_EncDecSelect()
254 tpu->cipher_ctrl = (mode << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS) | in MXC_TPU_RevA_Cipher_Config()
264 MXC_SETFIELD(tpu->cipher_ctrl, MXC_F_TPU_REVA_CIPHER_CTRL_SRC, key_src); in MXC_TPU_RevA_Cipher_KeySelect()
275 uint32_t key_src = tpu->cipher_ctrl & MXC_F_TPU_REVA_CIPHER_CTRL_SRC; in MXC_TPU_RevA_Cipher_DoOperation()
Dtpu_reva_regs.h76 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> TPU_REVA CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/FLC/
Dflc_es17.c436 MXC_CTB->cipher_ctrl = in mxc_encrypt_sequence()
441 MXC_CTB->cipher_ctrl = ((MXC_CTB->cipher_ctrl & ~MXC_F_CTB_CIPHER_CTRL_SRC) | in mxc_encrypt_sequence()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SYS/
Dsys_me18.c118 MXC_CTB->cipher_ctrl = MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY; in MXC_SYS_GetUSN()
121 MXC_CTB->cipher_ctrl |= MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128; in MXC_SYS_GetUSN()
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/
Dtpu_regs.h78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> TPU CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/
Dctb_regs.h78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/
Dctb_regs.h78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Include/
Dctb_regs.h78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Include/
Dctb_regs.h78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Include/
Dctb_regs.h77 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Include/
Dtpu_regs.h78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> TPU CIPHER_CTRL Register */ member