1 /** 2 * @file ctb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ctb_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_CTB_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_CTB_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ctb 67 * @defgroup ctb_registers CTB_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 69 * @details The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 70 */ 71 72 /** 73 * @ingroup ctb_registers 74 * Structure type to access the CTB Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> CTB CTRL Register */ 78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ 79 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> CTB HASH_CTRL Register */ 80 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> CTB CRC_CTRL Register */ 81 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> CTB DMA_SRC Register */ 82 __IO uint32_t dma_dest; /**< <tt>\b 0x14:</tt> CTB DMA_DEST Register */ 83 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> CTB DMA_CNT Register */ 84 __IO uint32_t maa_ctrl; /**< <tt>\b 0x1C:</tt> CTB MAA_CTRL Register */ 85 __O uint32_t din[4]; /**< <tt>\b 0x20:</tt> CTB DIN Register */ 86 __I uint32_t dout[4]; /**< <tt>\b 0x30:</tt> CTB DOUT Register */ 87 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> CTB CRC_POLY Register */ 88 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> CTB CRC_VAL Register */ 89 __IO uint32_t crc_prng; /**< <tt>\b 0x48:</tt> CTB CRC_PRNG Register */ 90 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> CTB HAM_ECC Register */ 91 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> CTB CIPHER_INIT Register */ 92 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> CTB CIPHER_KEY Register */ 93 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> CTB HASH_DIGEST Register */ 94 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> CTB HASH_MSG_SZ Register */ 95 union { 96 __IO uint32_t maa_maws; /**< <tt>\b 0xD0:</tt> CTB MAA_MAWS Register */ 97 __IO uint32_t aad_length[2]; /**< <tt>\b 0xD0:</tt> CTB AAD_LENGTH Register */ 98 }; 99 __IO uint32_t pld_length[2]; /**< <tt>\b 0xD8:</tt> CTB PLD_LENGTH Register */ 100 __IO uint32_t tagmic[4]; /**< <tt>\b 0xE0:</tt> CTB TAGMIC Register */ 101 } mxc_ctb_regs_t; 102 103 /* Register offsets for module CTB */ 104 /** 105 * @ingroup ctb_registers 106 * @defgroup CTB_Register_Offsets Register Offsets 107 * @brief CTB Peripheral Register Offsets from the CTB Base Peripheral Address. 108 * @{ 109 */ 110 #define MXC_R_CTB_CTRL ((uint32_t)0x00000000UL) /**< Offset from CTB Base Address: <tt> 0x0000</tt> */ 111 #define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from CTB Base Address: <tt> 0x0004</tt> */ 112 #define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from CTB Base Address: <tt> 0x0008</tt> */ 113 #define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from CTB Base Address: <tt> 0x000C</tt> */ 114 #define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from CTB Base Address: <tt> 0x0010</tt> */ 115 #define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from CTB Base Address: <tt> 0x0014</tt> */ 116 #define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from CTB Base Address: <tt> 0x0018</tt> */ 117 #define MXC_R_CTB_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from CTB Base Address: <tt> 0x001C</tt> */ 118 #define MXC_R_CTB_DIN ((uint32_t)0x00000020UL) /**< Offset from CTB Base Address: <tt> 0x0020</tt> */ 119 #define MXC_R_CTB_DOUT ((uint32_t)0x00000030UL) /**< Offset from CTB Base Address: <tt> 0x0030</tt> */ 120 #define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from CTB Base Address: <tt> 0x0040</tt> */ 121 #define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from CTB Base Address: <tt> 0x0044</tt> */ 122 #define MXC_R_CTB_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from CTB Base Address: <tt> 0x0048</tt> */ 123 #define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from CTB Base Address: <tt> 0x004C</tt> */ 124 #define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from CTB Base Address: <tt> 0x0050</tt> */ 125 #define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from CTB Base Address: <tt> 0x0060</tt> */ 126 #define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from CTB Base Address: <tt> 0x0080</tt> */ 127 #define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from CTB Base Address: <tt> 0x00C0</tt> */ 128 #define MXC_R_CTB_MAA_MAWS ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: <tt> 0x00D0</tt> */ 129 #define MXC_R_CTB_AAD_LENGTH ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: <tt> 0x00D0</tt> */ 130 #define MXC_R_CTB_PLD_LENGTH ((uint32_t)0x000000D8UL) /**< Offset from CTB Base Address: <tt> 0x00D8</tt> */ 131 #define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL) /**< Offset from CTB Base Address: <tt> 0x00E0</tt> */ 132 /**@} end of group ctb_registers */ 133 134 /** 135 * @ingroup ctb_registers 136 * @defgroup CTB_CTRL CTB_CTRL 137 * @brief Crypto Control Register. 138 * @{ 139 */ 140 #define MXC_F_CTB_CTRL_RST_POS 0 /**< CTRL_RST Position */ 141 #define MXC_F_CTB_CTRL_RST ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_RST_POS)) /**< CTRL_RST Mask */ 142 143 #define MXC_F_CTB_CTRL_INTR_POS 1 /**< CTRL_INTR Position */ 144 #define MXC_F_CTB_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_INTR_POS)) /**< CTRL_INTR Mask */ 145 146 #define MXC_F_CTB_CTRL_SRC_POS 2 /**< CTRL_SRC Position */ 147 #define MXC_F_CTB_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_SRC_POS)) /**< CTRL_SRC Mask */ 148 149 #define MXC_F_CTB_CTRL_BSO_POS 4 /**< CTRL_BSO Position */ 150 #define MXC_F_CTB_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_BSO_POS)) /**< CTRL_BSO Mask */ 151 152 #define MXC_F_CTB_CTRL_BSI_POS 5 /**< CTRL_BSI Position */ 153 #define MXC_F_CTB_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_BSI_POS)) /**< CTRL_BSI Mask */ 154 155 #define MXC_F_CTB_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */ 156 #define MXC_F_CTB_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */ 157 158 #define MXC_F_CTB_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */ 159 #define MXC_F_CTB_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */ 160 161 #define MXC_F_CTB_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */ 162 #define MXC_F_CTB_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_CTB_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */ 163 #define MXC_V_CTB_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */ 164 #define MXC_S_CTB_CTRL_WRSRC_NONE (MXC_V_CTB_CTRL_WRSRC_NONE << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */ 165 #define MXC_V_CTB_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */ 166 #define MXC_S_CTB_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_CTB_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */ 167 #define MXC_V_CTB_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */ 168 #define MXC_S_CTB_CTRL_WRSRC_READFIFO (MXC_V_CTB_CTRL_WRSRC_READFIFO << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */ 169 170 #define MXC_F_CTB_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */ 171 #define MXC_F_CTB_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_CTB_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */ 172 #define MXC_V_CTB_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */ 173 #define MXC_S_CTB_CTRL_RDSRC_DMADISABLED (MXC_V_CTB_CTRL_RDSRC_DMADISABLED << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */ 174 #define MXC_V_CTB_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */ 175 #define MXC_S_CTB_CTRL_RDSRC_DMAORAPB (MXC_V_CTB_CTRL_RDSRC_DMAORAPB << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */ 176 #define MXC_V_CTB_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */ 177 #define MXC_S_CTB_CTRL_RDSRC_RNG (MXC_V_CTB_CTRL_RDSRC_RNG << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */ 178 179 #define MXC_F_CTB_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */ 180 #define MXC_F_CTB_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */ 181 182 #define MXC_F_CTB_CTRL_DMADNEMSK_POS 15 /**< CTRL_DMADNEMSK Position */ 183 #define MXC_F_CTB_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DMADNEMSK_POS)) /**< CTRL_DMADNEMSK Mask */ 184 185 #define MXC_F_CTB_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */ 186 #define MXC_F_CTB_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */ 187 188 #define MXC_F_CTB_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */ 189 #define MXC_F_CTB_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */ 190 191 #define MXC_F_CTB_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */ 192 #define MXC_F_CTB_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */ 193 194 #define MXC_F_CTB_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */ 195 #define MXC_F_CTB_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */ 196 197 #define MXC_F_CTB_CTRL_ERR_POS 29 /**< CTRL_ERR Position */ 198 #define MXC_F_CTB_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_ERR_POS)) /**< CTRL_ERR Mask */ 199 200 #define MXC_F_CTB_CTRL_RDY_POS 30 /**< CTRL_RDY Position */ 201 #define MXC_F_CTB_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 202 203 #define MXC_F_CTB_CTRL_DONE_POS 31 /**< CTRL_DONE Position */ 204 #define MXC_F_CTB_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DONE_POS)) /**< CTRL_DONE Mask */ 205 206 /**@} end of group CTB_CTRL_Register */ 207 208 /** 209 * @ingroup ctb_registers 210 * @defgroup CTB_CIPHER_CTRL CTB_CIPHER_CTRL 211 * @brief Cipher Control Register. 212 * @{ 213 */ 214 #define MXC_F_CTB_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 215 #define MXC_F_CTB_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 216 217 #define MXC_F_CTB_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 218 #define MXC_F_CTB_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 219 220 #define MXC_F_CTB_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 221 #define MXC_F_CTB_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_CTB_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 222 #define MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 223 #define MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 224 #define MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 225 #define MXC_S_CTB_CIPHER_CTRL_SRC_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 226 #define MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 227 #define MXC_S_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 228 229 #define MXC_F_CTB_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 230 #define MXC_F_CTB_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 231 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 232 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DIS (MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 233 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 234 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 235 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 236 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES192 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 237 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 238 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES256 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 239 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 240 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DES (MXC_V_CTB_CIPHER_CTRL_CIPHER_DES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 241 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 242 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_TDES (MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 243 244 #define MXC_F_CTB_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 245 #define MXC_F_CTB_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 246 #define MXC_V_CTB_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 247 #define MXC_S_CTB_CIPHER_CTRL_MODE_ECB (MXC_V_CTB_CIPHER_CTRL_MODE_ECB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 248 #define MXC_V_CTB_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 249 #define MXC_S_CTB_CIPHER_CTRL_MODE_CBC (MXC_V_CTB_CIPHER_CTRL_MODE_CBC << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 250 #define MXC_V_CTB_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 251 #define MXC_S_CTB_CIPHER_CTRL_MODE_CFB (MXC_V_CTB_CIPHER_CTRL_MODE_CFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 252 #define MXC_V_CTB_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 253 #define MXC_S_CTB_CIPHER_CTRL_MODE_OFB (MXC_V_CTB_CIPHER_CTRL_MODE_OFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 254 #define MXC_V_CTB_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 255 #define MXC_S_CTB_CIPHER_CTRL_MODE_CTR (MXC_V_CTB_CIPHER_CTRL_MODE_CTR << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 256 #define MXC_V_CTB_CIPHER_CTRL_MODE_GCM ((uint32_t)0x5UL) /**< CIPHER_CTRL_MODE_GCM Value */ 257 #define MXC_S_CTB_CIPHER_CTRL_MODE_GCM (MXC_V_CTB_CIPHER_CTRL_MODE_GCM << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_GCM Setting */ 258 #define MXC_V_CTB_CIPHER_CTRL_MODE_CCM ((uint32_t)0x6UL) /**< CIPHER_CTRL_MODE_CCM Value */ 259 #define MXC_S_CTB_CIPHER_CTRL_MODE_CCM (MXC_V_CTB_CIPHER_CTRL_MODE_CCM << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CCM Setting */ 260 261 #define MXC_F_CTB_CIPHER_CTRL_HVC_POS 11 /**< CIPHER_CTRL_HVC Position */ 262 #define MXC_F_CTB_CIPHER_CTRL_HVC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_HVC_POS)) /**< CIPHER_CTRL_HVC Mask */ 263 264 #define MXC_F_CTB_CIPHER_CTRL_DTYPE_POS 12 /**< CIPHER_CTRL_DTYPE Position */ 265 #define MXC_F_CTB_CIPHER_CTRL_DTYPE ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_DTYPE_POS)) /**< CIPHER_CTRL_DTYPE Mask */ 266 267 #define MXC_F_CTB_CIPHER_CTRL_CCMM_POS 13 /**< CIPHER_CTRL_CCMM Position */ 268 #define MXC_F_CTB_CIPHER_CTRL_CCMM ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCMM_POS)) /**< CIPHER_CTRL_CCMM Mask */ 269 #define MXC_V_CTB_CIPHER_CTRL_CCMM_4 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CCMM_4 Value */ 270 #define MXC_S_CTB_CIPHER_CTRL_CCMM_4 (MXC_V_CTB_CIPHER_CTRL_CCMM_4 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_4 Setting */ 271 #define MXC_V_CTB_CIPHER_CTRL_CCMM_6 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CCMM_6 Value */ 272 #define MXC_S_CTB_CIPHER_CTRL_CCMM_6 (MXC_V_CTB_CIPHER_CTRL_CCMM_6 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_6 Setting */ 273 #define MXC_V_CTB_CIPHER_CTRL_CCMM_8 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CCMM_8 Value */ 274 #define MXC_S_CTB_CIPHER_CTRL_CCMM_8 (MXC_V_CTB_CIPHER_CTRL_CCMM_8 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_8 Setting */ 275 #define MXC_V_CTB_CIPHER_CTRL_CCMM_10 ((uint32_t)0x4UL) /**< CIPHER_CTRL_CCMM_10 Value */ 276 #define MXC_S_CTB_CIPHER_CTRL_CCMM_10 (MXC_V_CTB_CIPHER_CTRL_CCMM_10 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_10 Setting */ 277 #define MXC_V_CTB_CIPHER_CTRL_CCMM_12 ((uint32_t)0x5UL) /**< CIPHER_CTRL_CCMM_12 Value */ 278 #define MXC_S_CTB_CIPHER_CTRL_CCMM_12 (MXC_V_CTB_CIPHER_CTRL_CCMM_12 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_12 Setting */ 279 #define MXC_V_CTB_CIPHER_CTRL_CCMM_14 ((uint32_t)0x6UL) /**< CIPHER_CTRL_CCMM_14 Value */ 280 #define MXC_S_CTB_CIPHER_CTRL_CCMM_14 (MXC_V_CTB_CIPHER_CTRL_CCMM_14 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_14 Setting */ 281 #define MXC_V_CTB_CIPHER_CTRL_CCMM_16 ((uint32_t)0x7UL) /**< CIPHER_CTRL_CCMM_16 Value */ 282 #define MXC_S_CTB_CIPHER_CTRL_CCMM_16 (MXC_V_CTB_CIPHER_CTRL_CCMM_16 << MXC_F_CTB_CIPHER_CTRL_CCMM_POS) /**< CIPHER_CTRL_CCMM_16 Setting */ 283 284 #define MXC_F_CTB_CIPHER_CTRL_CCML_POS 16 /**< CIPHER_CTRL_CCML Position */ 285 #define MXC_F_CTB_CIPHER_CTRL_CCML ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCML_POS)) /**< CIPHER_CTRL_CCML Mask */ 286 #define MXC_V_CTB_CIPHER_CTRL_CCML_2 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CCML_2 Value */ 287 #define MXC_S_CTB_CIPHER_CTRL_CCML_2 (MXC_V_CTB_CIPHER_CTRL_CCML_2 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_2 Setting */ 288 #define MXC_V_CTB_CIPHER_CTRL_CCML_3 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CCML_3 Value */ 289 #define MXC_S_CTB_CIPHER_CTRL_CCML_3 (MXC_V_CTB_CIPHER_CTRL_CCML_3 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_3 Setting */ 290 #define MXC_V_CTB_CIPHER_CTRL_CCML_4 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CCML_4 Value */ 291 #define MXC_S_CTB_CIPHER_CTRL_CCML_4 (MXC_V_CTB_CIPHER_CTRL_CCML_4 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_4 Setting */ 292 #define MXC_V_CTB_CIPHER_CTRL_CCML_5 ((uint32_t)0x4UL) /**< CIPHER_CTRL_CCML_5 Value */ 293 #define MXC_S_CTB_CIPHER_CTRL_CCML_5 (MXC_V_CTB_CIPHER_CTRL_CCML_5 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_5 Setting */ 294 #define MXC_V_CTB_CIPHER_CTRL_CCML_6 ((uint32_t)0x5UL) /**< CIPHER_CTRL_CCML_6 Value */ 295 #define MXC_S_CTB_CIPHER_CTRL_CCML_6 (MXC_V_CTB_CIPHER_CTRL_CCML_6 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_6 Setting */ 296 #define MXC_V_CTB_CIPHER_CTRL_CCML_7 ((uint32_t)0x6UL) /**< CIPHER_CTRL_CCML_7 Value */ 297 #define MXC_S_CTB_CIPHER_CTRL_CCML_7 (MXC_V_CTB_CIPHER_CTRL_CCML_7 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_7 Setting */ 298 #define MXC_V_CTB_CIPHER_CTRL_CCML_8 ((uint32_t)0x7UL) /**< CIPHER_CTRL_CCML_8 Value */ 299 #define MXC_S_CTB_CIPHER_CTRL_CCML_8 (MXC_V_CTB_CIPHER_CTRL_CCML_8 << MXC_F_CTB_CIPHER_CTRL_CCML_POS) /**< CIPHER_CTRL_CCML_8 Setting */ 300 301 /**@} end of group CTB_CIPHER_CTRL_Register */ 302 303 /** 304 * @ingroup ctb_registers 305 * @defgroup CTB_HASH_CTRL CTB_HASH_CTRL 306 * @brief HASH Control Register. 307 * @{ 308 */ 309 #define MXC_F_CTB_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 310 #define MXC_F_CTB_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 311 312 #define MXC_F_CTB_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 313 #define MXC_F_CTB_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 314 315 #define MXC_F_CTB_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 316 #define MXC_F_CTB_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_CTB_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 317 #define MXC_V_CTB_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 318 #define MXC_S_CTB_HASH_CTRL_HASH_DIS (MXC_V_CTB_HASH_CTRL_HASH_DIS << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 319 #define MXC_V_CTB_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 320 #define MXC_S_CTB_HASH_CTRL_HASH_SHA1 (MXC_V_CTB_HASH_CTRL_HASH_SHA1 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 321 #define MXC_V_CTB_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 322 #define MXC_S_CTB_HASH_CTRL_HASH_SHA224 (MXC_V_CTB_HASH_CTRL_HASH_SHA224 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 323 #define MXC_V_CTB_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 324 #define MXC_S_CTB_HASH_CTRL_HASH_SHA256 (MXC_V_CTB_HASH_CTRL_HASH_SHA256 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 325 #define MXC_V_CTB_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 326 #define MXC_S_CTB_HASH_CTRL_HASH_SHA384 (MXC_V_CTB_HASH_CTRL_HASH_SHA384 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 327 #define MXC_V_CTB_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 328 #define MXC_S_CTB_HASH_CTRL_HASH_SHA512 (MXC_V_CTB_HASH_CTRL_HASH_SHA512 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 329 330 #define MXC_F_CTB_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 331 #define MXC_F_CTB_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 332 333 /**@} end of group CTB_HASH_CTRL_Register */ 334 335 /** 336 * @ingroup ctb_registers 337 * @defgroup CTB_CRC_CTRL CTB_CRC_CTRL 338 * @brief CRC Control Register. 339 * @{ 340 */ 341 #define MXC_F_CTB_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */ 342 #define MXC_F_CTB_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */ 343 344 #define MXC_F_CTB_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 345 #define MXC_F_CTB_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 346 347 #define MXC_F_CTB_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 348 #define MXC_F_CTB_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 349 350 #define MXC_F_CTB_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 351 #define MXC_F_CTB_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 352 353 #define MXC_F_CTB_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 354 #define MXC_F_CTB_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 355 356 #define MXC_F_CTB_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 357 #define MXC_F_CTB_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 358 359 /**@} end of group CTB_CRC_CTRL_Register */ 360 361 /** 362 * @ingroup ctb_registers 363 * @defgroup CTB_DMA_SRC CTB_DMA_SRC 364 * @brief Crypto DMA Source Address. 365 * @{ 366 */ 367 #define MXC_F_CTB_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ 368 #define MXC_F_CTB_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ 369 370 /**@} end of group CTB_DMA_SRC_Register */ 371 372 /** 373 * @ingroup ctb_registers 374 * @defgroup CTB_DMA_DEST CTB_DMA_DEST 375 * @brief Crypto DMA Destination Address. 376 * @{ 377 */ 378 #define MXC_F_CTB_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ 379 #define MXC_F_CTB_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ 380 381 /**@} end of group CTB_DMA_DEST_Register */ 382 383 /** 384 * @ingroup ctb_registers 385 * @defgroup CTB_DMA_CNT CTB_DMA_CNT 386 * @brief Crypto DMA Byte Count. 387 * @{ 388 */ 389 #define MXC_F_CTB_DMA_CNT_ADDR_POS 0 /**< DMA_CNT_ADDR Position */ 390 #define MXC_F_CTB_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */ 391 392 /**@} end of group CTB_DMA_CNT_Register */ 393 394 /** 395 * @ingroup ctb_registers 396 * @defgroup CTB_DIN CTB_DIN 397 * @brief Crypto Data Input. Data input can be written to this register instead of using 398 * the DMA. This register writes to the FIFO. This register occupies four 399 * successive words to allow the use of multi-store instructions. Words can be 400 * written to any location, they will be placed in the FIFO in the order they are 401 * written. The endian swap input control bit affects this register. 402 * @{ 403 */ 404 #define MXC_F_CTB_DIN_DATA_POS 0 /**< DIN_DATA Position */ 405 #define MXC_F_CTB_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DIN_DATA_POS)) /**< DIN_DATA Mask */ 406 407 /**@} end of group CTB_DIN_Register */ 408 409 /** 410 * @ingroup ctb_registers 411 * @defgroup CTB_DOUT CTB_DOUT 412 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 413 * the lower words of these four registers depending on the algorithm. For block 414 * cipher modes, this register holds the result of most recent encryption or 415 * decryption operation. These registers are affected by the endian swap bits. 416 * @{ 417 */ 418 #define MXC_F_CTB_DOUT_DATA_POS 0 /**< DOUT_DATA Position */ 419 #define MXC_F_CTB_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DOUT_DATA_POS)) /**< DOUT_DATA Mask */ 420 421 /**@} end of group CTB_DOUT_Register */ 422 423 /** 424 * @ingroup ctb_registers 425 * @defgroup CTB_CRC_POLY CTB_CRC_POLY 426 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 427 * LFSR) should be written to this register. This register is affected by the MSB 428 * control bit. 429 * @{ 430 */ 431 #define MXC_F_CTB_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */ 432 #define MXC_F_CTB_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */ 433 434 /**@} end of group CTB_CRC_POLY_Register */ 435 436 /** 437 * @ingroup ctb_registers 438 * @defgroup CTB_CRC_VAL CTB_CRC_VAL 439 * @brief CRC Value. This is the state for the Galois Field. This register holds the 440 * result of a CRC calculation or the current state of the LFSR. This register is 441 * affected by the MSB control bit. 442 * @{ 443 */ 444 #define MXC_F_CTB_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 445 #define MXC_F_CTB_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 446 447 /**@} end of group CTB_CRC_VAL_Register */ 448 449 /** 450 * @ingroup ctb_registers 451 * @defgroup CTB_CRC_PRNG CTB_CRC_PRNG 452 * @brief CRC PRNG Register. 453 * @{ 454 */ 455 #define MXC_F_CTB_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ 456 #define MXC_F_CTB_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ 457 458 /**@} end of group CTB_CRC_PRNG_Register */ 459 460 /** 461 * @ingroup ctb_registers 462 * @defgroup CTB_HAM_ECC CTB_HAM_ECC 463 * @brief Hamming ECC Register. 464 * @{ 465 */ 466 #define MXC_F_CTB_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 467 #define MXC_F_CTB_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_CTB_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 468 469 #define MXC_F_CTB_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 470 #define MXC_F_CTB_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_CTB_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 471 472 /**@} end of group CTB_HAM_ECC_Register */ 473 474 /** 475 * @ingroup ctb_registers 476 * @defgroup CTB_CIPHER_INIT CTB_CIPHER_INIT 477 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 478 * modes, this register holds the initial value. This register is updated with each 479 * encryption or decryption operation. This register is affected by the endian swap 480 * bits. 481 * @{ 482 */ 483 #define MXC_F_CTB_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 484 #define MXC_F_CTB_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 485 486 /**@} end of group CTB_CIPHER_INIT_Register */ 487 488 /** 489 * @ingroup ctb_registers 490 * @defgroup CTB_CIPHER_KEY CTB_CIPHER_KEY 491 * @brief Cipher Key. This register holds the key used for block cipher operations. The 492 * lower words are used for block ciphers that use shorter key lengths. This 493 * register is affected by the endian swap input control bits. 494 * @{ 495 */ 496 #define MXC_F_CTB_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 497 #define MXC_F_CTB_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 498 499 /**@} end of group CTB_CIPHER_KEY_Register */ 500 501 /** 502 * @ingroup ctb_registers 503 * @defgroup CTB_HASH_DIGEST CTB_HASH_DIGEST 504 * @brief This register holds the calculated hash value. This register is affected by the 505 * endian swap bits. 506 * @{ 507 */ 508 #define MXC_F_CTB_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 509 #define MXC_F_CTB_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 510 511 /**@} end of group CTB_HASH_DIGEST_Register */ 512 513 /** 514 * @ingroup ctb_registers 515 * @defgroup CTB_HASH_MSG_SZ CTB_HASH_MSG_SZ 516 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 517 * @{ 518 */ 519 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 520 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 521 522 /**@} end of group CTB_HASH_MSG_SZ_Register */ 523 524 /** 525 * @ingroup ctb_registers 526 * @defgroup CTB_MAA_MAWS CTB_MAA_MAWS 527 * @brief MAA Word Size Register. 528 * @{ 529 */ 530 #define MXC_F_CTB_MAA_MAWS_SIZE_POS 0 /**< MAA_MAWS_SIZE Position */ 531 #define MXC_F_CTB_MAA_MAWS_SIZE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_MAA_MAWS_SIZE_POS)) /**< MAA_MAWS_SIZE Mask */ 532 533 /**@} end of group CTB_MAA_MAWS_Register */ 534 535 /** 536 * @ingroup ctb_registers 537 * @defgroup CTB_AAD_LENGTH CTB_AAD_LENGTH 538 * @brief AAD Length Registers. 539 * @{ 540 */ 541 #define MXC_F_CTB_AAD_LENGTH_LENGTH_POS 0 /**< AAD_LENGTH_LENGTH Position */ 542 #define MXC_F_CTB_AAD_LENGTH_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_AAD_LENGTH_LENGTH_POS)) /**< AAD_LENGTH_LENGTH Mask */ 543 544 /**@} end of group CTB_AAD_LENGTH_Register */ 545 546 /** 547 * @ingroup ctb_registers 548 * @defgroup CTB_PLD_LENGTH CTB_PLD_LENGTH 549 * @brief PLD Length Registers. 550 * @{ 551 */ 552 #define MXC_F_CTB_PLD_LENGTH_LENGTH_POS 0 /**< PLD_LENGTH_LENGTH Position */ 553 #define MXC_F_CTB_PLD_LENGTH_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_LENGTH_POS)) /**< PLD_LENGTH_LENGTH Mask */ 554 555 /**@} end of group CTB_PLD_LENGTH_Register */ 556 557 /** 558 * @ingroup ctb_registers 559 * @defgroup CTB_TAGMIC CTB_TAGMIC 560 * @brief TAG/MIC Registers. 561 * @{ 562 */ 563 #define MXC_F_CTB_TAGMIC_LENGTH_POS 0 /**< TAGMIC_LENGTH Position */ 564 #define MXC_F_CTB_TAGMIC_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_TAGMIC_LENGTH_POS)) /**< TAGMIC_LENGTH Mask */ 565 566 /**@} end of group CTB_TAGMIC_Register */ 567 568 #ifdef __cplusplus 569 } 570 #endif 571 572 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_CTB_REGS_H_ 573
