1 /** 2 * @file ctb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ctb_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_CTB_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_CTB_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ctb 67 * @defgroup ctb_registers CTB_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 69 * @details The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 70 */ 71 72 /** 73 * @ingroup ctb_registers 74 * Structure type to access the CTB Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> CTB CTRL Register */ 78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ 79 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> CTB HASH_CTRL Register */ 80 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> CTB CRC_CTRL Register */ 81 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> CTB DMA_SRC Register */ 82 __IO uint32_t dma_dest; /**< <tt>\b 0x14:</tt> CTB DMA_DEST Register */ 83 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> CTB DMA_CNT Register */ 84 __R uint32_t rsv_0x1c; 85 __O uint32_t din[4]; /**< <tt>\b 0x20:</tt> CTB DIN Register */ 86 __I uint32_t dout[4]; /**< <tt>\b 0x30:</tt> CTB DOUT Register */ 87 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> CTB CRC_POLY Register */ 88 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> CTB CRC_VAL Register */ 89 __R uint32_t rsv_0x48; 90 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> CTB HAM_ECC Register */ 91 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> CTB CIPHER_INIT Register */ 92 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> CTB CIPHER_KEY Register */ 93 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> CTB HASH_DIGEST Register */ 94 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> CTB HASH_MSG_SZ Register */ 95 __IO uint32_t aad_length[2]; /**< <tt>\b 0xD0:</tt> CTB AAD_LENGTH Register */ 96 __IO uint32_t pld_length[2]; /**< <tt>\b 0xD8:</tt> CTB PLD_LENGTH Register */ 97 __IO uint32_t tagmic[4]; /**< <tt>\b 0xE0:</tt> CTB TAGMIC Register */ 98 __R uint32_t rsv_0xf0_0xff[4]; 99 __IO uint32_t sca_ctrl0; /**< <tt>\b 0x100:</tt> CTB SCA_CTRL0 Register */ 100 __IO uint32_t sca_ctrl1; /**< <tt>\b 0x104:</tt> CTB SCA_CTRL1 Register */ 101 __IO uint32_t sca_stat; /**< <tt>\b 0x108:</tt> CTB SCA_STAT Register */ 102 __IO uint32_t sca_ppx_addr; /**< <tt>\b 0x10C:</tt> CTB SCA_PPX_ADDR Register */ 103 __IO uint32_t sca_ppy_addr; /**< <tt>\b 0x110:</tt> CTB SCA_PPY_ADDR Register */ 104 __IO uint32_t sca_ppz_addr; /**< <tt>\b 0x114:</tt> CTB SCA_PPZ_ADDR Register */ 105 __IO uint32_t sca_pqx_addr; /**< <tt>\b 0x118:</tt> CTB SCA_PQX_ADDR Register */ 106 __IO uint32_t sca_pqy_addr; /**< <tt>\b 0x11C:</tt> CTB SCA_PQY_ADDR Register */ 107 __IO uint32_t sca_pqz_addr; /**< <tt>\b 0x120:</tt> CTB SCA_PQZ_ADDR Register */ 108 __IO uint32_t sca_rdsa_addr; /**< <tt>\b 0x124:</tt> CTB SCA_RDSA_ADDR Register */ 109 __IO uint32_t sca_res_addr; /**< <tt>\b 0x128:</tt> CTB SCA_RES_ADDR Register */ 110 __IO uint32_t sca_op_buff_addr; /**< <tt>\b 0x12C:</tt> CTB SCA_OP_BUFF_ADDR Register */ 111 __IO uint32_t sca_moddata; /**< <tt>\b 0x130:</tt> CTB SCA_MODDATA Register */ 112 __IO uint32_t sca_nrng; /**< <tt>\b 0x134:</tt> CTB SCA_NRNG Register */ 113 } mxc_ctb_regs_t; 114 115 /* Register offsets for module CTB */ 116 /** 117 * @ingroup ctb_registers 118 * @defgroup CTB_Register_Offsets Register Offsets 119 * @brief CTB Peripheral Register Offsets from the CTB Base Peripheral Address. 120 * @{ 121 */ 122 #define MXC_R_CTB_CTRL ((uint32_t)0x00000000UL) /**< Offset from CTB Base Address: <tt> 0x0000</tt> */ 123 #define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from CTB Base Address: <tt> 0x0004</tt> */ 124 #define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from CTB Base Address: <tt> 0x0008</tt> */ 125 #define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from CTB Base Address: <tt> 0x000C</tt> */ 126 #define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from CTB Base Address: <tt> 0x0010</tt> */ 127 #define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from CTB Base Address: <tt> 0x0014</tt> */ 128 #define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from CTB Base Address: <tt> 0x0018</tt> */ 129 #define MXC_R_CTB_DIN ((uint32_t)0x00000020UL) /**< Offset from CTB Base Address: <tt> 0x0020</tt> */ 130 #define MXC_R_CTB_DOUT ((uint32_t)0x00000030UL) /**< Offset from CTB Base Address: <tt> 0x0030</tt> */ 131 #define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from CTB Base Address: <tt> 0x0040</tt> */ 132 #define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from CTB Base Address: <tt> 0x0044</tt> */ 133 #define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from CTB Base Address: <tt> 0x004C</tt> */ 134 #define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from CTB Base Address: <tt> 0x0050</tt> */ 135 #define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from CTB Base Address: <tt> 0x0060</tt> */ 136 #define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from CTB Base Address: <tt> 0x0080</tt> */ 137 #define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from CTB Base Address: <tt> 0x00C0</tt> */ 138 #define MXC_R_CTB_AAD_LENGTH ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: <tt> 0x00D0</tt> */ 139 #define MXC_R_CTB_PLD_LENGTH ((uint32_t)0x000000D8UL) /**< Offset from CTB Base Address: <tt> 0x00D8</tt> */ 140 #define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL) /**< Offset from CTB Base Address: <tt> 0x00E0</tt> */ 141 #define MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000100UL) /**< Offset from CTB Base Address: <tt> 0x0100</tt> */ 142 #define MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000104UL) /**< Offset from CTB Base Address: <tt> 0x0104</tt> */ 143 #define MXC_R_CTB_SCA_STAT ((uint32_t)0x00000108UL) /**< Offset from CTB Base Address: <tt> 0x0108</tt> */ 144 #define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL) /**< Offset from CTB Base Address: <tt> 0x010C</tt> */ 145 #define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL) /**< Offset from CTB Base Address: <tt> 0x0110</tt> */ 146 #define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL) /**< Offset from CTB Base Address: <tt> 0x0114</tt> */ 147 #define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL) /**< Offset from CTB Base Address: <tt> 0x0118</tt> */ 148 #define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL) /**< Offset from CTB Base Address: <tt> 0x011C</tt> */ 149 #define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL) /**< Offset from CTB Base Address: <tt> 0x0120</tt> */ 150 #define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL) /**< Offset from CTB Base Address: <tt> 0x0124</tt> */ 151 #define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL) /**< Offset from CTB Base Address: <tt> 0x0128</tt> */ 152 #define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL) /**< Offset from CTB Base Address: <tt> 0x012C</tt> */ 153 #define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL) /**< Offset from CTB Base Address: <tt> 0x0130</tt> */ 154 #define MXC_R_CTB_SCA_NRNG ((uint32_t)0x00000134UL) /**< Offset from CTB Base Address: <tt> 0x0134</tt> */ 155 /**@} end of group ctb_registers */ 156 157 /** 158 * @ingroup ctb_registers 159 * @defgroup CTB_CTRL CTB_CTRL 160 * @brief Crypto Control Register. 161 * @{ 162 */ 163 #define MXC_F_CTB_CTRL_RST_POS 0 /**< CTRL_RST Position */ 164 #define MXC_F_CTB_CTRL_RST ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_RST_POS)) /**< CTRL_RST Mask */ 165 166 #define MXC_F_CTB_CTRL_INTR_POS 1 /**< CTRL_INTR Position */ 167 #define MXC_F_CTB_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_INTR_POS)) /**< CTRL_INTR Mask */ 168 169 #define MXC_F_CTB_CTRL_SRC_POS 2 /**< CTRL_SRC Position */ 170 #define MXC_F_CTB_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_SRC_POS)) /**< CTRL_SRC Mask */ 171 172 #define MXC_F_CTB_CTRL_BSO_POS 4 /**< CTRL_BSO Position */ 173 #define MXC_F_CTB_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_BSO_POS)) /**< CTRL_BSO Mask */ 174 175 #define MXC_F_CTB_CTRL_BSI_POS 5 /**< CTRL_BSI Position */ 176 #define MXC_F_CTB_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_BSI_POS)) /**< CTRL_BSI Mask */ 177 178 #define MXC_F_CTB_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */ 179 #define MXC_F_CTB_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */ 180 181 #define MXC_F_CTB_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */ 182 #define MXC_F_CTB_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */ 183 184 #define MXC_F_CTB_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */ 185 #define MXC_F_CTB_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_CTB_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */ 186 #define MXC_V_CTB_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */ 187 #define MXC_S_CTB_CTRL_WRSRC_NONE (MXC_V_CTB_CTRL_WRSRC_NONE << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */ 188 #define MXC_V_CTB_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */ 189 #define MXC_S_CTB_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_CTB_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */ 190 #define MXC_V_CTB_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */ 191 #define MXC_S_CTB_CTRL_WRSRC_READFIFO (MXC_V_CTB_CTRL_WRSRC_READFIFO << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */ 192 193 #define MXC_F_CTB_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */ 194 #define MXC_F_CTB_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_CTB_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */ 195 #define MXC_V_CTB_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */ 196 #define MXC_S_CTB_CTRL_RDSRC_DMADISABLED (MXC_V_CTB_CTRL_RDSRC_DMADISABLED << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */ 197 #define MXC_V_CTB_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */ 198 #define MXC_S_CTB_CTRL_RDSRC_DMAORAPB (MXC_V_CTB_CTRL_RDSRC_DMAORAPB << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */ 199 #define MXC_V_CTB_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */ 200 #define MXC_S_CTB_CTRL_RDSRC_RNG (MXC_V_CTB_CTRL_RDSRC_RNG << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */ 201 202 #define MXC_F_CTB_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */ 203 #define MXC_F_CTB_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */ 204 205 #define MXC_F_CTB_CTRL_DMADNEMSK_POS 15 /**< CTRL_DMADNEMSK Position */ 206 #define MXC_F_CTB_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DMADNEMSK_POS)) /**< CTRL_DMADNEMSK Mask */ 207 208 #define MXC_F_CTB_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */ 209 #define MXC_F_CTB_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */ 210 211 #define MXC_F_CTB_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */ 212 #define MXC_F_CTB_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */ 213 214 #define MXC_F_CTB_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */ 215 #define MXC_F_CTB_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */ 216 217 #define MXC_F_CTB_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */ 218 #define MXC_F_CTB_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */ 219 220 #define MXC_F_CTB_CTRL_ERR_POS 29 /**< CTRL_ERR Position */ 221 #define MXC_F_CTB_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_ERR_POS)) /**< CTRL_ERR Mask */ 222 223 #define MXC_F_CTB_CTRL_RDY_POS 30 /**< CTRL_RDY Position */ 224 #define MXC_F_CTB_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 225 226 #define MXC_F_CTB_CTRL_DONE_POS 31 /**< CTRL_DONE Position */ 227 #define MXC_F_CTB_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DONE_POS)) /**< CTRL_DONE Mask */ 228 229 /**@} end of group CTB_CTRL_Register */ 230 231 /** 232 * @ingroup ctb_registers 233 * @defgroup CTB_CIPHER_CTRL CTB_CIPHER_CTRL 234 * @brief Cipher Control Register. 235 * @{ 236 */ 237 #define MXC_F_CTB_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 238 #define MXC_F_CTB_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 239 240 #define MXC_F_CTB_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 241 #define MXC_F_CTB_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 242 243 #define MXC_F_CTB_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 244 #define MXC_F_CTB_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_CTB_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 245 #define MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 246 #define MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 247 #define MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 248 #define MXC_S_CTB_CIPHER_CTRL_SRC_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 249 #define MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 250 #define MXC_S_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 251 252 #define MXC_F_CTB_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 253 #define MXC_F_CTB_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 254 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 255 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DIS (MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 256 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 257 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 258 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 259 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES192 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 260 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 261 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES256 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 262 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 263 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DES (MXC_V_CTB_CIPHER_CTRL_CIPHER_DES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 264 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 265 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_TDES (MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 266 267 #define MXC_F_CTB_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 268 #define MXC_F_CTB_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 269 #define MXC_V_CTB_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 270 #define MXC_S_CTB_CIPHER_CTRL_MODE_ECB (MXC_V_CTB_CIPHER_CTRL_MODE_ECB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 271 #define MXC_V_CTB_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 272 #define MXC_S_CTB_CIPHER_CTRL_MODE_CBC (MXC_V_CTB_CIPHER_CTRL_MODE_CBC << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 273 #define MXC_V_CTB_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 274 #define MXC_S_CTB_CIPHER_CTRL_MODE_CFB (MXC_V_CTB_CIPHER_CTRL_MODE_CFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 275 #define MXC_V_CTB_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 276 #define MXC_S_CTB_CIPHER_CTRL_MODE_OFB (MXC_V_CTB_CIPHER_CTRL_MODE_OFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 277 #define MXC_V_CTB_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 278 #define MXC_S_CTB_CIPHER_CTRL_MODE_CTR (MXC_V_CTB_CIPHER_CTRL_MODE_CTR << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 279 280 #define MXC_F_CTB_CIPHER_CTRL_HVC_POS 11 /**< CIPHER_CTRL_HVC Position */ 281 #define MXC_F_CTB_CIPHER_CTRL_HVC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_HVC_POS)) /**< CIPHER_CTRL_HVC Mask */ 282 283 #define MXC_F_CTB_CIPHER_CTRL_DTYPE_POS 12 /**< CIPHER_CTRL_DTYPE Position */ 284 #define MXC_F_CTB_CIPHER_CTRL_DTYPE ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_DTYPE_POS)) /**< CIPHER_CTRL_DTYPE Mask */ 285 286 #define MXC_F_CTB_CIPHER_CTRL_CCMM_POS 13 /**< CIPHER_CTRL_CCMM Position */ 287 #define MXC_F_CTB_CIPHER_CTRL_CCMM ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCMM_POS)) /**< CIPHER_CTRL_CCMM Mask */ 288 289 #define MXC_F_CTB_CIPHER_CTRL_CCML_POS 16 /**< CIPHER_CTRL_CCML Position */ 290 #define MXC_F_CTB_CIPHER_CTRL_CCML ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCML_POS)) /**< CIPHER_CTRL_CCML Mask */ 291 292 /**@} end of group CTB_CIPHER_CTRL_Register */ 293 294 /** 295 * @ingroup ctb_registers 296 * @defgroup CTB_HASH_CTRL CTB_HASH_CTRL 297 * @brief HASH Control Register. 298 * @{ 299 */ 300 #define MXC_F_CTB_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 301 #define MXC_F_CTB_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 302 303 #define MXC_F_CTB_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 304 #define MXC_F_CTB_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 305 306 #define MXC_F_CTB_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 307 #define MXC_F_CTB_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_CTB_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 308 #define MXC_V_CTB_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 309 #define MXC_S_CTB_HASH_CTRL_HASH_DIS (MXC_V_CTB_HASH_CTRL_HASH_DIS << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 310 #define MXC_V_CTB_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 311 #define MXC_S_CTB_HASH_CTRL_HASH_SHA1 (MXC_V_CTB_HASH_CTRL_HASH_SHA1 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 312 #define MXC_V_CTB_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 313 #define MXC_S_CTB_HASH_CTRL_HASH_SHA224 (MXC_V_CTB_HASH_CTRL_HASH_SHA224 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 314 #define MXC_V_CTB_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 315 #define MXC_S_CTB_HASH_CTRL_HASH_SHA256 (MXC_V_CTB_HASH_CTRL_HASH_SHA256 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 316 #define MXC_V_CTB_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 317 #define MXC_S_CTB_HASH_CTRL_HASH_SHA384 (MXC_V_CTB_HASH_CTRL_HASH_SHA384 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 318 #define MXC_V_CTB_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 319 #define MXC_S_CTB_HASH_CTRL_HASH_SHA512 (MXC_V_CTB_HASH_CTRL_HASH_SHA512 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 320 321 #define MXC_F_CTB_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 322 #define MXC_F_CTB_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 323 324 /**@} end of group CTB_HASH_CTRL_Register */ 325 326 /** 327 * @ingroup ctb_registers 328 * @defgroup CTB_CRC_CTRL CTB_CRC_CTRL 329 * @brief CRC Control Register. 330 * @{ 331 */ 332 #define MXC_F_CTB_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */ 333 #define MXC_F_CTB_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */ 334 335 #define MXC_F_CTB_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 336 #define MXC_F_CTB_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 337 338 #define MXC_F_CTB_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 339 #define MXC_F_CTB_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 340 341 #define MXC_F_CTB_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 342 #define MXC_F_CTB_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 343 344 #define MXC_F_CTB_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 345 #define MXC_F_CTB_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 346 347 #define MXC_F_CTB_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 348 #define MXC_F_CTB_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 349 350 /**@} end of group CTB_CRC_CTRL_Register */ 351 352 /** 353 * @ingroup ctb_registers 354 * @defgroup CTB_DMA_SRC CTB_DMA_SRC 355 * @brief Crypto DMA Source Address. 356 * @{ 357 */ 358 #define MXC_F_CTB_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ 359 #define MXC_F_CTB_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ 360 361 /**@} end of group CTB_DMA_SRC_Register */ 362 363 /** 364 * @ingroup ctb_registers 365 * @defgroup CTB_DMA_DEST CTB_DMA_DEST 366 * @brief Crypto DMA Destination Address. 367 * @{ 368 */ 369 #define MXC_F_CTB_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ 370 #define MXC_F_CTB_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ 371 372 /**@} end of group CTB_DMA_DEST_Register */ 373 374 /** 375 * @ingroup ctb_registers 376 * @defgroup CTB_DMA_CNT CTB_DMA_CNT 377 * @brief Crypto DMA Byte Count. 378 * @{ 379 */ 380 #define MXC_F_CTB_DMA_CNT_ADDR_POS 0 /**< DMA_CNT_ADDR Position */ 381 #define MXC_F_CTB_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */ 382 383 /**@} end of group CTB_DMA_CNT_Register */ 384 385 /** 386 * @ingroup ctb_registers 387 * @defgroup CTB_DIN CTB_DIN 388 * @brief Crypto Data Input. Data input can be written to this register instead of using 389 * the DMA. This register writes to the FIFO. This register occupies four 390 * successive words to allow the use of multi-store instructions. Words can be 391 * written to any location, they will be placed in the FIFO in the order they are 392 * written. The endian swap input control bit affects this register. 393 * @{ 394 */ 395 #define MXC_F_CTB_DIN_DATA_POS 0 /**< DIN_DATA Position */ 396 #define MXC_F_CTB_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DIN_DATA_POS)) /**< DIN_DATA Mask */ 397 398 /**@} end of group CTB_DIN_Register */ 399 400 /** 401 * @ingroup ctb_registers 402 * @defgroup CTB_DOUT CTB_DOUT 403 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 404 * the lower words of these four registers depending on the algorithm. For block 405 * cipher modes, this register holds the result of most recent encryption or 406 * decryption operation. These registers are affected by the endian swap bits. 407 * @{ 408 */ 409 #define MXC_F_CTB_DOUT_DATA_POS 0 /**< DOUT_DATA Position */ 410 #define MXC_F_CTB_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DOUT_DATA_POS)) /**< DOUT_DATA Mask */ 411 412 /**@} end of group CTB_DOUT_Register */ 413 414 /** 415 * @ingroup ctb_registers 416 * @defgroup CTB_CRC_POLY CTB_CRC_POLY 417 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 418 * LFSR) should be written to this register. This register is affected by the MSB 419 * control bit. 420 * @{ 421 */ 422 #define MXC_F_CTB_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */ 423 #define MXC_F_CTB_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */ 424 425 /**@} end of group CTB_CRC_POLY_Register */ 426 427 /** 428 * @ingroup ctb_registers 429 * @defgroup CTB_CRC_VAL CTB_CRC_VAL 430 * @brief CRC Value. This is the state for the Galois Field. This register holds the 431 * result of a CRC calculation or the current state of the LFSR. This register is 432 * affected by the MSB control bit. 433 * @{ 434 */ 435 #define MXC_F_CTB_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 436 #define MXC_F_CTB_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 437 438 /**@} end of group CTB_CRC_VAL_Register */ 439 440 /** 441 * @ingroup ctb_registers 442 * @defgroup CTB_HAM_ECC CTB_HAM_ECC 443 * @brief Hamming ECC Register. 444 * @{ 445 */ 446 #define MXC_F_CTB_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 447 #define MXC_F_CTB_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_CTB_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 448 449 #define MXC_F_CTB_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 450 #define MXC_F_CTB_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_CTB_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 451 452 /**@} end of group CTB_HAM_ECC_Register */ 453 454 /** 455 * @ingroup ctb_registers 456 * @defgroup CTB_CIPHER_INIT CTB_CIPHER_INIT 457 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 458 * modes, this register holds the initial value. This register is updated with each 459 * encryption or decryption operation. This register is affected by the endian swap 460 * bits. 461 * @{ 462 */ 463 #define MXC_F_CTB_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 464 #define MXC_F_CTB_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 465 466 /**@} end of group CTB_CIPHER_INIT_Register */ 467 468 /** 469 * @ingroup ctb_registers 470 * @defgroup CTB_CIPHER_KEY CTB_CIPHER_KEY 471 * @brief Cipher Key. This register holds the key used for block cipher operations. The 472 * lower words are used for block ciphers that use shorter key lengths. This 473 * register is affected by the endian swap input control bits. 474 * @{ 475 */ 476 #define MXC_F_CTB_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 477 #define MXC_F_CTB_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 478 479 /**@} end of group CTB_CIPHER_KEY_Register */ 480 481 /** 482 * @ingroup ctb_registers 483 * @defgroup CTB_HASH_DIGEST CTB_HASH_DIGEST 484 * @brief This register holds the calculated hash value. This register is affected by the 485 * endian swap bits. 486 * @{ 487 */ 488 #define MXC_F_CTB_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 489 #define MXC_F_CTB_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 490 491 /**@} end of group CTB_HASH_DIGEST_Register */ 492 493 /** 494 * @ingroup ctb_registers 495 * @defgroup CTB_HASH_MSG_SZ CTB_HASH_MSG_SZ 496 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 497 * @{ 498 */ 499 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 500 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 501 502 /**@} end of group CTB_HASH_MSG_SZ_Register */ 503 504 /** 505 * @ingroup ctb_registers 506 * @defgroup CTB_AAD_LENGTH CTB_AAD_LENGTH 507 * @brief AAD Length Registers. 508 * @{ 509 */ 510 #define MXC_F_CTB_AAD_LENGTH_LENGTH_POS 0 /**< AAD_LENGTH_LENGTH Position */ 511 #define MXC_F_CTB_AAD_LENGTH_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_AAD_LENGTH_LENGTH_POS)) /**< AAD_LENGTH_LENGTH Mask */ 512 513 /**@} end of group CTB_AAD_LENGTH_Register */ 514 515 /** 516 * @ingroup ctb_registers 517 * @defgroup CTB_PLD_LENGTH CTB_PLD_LENGTH 518 * @brief PLD Length Registers. 519 * @{ 520 */ 521 #define MXC_F_CTB_PLD_LENGTH_LENGTH_POS 0 /**< PLD_LENGTH_LENGTH Position */ 522 #define MXC_F_CTB_PLD_LENGTH_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_LENGTH_POS)) /**< PLD_LENGTH_LENGTH Mask */ 523 524 /**@} end of group CTB_PLD_LENGTH_Register */ 525 526 /** 527 * @ingroup ctb_registers 528 * @defgroup CTB_TAGMIC CTB_TAGMIC 529 * @brief TAG/MIC Registers. 530 * @{ 531 */ 532 #define MXC_F_CTB_TAGMIC_LENGTH_POS 0 /**< TAGMIC_LENGTH Position */ 533 #define MXC_F_CTB_TAGMIC_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_TAGMIC_LENGTH_POS)) /**< TAGMIC_LENGTH Mask */ 534 535 /**@} end of group CTB_TAGMIC_Register */ 536 537 /** 538 * @ingroup ctb_registers 539 * @defgroup CTB_SCA_CTRL0 CTB_SCA_CTRL0 540 * @brief SCA Control 0 Register. 541 * @{ 542 */ 543 #define MXC_F_CTB_SCA_CTRL0_STC_POS 0 /**< SCA_CTRL0_STC Position */ 544 #define MXC_F_CTB_SCA_CTRL0_STC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_STC_POS)) /**< SCA_CTRL0_STC Mask */ 545 546 #define MXC_F_CTB_SCA_CTRL0_SCAIE_POS 1 /**< SCA_CTRL0_SCAIE Position */ 547 #define MXC_F_CTB_SCA_CTRL0_SCAIE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_SCAIE_POS)) /**< SCA_CTRL0_SCAIE Mask */ 548 549 #define MXC_F_CTB_SCA_CTRL0_ABORT_POS 2 /**< SCA_CTRL0_ABORT Position */ 550 #define MXC_F_CTB_SCA_CTRL0_ABORT ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ABORT_POS)) /**< SCA_CTRL0_ABORT Mask */ 551 552 #define MXC_F_CTB_SCA_CTRL0_ERMEM_POS 4 /**< SCA_CTRL0_ERMEM Position */ 553 #define MXC_F_CTB_SCA_CTRL0_ERMEM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ERMEM_POS)) /**< SCA_CTRL0_ERMEM Mask */ 554 555 #define MXC_F_CTB_SCA_CTRL0_MANPARAM_POS 5 /**< SCA_CTRL0_MANPARAM Position */ 556 #define MXC_F_CTB_SCA_CTRL0_MANPARAM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_MANPARAM_POS)) /**< SCA_CTRL0_MANPARAM Mask */ 557 558 #define MXC_F_CTB_SCA_CTRL0_HWKEY_POS 6 /**< SCA_CTRL0_HWKEY Position */ 559 #define MXC_F_CTB_SCA_CTRL0_HWKEY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_HWKEY_POS)) /**< SCA_CTRL0_HWKEY Mask */ 560 561 #define MXC_F_CTB_SCA_CTRL0_OPCODE_POS 8 /**< SCA_CTRL0_OPCODE Position */ 562 #define MXC_F_CTB_SCA_CTRL0_OPCODE ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CTRL0_OPCODE_POS)) /**< SCA_CTRL0_OPCODE Mask */ 563 564 #define MXC_F_CTB_SCA_CTRL0_MODADDR_POS 16 /**< SCA_CTRL0_MODADDR Position */ 565 #define MXC_F_CTB_SCA_CTRL0_MODADDR ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CTRL0_MODADDR_POS)) /**< SCA_CTRL0_MODADDR Mask */ 566 567 #define MXC_F_CTB_SCA_CTRL0_ECCSIZE_POS 24 /**< SCA_CTRL0_ECCSIZE Position */ 568 #define MXC_F_CTB_SCA_CTRL0_ECCSIZE ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CTRL0_ECCSIZE_POS)) /**< SCA_CTRL0_ECCSIZE Mask */ 569 570 /**@} end of group CTB_SCA_CTRL0_Register */ 571 572 /** 573 * @ingroup ctb_registers 574 * @defgroup CTB_SCA_CTRL1 CTB_SCA_CTRL1 575 * @brief SCA Control 1 Register. 576 * @{ 577 */ 578 #define MXC_F_CTB_SCA_CTRL1_MAN_POS 0 /**< SCA_CTRL1_MAN Position */ 579 #define MXC_F_CTB_SCA_CTRL1_MAN ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_MAN_POS)) /**< SCA_CTRL1_MAN Mask */ 580 581 #define MXC_F_CTB_SCA_CTRL1_AUTOCARRY_POS 1 /**< SCA_CTRL1_AUTOCARRY Position */ 582 #define MXC_F_CTB_SCA_CTRL1_AUTOCARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_AUTOCARRY_POS)) /**< SCA_CTRL1_AUTOCARRY Mask */ 583 584 #define MXC_F_CTB_SCA_CTRL1_PLUSONE_POS 2 /**< SCA_CTRL1_PLUSONE Position */ 585 #define MXC_F_CTB_SCA_CTRL1_PLUSONE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_PLUSONE_POS)) /**< SCA_CTRL1_PLUSONE Mask */ 586 587 #define MXC_F_CTB_SCA_CTRL1_NRNG_POS 5 /**< SCA_CTRL1_NRNG Position */ 588 #define MXC_F_CTB_SCA_CTRL1_NRNG ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_NRNG_POS)) /**< SCA_CTRL1_NRNG Mask */ 589 590 #define MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS 8 /**< SCA_CTRL1_CARRYPOS Position */ 591 #define MXC_F_CTB_SCA_CTRL1_CARRYPOS ((uint32_t)(0x3FFUL << MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS)) /**< SCA_CTRL1_CARRYPOS Mask */ 592 593 /**@} end of group CTB_SCA_CTRL1_Register */ 594 595 /** 596 * @ingroup ctb_registers 597 * @defgroup CTB_SCA_STAT CTB_SCA_STAT 598 * @brief SCA Status Register. 599 * @{ 600 */ 601 #define MXC_F_CTB_SCA_STAT_BUSY_POS 0 /**< SCA_STAT_BUSY Position */ 602 #define MXC_F_CTB_SCA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_BUSY_POS)) /**< SCA_STAT_BUSY Mask */ 603 604 #define MXC_F_CTB_SCA_STAT_SCAIF_POS 1 /**< SCA_STAT_SCAIF Position */ 605 #define MXC_F_CTB_SCA_STAT_SCAIF ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_SCAIF_POS)) /**< SCA_STAT_SCAIF Mask */ 606 607 #define MXC_F_CTB_SCA_STAT_PVF1_POS 2 /**< SCA_STAT_PVF1 Position */ 608 #define MXC_F_CTB_SCA_STAT_PVF1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_PVF1_POS)) /**< SCA_STAT_PVF1 Mask */ 609 610 #define MXC_F_CTB_SCA_STAT_PVF2_POS 3 /**< SCA_STAT_PVF2 Position */ 611 #define MXC_F_CTB_SCA_STAT_PVF2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_PVF2_POS)) /**< SCA_STAT_PVF2 Mask */ 612 613 #define MXC_F_CTB_SCA_STAT_FSMERR_POS 4 /**< SCA_STAT_FSMERR Position */ 614 #define MXC_F_CTB_SCA_STAT_FSMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_FSMERR_POS)) /**< SCA_STAT_FSMERR Mask */ 615 616 #define MXC_F_CTB_SCA_STAT_COMPERR_POS 5 /**< SCA_STAT_COMPERR Position */ 617 #define MXC_F_CTB_SCA_STAT_COMPERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_COMPERR_POS)) /**< SCA_STAT_COMPERR Mask */ 618 619 #define MXC_F_CTB_SCA_STAT_MEMERR_POS 6 /**< SCA_STAT_MEMERR Position */ 620 #define MXC_F_CTB_SCA_STAT_MEMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_MEMERR_POS)) /**< SCA_STAT_MEMERR Mask */ 621 622 #define MXC_F_CTB_SCA_STAT_CARRY_POS 8 /**< SCA_STAT_CARRY Position */ 623 #define MXC_F_CTB_SCA_STAT_CARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_CARRY_POS)) /**< SCA_STAT_CARRY Mask */ 624 625 #define MXC_F_CTB_SCA_STAT_GTE2I2_POS 9 /**< SCA_STAT_GTE2I2 Position */ 626 #define MXC_F_CTB_SCA_STAT_GTE2I2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_GTE2I2_POS)) /**< SCA_STAT_GTE2I2 Mask */ 627 628 #define MXC_F_CTB_SCA_STAT_ALUNEG1_POS 10 /**< SCA_STAT_ALUNEG1 Position */ 629 #define MXC_F_CTB_SCA_STAT_ALUNEG1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_ALUNEG1_POS)) /**< SCA_STAT_ALUNEG1 Mask */ 630 631 #define MXC_F_CTB_SCA_STAT_ALUNEG2_POS 11 /**< SCA_STAT_ALUNEG2 Position */ 632 #define MXC_F_CTB_SCA_STAT_ALUNEG2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_ALUNEG2_POS)) /**< SCA_STAT_ALUNEG2 Mask */ 633 634 /**@} end of group CTB_SCA_STAT_Register */ 635 636 /** 637 * @ingroup ctb_registers 638 * @defgroup CTB_SCA_PPX_ADDR CTB_SCA_PPX_ADDR 639 * @brief PPX Coordinate Data Pointer Register. 640 * @{ 641 */ 642 #define MXC_F_CTB_SCA_PPX_ADDR_ADDR_POS 0 /**< SCA_PPX_ADDR_ADDR Position */ 643 #define MXC_F_CTB_SCA_PPX_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPX_ADDR_ADDR_POS)) /**< SCA_PPX_ADDR_ADDR Mask */ 644 645 /**@} end of group CTB_SCA_PPX_ADDR_Register */ 646 647 /** 648 * @ingroup ctb_registers 649 * @defgroup CTB_SCA_PPY_ADDR CTB_SCA_PPY_ADDR 650 * @brief PPY Coordinate Data Pointer Register. 651 * @{ 652 */ 653 #define MXC_F_CTB_SCA_PPY_ADDR_ADDR_POS 0 /**< SCA_PPY_ADDR_ADDR Position */ 654 #define MXC_F_CTB_SCA_PPY_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPY_ADDR_ADDR_POS)) /**< SCA_PPY_ADDR_ADDR Mask */ 655 656 /**@} end of group CTB_SCA_PPY_ADDR_Register */ 657 658 /** 659 * @ingroup ctb_registers 660 * @defgroup CTB_SCA_PPZ_ADDR CTB_SCA_PPZ_ADDR 661 * @brief PPZ Coordinate Data Pointer Register. 662 * @{ 663 */ 664 #define MXC_F_CTB_SCA_PPZ_ADDR_ADDR_POS 0 /**< SCA_PPZ_ADDR_ADDR Position */ 665 #define MXC_F_CTB_SCA_PPZ_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPZ_ADDR_ADDR_POS)) /**< SCA_PPZ_ADDR_ADDR Mask */ 666 667 /**@} end of group CTB_SCA_PPZ_ADDR_Register */ 668 669 /** 670 * @ingroup ctb_registers 671 * @defgroup CTB_SCA_PQX_ADDR CTB_SCA_PQX_ADDR 672 * @brief PQX Coordinate Data Pointer Register. 673 * @{ 674 */ 675 #define MXC_F_CTB_SCA_PQX_ADDR_ADDR_POS 0 /**< SCA_PQX_ADDR_ADDR Position */ 676 #define MXC_F_CTB_SCA_PQX_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQX_ADDR_ADDR_POS)) /**< SCA_PQX_ADDR_ADDR Mask */ 677 678 /**@} end of group CTB_SCA_PQX_ADDR_Register */ 679 680 /** 681 * @ingroup ctb_registers 682 * @defgroup CTB_SCA_PQY_ADDR CTB_SCA_PQY_ADDR 683 * @brief PQY Coordinate Data Pointer Register. 684 * @{ 685 */ 686 #define MXC_F_CTB_SCA_PQY_ADDR_ADDR_POS 0 /**< SCA_PQY_ADDR_ADDR Position */ 687 #define MXC_F_CTB_SCA_PQY_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQY_ADDR_ADDR_POS)) /**< SCA_PQY_ADDR_ADDR Mask */ 688 689 /**@} end of group CTB_SCA_PQY_ADDR_Register */ 690 691 /** 692 * @ingroup ctb_registers 693 * @defgroup CTB_SCA_PQZ_ADDR CTB_SCA_PQZ_ADDR 694 * @brief PQZ Coordinate Data Pointer Register. 695 * @{ 696 */ 697 #define MXC_F_CTB_SCA_PQZ_ADDR_ADDR_POS 0 /**< SCA_PQZ_ADDR_ADDR Position */ 698 #define MXC_F_CTB_SCA_PQZ_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQZ_ADDR_ADDR_POS)) /**< SCA_PQZ_ADDR_ADDR Mask */ 699 700 /**@} end of group CTB_SCA_PQZ_ADDR_Register */ 701 702 /** 703 * @ingroup ctb_registers 704 * @defgroup CTB_SCA_RDSA_ADDR CTB_SCA_RDSA_ADDR 705 * @brief SCA RDSA Address Register. 706 * @{ 707 */ 708 #define MXC_F_CTB_SCA_RDSA_ADDR_ADDR_POS 0 /**< SCA_RDSA_ADDR_ADDR Position */ 709 #define MXC_F_CTB_SCA_RDSA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RDSA_ADDR_ADDR_POS)) /**< SCA_RDSA_ADDR_ADDR Mask */ 710 711 /**@} end of group CTB_SCA_RDSA_ADDR_Register */ 712 713 /** 714 * @ingroup ctb_registers 715 * @defgroup CTB_SCA_RES_ADDR CTB_SCA_RES_ADDR 716 * @brief SCA Result Address Register. 717 * @{ 718 */ 719 #define MXC_F_CTB_SCA_RES_ADDR_ADDR_POS 0 /**< SCA_RES_ADDR_ADDR Position */ 720 #define MXC_F_CTB_SCA_RES_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RES_ADDR_ADDR_POS)) /**< SCA_RES_ADDR_ADDR Mask */ 721 722 /**@} end of group CTB_SCA_RES_ADDR_Register */ 723 724 /** 725 * @ingroup ctb_registers 726 * @defgroup CTB_SCA_OP_BUFF_ADDR CTB_SCA_OP_BUFF_ADDR 727 * @brief SCA Operation Buffer Address Register. 728 * @{ 729 */ 730 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR_POS 0 /**< SCA_OP_BUFF_ADDR_ADDR Position */ 731 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR_POS)) /**< SCA_OP_BUFF_ADDR_ADDR Mask */ 732 733 /**@} end of group CTB_SCA_OP_BUFF_ADDR_Register */ 734 735 /** 736 * @ingroup ctb_registers 737 * @defgroup CTB_SCA_MODDATA CTB_SCA_MODDATA 738 * @brief SCA Modulo Data Input Register. 739 * @{ 740 */ 741 #define MXC_F_CTB_SCA_MODDATA_DATA_POS 0 /**< SCA_MODDATA_DATA Position */ 742 #define MXC_F_CTB_SCA_MODDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_MODDATA_DATA_POS)) /**< SCA_MODDATA_DATA Mask */ 743 744 /**@} end of group CTB_SCA_MODDATA_Register */ 745 746 #ifdef __cplusplus 747 } 748 #endif 749 750 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_CTB_REGS_H_ 751
